Memory device and method of manufacturing the same

Abstract

The application provides a memory device and a preparation method thereof, and relates to the technical field of semiconductors, and comprises the following steps: forming a plurality of first-direction embedded gate structures on a substrate; patterning the substrate to cut off the embedded gate structures, and forming a plurality of parallel and spaced active structures and isolation grooves between the active structures in a second direction; wherein the active structure is an island-shaped columnar body, and the active structure comprises the embedded gate structure; forming an isolation structure in the isolation groove, and the surface of the isolation structure is flush with the surface of the active structure; and forming a plurality of first-direction conductive word lines on the surface of the isolation structure and the active structure, and the conductive word lines cover the upper surface of the embedded gate structure in the active structure. The application achieves the purposes of weakening the hammering effect and improving the performance of the memory device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a memory device and its fabrication method. Background Technology

[0002] In existing memory device fabrication processes, buried gates typically penetrate both the active and isolation structures. When a buried gate in a row of the memory matrix is ​​activated or repeatedly refreshed, it can easily generate noise or interference to adjacent rows, resulting in a row hammering effect. This can cause data errors in one or more cells within a neighboring row, thereby affecting memory performance. Summary of the Invention

[0003] In view of this, the purpose of the present invention is to provide a memory device and a method for manufacturing the same, which can avoid the impact of the buried gate structure in the same row of active structure on the buried gate structure when the conductive word line is energized, reduce the impact of the hammer effect, and improve the performance of the memory device.

[0004] To achieve the above objectives, the technical solutions adopted in the embodiments of the present invention are as follows:

[0005] A method for fabricating a storage device, comprising:

[0006] Several buried gate structures in a first orientation are formed on the substrate;

[0007] The substrate is patterned, the buried gate structure is cut off, and a plurality of parallel spaced active structures and isolation trenches between the active structures are formed in a second direction; wherein, the active structure is an island-shaped columnar body, and the active structure includes the buried gate structure.

[0008] An isolation structure is formed in the isolation groove, and the surface of the isolation structure is flush with the surface of the active structure.

[0009] A plurality of conductive word lines in a first direction are formed on the surfaces of the isolation structure and the active structure, and the conductive word lines cover the upper surface of the buried gate structure in the active structure.

[0010] In one embodiment, the step of forming a plurality of buried gate structures in a first orientation on the substrate includes:

[0011] A first mask layer is formed on the substrate surface;

[0012] The first mask layer is patterned to form a plurality of first trenches in a first direction that expose the surface of the substrate;

[0013] Using the first mask layer as an etching mask, a portion of the substrate under the first trench is etched away to form a plurality of buried word line trenches in the first direction.

[0014] A conductive material layer is filled into the buried word line trench, so that the upper surface of the conductive material layer is flush with the upper surface of the substrate, forming a buried gate structure.

[0015] In one embodiment, the steps of patterning the substrate, cutting the buried gate structure, and forming a plurality of parallel-spaced active structures and isolation trenches between the active structures in a second direction include:

[0016] A first nitride layer is formed on the substrate surface, and the first nitride layer is patterned to form a plurality of active region mask structures arranged in parallel and spaced apart in the second direction.

[0017] Using the active region mask structure as an etching mask, the exposed substrate is etched away to cut off the buried gate structure, forming a plurality of parallel spaced active structures and isolation trenches between the active structures; wherein the depth of the active structure is greater than the depth of the buried gate structure.

[0018] In one embodiment, the step of patterning the first nitride layer includes:

[0019] A second mask layer is formed on the top surface of the first nitrided layer;

[0020] The second mask layer is patterned to form a strip-shaped mask in the second direction. The second mask layer is used as an etching mask to etch away the exposed first nitride layer, so that the first nitride layer forms a strip-shaped structure in the second direction.

[0021] The strip mask in the second direction is cut into island-shaped masks of a preset length. The island-shaped mask is used as an etching mask to etch away the exposed first nitride layer, so that the first nitride layer forms a number of parallel and spaced active region mask structures.

[0022] In one embodiment, the step of forming an isolation structure in the isolation groove, the surface of the isolation structure being flush with the surface of the active structure, includes:

[0023] A chemical vapor deposition process is performed to form an isolation structure in the isolation tank;

[0024] The top surfaces of the isolation structure and the active structure are leveled so that the top surface of the isolation structure is flush with the top surface of the active structure.

[0025] In one embodiment, the step of forming a plurality of conductive word lines in a first direction on the surfaces of the isolation structure and the active structure includes:

[0026] A conductive layer is formed on the top surface of the isolation structure and the active structure;

[0027] The conductive layer is patterned to form a plurality of conductive word lines in a first direction and a second trench between the conductive word lines.

[0028] In one embodiment, the step of patterning the conductive layer includes:

[0029] A second nitride layer is formed on the top surface of the conductive layer;

[0030] The second nitride layer is patterned to expose a portion of the conductive layer;

[0031] Using the second nitride layer as an etching mask, the exposed conductive layer is etched away to form a plurality of conductive word lines in a first direction and a second trench between the conductive word lines.

[0032] In one embodiment, it further includes:

[0033] An isolation layer is formed, which fills the second trench and covers the conductive word line.

[0034] In one embodiment, prior to filling the embedded word line trench with a conductive material layer, a gate dielectric layer is formed on the inner wall of the embedded word line trench.

[0035] In one embodiment, the gate dielectric layer includes a silicon oxide layer, the conductive material layer includes a tungsten conductive layer, and the isolation structure includes a silicon oxide structure.

[0036] A memory device includes: a substrate, and a plurality of buried gate structures, an isolation structure, a plurality of active structures arranged in parallel and spaced apart in a second direction, and a plurality of conductive word lines in a first direction formed on the substrate.

[0037] The active structure is in the form of an island-shaped column, and the isolation structure is located in the isolation groove between the active structures, with the surface of the active structure flush with that of the isolation structure;

[0038] The buried gate structure is located in the active structure, and the surface of the buried gate structure is flush with the surface of the active structure.

[0039] The conductive word line contacts the top surface of the embedded word line structure and the isolation structure, and the embedded gate structure arranged along the first direction is electrically connected on the top surface of the isolation structure.

[0040] In one embodiment, the buried gate structure includes a buried word line trench and a conductive material layer, the conductive material layer filling the buried word line trench, the width of the buried word line trench being greater than or equal to the width of the conductive word line.

[0041] In one embodiment, the memory device includes a gate dielectric layer and a barrier layer, the gate dielectric layer being formed on the inner wall of an embedded word line trench, and the barrier layer being formed on the surface of the gate dielectric layer.

[0042] In one embodiment, the bottoms of the plurality of buried gate structures are flush.

[0043] In one embodiment, the storage device further includes an isolation layer formed on the conductive word lines and filling the spaces between the conductive word lines.

[0044] The above-mentioned method for fabricating memory devices involves, firstly, forming a plurality of buried gate structures in a first direction on a substrate; secondly, patterning the substrate, cutting the buried gate structures, and forming a plurality of parallel-spaced active structures and isolation trenches between the active structures in a second direction; wherein the active structures are island-shaped pillars and include buried gate structures; thirdly, forming isolation structures in the isolation trenches, the surface of the isolation structures being flush with the surface of the active structures; and finally, forming a plurality of conductive word lines in the first direction on the surfaces of the isolation structures and the active structures, the conductive word lines covering the upper surface of the buried gate structures in the active structures. Compared to first forming an active structure and an isolation structure on a substrate, and then forming a buried gate structure that penetrates the active structure and the isolation structure, the memory device prepared in this application first forms a buried gate structure on a substrate, and then forms an active structure and an isolation structure. This cuts off the buried gate structure, so that the buried gate structure exists only in the active structure. The buried gate structures in each active structure are connected by conductive word lines on the surfaces of the active structure and the isolation structure. The buried gate structure does not penetrate the active structure and the isolation structure, which avoids affecting the adjacent buried gate structures when energizing the buried gate structure in the same direction of the active structure through the conductive word lines. This reduces the impact of the hammer effect and improves the performance of the memory device.

[0045] Other features and advantages of the embodiments of the present invention will be set forth in the following description, or some features and advantages may be inferred from the description or determined without doubt, or may be learned by practicing the techniques described above in the embodiments of the present invention.

[0046] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0047] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0048] Figure 1 This is a flowchart illustrating a method for fabricating a storage device according to one embodiment;

[0049] Figure 2 A schematic diagram illustrating the fabrication of an embedded character line groove according to one embodiment;

[0050] Figure 3 This is a front view of a storage device after forming an embedded word line trench, as provided in one embodiment.

[0051] Figure 4 This is a partial enlarged view of A on the memory device after forming a buried gate structure, provided in one embodiment;

[0052] Figure 5 This is a front view of a storage device after forming an active structure, provided in one embodiment.

[0053] Figure 6 This is a front view of a storage device after forming a strip mask on a substrate, as provided in one embodiment.

[0054] Figure 7a A top view of a first-time patterned etched strip mask storage device provided in one embodiment;

[0055] Figure 7b A top view of a second patterned etched strip mask storage device provided in one embodiment;

[0056] Figure 7c This is a front view of a storage device after forming an island-shaped mask, provided in one embodiment;

[0057] Figure 8 A front view of a storage device after forming an isolation structure, provided in one embodiment;

[0058] Figure 9a This is a front view of a memory device with a conductive layer and a second nitride layer coated on a substrate, provided in one embodiment.

[0059] Figure 9b A front view of a storage device after forming conductive word lines, provided in one embodiment;

[0060] Figure 9c A top view of a storage device after forming conductive word lines, provided in one embodiment;

[0061] Figure 10 This is a front view of a storage device after an isolation layer has been formed, as provided in one embodiment.

[0062] icon:

[0063] 201-Substrate; 202-Word line structure; 203-First trench; 301-Buried word line trench; 401-Gate dielectric layer; 402-Blocking layer; 403-Tungsten conductive layer; 501-Active region mask structure; 502-Active structure; 503-Buried gate structure; 601-Strip mask; 602-Strip structure; 701-Island mask; 801-Isolation structure; 901-Conductive layer; 902-Second nitride layer; 903-Strip mask structure; 904-Conductive word line; 905-Second trench; 100-Isolation layer. Detailed Implementation

[0064] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate preferred embodiments of the application. However, this application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0065] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0066] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this invention, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0067] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0068] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that when the terms “comprise” and / or “comprising” are used in this specification, the presence of the stated feature, integer, step, operation, element, and / or part is established, but the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups is not excluded. Meanwhile, when used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0069] Embodiments of the invention are described herein with reference to cross-sectional views illustrating ideal embodiments (and intermediate structures) of the invention, thus allowing for variations in the illustrated shape due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. For instance, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, the buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device and do not limit the scope of the invention.

[0070] In the fabrication process of typical memory devices, the active region and isolation structure are first formed, and then word line trenches are etched to create the buried gate structure. The buried gate penetrates through the active and isolation structures. When a row of buried gates in a memory matrix is ​​activated or repeatedly refreshed, it can generate noise or interference to adjacent rows. If the activation frequency of adjacent rows is too high before adjacent cells are activated or refreshed, the adjacent cells will become fragile, resulting in charge loss or leakage problems, causing data errors in one or more cells within the adjacent row. This phenomenon is called the hammer effect. When a memory device is prone to the hammer effect, it will affect the performance of the memory device.

[0071] To address the aforementioned problems, this application provides a method for fabricating a storage device, see [link to relevant documentation]. Figure 1 The flowchart shown illustrates a method for fabricating a storage device, which includes:

[0072] Step S102: A plurality of buried gate structures in a first direction are formed on the substrate.

[0073] A substrate is provided, and a plurality of buried gate structures in a first direction are formed on the substrate. The buried gate structures are evenly spaced and are word line trenches filled with conductive material.

[0074] The substrate can be undoped single-crystal silicon, doped single-crystal silicon, silicon-on-insulator (SOI), silicon-on-insulator stacked (SSOI), silicon-on-insulator stacked (S-SiGeOI), silicon-on-insulator (SiGeOI), and germanium-on-insulator (GeOI), etc. For example, in this embodiment, the substrate material can be single-crystal silicon.

[0075] Step S104: Pattern the substrate, cut the buried gate structure, and form a plurality of parallel spaced active structures and isolation trenches between the active structures in the second direction.

[0076] The aforementioned active structure is an island-shaped columnar body, and the active structure includes a buried gate structure. After forming several buried gate structures in a first direction on the substrate, the substrate is patterned and etched to cut the buried gate structures on the substrate, forming several active structures arranged in parallel and spaced-apart as island-shaped columnar bodies. The buried gate structures are located in the active structures, and the height of the etched island-shaped columnar bodies is less than the height of the substrate. The connecting regions between each active structure form isolation trenches.

[0077] Step S106: An isolation structure is formed in the isolation groove, and the surface of the isolation structure is flush with the surface of the active structure.

[0078] An isolation material is filled into the isolation groove between each island-shaped columnar active structure to form an isolation structure. The isolation structure surrounds the active structure. The height of the isolation structure is the same as the height of the island-shaped columnar structure, so that the top surface of the isolation structure is flush with the top surface of the active structure, that is, the top surface of the isolation structure and the top surface of the active structure are at the same horizontal plane.

[0079] In step S108, a plurality of conductive word lines in a first direction are formed on the surfaces of the isolation structure and the active structure, and the conductive word lines cover the upper surface of the buried gate structure in the active structure.

[0080] The direction of the conductive word lines is consistent with the direction of the word line trenches that constitute the buried gate structure. The bottom surface of the conductive word lines contacts the upper surface of the isolation structure and the active structure, and covers the top surface of the buried gate structure in each active structure, electrically connecting the buried gate structures in the same row.

[0081] The above-mentioned method for fabricating memory devices involves, firstly, forming a plurality of buried gate structures in a first direction on a substrate; secondly, patterning the substrate, cutting the buried gate structures, and forming a plurality of parallel-spaced active structures and isolation trenches between the active structures in a second direction; wherein the active structures are island-shaped pillars and include buried gate structures; thirdly, forming isolation structures in the isolation trenches, the surface of the isolation structures being flush with the surface of the active structures; and finally, forming a plurality of conductive word lines in the first direction on the surfaces of the isolation structures and the active structures, the conductive word lines covering the upper surface of the buried gate structures in the active structures. Compared to first forming an active structure and an isolation structure on a substrate, and then forming a buried gate structure that penetrates the active structure and the isolation structure, the memory device prepared in this application first forms a buried gate structure on a substrate, and then forms an active structure and an isolation structure. This cuts off the buried gate structure, so that the buried gate structure exists only in the active structure. The buried gate structures in each active structure are connected by conductive word lines on the surfaces of the active structure and the isolation structure. The buried gate structure does not penetrate the active structure and the isolation structure, which avoids affecting the adjacent buried gate structures when energizing the buried gate structure in the same direction of the active structure through the conductive word lines. This reduces the impact of the hammer effect and improves the performance of the memory device.

[0082] like Figures 2-3 As shown, in one embodiment, step S102 includes:

[0083] S1022, a first mask layer is formed on the substrate surface.

[0084] A photoresist layer is covered on the top surface of substrate 201, and the photoresist layer is used as the first mask layer.

[0085] S1024, patterning the first mask layer to form a plurality of first trenches in a first direction on the surface of the exposed substrate.

[0086] like Figure 2 As shown, the first mask layer is patterned and etched to obtain several parallel and spaced word line structures 202. The trenches between adjacent word line structures that expose the surface of the substrate 201 are referred to as the first trenches 203. The first mask layer forms a mask pattern on the substrate 201 that covers the area to be retained. That is, the pattern formed by the first mask layer exposes the position of the word line trenches on the substrate in which the buried gate structure is subsequently formed.

[0087] S1026, using the first mask layer as an etching mask, etch away part of the substrate under the first trench to form a plurality of buried word line trenches in the first direction.

[0088] The substrate not covered by the first mask layer is etched away, and the etching depth is less than the height of the substrate, resulting in several buried word line trenches in the first direction formed on the substrate, thus removing the word line structure formed by the first mask layer.

[0089] S1028, a conductive material layer is filled in the buried word line trench, so that the upper surface of the conductive material layer is flush with the upper surface of the substrate, forming a buried gate structure.

[0090] like Figure 3 As shown, a conductive material layer is deposited in the buried word line trench 301. The conductive material layer can be, for example, a TiN / W metal layer. The conductive material layer is planarized so that it is flush with the substrate surface, thereby forming several buried gate structures in the first direction on the substrate.

[0091] In one embodiment, prior to step S1028, the method further includes: forming a gate dielectric layer on the inner wall (including sidewalls and bottom) of the buried word line trench, the gate dielectric layer comprising a silicon oxide layer, and depositing a barrier layer on the surface of the gate dielectric layer. First, the gate dielectric layer, also known as the gate oxide layer, is deposited in the buried word line trench, followed by the sequential deposition of the barrier layer and a conductive material layer.

[0092] In one embodiment, the gate dielectric layer includes a silicon nitride layer, the barrier layer includes a titanium nitride layer, the conductive material layer includes a tungsten conductive layer, and the isolation structure includes a silicon oxide structure. Figure 4 As shown, Figure 4 for Figure 3 The enlarged view of section A shows the deposition of silicon nitride sidewalls and bottom in a buried word line trench using atomic layer deposition (ALD) technology, forming a gate dielectric layer 401 (silicon oxide layer) within the trench. Then, titanium nitride is deposited on the surface (including side and bottom surfaces) of the gate dielectric layer 401 using ALD, covering it to form a barrier layer 402. The gate dielectric layer 401 surrounds the barrier layer 402. Next, a tungsten conductive layer 403 is deposited on the barrier layer 402, surrounding its sidewalls and bottom. The top surfaces of the gate dielectric layer 401, barrier layer 402, and tungsten conductive layer 403 are all flush with the top surface of the substrate.

[0093] In one feasible embodiment, the atomic layer deposition reaction gas used in the gate dielectric layer 401 may be NH3 or N2 / H2 mixed reaction gas; the atomic layer deposition reaction gas used in the barrier layer 402 may be LTO520 / O2 or Nzero / O2.

[0094] like Figure 5 As shown, in one embodiment, step S104 includes:

[0095] S1042, a first nitride layer is formed on the substrate surface, the first nitride layer is patterned, and a plurality of active region mask structures are arranged in parallel and spaced apart in the second direction.

[0096] A nitride layer is deposited on the substrate surface, for example, a silicon nitride layer, and the first nitride layer is patterned and etched, such as... Figure 5 As shown, the first nitride layer forms an active region mask structure 501 arranged in parallel intervals in the second direction. The active region mask structure 501 in the second direction simultaneously covers two rows (in the first direction) of buried gate structures.

[0097] S1044 uses the active region mask structure as an etching mask to etch away the exposed substrate, thereby cutting off the buried gate structure and forming several parallel spaced active structures and isolation trenches between the active structures.

[0098] The aforementioned active region mask structure 501 covers the substrate that needs to be retained, exposing the substrate that needs to be removed, such as... Figure 5 As shown, the substrate exposed by the active region mask structure 501 is etched away to obtain the active structure 502. The depth of the active structure 502 is greater than the depth of the buried gate structure 503, and the interconnecting regions between the active structures 502 form isolation trenches. Since the depth of the active structure 502 is greater than the depth of the buried gate structure 503, a path is formed outside the buried gate structure 503, connecting the source and drain regions on the left and right sides of the buried gate structure 503.

[0099] In one embodiment, step S1042 includes: forming a second mask layer on the top surface of the first nitride layer; patterning the second mask layer to form a strip-shaped mask in a second direction; using the second mask layer as an etching mask to etch away the exposed first nitride layer, thereby forming a strip-shaped structure in the second direction of the first nitride layer; cutting the strip-shaped mask in the second direction into island-shaped masks of a predetermined length; using the island-shaped masks as etching masks to etch away the exposed first nitride layer, thereby forming a plurality of parallel and spaced active region mask structures in the first nitride layer. For example, the first nitride layer may be a silicon nitride layer.

[0100] A second mask layer is deposited above the first nitride layer, such as Figure 6 As shown, the second mask layer is patterned and etched to form a strip mask 601 in the second direction. The strip mask 601 exposes the first nitride layer that needs to be removed. Using the strip mask 601 formed by the second mask layer as an etching mask, the exposed first nitride layer is etched and removed, and the first nitride layer forms a strip structure 602 in the second direction.

[0101] like Figures 7a-7cAs shown, the strip mask 601 is patterned and etched twice to cut and form several parallel and spaced island masks 701. The island masks 701 are used as etching masks to etch and remove the exposed first nitride layer, so that the strip structure 602 formed by the first nitride layer has several parallel and spaced active region mask structures 501. As shown in the figure, each active region mask structure 501 in the second direction covers two rows (in the first direction) of buried gate structures 503.

[0102] like Figure 8 As shown, in one embodiment, step S106 includes:

[0103] S1062, chemical vapor deposition process is performed to form an isolation structure in the isolation tank.

[0104] superior Figure 5 An isolation trench is formed by connecting regions between active structures 502. Silicon oxide material is filled into the isolation trench as an isolation material by chemical vapor deposition. The active region mask structure 501 on the top surface of the active structure 502 is removed, and the isolation material forms an isolation structure 801 in the isolation trench.

[0105] S1064, flatten the top surfaces of the isolation structure 801 and the active structure 502 so that the top surface of the isolation structure 801 is flush with the top surface of the active structure 502.

[0106] The top surface of the isolation structure 801 is planarized by chemical polishing process, so that the top surface of the isolation structure 801 and the top surface of the active structure 502 are on the same horizontal plane.

[0107] In one embodiment, step S108 includes:

[0108] S1082, a conductive layer is formed on the top surface of the isolation structure 801 and the active structure 502.

[0109] like Figure 9a As shown, a conductive layer 901 is deposited on the top surface of the isolation structure 801 and the active structure 502. This conductive layer may be a tungsten metal layer.

[0110] S1084, a patterned conductive layer is formed to create a plurality of conductive character lines in a first direction and a second trench between the conductive character lines.

[0111] In one embodiment, a second nitride layer 902 (silicon nitride layer) is formed on the top surface of the conductive layer 901; the second nitride layer 902 is patterned to expose a portion of the conductive layer 901. A photoresist layer is covered on the top surface of the second nitride layer 902, and the photoresist layer above the second nitride layer 902 is patterned and etched to obtain a strip mask structure 903, such as... Figure 9aAs shown, using a strip-shaped mask structure 903 as an etching mask, the second nitride layer 902 is patterned and etched to expose a portion of the conductive layer. The aforementioned photoresist layer can be a photosensitive, corrosion-resistant coating material composed of photosensitive resin, sensitizer, and solvent.

[0112] Remove the strip mask structure 903, and use the second nitride layer 902 as an etching mask to etch away the exposed conductive layer, such as... Figure 9b As shown, several conductive word lines 904 in a first direction and second trenches 905 between the conductive word lines are formed. The strip mask structure 903 and... Figure 2 The word line structure 202 in the middle is in the same position and orientation as the substrate, so that the formed conductive word line exactly covers the middle position of the word line trench.

[0113] like Figure 9c As shown, Figure 9c for Figure 9b In the top view, the width of the conductive word line 904 is smaller than the width of the buried gate structure 503 in the active structure. The conductive word line 904 electrically connects the lower buried gate structures 503 in the same row. By covering the buried gate structures in the active structure with the conductive word line 904, noise or interference to the buried gates in adjacent rows is avoided when a row of buried gates is activated or repeatedly refreshed, thus reducing the hammering effect.

[0114] like Figure 10 As shown, in one embodiment, the fabrication method of the above-mentioned memory device further includes: forming an isolation layer 100, wherein the isolation layer 100 fills the second trench 905 and covers the conductive word line 904. The isolation layer 100 is deposited on the top surface of the conductive word line 904 using low-pressure chemical vapor deposition. In a feasible embodiment, the isolation layer 100 may be a silicon nitride layer, and the reactive gas for low-pressure chemical vapor deposition may be SiH4 or SiH2Cl2.

[0115] In one feasible implementation, the above etching process can be dry etching, and the etching gas can be SF6, CF4, Cl2, CHF3, O2, Ar or a mixture of gases.

[0116] This application also provides a storage device manufactured by any of the above-described preparation methods, such as... Figures 9b-9c As shown, the memory device includes: a substrate 201, and a plurality of buried gate structures 503, an isolation structure 801, a plurality of active structures 502 arranged in parallel and spaced apart in a second direction, and a plurality of conductive word lines 904 in a first direction formed on the substrate.

[0117] The active structure 502 is an island-shaped column, and the isolation structure 801 is located in the isolation groove between the active structures. The surfaces of the active structure 502 and the isolation structure 801 are flush.

[0118] The buried gate structure 503 is located in the active structure, and the surface of the buried gate structure 503 is flush with the surface of the active structure 502.

[0119] The conductive word line 904 contacts the top surface of the embedded word line structure 503 and the isolation structure 801, and the embedded gate structure 503 arranged along the first direction is electrically connected on the top surface of the isolation structure 801.

[0120] In one embodiment, the buried gate structure includes a buried word line trench and a conductive material layer, the conductive material layer filling the buried word line trench, such as... Figure 9c As shown, the width of the embedded character line groove is greater than or equal to the width of the conductive character line.

[0121] In one implementation, such as Figure 4 As shown, the memory device includes a gate dielectric layer 401 and a barrier layer 402. The gate dielectric layer 401 is formed on the inner wall and bottom of an embedded word line trench, and the barrier layer 402 is formed on the surface of the gate dielectric layer 401, such that the gate dielectric layer 401 surrounds the barrier layer 402. In one feasible embodiment, the gate dielectric layer 401 may be a silicon oxide layer, and the barrier layer 402 may be a titanium nitride layer.

[0122] In one embodiment, the bottoms of the aforementioned buried gate structures are flush. Since the buried word line trenches are first etched on the substrate, the bottoms of the buried gate structures are on the same horizontal plane, that is, the word line trenches forming the buried gate structures have the same depth in the substrate (in the prior art, the active structure and isolation structure are first formed on the substrate, and then the word line trenches are etched. Due to the difference in etching rate, the etched word line trenches are easily uneven, which in turn makes the bottom of the buried gate structure uneven).

[0123] In one embodiment, the memory device further includes an isolation layer 100 formed on the conductive word lines 904 and filling the second trench 905 between the conductive word lines 904.

[0124] This application also provides a storage device, which includes the above-described storage device.

[0125] It should be understood that, although Figure 1The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figure 1 At least some of the steps in the process may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but may be executed at different times. The execution order of these steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least some of the steps or stages in other steps.

[0126] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0127] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A method for manufacturing a storage device, characterized in that, include: Several buried gate structures in a first orientation are formed on the substrate; A first nitride layer is formed on the substrate surface, and the first nitride layer is patterned to form a plurality of active region mask structures arranged in parallel and spaced apart in a second direction. Using the active region mask structure as an etching mask, the exposed substrate is etched away to cut off the buried gate structure, forming a plurality of parallel spaced active structures and isolation trenches between the active structures; wherein, the depth of the active structure is greater than the depth of the buried gate structure; wherein, the active structure is an island-shaped columnar body, and the active structure includes the buried gate structure. An isolation structure is formed in the isolation groove, and the surface of the isolation structure is flush with the surface of the active structure. A plurality of conductive word lines in a first direction are formed on the surfaces of the isolation structure and the active structure, and the conductive word lines cover the upper surface of the buried gate structure in the active structure.

2. The method for fabricating the storage device according to claim 1, characterized in that, The step of forming a plurality of buried gate structures in a first orientation on the substrate includes: A first mask layer is formed on the substrate surface; The first mask layer is patterned to form a plurality of first trenches in a first direction that expose the surface of the substrate; Using the first mask layer as an etching mask, a portion of the substrate under the first trench is etched away to form a plurality of buried word line trenches in the first direction. A conductive material layer is filled into the buried word line trench, so that the upper surface of the conductive material layer is flush with the upper surface of the substrate, forming a buried gate structure.

3. The method for manufacturing the storage device according to claim 1, characterized in that, The step of patterning the first nitride layer includes: A second mask layer is formed on the top surface of the first nitrided layer; The second mask layer is patterned to form a strip-shaped mask in the second direction. The second mask layer is used as an etching mask to etch away the exposed first nitride layer, so that the first nitride layer forms a strip-shaped structure in the second direction. The strip mask in the second direction is cut into island-shaped masks of a preset length. The island-shaped mask is used as an etching mask to etch away the exposed first nitride layer, so that the first nitride layer forms a number of parallel and spaced active region mask structures.

4. The method for manufacturing the storage device according to claim 1, characterized in that, The step of forming an isolation structure in the isolation groove, wherein the surface of the isolation structure is flush with the surface of the active structure, includes: A chemical vapor deposition process is performed to form an isolation structure in the isolation tank; The top surfaces of the isolation structure and the active structure are leveled so that the top surface of the isolation structure is flush with the top surface of the active structure.

5. The method for manufacturing the storage device according to claim 1, characterized in that, The step of forming a plurality of conductive word lines in a first direction on the surfaces of the isolation structure and the active structure includes: A conductive layer is formed on the top surface of the isolation structure and the active structure; The conductive layer is patterned to form a plurality of conductive word lines in a first direction and a second trench between the conductive word lines.

6. The method for manufacturing the storage device according to claim 5, characterized in that, The step of patterning the conductive layer to form a plurality of conductive word lines in a first direction and a second trench between the conductive word lines includes: A second nitride layer is formed on the top surface of the conductive layer; The second nitride layer is patterned to expose a portion of the conductive layer; Using the second nitride layer as an etching mask, the exposed conductive layer is etched away to form a plurality of conductive word lines in a first direction and a second trench between the conductive word lines.

7. The method for manufacturing the storage device according to claim 5, characterized in that, Also includes: An isolation layer is formed, which fills the second trench and covers the conductive word line.

8. The method for manufacturing the storage device according to claim 2, characterized in that, Before filling the embedded word line trench with a conductive material layer, the method further includes forming a gate dielectric layer on the inner wall of the embedded word line trench.

9. The method for manufacturing the storage device according to claim 8, characterized in that, The gate dielectric layer includes a silicon oxide layer, the conductive material layer includes a tungsten conductive layer, and the isolation structure includes a silicon oxide structure.

10. A storage device, characterized in that, The memory device is fabricated using the fabrication method of any one of claims 1-9. The memory device includes: a substrate, and a plurality of buried gate structures, an isolation structure, a plurality of active structures arranged in parallel and spaced apart in a second direction, and a plurality of conductive word lines in a first direction formed on the substrate. The active structure is in the form of an island-shaped column, and the isolation structure is located in the isolation groove between the active structures, with the surface of the active structure flush with that of the isolation structure; The buried gate structure is located in the active structure, and the surface of the buried gate structure is flush with the surface of the active structure. The conductive word line contacts the top surface of the buried gate structure and the isolation structure, and the buried gate structure arranged along the first direction is electrically connected on the top surface of the isolation structure.

11. The storage device according to claim 10, characterized in that, The buried gate structure includes a buried word line trench and a conductive material layer. The conductive material layer is filled in the buried word line trench, and the width of the buried word line trench is greater than or equal to the width of the conductive word line.

12. The storage device according to claim 11, characterized in that, The storage device includes a gate dielectric layer and a barrier layer, the gate dielectric layer being formed on the inner wall of an embedded word line trench, and the barrier layer being formed on the surface of the gate dielectric layer.

13. The storage device according to claim 10, characterized in that, The bottoms of the plurality of buried gate structures are flush.

14. The storage device according to claim 10, characterized in that, It also includes an isolation layer formed on the conductive word lines and filling the spaces between the conductive word lines.

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