Resistive random access memory element, memory device, and method of manufacturing the same

Abstract

The application provides a resistive random access memory element, a memory device and a preparation method thereof. The memory element comprises a first electrode, a resistance change memory layer and a second electrode arranged in sequence. The material of the second electrode is MNx, and the material of the resistance change memory layer is MOy, wherein M is selected from one of Ti, Ta and Al. The metal atoms of the second electrode and the metal atoms of the resistance change memory layer are set as the same metal element, and the conductive channel formed thereby has the same metal atoms, which can effectively avoid the M metal atoms participating in the formation of the conductive channel from being excessively rich, thereby improving the service life and durability of the device, improving the retention capability of the device, and further obtaining better device performance. By controlling the proportion of N in the second electrode, the second electrode can have conductivity, and the migration and diffusion of metal ions into the resistance change memory layer have higher controllability.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor integrated circuit design and manufacturing, and in particular relates to a resistive random access memory element, a memory device and its preparation method. Background Technology

[0002] Resistive random-access memory (ReRAM) is a type of non-volatile memory (NVM) that has gained increasing attention in the field due to its smaller size, faster read / write speeds, longer data retention times, lower power consumption, higher reliability, and compatibility with semiconductor fabrication processes. The basic structure of ReRAM consists of a variable resistor layer sandwiched between upper and lower electrodes. An applied voltage causes the variable resistor material to switch between a high resistance state (HRS) and a low resistance state (LRS), and these different resistance states are then encoded as 1 or 0 to store and identify data.

[0003] Current resistive random access memory (ReRAM) is mainly divided into conductive-bridge random access memory (CBRAM) and oxide-vacancy random access memory (OxRAM). Its structure primarily consists of three parts: a top electrode (TE), a resistive switching layer (SL), and a bottom electrode (BE). In OxRAM, oxygen ions in the resistive switching layer (SL) migrate under the influence of an electric field, eventually forming conductive channels (filaments) composed of oxygen vacancies. In conductive-bridge random access memory, metal in one electrode is ionized under the influence of an electric field and enters the resistive switching layer (SL), ultimately forming conductive channels composed of metal particles. Existing resistive random access memory devices often face various reliability issues; for example, their cycle characteristics and retention capabilities are limited by the materials used.

[0004] It should be noted that the above introduction to the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of this application and facilitating understanding by those skilled in the art. It should not be assumed that these technical solutions are known to those skilled in the art simply because they have been described in the background section of this application. Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a resistive random access memory element, a memory device and a method for manufacturing the same, so as to solve the problem of insufficient reliability of resistive random access memory in the prior art.

[0006] To achieve the above and other related objectives, the present invention provides a resistive random access memory element, the resistive random access memory element comprising: a first electrode, a resistive switching memory layer and a second electrode arranged in sequence; the material of the second electrode is MNx, wherein M is selected from Ti, Ta and Al, and 0≤x≤1.

[0007] Optionally, the second electrode MNx includes n second sub-electrode layers, n≥2, and the proportion of N in the n second sub-electrode layers decreases layer by layer from the resistive switching memory layer away from the resistive switching memory layer.

[0008] Optionally, the difference in N ratio x between two adjacent second sub-electrode layers is greater than or equal to 0.05.

[0009] Optionally, among the n second sub-electrode layers, the thickness of the second sub-electrode layer with the largest N-proportion x is less than or equal to 5 nanometers.

[0010] Optionally, in the n second sub-electrode layers, the thickness of the second sub-electrode layer increases as its N-proportion x decreases.

[0011] Optionally, the N-ratio x in the second electrode MNx decreases linearly from the resistive switching memory layer toward the direction away from the resistive switching memory layer.

[0012] Optionally, the proportion of N in the second electrode MNx is greater than or equal to 0.3 and less than or equal to the stoichiometric ratio of M and N.

[0013] Optionally, the material of the resistive switching memory layer is MOy, and the metal atoms in the resistive switching memory layer MOy are the same as the metal atoms in the second electrode MNx, wherein M is selected from Ti, Ta and Al, and 0≤y≤1.

[0014] Optionally, the metal atoms of the conductive channel of the resistive random access memory element are M, which are the same as the metal atoms in the second electrode MNx and the resistive switching memory layer MOy. The metal atoms M migrate to the second electrode and the resistive switching memory layer to form conductive channels composed of metal atoms M, so that the resistive switching memory layer is transformed into a low-resistance state, or / and the O in the resistive switching memory layer migrates to form conductive channels formed by oxygen holes in the resistive switching memory layer, so that the resistive switching memory layer is transformed into a low-resistance state.

[0015] Optionally, the material of the first electrode is an inert metal or a metal nitride, wherein the inert metal includes one of W and Pt, and the metal nitride includes one of TiN and TaN.

[0016] Optionally, the sidewalls of the first electrode, the resistive switching storage layer, and the second electrode are further formed with sidewall structures.

[0017] Optionally, the resistive random access memory element further includes: an interlayer dielectric layer disposed on the second electrode; an electrode hole structure exposing the second electrode is formed in the interlayer dielectric layer, the electrode hole structure including a damascus structure; the electrode hole structure is filled with a metal electrode, the metal atom M in the metal electrode being the same as the metal atom in the second electrode MNx.

[0018] The present invention also provides a resistive random access memory device, the resistive random access memory device comprising an array of a plurality of resistive random access memory elements as described in any of the above embodiments.

[0019] The present invention also provides a method for fabricating a resistive random access memory element, the method comprising the steps of: forming a first electrode, a resistive switching memory layer and a second electrode arranged in sequence, wherein the material of the second electrode is MNx, wherein M is selected from Ti, Ta and Al, and 0≤x≤1.

[0020] Optionally, forming the second electrode includes: growing n second sub-electrode layers layer by layer on the resistive switching memory layer by a deposition method, and controlling the proportion of N in each second sub-electrode layer such that the proportion x of N in the n second sub-electrode layers decreases layer by layer from the resistive switching memory layer away from the resistive switching memory layer.

[0021] Optionally, forming the second electrode includes: growing n second sub-electrode layers layer by layer on the resistive switching memory layer by deposition, controlling the proportion of N in each second sub-electrode layer such that the proportion x of N in the n second sub-electrode layers decreases layer by layer from the resistive switching memory layer away from the resistive switching memory layer; and performing an annealing process in an N atmosphere to diffuse N in the second sub-electrode layers such that the proportion x of N in the second electrode MNx decreases linearly from the resistive switching memory layer away from the resistive switching memory layer.

[0022] Optionally, the proportion of N in each of the second sub-electrode layers can be adjusted by controlling the ambient atmosphere, power, and bias voltage during the deposition process.

[0023] Optionally, the preparation method further includes the step of forming a sidewall structure on the sidewalls of the first electrode, the resistive switching memory layer, and the second electrode.

[0024] Optionally, the preparation method further includes the steps of: forming an interlayer dielectric layer on the second electrode; forming an electrode pore structure in the interlayer dielectric layer to expose the second electrode, the electrode pore structure including a damascus structure; and forming a metal electrode in the electrode pore structure, wherein the metal atoms in the metal electrode are M and are the same as the metal atoms in the second electrode MNx and the resistive switching memory layer MOy.

[0025] Optionally, forming the resistive switching memory layer includes: growing multiple MOy material layers layer by layer by deposition method, and adjusting the proportion of O in each MOy material layer by controlling the ambient atmosphere, power and bias voltage during the deposition process.

[0026] As described above, the resistive random access memory element and its fabrication method of the present invention have the following beneficial effects:

[0027] In this invention, the material of the second electrode is set to MNx, and the material of the resistive switching memory layer is set to MOy. The metal atoms of the second electrode and the metal atoms of the resistive switching memory layer are set to be the same metal atoms, and at the same time, they have the same metal atoms as the conductive channel. This can effectively avoid the excessive enrichment of M metal atoms participating in the formation of the conductive channel, thereby improving the device's lifespan and durability, and improving the device's retention capability, thus obtaining better device performance.

[0028] By controlling the N ratio in the second electrode MNx, this invention enables the second electrode to be conductive while also providing greater controllability for the migration and diffusion of metal ions into the resistive switching memory layer.

[0029] The fabrication process of this invention allows for control of the N ratio in the second electrode MNx to meet different requirements, facilitating adjustments to device performance and providing greater controllability. Attached Figure Description

[0030] The accompanying drawings, which form part of this specification, are used to provide a further understanding of the embodiments of this application and to illustrate the implementation of this application, together with the textual description, to explain the principles of this application. Obviously, the drawings described below are merely some embodiments of this application.

[0031] Figure 1 The diagram shown is a structural schematic of a resistive random access memory element according to an embodiment of the present invention.

[0032] Figure 2 The diagram shown is a structural schematic of another resistive random access memory element according to an embodiment of the present invention.

[0033] Figures 3 to 11 The diagram shows the structural schematics of each step in the fabrication method of the resistive random access memory element according to an embodiment of the present invention.

[0034] Figure 12 The diagram shows the cyclic characteristics of the resistive random access memory element implemented in this invention.

[0035] Figure 13 The diagram shows the cyclic characteristics of a resistive random access memory element implemented using conventional methods.

[0036] Component designation explanation

[0037] 101 First Electrode

[0038] 102 Resistive Switching Memory Layer

[0039] 103, 104 Second Electrode

[0040] 1031, 1032, 1033 Second Sub-Electrode Layer

[0041] 201 metal layer

[0042] 202 Interlayer Dielectric Layer

[0043] 203 Conductive Hole

[0044] 105 Sidewall Structure

[0045] 106 Insulation Layer

[0046] 107 Electrode Hole Structure Detailed Implementation

[0047] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0048] It should be emphasized that the term "including / comprises" as used herein refers to the presence of a feature, whole, step, or component, but does not exclude the presence or addition of one or more other features, wholes, steps, or components.

[0049] Features described and / or illustrated for one embodiment may be used in the same or similar manner in one or more other embodiments, combined with features in other embodiments, or substituted for features in other embodiments.

[0050] In the detailed description of embodiments of the present invention, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged and not to scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. In actual fabrication, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0051] For ease of description, spatial relation terms such as “below,” “under,” “lower than,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include directions other than those depicted in the drawings for devices in use or operation. Furthermore, when a layer is referred to as being “between” two layers, it may be the only layer between the two layers, or there may be one or more layers in between.

[0052] In the context of this application, the structure described above the first feature may include embodiments in which the first and second features are formed in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0053] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0054] like Figure 1As shown, this embodiment provides a resistive random access memory (RAM) element, which includes a first electrode 101, a resistive switching memory layer 102, and a second electrode 103 arranged sequentially. The material of the second electrode 103 is MNx (metal nitride), and the material of the resistive switching memory layer 102 is MOy (metal oxide), wherein M is selected from Ti (titanium), Ta (tantalum), and Al (aluminum), and 0≤x≤1, 0≤y≤1. For example, the material of the second electrode 103 can be TiNx, and the material of the resistive switching memory layer 102 can be TiOy; or, the material of the second electrode 103 can be TaNx, and the material of the resistive switching memory layer 102 can be TaOy; or, the material of the second electrode 103 can be AlNx, and the material of the resistive switching memory layer 102 can be AlOy. In this invention, the material of the second electrode 103 is set to MNx, and the material of the resistive switching memory layer 102 is set to MOy. The metal atoms of the second electrode 103 and the metal atoms of the resistive switching memory layer 102 are set to the same metal atoms, and at the same time, they have the same metal atoms as the conductive channel formed. This can effectively avoid the excessive enrichment of M metal atoms participating in the formation of the conductive channel, thereby improving the device's lifespan and durability, and improving the device's retention capability, thus obtaining better device performance.

[0055] In one embodiment, the material of the first electrode 101 is an inert metal or a metal nitride. Specifically, the inert metal can be one of W and Pt, and the metal nitride can be one of TiN and TaN.

[0056] In one embodiment, the second electrode 103 includes n second sub-electrode layers 1031, 1032, 1033, where n ≥ 2, and the N (nitrogen) ratio x in the n second sub-electrode layers 1031, 1032, 1033 decreases layer by layer from the resistive switching memory layer 102 toward the direction away from the resistive switching memory layer 102.

[0057] like Figure 1 As shown, in a specific example, the second electrode 103 includes three second sub-electrode layers 1031, 1032, and 1033. The ratio of N in the three second sub-electrode layers 1031, 1032, and 1033 can be x1, x2, and x3, respectively. x1, x2, and x3 decrease layer by layer from the resistive switching memory layer 102 away from the resistive switching memory layer 102, i.e., x1 > x2 > x3.

[0058] In one embodiment, the N ratio x in the second electrode 103 is greater than or equal to 0.3 to ensure that it has a good control effect on the migration and diffusion of metal ions into the resistive switching memory layer 102, and the N ratio x is less than or equal to the stoichiometric ratio of M and N to avoid the N ratio being too high and affecting the structural stability and conductivity of the second electrode 103. The difference in the N ratio x in two adjacent second sub-electrode layers 1031, 1032, and 1033 is greater than or equal to 0.05 to form a better control effect on the migration and diffusion of metal ions through the N ratio gradient.

[0059] In a specific example, taking the second electrode 103 as AlNx, the stoichiometric ratio of Al to N is 1, and the N ratio x can range from 0.3 to 1. For example, in AlNx, the values ​​of x1, x2, and x3 can be 1, 0.8, and 0.6, respectively. That is, the materials of the three second sub-electrode layers 1031, 1032, and 1033 are AlN, AlN, and AlN, respectively. 0.8 AlN 0.6 Of course, the values ​​of x1, x2, and x3 can also be 0.8, 0.5, and 0.3, respectively, meaning the materials of the three second sub-electrode layers 1031, 1032, and 1033 are AlN. 0.8 AlN 0.5 and AlN 0.3 Of course, the value of N in each of the second sub-electrode layers 1031, 1032, and 1033 in the AlNx can be set according to the actual device requirements and is not limited to the examples listed above. In other embodiments, the material of the second electrode 103 can also be TiNx or TaNx, and its specific value can be set according to the parameter requirements of the device. The number of second sub-electrode layers 1031, 1032, and 1033 included in the second electrode 103 can also be set to a greater number of layers, such as 4 to 10 layers. By controlling the N ratio in the second electrode 103, this invention can achieve both conductivity of the second electrode 103 and higher controllability of the migration and diffusion of metal ions into the resistive switching memory layer 102.

[0060] In one embodiment, among the n second sub-electrode layers 1031, 1032, and 1033, the second sub-electrode layer 1031, 1032, and 1033 with the largest N-ratio x has a thickness of less than or equal to 5 nanometers, to ensure that subsequent metal atoms can pass through the second sub-electrode layer 1031, 1032, and 1033 with the largest N-ratio x to reach the resistive switching memory layer 102 and form a conductive channel. In another embodiment, among the n second sub-electrode layers 1031, 1032, and 1033, the thickness of the second sub-electrode layer 1031, 1032, and 1033 increases as its N-ratio x decreases.

[0061] In one embodiment, Figure 2 The diagram shows a schematic of another type of resistive random access memory element. Figure 2 In the resistive random access memory (RAM) element, the N-ratio x in the second electrode 104 decreases linearly from the resistive switching memory layer 102 toward the direction away from the resistive switching memory layer 102. This resistive RAM element eliminates the step-like layer-by-layer change of the N-ratio as in the above embodiment, and sets the N-ratio x to a linear change, which makes the migration and diffusion of metal atoms smoother and more controllable.

[0062] In one embodiment, the metal atoms of the conductive channel of the resistive random access memory element are M, which are the same as the metal atoms in the second electrode 103 and the resistive switching memory layer 102. The metal atoms M migrate to the second electrode 103 and the resistive switching memory layer 102 to form conductive channels composed of metal atoms M, so that the resistive switching memory layer 102 is transformed into a low-resistance state, or / and the O (oxygen) in the resistive switching memory layer 102 migrates to form conductive channels formed by oxygen holes in the resistive switching memory layer 102, so that the resistive switching memory layer 102 is transformed into a low-resistance state.

[0063] In one embodiment, see Figure 10 or Figure 11 The sidewalls of the first electrode, the resistive switching storage layer, and the second electrode may also be formed with sidewall structures 105.

[0064] In one embodiment, see Figure 10 or Figure 11 The resistive random access memory element may further include: an interlayer dielectric layer 106 disposed on the second electrode; an electrode hole structure exposing the second electrode is formed in the interlayer dielectric layer 106, the electrode hole structure including a damascus structure; and a metal electrode 107 filled in the electrode hole structure, wherein the metal atoms in the metal electrode 107 are M and the same as the metal atoms in the second electrode MNx.

[0065] This embodiment also provides a resistive random access memory device, which includes an array composed of a plurality of resistive random access memory elements as described in any of the above embodiments.

[0066] like Figures 3 to 11 As shown, this embodiment also provides a method for fabricating a resistive random access memory element. The fabrication method includes the steps of forming a first electrode 101, a resistive switching memory layer 102, and a second electrode 103 arranged sequentially. The material of the second electrode 103 is MNx, and the material of the resistive switching memory layer 102 is MOy. M is selected from Ti, Ta, and Al, and 0≤x≤1 and 0≤y≤1.

[0067] Specifically, the preparation method includes the following steps:

[0068] like Figure 3 As shown, step 1) is performed first, providing a circuit substrate, the substrate including a substrate, a metal layer 201 disposed on the substrate, an insulating layer 106 disposed on the metal layer 201, and a conductive hole 203 disposed in the insulating layer 106.

[0069] The substrate can be, for example, a silicon substrate, a germanium substrate, a germanium-silicon substrate, a III-V compound substrate, a silicon carbide substrate, an SOI substrate, etc. Various circuit elements, such as NMOS transistors, PMOS transistors, capacitors, resistors, etc., can be formed in the substrate to achieve corresponding circuit functions.

[0070] like Figure 4 As shown, then step 2) is performed, in which a first electrode 101 is formed on the circuit substrate by a deposition method. The material of the first electrode 101 is an inert metal or a metal nitride. Specifically, the inert metal can be one of W and Pt, and the metal nitride can be one of TiN and TaN.

[0071] like Figure 5 As shown, then step 3) is performed to form a resistive switching memory layer 102 on the first electrode 101. Specifically, multiple MOy material layers can be grown layer by layer by deposition method, and the proportion of O in each MOy material layer can be adjusted by controlling the ambient atmosphere, power and bias voltage during the deposition process.

[0072] like Figure 6 As shown, step 4) is then performed, in which the second electrode 103 is formed in the resistive switching memory layer 102.

[0073] In one embodiment, forming the second electrode 103 includes the following steps: growing n second sub-electrode layers 1031, 1032, and 1033 sequentially on the resistive switching memory layer 102 using a deposition method, and controlling the proportion of N in each of the n second sub-electrode layers 1031, 1032, and 1033 such that the proportion x of N in each of the n second sub-electrode layers 1031, 1032, and 1033 decreases sequentially from the resistive switching memory layer 102 away from it. Specifically, the proportion of N in each of the second sub-electrode layers 1031, 1032, and 1033 can be adjusted by controlling the ambient atmosphere, power, and bias voltage during the deposition process.

[0074] In another embodiment, forming the second electrode 104 includes: growing n second sub-electrode layers layer by layer on the resistive switching memory layer 102 by deposition; controlling the proportion of N in each second sub-electrode layer such that the proportion x of N in the n second sub-electrode layers decreases layer by layer from the resistive switching memory layer 102 away from the resistive switching memory layer 102; and performing an annealing process in an N atmosphere to diffuse N in the second sub-electrode layers such that the proportion x of N in the second electrode 104 decreases linearly from the resistive switching memory layer 102 away from the resistive switching memory layer 102, resulting in a device structure as shown below. Figure 11 As shown.

[0075] like Figure 7 As shown, step 5) is then performed to pattern the second electrode 103 and the resistive switching memory layer 102. Specifically, silicon nitride can be grown as a hard mask, and after patterning the silicon nitride using photolithography and etching, the second electrode 103 and the resistive switching memory layer 102 can be etched using silicon nitride as a mask to form the desired pattern.

[0076] like Figure 8 As shown, step 6) is then performed, forming a sidewall structure 105 on the sidewalls of the first electrode 101, the resistive switching memory layer 102, and the second electrode 103. Specifically, the sidewall structure 105 can be formed by a deposition method, after which the silicon nitride hard mask described above is removed.

[0077] like Figure 9 As shown, step 7) is then performed, in which an interlayer dielectric layer 202 is formed on the second electrode 103. The interlayer dielectric layer 202 may be, for example, silicon dioxide.

[0078] like Figure 10 As shown, step 8) is performed last, forming an electrode hole structure 107 in the interlayer dielectric layer 202 to expose the second electrode 103; a metal electrode is formed in the electrode hole structure 107, wherein the metal atoms in the metal electrode are M, which are the same as the metal atoms in the second electrode 103 and the resistive switching memory layer 102.

[0079] In one embodiment, the electrode hole structure 107 includes a damascus structure.

[0080] Figure 12 This is shown as the cyclic characteristics of the resistive random access memory element implemented in this invention. Figure 13 This displays the cyclic characteristics of a resistive random access memory element implemented using a conventional method. The dots represent the high resistance of the device, and the triangles represent the low resistance. From... Figure 12 and Figure 13 The comparison shows that Figure 12The resistive random access memory element implemented in this invention has more concentrated high and low resistance values, and in a 1000-cycle test, the resistive random access memory element implemented in this invention basically successfully completed 1000 cycles. Figure 13 Conventional methods for implementing resistive random access memory (RAM) devices often result in numerous cycle failures. Therefore, this invention can effectively improve device lifespan and durability, enhance retention capabilities, and ultimately achieve better device performance.

[0081] As described above, the resistive random access memory element, memory device, and fabrication method of the present invention have the following beneficial effects:

[0082] In this invention, the material of the second electrode is set to MNx, and the material of the resistive switching memory layer is set to MOy. The metal atoms of the second electrode and the metal atoms of the resistive switching memory layer are set to be the same metal atoms, and at the same time, they have the same metal atoms as the conductive channel. This can effectively avoid the excessive enrichment of M metal atoms participating in the formation of the conductive channel, thereby improving the device's lifespan and durability, and improving the device's retention capability, thus obtaining better device performance.

[0083] By controlling the N ratio in the second electrode, this invention enables the second electrode to be conductive while also providing greater controllability for the migration and diffusion of metal ions into the resistive switching memory layer.

[0084] The fabrication process of this invention allows for control of the N ratio in the second electrode to meet different requirements, facilitating adjustments to device performance and providing greater controllability.

[0085] Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0086] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A resistive random access memory element, characterized in that, The resistive random access memory element includes: The first electrode, the resistive switching memory layer, and the second electrode are arranged in sequence. The material of the second electrode is MNx, where M is selected from Ti, Ta and Al, and 0≤x≤1; The resistive switching memory layer is made of MOy, and the metal atoms in the MOy resistive switching memory layer are the same as the metal atoms in the second electrode MNx, wherein M is selected from Ti, Ta and Al, and 0≤y≤1; The second electrode MNx includes n second sub-electrode layers, n≥2, and the N-ratio x of the n second sub-electrode layers decreases layer by layer from the resistive switching memory layer away from the resistive switching memory layer. Among the n second sub-electrode layers, the thickness of the second sub-electrode layer increases as its N-ratio x decreases, and the range of x in the second electrode MNx is 0.3≤x≤1.

2. The resistive random access memory element according to claim 1, characterized in that: The difference in the N ratio x between two adjacent second sub-electrode layers is greater than or equal to 0.

05.

3. The resistive random access memory element according to claim 1, characterized in that: Among the n second sub-electrode layers, the second sub-electrode layer with the largest N-proportion x has a thickness of less than or equal to 5 nanometers.

4. The resistive random access memory element according to claim 1, characterized in that: The proportion of N in the second electrode MNx decreases linearly from the resistive switching memory layer toward the direction away from the resistive switching memory layer.

5. The resistive random access memory element according to claim 1, characterized in that: The conductive channel of the resistive random access memory element has metal atoms M, which are the same as those in the second electrode MNx and the resistive switching memory layer MOy. Metal atoms M migrate to the second electrode and the resistive switching memory layer to form conductive channels composed of metal atoms M, thereby causing the resistive switching memory layer to transition to a low-resistance state, or / and causing O in the resistive switching memory layer to migrate and form conductive channels formed by oxygen holes in the resistive switching memory layer. This causes the resistive switching memory layer to switch to a low-resistivity state.

6. The resistive random access memory element according to claim 1, characterized in that: The material of the first electrode is an inert metal or a metal nitride, wherein the inert metal includes one of W and Pt, and the metal nitride includes one of TiN and TaN.

7. The resistive random access memory element according to claim 1, characterized in that: The sidewalls of the first electrode, the resistive switching memory layer, and the second electrode are also formed with sidewall structures.

8. The resistive random access memory element according to claim 1, characterized in that: The resistive random access memory element further includes: an interlayer dielectric layer disposed on the second electrode; an electrode hole structure exposing the second electrode is formed in the interlayer dielectric layer, the electrode hole structure including a damascus structure; a metal electrode is filled in the electrode hole structure, the metal atom in the metal electrode being M and the same as the metal atom in the second electrode MNx.

9. A resistive random access memory device, characterized in that, The resistive random access memory device includes an array of multiple resistive random access memory elements as described in any one of claims 1 to 8.

10. A method for fabricating a resistive random access memory element as described in any one of claims 1 to 8, characterized in that, The preparation method includes the following steps: A first electrode, a resistive switching memory layer, and a second electrode are formed in sequence. The material of the second electrode is MNx, where M is selected from Ti, Ta, and Al, and 0 ≤ x ≤ 1. The material of the resistive switching memory layer is MOy, and the metal atoms in the MOy layer are the same as those in the MNx layer of the second electrode. M is selected from Ti, Ta, and Al, and 0 ≤ y ≤ 1. n second sub-electrode layers are grown layer by layer on the resistive switching memory layer by deposition. By controlling the proportion of N in each second sub-electrode layer, the proportion x of N in the n second sub-electrode layers decreases layer by layer from the resistive switching memory layer away from it. The thickness of the second sub-electrode layer increases as its proportion x decreases, and the range of x in the second electrode MNx is 0.3 ≤ x ≤ 1.

11. The method for fabricating a resistive random access memory element according to claim 10, characterized in that: Forming the second electrode includes: n second sub-electrode layers are grown layer by layer on the resistive switching memory layer by deposition method. By controlling the proportion of N in each second sub-electrode layer, the proportion x of N in the n second sub-electrode layers decreases layer by layer from the resistive switching memory layer away from the resistive switching memory layer. By performing an annealing process under an N atmosphere, N diffuses into the second sub-electrode layer, causing the N ratio x in the second electrode MNx to decrease linearly from the resistive switching memory layer toward the direction away from the resistive switching memory layer.

12. The method for fabricating a resistive random access memory element according to claim 10 or 11, characterized in that: The proportion of N in each of the second sub-electrode layers is adjusted by controlling the ambient atmosphere, power, and bias voltage during the deposition process.

13. The method for fabricating a resistive random access memory element according to claim 10, characterized in that: It also includes the step of forming a sidewall structure on the sidewalls of the first electrode, the resistive switching storage layer, and the second electrode.

14. The method for fabricating a resistive random access memory element according to claim 10, characterized in that: It also includes the following steps: An interlayer dielectric layer is formed on the second electrode; An electrode hole structure is formed in the interlayer dielectric layer to expose the second electrode, the electrode hole structure including a damascus structure; A metal electrode is formed in the electrode hole structure, and the metal atom M in the metal electrode is the same as the metal atom in the second electrode MNx and the resistive switching memory layer MOy.

15. The method for fabricating a resistive random access memory element according to claim 10, characterized in that: Forming the resistive switching memory layer includes: Multilayer MOy material layers were grown layer by layer by deposition, and the proportion of O in each MOy material layer was adjusted by controlling the ambient atmosphere, power and bias voltage during the deposition process.

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