Optical node apparatus

Abstract

An optical node device has a liquid crystal display device. Each pixel has a first transistor connected between a positive polarity pixel data line and a first holding capacitor, a gate supplied with a row scan signal; a second transistor connected between a negative polarity pixel data line and a second holding capacitor, a gate supplied with the row scan signal; a fifth transistor connected between a first source follower circuit inputting a voltage of the first holding capacitor and a pixel electrode, a gate supplied with a first control signal; and a sixth transistor connected between a second source follower circuit inputting a voltage of the second holding capacitor and the pixel electrode, a gate supplied with a second control signal turned on alternately with the first control signal. Threshold voltages of the fifth transistor and the sixth transistor are different from threshold voltages of other transistors of the first conductivity type.

Description

TECHNICAL FIELD

[0001] The present application relates to an optical node device. BACKGROUND

[0002] Optical networks are used to support modern demands regarding high-speed and large-capacity electric communication. These networks generally use a technology known as optical wavelength division multiplexing (WDM) to utilize as much of the optical spectrum as possible.

[0003] In many optical networks, an optical node device corresponding to a branching point of an optical network is used. Generally, in the optical node device, it is desirable to use a reconfigurable optical add / drop multiplexer (ROADM) device having a reconfigurable add / drop function.

[0004] In order to realize a ROADM system, a wavelength selective switch (WSS) can be used for routing of arbitrary wavelength channels. In the WSS, an optical beam deflection device such as a spatial light modulator can also be used to select a wavelength for deflection to a desired output port. Currently, a WSS employing a spatial light modulator using a reflective liquid crystal display device is used.

[0005] Prior Art Documents

[0006] Patent Documents

[0007] Patent Document 1: Japanese Patent No. 5549614;

[0008] Patent Document 2: Japanese Patent Application Laid-Open No. 2009-223289. SUMMARY

[0009] In the WSS employing a spatial light modulator using the above-described reflective liquid crystal display device, by expanding the dynamic range of the reflective liquid crystal display device, it is possible to improve the S / N ratio of an optical signal, and in addition, it is possible to increase the number of channels.

[0010] In view of the above-described problems, an object of the present embodiment is to provide an optical node device capable of expanding a dynamic range.

[0011] As an optical node device, an optical node device according to one embodiment of the present embodiment has:

[0012] a liquid crystal display device;

[0013] an input / output section having an input port that causes incident light to be incident and an output port that emits output light corresponding to each wavelength included in the incident light;

[0014] a dispersion element that spatially disperses light of each wavelength included in the incident light according to each wavelength and emits the output light toward the input / output section; and

[0015] a lens that condenses light of each wavelength dispersed by the dispersion element onto the surface of the liquid crystal display device, and emits light of each wavelength reflected by the liquid crystal display device toward the dispersion element side,

[0016] the liquid crystal display device has a plurality of pixels provided in a cross portion where a plurality of pixel data lines each of which is a group of a positive polarity pixel data line supplied with a positive polarity pixel signal and a negative polarity pixel data line supplied with a negative polarity pixel signal and a plurality of row scan lines cross each other, each of the plurality of pixels including:

[0017] a display element having a liquid crystal layer interposed between a pixel electrode and a common electrode;

[0018] a first holding capacitor for holding the positive polarity pixel signal;

[0019] a first transistor having a source-drain path connected between the positive polarity pixel data line and the first holding capacitor and a gate supplied with the row scan signal;

[0020] a second holding capacitor for holding the negative polarity pixel signal;

[0021] a second transistor having a source-drain path connected between the negative polarity pixel data line and the second holding capacitor and a gate supplied with the row scan signal;

[0022] a first source follower circuit including a third transistor to which a voltage of the first holding capacitor is input to a gate;

[0023] a second source follower circuit including a fourth transistor to which a voltage of the second holding capacitor is input to a gate;

[0024] a fifth transistor having a source-drain path connected between an output terminal of the first source follower circuit and the pixel electrode and a gate supplied with a first control signal; and

[0025] a sixth transistor having a source-drain path connected between an output terminal of the second source follower circuit and the pixel electrode and a gate supplied with a second control signal turned on alternately with the first control signal,

[0026] wherein the first transistor and the second transistor, the fifth transistor and the sixth transistor are transistors of a first conductivity type, the third transistor and the fourth transistor are transistors of a second conductivity type, and light of each wavelength condensed by the lens is reflected toward a direction determined by a path.

[0027] An optical node device according to one embodiment includes:

[0028] a liquid crystal display device;

[0029] an input-output section having an input port that causes incident light to be incident and an output port that emits output light corresponding to each wavelength included in the incident light;

[0030] a dispersion element that disperses light of each wavelength included in the incident light in space according to each wavelength and emits the output light toward the input-output section; and

[0031] a lens that condenses light of each wavelength dispersed by the dispersion element onto a surface of the liquid crystal display device by each wavelength and emits light of each wavelength reflected by the liquid crystal display device toward the dispersion element,

[0032] The liquid crystal display device includes a plurality of pixels provided in a cross portion where a plurality of pixel data lines each of which is a group of a positive polarity pixel data line supplied with a positive polarity pixel signal and a negative polarity pixel data line supplied with a negative polarity pixel signal and a plurality of row scan lines cross each other, each of the plurality of pixels including:

[0033] a display element having a liquid crystal layer interposed between a pixel electrode and a common electrode;

[0034] a first hold capacitor for holding the positive polarity pixel signal;

[0035] a first transistor having a source-drain path connected between the positive polarity pixel data line and the first hold capacitor and a gate supplied with the row scan signal;

[0036] a second hold capacitor for holding the negative polarity pixel signal;

[0037] a second transistor having a source-drain path connected between the negative polarity pixel data line and the second hold capacitor and a gate supplied with the row scan signal;

[0038] a first source follower circuit including a third transistor to which a voltage of the first hold capacitor is input to a gate;

[0039] a second source follower circuit including a fourth transistor to which a voltage of the second hold capacitor is input to a gate;

[0040] a fifth transistor whose source-drain path is connected between the output terminal of the first source follower circuit and the pixel electrode and whose gate is supplied with a first control signal; and

[0041] a sixth transistor whose source-drain path is connected between the output terminal of the second source follower circuit and the pixel electrode and whose gate is supplied with a second control signal which is turned on alternately with the first control signal,

[0042] wherein the first transistor and the second transistor, the fifth transistor and the sixth transistor are transistors of a first conductivity type, the third transistor and the fourth transistor are transistors of a second conductivity type, the threshold voltages of the fifth transistor and the sixth transistor are different from the threshold voltage of a normal transistor of the first conductivity type, and light of each wavelength condensed by the lens is reflected in a direction determined by the routing for each wavelength.

[0043] As the optical node device, an optical node device according to one embodiment includes:

[0044] a liquid crystal display device;

[0045] an input-output section having an input port that causes incident light to be incident and an output port that emits emission light corresponding to each wavelength included in the incident light;

[0046] a dispersion element that disperses light of each wavelength included in the incident light in space according to each wavelength and emits the emission light toward the input-output section; and

[0047] a lens that condenses light of each wavelength dispersed by the dispersion element to a surface of the liquid crystal display device according to each wavelength and emits light of each wavelength reflected by the liquid crystal display device toward the dispersion element,

[0048] the liquid crystal display device has a plurality of pixels disposed at intersections of a plurality of pixel data lines each of which is a group of a positive polarity pixel data line supplied with a positive polarity pixel signal and a negative polarity pixel data line supplied with a negative polarity pixel signal and a plurality of row scan lines, and each of the plurality of pixels includes:

[0049] a display element having a liquid crystal layer interposed between a pixel electrode and a common electrode;

[0050] a first holding capacitor for holding the positive polarity pixel signal;

[0051] a first transistor whose source-drain path is connected between the positive polarity pixel data line and the first holding capacitor and whose gate is supplied with the row scan signal;

[0052] a second holding capacitor for holding the negative polarity pixel signal;

[0053] a second transistor whose source-drain path is connected between the negative polarity pixel data line and the second holding capacitor, and whose gate is supplied with the row scan signal;

[0054] a first source follower circuit including a third transistor to which the voltage of the first holding capacitor is input to the gate;

[0055] a second source follower circuit including a fourth transistor to which the voltage of the second holding capacitor is input to the gate;

[0056] a fifth transistor whose source-drain path is connected between the output terminal of the first source follower circuit and the pixel electrode, and whose gate is supplied with a first control signal; and

[0057] a sixth transistor whose source-drain path is connected between the output terminal of the second source follower circuit and the pixel electrode, and whose gate is supplied with a second control signal which is turned on alternately with the first control signal,

[0058] wherein the first and second transistors, the fifth and sixth transistors are transistors of a first conductivity type, the third and fourth transistors are transistors of a second conductivity type, the threshold voltages of the first, second, fifth and sixth transistors are different from the threshold voltage of a usual transistor of the first conductivity type, and light of each wavelength condensed by the lens is reflected in a direction determined by the passage route for each wavelength.

[0059] As an optical node device, an optical node device according to an embodiment of the present application includes:

[0060] a liquid crystal display device;

[0061] an input-output section having an input port that allows incident light to be incident and an output port that emits emission light corresponding to each wavelength included in the incident light;

[0062] a dispersion element that disperses light of each wavelength included in the incident light in space according to each wavelength and emits the emission light toward the input-output section; and

[0063] a lens that condenses light of each wavelength dispersed by the dispersion element to a surface of the liquid crystal display device according to each wavelength and emits light of each wavelength reflected by the liquid crystal display device toward the dispersion element,

[0064] The liquid crystal display device has a plurality of pixels provided in a crossing portion where a plurality of pixel data lines of a group in which a positive polarity pixel data line supplied with a positive polarity pixel signal and a negative polarity pixel data line supplied with a negative polarity pixel signal are grouped and a plurality of row scan lines cross each other, and each of the plurality of pixels includes:

[0065] A display element having a liquid crystal layer interposed between a pixel electrode and a common electrode;

[0066] A first holding capacitor for holding the positive polarity pixel signal;

[0067] A first transistor having a source-drain path connected between the positive polarity pixel data line and the first holding capacitor and a gate supplied with the row scan signal;

[0068] A second holding capacitor for holding the negative polarity pixel signal;

[0069] A second transistor having a source-drain path connected between the negative polarity pixel data line and the second holding capacitor and a gate supplied with the row scan signal;

[0070] A first source follower circuit including a third transistor to which a voltage of the first holding capacitor is input to a gate;

[0071] A second source follower circuit including a fourth transistor to which a voltage of the second holding capacitor is input to a gate;

[0072] A fifth transistor having a source-drain path connected between an output terminal of the first source follower circuit and the pixel electrode and a gate supplied with a first control signal; and

[0073] A sixth transistor having a source-drain path connected between an output terminal of the second source follower circuit and the pixel electrode and a gate supplied with a second control signal turned on alternately with the first control signal,

[0074] wherein the first transistor and the second transistor, the fifth transistor and the sixth transistor are transistors of a first conductivity type, the third transistor and the fourth transistor are transistors of a second conductivity type, threshold voltages of the third transistor and the fourth transistor are different from a threshold voltage of a usual transistor of the second conductivity type, threshold voltages of the fifth transistor and the sixth transistor are different from a threshold voltage of a usual transistor of the first conductivity type, and light of each wavelength condensed by the lens is reflected in a direction determined by a passing route for each wavelength.

[0075] According to the present embodiment, it is possible to expand the dynamic range. BRIEF DESCRIPTION OF DRAWINGS

[0076] Figure 1 FIG. 1 is a diagram showing the structure of a wavelength selective switch array according to the first embodiment.

[0077] Figure 2 FIG. 1 is a diagram showing the structure of a wavelength selective switch array according to the first embodiment.

[0078] Figure 3 FIG. 1 is a diagram showing the structure of a wavelength selective switch array according to the first embodiment.

[0079] Figure 4 FIG. 1 is a diagram showing the structure of a wavelength selective switch array according to the first embodiment.

[0080] Figure 5 FIG. 1 is a diagram showing the structure of a wavelength selective switch array according to the first embodiment.

[0081] Figure 6 FIG. 1 is a diagram showing the structure of a wavelength selective switch array according to the first embodiment.

[0082] Figure 7 FIG. 1 is a diagram showing the structure of a wavelength selective switch array according to the first embodiment.

[0083] Figure 8 FIG. 1 is a diagram showing the structure of a wavelength selective switch array according to the first embodiment.

[0084] Figure 9 FIG. 1 is a diagram showing the structure of a wavelength selective switch array according to the first embodiment.

[0085] Figure 10 FIG. 1 is a diagram showing the structure of a wavelength selective switch array according to the first embodiment.

[0086] Figure 11 FIG. 1 is a diagram showing the structure of a wavelength selective switch array according to the first embodiment.

[0087] Figure 12 FIG. 1 is a diagram showing the structure of a wavelength selective switch array according to the first embodiment.

[0088] Figure 13 FIG. 1 is a diagram showing the structure of a wavelength selective switch array according to the first embodiment.

[0089] Figure 14 FIG. 1 is a diagram showing the structure of a wavelength selective switch array according to the first embodiment.

[0090] Figure 15 Graphs showing the relationship between input voltage and output voltage of pixels according to the comparative example and the fifth embodiment.

[0091] Figure 16 A diagram showing the structure of a pixel of a reflective liquid crystal display device according to a sixth embodiment.

[0092] Figure 17 Graphs showing the relationship between input voltage and output voltage of pixels according to the comparative example and the sixth embodiment.

[0093] Figure 18 FIG. 1 is a planar layout diagram of pixels in a reflective liquid crystal display device according to the seventh embodiment.

[0094] Figure 19 It is a cross-sectional view of a pixel of a reflective liquid crystal display device according to the seventh embodiment.

[0095] Figure 20 FIG. 1 is a planar layout diagram of pixels in a reflective liquid crystal display device according to an eighth embodiment.

[0096] Figure 21 FIG. 1 is a planar layout diagram of pixels in a reflective liquid crystal display device according to a ninth embodiment.

[0097] Figure 22 FIG. 1 is a planar layout diagram of pixels in a reflective liquid crystal display device according to a tenth embodiment. DETAILED DESCRIPTION

[0098] Hereinafter, this embodiment will be described in detail based on the accompanying drawings. In addition, this embodiment is not limited to the embodiment described below. In addition, the constituent elements in the following embodiments include elements that can be easily replaced by those skilled in the art, or substantially the same elements.

[0099] <First embodiment>

[0100] Figure 1 and Figure 2 This is a diagram showing the configuration of a wavelength selective switch (WSS) array according to the first embodiment. Figure 1 This is a diagram showing the WSS array 10 as viewed from a direction opposite to the x-axis direction. Figure 2 This is a diagram showing the WSS array 10 as viewed from a direction opposite to the y-axis direction.

[0101] The WSS array 10 corresponds to an example of an “optical node device” of the present disclosure.

[0102] The WSS array 10 of the present disclosure uses at least 2 WSSs in a single package. The WSS array 10 of the present disclosure does not require dedicated optical elements, and enables independent action of each WSS within the WSS array 10. In contrast, the optical elements can be largely shared among the respective WSS devices, and thus, cost reduction and downsizing can be achieved. Such a device is desirably suitable for use in modern communication networks, for example, as a reconfigurable optical add / drop multiplexer (ROADM). Further, an array having 1 or more coupled 2 WSSs can be desirably suitable for use as a constituent element within a branching node using a path and select (RS) architecture.

[0103] Referring to Figure 1 The WSS array 10 includes 2 independent WSS devices WSS1 and WSS2 that can act as respective independent WSS devices. In the present disclosure, the term "independent" refers to the function of the WSS device WSS1 that independently processes 1 or more WDM signals regardless of the WSS device WSS2, and vice versa. In the present disclosure, the term "process" is used broadly, and for example, includes modulating, attenuating, blocking, direction switching, and / or switching of each wavelength channel constituting each WDM signal.

[0104] The WSS array 10 includes an input / output section 11 and an optical system 12. The optical system 12 is configured to perform beam shaping of each WDM signal beam. In addition, the optical system 12 is configured to disperse (demultiplex) each WDM signal spectrum into wavelength channels (or groups of wavelength channels) constituting them. Further, the optical system 12 is configured to combine (multiplex) the dispersed wavelength channel (or group of wavelength channel) spectrum into 1 or more WDM signals. Also, the WSS array 10 includes a reflective liquid crystal display device 13. The reflective liquid crystal display device 13 is configured to optically process the dispersed wavelength channels, for example, in order to direction switch each wavelength channel along a prescribed path within the WSS array 10.

[0105] The reflective liquid crystal display device 13 corresponds to an example of the "liquid crystal display device" of the present disclosure. Regarding the reflective liquid crystal display device 13, detailed description will be made after the second embodiment.

[0106] The WSS array 10 is able to share the single optical system 12 and the reflective liquid crystal display device 13 between several WSS devices, in this case, WSS devices WSSl and WSS2, of the WSS array 10 by using an architecture that is symmetrical about the symmetry axis 14. However, the WSS devices WSSl and WSS2 are able to share most of the same optical components, while the architecture of the first embodiment is a device that enables independent control of the WSS devices WSSl and WSS2 of the WSS array 10. Therefore, the WSS array 10 of the first embodiment is miniaturized and the optical complexity is reduced. In addition to this, the WSS array 10 provides multiple WSS devices that retain the independent processing capabilities that are unique to larger and more costly devices.

[0107] In the present disclosure, the input-output section 11 can include several input ports and output ports for transferring one or more optical WDM signals. For example, the device can include several optical fibers, planar waveguides, etc., but any one of them can be assigned as an input port or an output port. In the first embodiment described below, the input ports or the output ports are installed as optical fibers 15. However, any other kind of port can be used without departing from the scope of the present invention.

[0108] The input-output section 11 includes an input-output section 11-1 for the WSS device WSSl. The input-output section 11-1 includes an input optical fiber 1 and several output optical fibers la, lb,..., ln. Here, n is a natural number. The input-output section 11 also includes an input-output section 11-2 for the WSS device WSS2. The input-output section 11-2 includes an input optical fiber 2 and several output optical fibers 2a, 2b,..., 2n. Here, n is a natural number. Therefore, Figure 1 An array of two 1 x N WSS devices including the WSS devices WSSl and WSS2 is shown as an example. In other words, the input-output section 11 of the WSS array 10 includes an array of the input optical fiber 1, the output optical fibers la, lb,..., ln, the input optical fiber 2, and the output optical fibers 2a, 2b,..., 2n that form a stack of optical fibers arranged in the y-axis direction.

[0109] The input-output section 11 also includes an array of collimating lenses 16 in the form of a microlens array. The array of collimating lenses 16 is arranged in front of the array of corresponding optical power elements, for example, the output section and / or input section of the optical fiber (z direction). In the present disclosure, the collimating lens 16 includes any optical element that guides and / or changes the direction of the light beam, and / or has the ability to focus a group of light rays. A first group including input optical fiber 1, output optical fiber 1a, 1b, ..., 1n is combined with a first group of paired collimating lenses 16 to form the input-output section 11-1 of the WSS device WSS1. A second group including input optical fiber 2, output optical fiber 2a, 2b, ..., 2n is combined with a second group of paired collimating lenses 16 to form the input-output section 11-2 of the WSS device WSS2. In Figure 1 In FIG. 1 , the WSS array 10 is shown mounted as a microlens array, but other types of WSS arrays can be used without departing from the scope of the present invention.

[0110] In the present disclosure, for example, the optical axes of the first group of optical fibers are shifted relative to the optical axes of the first group of collimating lenses 16. Due to this relative positional shift between the array of input and output ports and the array of collimating lenses 16, the first group of input and output beams are sent out in such a manner that they enter (or exit) the optical system 12 at an angle θ1 relative to the symmetry axis 14. Thus, the group of input and output beams from the WSS device WSS1 is sent out at an angle θ1 in a generally downward direction (opposite to the y-axis direction).

[0111] Similarly, the optical axis of the second group of optical fibers is shifted relative to the optical axis of the second group of collimating lenses 16. The second group of input beams and output beams are sent out so as to enter (or exit) the optical system 12 at an angle θ2 relative to the symmetry axis 14. Thus, the group of input beams and output beams from the WSS device WSS2 is sent out along an angle θ2 in the ascending direction (y-axis direction) as a whole.

[0112] As mentioned above, Figure 1 The illustrated example is a WSS array 10 using two 1×N WSSs, namely WSS devices WSS1 and WSS2. Figure 1 In the example shown, WSS device WSS1 includes a single input fiber 1 for inputting a WDM signal beam 31 into the device, and a single input fiber 2 for inputting a WDM signal beam 32 into the device. The input fiber / output fiber configuration shown here is merely illustrative and is not intended to limit the scope of the present invention. Rather, any useful input / output port combination may be used without departing from the scope of the present invention.

[0113] The WDM signal beam 31 is launched from the input fiber 1 towards the device, passes through the collimating lens 16 and proceeds in the y-z plane at an angle θ1through the optical system 12. Thereafter, the WDM signal beam 31 is incident on the lens 21 for shaping the WDM signal beam 31 into the x direction. In one example, the lens 21 can also be a cylindrical lens with the cylindrical axis extending along the y direction. Thus, when viewed from the viewpoint as Figure 1 indicated, the lens 21 does not affect the WDM signal beam 31.

[0114] After passing through the lens 21, the WDM signal beam 31 is incident on the lens 22. In the example as Figure 1 indicated, the lens 22 can also be a cylindrical lens with the cylindrical axis extending along the x direction. The action of the lens 22 is dependent on the reflective liquid crystal display device 13 positioned on the focal plane of the lens 22. Also, the center (cylindrical axis) of the lens 22 is located on the symmetry axis 14. Since the reflective liquid crystal display device 13 is positioned on the focal plane of the lens 22, any set of parallel rays entering the lens 22 is focused to the same height on the reflective liquid crystal display device 13. Conversely, any set of rays starting from the same height on the reflective liquid crystal display device 13 emerges from the lens 22 as a set of parallel rays.

[0115] For example, as Figure 1 indicated, any incident beam (e.g., the WDM signal beam 31) proceeding along the angle θ1is imparted by the lens 22 with a direction towards the position LC1in the y axis direction on the reflective liquid crystal display device 13. Conversely, the set of rays 41 starting from the position LC1on the reflective liquid crystal display device 13 exits the lens 22 as parallel rays proceeding at the same angle θ1, as Figure 1 indicated. Likewise, any incident beam (e.g., the WDM signal beam 32) proceeding along the angle θ2is imparted by the lens 22 with a direction towards the position LC2in the y axis direction on the reflective liquid crystal display device 13. Conversely, the set of rays 42 starting from the position LC2on the reflective liquid crystal display device 13 exits the lens 22 as parallel rays proceeding at the same angle θ2, as Figure 1 indicated.

[0116] If we go back to the propagation of the WDM signal beam 31 through the optical system 12, after passing through the lens 22, as Figure 1 and Figure 2 indicated, the WDM signal beam 31 passes through the dispersive element 24 which angularly disperses the wavelength channels of the WDM signal beam 31. In the present disclosure, the dispersive element 24 can be a transmission type optical component such as a diffraction grating, a prism, etc.

[0117] The dispersed wavelength channels, after passing through the dispersive element 24, as Figure 1 andFigure 2 As shown, the lens 23 collects the dispersed wavelength channels onto the surface of the reflective liquid crystal display device 13 for each wavelength channel. In the present disclosure, the lens 23 may also be a cylindrical lens.

[0118] The reflective liquid crystal display device 13 is a two-dimensional pixelated optical element, such as a pixelated spatial light modulator. As described in more detail below, the two-dimensional pixelated optical element is capable of reflecting or redirecting one or more of the dispersed wavelength channels so that the one or more dispersed wavelength channels are routed to any one of the output optical fibers.

[0119] Regarding the WSS device WSS1, according to the present disclosure, since it has the lens 22, all the light rays starting from the position LC1 on the reflective liquid crystal display device 13 are as follows. Figure 1 As shown, the light rays are output from lens 22 along angle θ1. However, all light rays originating from position LC1 on reflective liquid crystal display device 13 are shifted relative to each other by only an amount corresponding to the deflection angle from reflective liquid crystal display device 13. Therefore, with an appropriate setting of the deflection angle, the reflected output light rays can be routed to any of output fibers 1a, 1b, ..., 1n. Here, the reflected output light rays are, for example, reflected output light rays corresponding to a group of one or more light rays 41, each of which can contain one or more wavelength channels of WDM signal beam 31. Furthermore, in the present disclosure, since each of collimating lenses 16 is shifted by the same amount relative to its corresponding output fiber, the respective output beams can be recombined to the respective output fibers with improved efficiency.

[0120] Similarly, regarding the WSS device WSS2, according to the present disclosure, since it has the lens 22, all the light rays starting from the position LC2 on the reflective liquid crystal display device 13 are as follows. Figure 1 As shown, the light rays are output from lens 22 along angle θ2. However, all light rays originating from position LC2 on reflective liquid crystal display device 13 are shifted relative to each other by only an amount corresponding to the deflection angle from reflective liquid crystal display device 13. Therefore, with an appropriate setting of the deflection angle, the reflected output light rays can be routed to any of output fibers 2a, 2b, ..., 2n. Here, the reflected output light rays are, for example, reflected output light rays corresponding to a group of one or more light rays 42, each of which can contain one or more wavelength channels of WDM signal beam 32. Furthermore, in the present disclosure, since each of collimating lenses 16 is shifted by the same amount relative to its corresponding output fiber, the respective output beams can be recombined to the respective output fibers with improved efficiency.

[0121] Thus, the combination of the input-output section 11 and the lens 22 sends a given set of beams along a given angle (for example, the angle θ1 in the case of the WSS device WSS1 and the angle θ2 in the case of the WSS device WSS2). The combination of the input-output section 11 and the lens 22 then brings about a WSS array device that directs these beams in a manner that depends only on the position on the reflective liquid crystal display 13 (the position LC1 and the position LC2) towards. Thus, the WSS array 10 enables the two sets of WDM signal beams 31 and 32 from and towards the WSS devices WSS1 and WSS2 to share the same optical system 12 and reflective liquid crystal display 13. On the other hand, the WSS array 10 maintains the ability of a WSS array to process each wavelength channel separately.

[0122] With reference to Figure 2 , the stack of optical fibers and microlenses that constitutes the input-output section 11 is viewed from the top of the stack of optical fibers, and thus only the input fiber 1 is visible together with the corresponding collimating lens 16. The following description is made with respect to the WSS device WSS1, but the same description applies to the WSS device WSS2 by virtue of the symmetry of the system.

[0123] As mentioned above, in the case of the WSS device WSS1, the WDM signal beam 31 is incident on the system via the input fiber 1. In Figure 2 , the angle θ1 is directed into the plane of the paper and thus is not visible. In the present disclosure, the WDM signal beam 31 contains several wavelength channels having a range of wavelengths from the longest wavelength λ1 to the shortest wavelength λn. In several examples, the number of wavelength channels can also be larger, for example, 96 wavelength channels having a fixed grid with 50 GHz or 100 GHz spacing. In other examples, the device can use a frequency spacing of, for example, 12.5 GHz, and can be used in an adaptive grid system with more than 97 wavelength channels, for example, more than 130 wavelength channels.

[0124] The WDM signal beam 31 is first incident on the lens 21. The lens 21 functions in a manner that expands the beam to a diameter that is suitable for achieving the desired beam size on the dispersive element 24. For example, the collimating lens 16 and the lens 21 can also function as an expansion telescope. In the present disclosure, as mentioned above, the lens 21 is a cylindrical lens that is oriented in a manner that the beam is expanded in the direction of the dispersion axis of the dispersive element 24. Figure 2As shown, dispersion element 24 functions to angularly disperse the wavelength channels of WDM signal beam 31 in the x-axis direction. After being angularly dispersed in the x-axis direction by dispersion element 24, each of wavelength channels 51 to 5n is focused onto the surface of reflective liquid crystal display device 13 by lens 23. Consequently, wavelength channels 51 to 5n are spatially dispersed in the wavelength dispersion direction (x-axis direction) on reflective liquid crystal display device 13 according to their wavelengths.

[0125] Figure 3 This is a diagram showing a reflective liquid crystal display device using a WSS array according to the first embodiment. Figure 3 This is a diagram showing the reflective liquid crystal display device 13 as viewed from the z-axis direction.

[0126] Figure 3 An example of the distribution of wavelength channels on the surface of the reflective liquid crystal display device 13 is more clearly shown in FIG. More generally, the wavelength channels can be arranged as long strips or elliptical spots on the two-dimensional surface of the reflective liquid crystal display device 13. In short, the wavelength channels are processed as discrete wavelength signals that can be independently acted upon by the reflective liquid crystal display device 13. However, in the present disclosure, the reflective liquid crystal display device 13 does not need to be limited to acting upon individual wavelength channels, but can also act upon groups of wavelength channels. Further, as Figure 3 As shown, the wavelength channels or groups of wavelength channels do not need to have fixed bandwidths. This is because the reflective liquid crystal display device 13 can be implemented as a spatial light modulator that is fully dynamically reconfigurable. Therefore, the present disclosure can be implemented in current fixed grid architectures and / or in highly adaptable grid architectures currently or in the future.

[0127] Refer again Figure 2 The reflective liquid crystal display device 13 selectively changes the direction of one or more wavelength channels 51 to 5n to a certain direction. Furthermore, the reflective liquid crystal display device 13 can make the selected one or more wavelength channels 51 to 5n finally go to one or more output ports (for example, at Figure 2 One or more output optical fibers on the back side of the paper (see Figure 1 )) to change the direction. Figure 2 In the case shown, the direction conversion by the reflective liquid crystal display device 13 is performed along an angle lying in a plane (yz plane) perpendicular to the paper. Figure 1The wavelength channels 51 to 5n undergo direction conversion as previously described in greater detail. After being reflected by the reflective liquid crystal display device 13, the converted wavelength channels 51 to 5n are incident again on the lens 23, further converted to reach the dispersion element 24, and then recombined within the dispersion element 24. For example, the wavelength channels 51 to 5n, which undergo direction conversion at the same angle, are recombined into a single beam, which is then redirected in a direction that enables the processed signal to be output at one of the output ports.

[0128] For example, a WDM signal beam 31 comprising three WDM channels having wavelengths λ1, λ2 and λ3 and channel bandwidths δλ1, δλ2 and δλ3, respectively, is studied. Figure 1 In the example shown, the WDM signal beam 31 enters the system at an angle θ1. Furthermore, the WDM signal beam 31 traveling at an angle θ1 passes through the center of the lens 22 and is deflected without deviating from the angle θ1. After passing through the dispersion element 24, the three wavelength channels of the WDM signal beam 31 are angularly dispersed in an orthogonal plane (the xz plane). Meanwhile, all channels after angular dispersion continue to travel at an angle θ1. Subsequently, as Figure 3 As shown, the three dispersed wavelength channels are focused by the lens 23 to different positions on the reflective liquid crystal display device 13.

[0129] Regarding the routing function of the device, several different routing combinations can be performed. For example, the study expects that 3 wavelength channels will be routed to Figure 1 The corresponding portion of the reflective liquid crystal display device 13 deflects the wavelength channels of wavelengths λ1, λ2 and λ3 so that the wavelength channels of wavelengths λ1, λ2 and λ3 are respectively along Figure 1 One of the light beams 41 shown returns. The function of the dispersive element 24 for the return paths of these wavelength channels is to recombine (multiplex) the individual wavelength channels so that they form the same beam as the currently propagating wave. This combined beam is then redirected by lens 22 to an angle θ1 and propagates along output beam 31c, which has been displaced from the current WDM signal beam 31. The function of the collimating lens 16 is to combine the recombined and redirected output beam 31c with the output optical fiber 1n. Thus, in this operating mode, the WSS device WSS1 allows all three wavelength channels of the WDM signal beam 31 to pass from the input optical fiber 1 to the output optical fiber 1n.

[0130] In another example, depending on the situation, it is desired to route several of the wavelength channels to different output fibers, respectively. For example, depending on the situation, the reflective liquid crystal display device 13 deflects the wavelength channels of wavelength λ1 along the output beam 31a, deflects the wavelength channels of wavelength λ2 along the output beam 31b, and deflects the wavelength channels of wavelength λ3 along the output beam 31c. Here, the role of the dispersing element 24 is also to convert the direction of each of these output beams. However, in this case, the dispersing element 24 does not recombine the output beams in such a way that the output beams become a single beam, but rather generates 3 output beams that advance in a fan-like spread. Furthermore, these output beams each start from the same y-axis direction position LCI on the reflective liquid crystal display device 13, and thus, these output beams exit the lens 22 as a set of parallel rays of light that propagate along the same angle θ1 as the original WDM signal beam 31. However, since each of the output beams is incident on the lens 22 at a different height (different position in the y-axis direction), the output beams are displaced from each other. As a result, for example, the wavelength channels of wavelength λ1 propagate along the output beam 31a, the wavelength channels of wavelength λ2 propagate along the output beam 31b, and the wavelength channels of wavelength λ3 propagate along the output beam 31c. Thus, in this configuration, the role of the WSS device WSS1 is to route the wavelength channels of wavelength λ1 from the input fiber 1 to the output fiber 1a. In addition, the role of the WSS device WSS1 is to route the wavelength channels of wavelength λ2 from the input fiber 1 to the output fiber 1b. In addition, the role of the WSS device WSS1 is to route the wavelength channels of wavelength λ3 from the input fiber 1 to the output fiber In.

[0131] In view of the above, the WSS array 10 of the present disclosure can obviously route any of the wavelength channels of the WDM signal beam to any of the output fibers as desired. Furthermore, depending on the situation, it is possible to route the wavelength channels of the WDM signal beam 31 to the output fibers 1a to In using the WSS device WSS2 as well. Figure 1 The symmetry of the system shown in FIG. 1, the above explanation applies equally to the case of routing the WDM signal beam 32 using the WSS device WSS2 as well. This is because, as shown in FIG. 2, the dispersed wavelength channels of the WSS devices WSS1 and WSS2 eventually converge light onto different portions of the reflective liquid crystal display device 13. And, in the example shown in FIG. 2, although 1 input port and n output ports are used, it should be understood that the output ports can be reconfigured as input ports, and vice versa. Furthermore, any number of input ports and output ports can be used without departing from the scope of the present disclosure. Likewise, Figure 3 Figures 1 to 3 In the example shown in FIG. 2, although 1 input port and n output ports are used, it should be understood that the output ports can be reconfigured as input ports, and vice versa. Furthermore, any number of input ports and output ports can be used without departing from the scope of the present disclosure. Likewise, Figures 1 to 3 ​An explicitly shown example is a WSS array 10 using 2 WSS devices WSS1 and WSS2, but any number of WSS devices can be used without departing from the scope of the present application. For example, in a case where the input / output section 11 is designed to use 4 independent delivery angles, the WSS array 10 can also provide 4 independent WSS devices.

[0132] [Second Embodiment and Comparative Example]

[0133] Hereinafter, a second embodiment will be described, but in order to easily understand the second embodiment, a comparative example will be described first.

[0134] (Comparative Example)

[0135] Figure 4 is a diagram showing the structure of a pixel of a reflective liquid crystal display device of a comparative example. The reflective liquid crystal display device includes a plurality of pixels Pix arranged in a matrix shape. Figure 4 is a diagram showing the structure of a pixel Pix of the jth row and the ith column (i, j are natural numbers).

[0136] As shown in Figure 4 , the pixel Pix includes a holding capacitor (capacitor) Csl that holds a positive polarity pixel signal and a switching transistor Trl for writing the positive polarity pixel signal into the holding capacitor Csl. The transistor Trl is an N-channel MOS (Metal Oxide Semiconductor) (hereinafter, referred to as NMOS) transistor, but the present application is not limited thereto. Also, the pixel Pix includes a holding capacitor Cs2 that holds a negative polarity pixel signal and a switching transistor Tr2 for writing the negative polarity pixel signal into the holding capacitor Cs2. The transistor Tr2 is an NMOS transistor, but the present application is not limited thereto.

[0137] The transistor Trl corresponds to an example of the "first transistor" of the present disclosure. The transistor Tr2 corresponds to an example of the "second transistor" of the present disclosure.

[0138] Further, the pixel Pix includes a source follower circuit 61 as an impedance conversion buffer connected to a signal accumulation node (terminal on the high potential side in this example) of the hold capacitor Cs1. The source follower circuit 61 includes transistors Tr3 and Tr7. Each of the transistors Tr3 and Tr7 is a P-channel MOS (hereinafter, referred to as PMOS) transistor, but the present disclosure is not limited thereto. Further, the pixel Pix includes a source follower circuit 62 as an impedance conversion buffer connected to a signal accumulation node (terminal on the high potential side in this example) of the hold capacitor Cs2. The source follower circuit 62 includes transistors Tr4 and Tr8. Each of the transistors Tr4 and Tr8 is a PMOS transistor, but the present disclosure is not limited thereto.

[0139] The source follower circuit 61 corresponds to an example of the "first source follower circuit" of the present disclosure. The source follower circuit 62 corresponds to an example of the "second source follower circuit" of the present disclosure. The transistor Tr3 corresponds to an example of the "third transistor" of the present disclosure. The transistor Tr4 corresponds to an example of the "fourth transistor" of the present disclosure.

[0140] Further, the pixel Pix includes a transistor Tr5 connected between an output terminal a of the source follower circuit 61 and the pixel electrode PE. The transistor Tr5 is a switching transistor capable of controlling the conduction or non-conduction of the output voltage of the source follower circuit 61 to the pixel electrode PE. The transistor Tr5 is an NMOS transistor, but the present disclosure is not limited thereto. Further, the pixel Pix includes a transistor Tr6 connected between an output terminal b of the source follower circuit 62 and the pixel electrode PE, and includes a switching transistor capable of controlling the conduction or non-conduction of the output voltage of the source follower circuit 62 to the pixel electrode PE. The transistor Tr6 is an NMOS transistor, but the present disclosure is not limited thereto.

[0141] The transistor Tr5 corresponds to an example of the "fifth transistor" of the present disclosure. The transistor Tr6 corresponds to an example of the "sixth transistor" of the present disclosure.

[0142] Further, the pixel Pix includes a liquid crystal display element LC. The liquid crystal display element LC has a liquid crystal display body (liquid crystal layer) LCM interposed between the pixel electrode PE and the common electrode CE disposed opposite to each other. Although the common electrode CE is formed on the counter substrate of the reflective liquid crystal display device, the present disclosure is not limited thereto.

[0143] The pixel data lines Di+ and Di- are supplied with mutually different polarities of pixel signals sampled by a pixel data line drive circuit not shown. The drain terminal of the transistor Trl is connected to the pixel data line Di+. The drain terminal of the transistor Tr2 is connected to the pixel data line Di-. The gate terminals of the transistors Trl and Tr2 are connected to the same row scan line (gate line) in the same row. The transistors Trl and Tr2 are simultaneously brought into the ON state when a scan pulse (row scan signal) is supplied from a vertical scan circuit not shown to the gate terminals via the row scan line Gj, and the positive polarity pixel signal and the negative polarity pixel signal are respectively accumulated in the hold capacitors Csl and Cs2.

[0144] The pixel data line Di+ corresponds to an example of the "positive polarity pixel data line" of the present disclosure. The pixel data line Di- corresponds to an example of the "negative polarity pixel data line" of the present disclosure.

[0145] The transistor Tr3 of the source follower circuit 61 functions as a signal input transistor, and the transistor Tr7 functions as a constant current load transistor. The transistor Tr4 of the source follower circuit 62 functions as a signal input transistor, and the transistor Tr8 functions as a constant current load transistor. The gate terminals of the transistors Tr7 and Tr8 as constant current load transistors are commonly connected to the same wiring B for the same row of pixels, and are configured to enable bias control of the constant current load transistors. The input resistances of the source follower circuits 61 and 62 composed of MOS transistors are very large (almost infinite). Therefore, the storage charges of the hold capacitors Csl and Cs2 are retained after one vertical scan period until a new write signal is written, without leaking, as in the conventional active matrix liquid crystal display device.

[0146] The transistors Tr5 and Tr6 switch the output voltages of the source follower circuits 61 and 62 to be respectively supplied to the liquid crystal display element LC.

[0147] The gate terminal of the transistor Tr5 that performs switching of the pixel signal of the positive polarity and the gate terminal of the transistor Tr6 that performs switching of the pixel signal of the negative polarity are independent. The gate terminal of the transistor Tr5 is connected to the wiring S+ to which the positive polarity side gate control signal is supplied, and the gate terminal of the transistor Tr6 is connected to the wiring S- to which the negative polarity side gate control signal is supplied. By alternately turning on the positive polarity side gate control signal and the negative polarity side gate control signal, the transistors Tr5 and Tr6 alternately become in the on state, and it is possible to supply the liquid crystal display element LC with the pixel signal that is inverted to the positive polarity and the negative polarity. That is, the pixel Pix itself has a polarity inversion function. By controlling the transistors Tr5 and Tr6 at high speed, the pixel Pix can be ac-driven at a high frequency that is not limited by the vertical scanning frequency.

[0148] The positive polarity side gate control signal corresponds to an example of the "first control signal" of the present disclosure. The negative polarity side gate control signal that is alternately turned on with the positive polarity side gate control signal corresponds to an example of the "second control signal" of the present disclosure.

[0149] Figure 5 is a diagram showing an outline of ac driving control of a reflective liquid crystal display device of a comparative example.

[0150] During the period in which the positive polarity side gate control signal applied to the wiring S+ is at the high level, the positive polarity side switching transistor Tr5 becomes in the on state. When the buffer load control signal applied to the wiring B becomes at the low level during this period, the source follower circuit 61 becomes active, and the pixel electrode PE is charged to the pixel signal level of the positive polarity. At the time when the pixel electrode PE becomes in the fully charged state, the buffer load control signal of the wiring B becomes at the high level, and if the positive polarity side gate control signal becomes at the low level, the pixel electrode PE becomes in the floating state, and the pixel voltage of the positive polarity is held in the liquid crystal display element LC.

[0151] On the other hand, during the period in which the negative polarity side gate control signal applied to the wiring S- is at the high level, the negative polarity side switching transistor Tr6 becomes in the on state. When the buffer load control signal applied to the wiring B becomes at the low level during this period, the source follower circuit 62 becomes active, and the pixel electrode PE is charged to the pixel signal level of the negative polarity. At the time when the pixel electrode PE becomes in the fully charged state, the buffer load control signal of the wiring B becomes at the high level, and if the negative polarity side gate control signal becomes at the low level, the pixel electrode PE becomes in the floating state, and the pixel voltage of the negative polarity is held in the liquid crystal display element LC.

[0152] Further, by alternately repeating this operation, the pixel electrode voltage VPE to which the pixel signal of positive polarity and negative polarity is applied to the pixel electrode PE is AC-converted. The pixel Pix is not configured to directly transfer the charge held in the hold capacitors Cs1 and Cs2 to the liquid crystal display element LC but to supply the voltage via the source follower circuits 61 and 62. Therefore, the pixel Pix does not have a problem of charge neutralization even if the pixel electrode PE is repeatedly charged and discharged with positive polarity and negative polarity, and can achieve driving without voltage level attenuation.

[0153] Further, as shown in FIG. 6, the common voltage Vcom applied to the common electrode CE is inverted with respect to a reference potential level which is substantially equal to the inversion reference potential Vc of the potential of the pixel electrode PE in synchronization with the polarity switching of the pixel electrode PE. Since the substantial AC driving voltage of the liquid crystal display LCM is the difference voltage between the pixel electrode PE and the common electrode CE, the AC voltage VLC without a DC component is applied to the liquid crystal display LCM. In this way, the pixel Pix can reduce the amplitude of the voltage supplied to the pixel electrode PE side by switching the applied voltage of the common electrode CE in a manner opposite to the pixel electrode PE. Therefore, the pixel Pix can reduce the transistor withstand voltage of the circuit for driving the pixel electrode PE and the power consumption. Figure 5 Further, in consideration of the consumed current in the reflective liquid crystal display device, the transistors Tr7 and Tr8 are controlled so as not to be activated all the time but to be activated only during a limited period within the ON period of the transistors Tr5 and Tr6. For example, it is assumed that the current of the stable source follower circuit 61 and 62 per 1 pixel Pix is a small current of 1 μA (microampere). However, under the condition that the source follower circuits 61 and 62 of all the pixels stably consume the current, there is a problem that the consumed current of the reflective liquid crystal display device is extremely large. For example, in a reflective liquid crystal display device of full high definition 2 million pixels, the consumed current is expected to reach even 2 A. Therefore, as described in Patent Document 2, a method of reducing the consumed current is proposed.

[0154] As shown in FIG. 6, the gate bias voltage (wiring B) of the transistors Tr7 and Tr8 as constant current load transistors is limited only to the transition period of the polarity switching of the pixel electrode PE during the low level period. Further, the gate bias voltage (wiring B) of the transistors Tr7 and Tr8 becomes high immediately after the pixel electrode voltage VPE is charged and discharged to the target level, and the current of the source follower circuits 61 and 62 stops. Therefore, the pixel Pix is configured to include the source follower circuits 61 and 62 in all the pixels, and can suppress the substantial consumed current to be small.

[0155] Figure 5 As shown in FIG. 6, the gate bias voltage (wiring B) of the transistors Tr7 and Tr8 as constant current load transistors is limited only to the transition period of the polarity switching of the pixel electrode PE during the low level period. Further, the gate bias voltage (wiring B) of the transistors Tr7 and Tr8 becomes high immediately after the pixel electrode voltage VPE is charged and discharged to the target level, and the current of the source follower circuits 61 and 62 stops. Therefore, the pixel Pix is configured to include the source follower circuits 61 and 62 in all the pixels, and can suppress the substantial consumed current to be small.

[0156] ​The AC drive frequency of the liquid crystal display LCM is independent of the vertical scanning frequency and can be freely set with the inversion control period in the pixel Pix. For example, assuming that the vertical scanning frequency is 60 Hz (hertz) used in a general television video signal, the number of scanning lines n = 1125 lines for full high definition. Also, assuming that the polarity of the pixel Pix is switched at a period of about 15 lines, the AC drive frequency of the liquid crystal display LCM is 60 (Hz) x 1125 (lines) ÷ (15 x 2) = 2.25 (kHz). Thus, compared with the conventional reflective liquid crystal display device, the pixel Pix can drastically increase the liquid crystal drive frequency. As a result, compared with the case where the AC drive of the liquid crystal display LCM is low frequency, the pixel Pix can suppress burning and can greatly improve the display quality degradation of reliability, stability, and light spot, and the like.

[0157] Figure 6 is a graph showing the relationship from the black level to the white level of the pixel signal of positive polarity and the pixel signal of negative polarity.

[0158] The pixel signal 91 of positive polarity indicates the black level of the minimum gray scale at the minimum level and the white level of the maximum gray scale at the maximum level across the inversion center c. On the other hand, the pixel signal 92 of negative polarity indicates the white level of the maximum gray scale at the minimum level and the black level of the minimum gray scale at the maximum level across the inversion center c. Thus, the pixel signal 91 of positive polarity and the pixel signal 92 of negative polarity are of opposite polarity.

[0159] Referring again to Figure 4 In the pixel Pix, the transistors Trl, Tr2, Tr5, and Tr6 are constituted by NMOS transistors and the transistors Tr3, Tr4, Tr7, and Tr8 are constituted by PMOS transistors. That is, the transistors Tr3 and Tr4 as source follower transistors are PMOS transistors. Further, the transistors Tr5 and Tr6 as polarity switching switches are NMOS transistors.

[0160] The source follower circuits 61 and 62 using PMOS transistors are amplifiers having a gain of about 0.87 times. In addition, the dynamic range of the voltage applied to the liquid crystal display element LC must be in the linear region, and therefore the source follower circuits 61 and 62 cannot use a high input voltage region in which the input voltage vs output voltage characteristic is nonlinear.

[0161] Figure 7 is a graph showing the relationship of the input voltage and the output voltage of the pixel of the comparative example and the second embodiment. The input voltage is the voltage applied to the pixel data lines D+ and D-. The output voltage is the voltage applied to the pixel electrode PE.

[0162] In the present disclosure, the voltage of the power supply voltage VDD and the high level of each control signal is set to 5.5 V.

[0163] The waveform 71 is a waveform showing the relationship between the input voltage and the output voltage of the pixel Pix of the reflective liquid crystal display device of the comparative example.

[0164] First, the lowest voltage of the output voltage of the pixel Pix is described. In the source follower circuits 61 and 62, a bias voltage of about 1.9 V is applied to the output voltage with respect to the input voltage. Therefore, even if the voltage of the hold capacitors Cs1 and Cs2 is maintained at 0 V, the voltage of the output terminals a and b does not become 0 V but 1.9 V.

[0165] Next, the highest voltage of the output voltage of the pixel Pix is described. The highest voltage at which the source-drain terminals of a general NMOS transistor can be turned on is a voltage obtained by subtracting the threshold voltage Vth from 5.5 V (the power supply voltage VDD). In a general NMOS, the threshold voltage Vth is about 0.8 V in the case where the source terminal and the drain terminal are 0 V.

[0166] However, as described above, in the pixel Pix, the lowest voltage of the output voltage of the source follower circuits 61 and 62 is 1.9 V. That is, the lowest voltage of the source terminal and the drain terminal of the transistors Tr5 and Tr6 is 1.9 V. Therefore, the substrate effect (substrate bias effect) occurs in the transistors Tr5 and Tr6. The threshold voltage Vth of the transistors Tr5 and Tr6 rises about 0.7 V due to the substrate effect, and becomes about 1.5 V. Therefore, the highest voltage at which the transistors Tr5 and Tr6 can be turned on between the source terminal and the drain terminal is a voltage obtained by subtracting the threshold voltage 1.5 V from 5.5 V, that is, 4.0 V (= 5.5 V - 1.5 V).

[0167] As shown in the waveform 71, the pixel Pix is a linear region in which the output voltage to the pixel electrode PE changes in the range of 1.9 V to 4 V in the range of 0 V to 3 V of the input voltage. However, due to the substrate effect of the transistors Tr5 and Tr6, the output voltage of the pixel Pix saturates from 4 V. The dynamic range of the voltage applied to the liquid crystal display element LC must be the linear region. Therefore, for the range of 0 V to 3 V of the input voltage, the dynamic range of the output voltage of the pixel Pix becomes 2.1 V of the range of 1.9 V to 4 V. If the voltage range (dynamic range) applied to the liquid crystal display element LC becomes narrow, it can cause a decrease in contrast and a decrease in luminance. Therefore, it is desirable to expand the dynamic range of the output voltage in the pixel Pix.

[0168] (Second Embodiment)

[0169] Figure 8FIG. 1 is a diagram showing a structure of a pixel of a reflective liquid crystal display device according to a first embodiment of the present disclosure.

[0170] For the constituent elements of the pixel Pixl of the reflective liquid crystal display device of the second embodiment that are the same as those of the pixel Pix of the comparative example, the same reference numerals are attached, and the description is omitted.

[0171] The pixel Pixl includes transistors Tr15 and Tr16 in place of the transistors Tr5 and Tr6, as compared with the pixel Pix.

[0172] The transistor Tr15 corresponds to an example of the "fifth transistor" of the present disclosure. The transistor Tr16 corresponds to an example of the "sixth transistor" of the present disclosure.

[0173] The transistors Tr15 and Tr16 are NMOS transistors of a LowVth (low threshold) in which the threshold voltage Vth is lower than that of the transistors Tr5 and Tr6 that are normal NMOS transistors. As described above, the threshold voltage Vth of the transistors Tr5 and Tr6 that are normal NMOS transistors is about 0.8 V. On the other hand, the threshold voltage Vth of the transistors Tr15 and Tr16 that are LowVth NMOS transistors is in a range of more than 0 V and less than 0.8 V, and can be exemplified as about 0.4 V, for example, but the present disclosure is not limited thereto.

[0174] The transistors Tr15 and Tr16 are transistors that realize a switching function. When the threshold voltage Vth of a transistor is low, the drain current becomes large, and thus the transistor is not normally suitable as a switch.

[0175] Figure 9 FIG. 8 is a diagram showing VG (gate voltage)-ID (drain current) characteristics of NMOS transistors. Waveform 81 is a waveform showing the VG-ID characteristics of the transistors Tr5 and Tr6 that are normal NMOS transistors. Waveform 82 is a waveform showing the VG-ID characteristics of the transistors Tr15 and Tr16 that are LowVth NMOS transistors.

[0176] The threshold voltage Vth is a gate voltage at which the drain current ID flows (turns on). The threshold voltage Vth of the transistors Tr5 and Tr6 that are normal NMOS transistors is 0.8 V, and, in contrast, the threshold voltage Vth of the transistors Tr15 and Tr16 that are LowVth NMOS transistors is 0.4 V.

[0177] Referring again to FIG. 6, Figure 7 In the pixel Pix of the comparative example, for an input voltage in a range of 0 V to 3 V, the output voltage is in a range of 1.9 V to 4.0 V. This output voltage is in a range of 1.9 V to 4.0 V Figure 4In the structure of the pixel Pix shown, the voltage of the pixel electrode PE is also the voltage of the output terminal a of the source follower circuit 61 or the output terminal b of the source follower circuit 62. That is, the output voltage of the pixel Pix is only the voltage of the output terminal a or the output terminal b conducted between the source terminal and the drain terminal of the transistor Tr5 or Tr6 and applied to the pixel electrode PE. Therefore, the output voltage of the pixel Pix becomes in the range of 1.9 V to 4.0 V, and the dynamic range becomes 2.1 V.

[0178] As described above, the drain current of the NMOS transistor of Low Vth is large. The drain current increases when the source voltage is 0 V and the drain voltage is 0 V or more, in the case where the gate voltage is off (0 V).

[0179] In the use of the pixel Pixl, the source voltage (the voltage of the output terminals a and b) of the transistors Tr15 and Tr16 is in the range of 1.9 V to 4.0 V, and the drain voltage (the voltage of the pixel electrode PE) is also in the range of 1.9 V to 4.0 V. That is, both the source voltage and the drain voltage of the transistors Tr15 and Tr16 are voltages higher than 0 V. Therefore, even if there is a little drain current, the transistors Tr15 and Tr16 can normally function as switches.

[0180] If the threshold voltage Vth of the transistors Tr15 and Tr16 is low, in the case where the gate voltage is on (5.5 V), a high voltage applied to the source terminal can be conducted to the drain terminal. The reason is as follows.

[0181] In the pixel Pix of the comparative example, the transistors Tr5 and Tr6 are normal NMOS transistors. Therefore, even if the output terminals a and b of the source follower circuits 61 and 62 are increased in voltage, the transistors Tr5 and Tr6 can only conduct a voltage obtained by subtracting the threshold voltage Vth from 5.5 V, that is, a voltage of (5.5 V - Vth) or less, to the pixel electrode PE. In addition, since the substrate effect occurs in the transistors Tr5 and Tr6, the threshold voltage Vth rises by about 0.7 V from 0.8 V to 1.5 V. Therefore, as described above, the transistors Tr5 and Tr6 can only conduct a voltage of 4.0 V (= 5.5 V - 1.5 V) or less to the pixel electrode PE. Therefore, as described above, in the pixel Pix, the dynamic range of the output voltage becomes 2.1 V.

[0182] On the other hand, the threshold voltage Vth of transistors Tr15 and Tr16 is 0.4V. Furthermore, since transistors Tr15 and Tr16 are NMOS transistors, a substrate effect occurs when the source and drain voltages are higher than the well voltage (0V). Consequently, the threshold voltage Vth of transistors Tr15 and Tr16 rises by approximately 0.7V from 0.4V to 1.1V. Consequently, transistors Tr15 and Tr16 can conduct voltages of 4.4V (=5.5V-1.1V) or less to the pixel electrode PE.

[0183] Figure 7 Waveform 72 illustrates the relationship between the input voltage and output voltage of pixel Pix1 in the second embodiment. Transistors Tr15 and Tr16 can conduct voltages ranging from 1.9V to 4.4V to pixel electrode PE, relative to an input voltage range of 0V to 4V. Therefore, compared to pixel Pix in the comparative example, pixel Pix1 can extend its dynamic range to 2.5V, from 1.9V to 4.4V. Consequently, pixel Pix1 can suppress a decrease in contrast and brightness. Furthermore, pixel Pix1 can increase the reflection angle of reflected light.

[0184] If the reflective liquid crystal display device of the second embodiment, which can suppress the reduction in contrast and the reduction in brightness, is applied to the WSS array 10 of the first embodiment, the output beams 31a to 31c (see Figure 1 ) is reduced, and the brightness reduction can be suppressed. As a result, the WSS array 10 can improve the S / N (signal / noise) ratio of the wavelength channel.

[0185] Furthermore, if the reflective liquid crystal display device of the second embodiment capable of increasing the reflection angle of reflected light is applied to the WSS array 10 of the first embodiment, the output beams 31a to 31c (see FIG. Figure 1 ). Thus, the WSS array 10 can improve the S / N ratio of the wavelength channels. Alternatively, the WSS array 10 can output a new output beam while maintaining the spatial spacing between the output beams 31a to 31c. Thus, the WSS array 10 can increase the number of wavelength channels.

[0186] <Third embodiment>

[0187] Figure 10 A diagram showing the structure of a pixel of a reflective liquid crystal display device according to a third embodiment.

[0188] Among the components of the pixel Pix2 of the reflective liquid crystal display device of the third embodiment, the components identical to those of the pixel Pix of the comparative example or the pixel Pix1 of the second embodiment are denoted by the same reference numerals, and description thereof will be omitted.

[0189] In comparison with the pixel Pix, the pixel Pix2 includes transistors Tr25 and Tr26 in place of the transistors Tr5 and Tr6.

[0190] The transistor Tr25 corresponds to an example of the "fifth transistor" of the present disclosure. The transistor Tr26 corresponds to an example of the "sixth transistor" of the present disclosure.

[0191] The transistors Tr25 and Tr26 are depletion-mode NMOS transistors. The threshold voltage Vth of the transistors Tr25 and Tr26 can be exemplified as about -0.9 V, for example, in a range of 0 V or less, but the present application is not limited thereto.

[0192] The lowest voltage of the source voltage (voltage of the output terminal a and b) and the drain voltage (voltage of the pixel electrode PE) of the transistors Tr25 and Tr26 is 1.9 V. Therefore, the transistors Tr25 and Tr26, in a case where the gate voltage is off (0 V), can leak 1.9 V between the source and the drain as long as it is.

[0193] Referring again to Figure 9 , the waveform 83 is a waveform showing the VG-ID characteristic of the transistors Tr25 and Tr26 which are depletion-mode NMOS transistors.

[0194] The threshold voltage Vth of the transistors Tr5 and Tr6 which are normal NMOS transistors is 0.8 V, in contrast to which the threshold voltage Vth of the transistors Tr25 and Tr26 which are depletion-mode NMOS transistors is -0.9 V.

[0195] Further, the arrow 85 shows the range of VG (gate voltage) in which the transistors Tr25 and Tr26 can be turned on. A normal NMOS transistor, in a case where the source voltage and the drain voltage are 0 V, becomes off if the gate voltage is lower than 0.8 V. On the other hand, the lowest voltage of the source voltage and the drain voltage of the transistors Tr25 and Tr26 which are depletion-mode NMOS transistors is 1.9 V. Therefore, the transistors Tr25 and Tr26, in a case where the source voltage and the drain voltage are converted to 0 V, become off if the gate voltage is lower than -1.1 V (= -1.9 V + 0.8 V).

[0196] In fact, the substrate effect generated in the transistors Tr25 and Tr26 needs to be taken into consideration. Therefore, the threshold voltage Vth of the transistors Tr25 and Tr26 is set taking the substrate effect into consideration. In the third embodiment, the threshold voltage Vth of the transistors Tr25 and Tr26 is set to -0.9 V.

[0197] Figure 11is a graph showing the relationship between the input voltage and the output voltage of the pixel of the comparative example and the third embodiment.

[0198] Waveform 71 is a waveform showing the relationship between the input voltage and the output voltage of the pixel Pix of the reflective liquid crystal display device of the comparative example. Waveform 73 is a waveform showing the relationship between the input voltage and the output voltage of the pixel Pix2 of the reflective liquid crystal display device of the third embodiment.

[0199] In the pixel Pix of the comparative example, for the range of the input voltage of 0 V to 3 V, the output voltage is in the range of 1.9 V to 4.0 V. In the pixel Pix2 of the third embodiment, for the range of the input voltage of 0 V to 4.5 V, the output voltage is in the range of 1.9 V to 5.3 V. Figure 4 In the structure of the pixel Pix shown in FIG. 7, the output voltage is the voltage of the pixel electrode PE, but at the same time, it is also the voltage of the output terminal a of the source follower circuit 61 or the output terminal b of the source follower circuit 62. That is, the output voltage of the pixel Pix is nothing but the voltage of the output terminal a or the output terminal b is conducted between the source terminal and the drain terminal of the transistor Tr5 or Tr6, and is applied to the pixel electrode PE. Therefore, the output voltage of the pixel Pix is in the range of 1.9 V to 4.0 V, and the dynamic range is 2.1 V.

[0200] On the other hand, in the transistors Tr25 and Tr26 whose threshold voltage Vth is -0.9 V, in the case where the voltage of the output terminals a and b of the source follower circuits 61 and 62 or the voltage of the pixel electrode PE is high, the threshold voltage Vth becomes 0.2 V including the substrate effect. Therefore, the transistors Tr25 and Tr26 can conduct the voltage of 5.3 V (= 5.5 V - 0.2 V) or less to the pixel electrode PE.

[0201] As shown in the waveform 73, the transistors Tr25 and Tr26 can conduct the voltage in the range of 1.9 V to 5.3 V to the pixel electrode PE for the range of the input voltage of 0 V to 4.5 V. Therefore, for the range of the input voltage of 0 V to 4.5 V, the pixel Pix2 can expand the dynamic range to 3.4 V from 1.9 V to 5.3 V.

[0202] The pixel Pix2 can normally switch the output voltage in the range of 1.9 V to 5.3 V without leakage, and can expand the dynamic range compared to the pixel Pix of the comparative example. Thereby, the pixel Pix2 can suppress the reduction of the contrast, and can suppress the reduction of the brightness. In addition, the pixel Pix2 can increase the reflection angle of the reflected light.

[0203] <Fourth Embodiment>

[0204] Figure 12 is a graph showing the structure of the pixel of the reflective liquid crystal display device of the fourth embodiment.

[0205] Among the constituent elements of the pixel Pix3 of the reflective liquid crystal display device of the fourth embodiment, the same constituent elements as those of the pixel Pix, the pixel Pixl of the second embodiment, or the pixel Pix2 of the third embodiment are denoted by the same reference numerals, and the description thereof is omitted.

[0206] The pixel Pix3 includes transistors Tr35 and Tr36 in place of the transistors Tr5 and Tr6, in comparison with the pixel Pix.

[0207] The transistor Tr35 corresponds to an example of the "fifth transistor" of the present disclosure. The transistor Tr36 corresponds to an example of the "sixth transistor" of the present disclosure.

[0208] The transistors Tr35 and Tr36 are depletion type NMOS transistors. The threshold voltage Vth of the transistors Tr35 and Tr36 can be exemplified as around 0 V, for example, in a range of 0 V or less, but the present application is not limited thereto.

[0209] Further, the pixel Pix3 includes source follower circuits 63 and 64 in place of the source follower circuits 61 and 62, in comparison with the pixel Pix. The source follower circuit 63 includes the transistor Tr33 in place of the transistor Tr3, in comparison with the source follower circuit 61. The source follower circuit 64 includes the transistor Tr34 in place of the transistor Tr4, in comparison with the source follower circuit 62.

[0210] The transistor Tr33 corresponds to an example of the "third transistor" of the present disclosure. The transistor Tr34 corresponds to an example of the "fourth transistor" of the present disclosure.

[0211] The transistors Tr33 and Tr34 are depletion type PMOS transistors. The threshold voltage Vth of the transistors Tr33 and Tr34 can be exemplified as around +0.4 V, for example, in a range of 0 V or more, but the present application is not limited thereto.

[0212] In the fourth embodiment, the transistors Tr33 and Tr34 are depletion type PMOS transistors, but the present disclosure is not limited thereto. The transistors Tr33 and Tr34 can also be LowVth PMOS transistors. The LowVth PMOS transistor is a transistor in which the threshold voltage Vth is changed in the positive direction, in comparison with a general PMOS transistor.

[0213] The transistors Tr33 and Tr34 are made to have a threshold voltage Vth of +0.4 V by ion implantation to the channel portion. The threshold voltage Vth of the transistors Tr33 and Tr34 is +0.4 V, and thus even if the gate voltage is set to be off (0 V), it is in a constant-on state in which the source and the drain are conductive.

[0214] The gate terminals of the transistors Tr33 and Tr34 are connected with the hold capacitors Cs1 and Cs2, respectively, and are fixed to the pixel signal voltage. Therefore, the transistors Tr33 and Tr34 functioning as signal input transistors do not perform on-off control of the source-drain current with the gate voltage. The on-off control of the source-drain current of the transistors Tr33 and Tr34 is performed by the gate bias control signal supplied to the wiring B connected to the gate terminals of the transistors Tr7 and Tr8 functioning as constant current load transistors. Therefore, the transistors Tr33 and Tr34 can control the resistance value between the source and the drain with the gate voltage, and thus do not need to break the source-drain current even if the gate voltage is 5.5 V. Thus, the transistors Tr33 and Tr34 can avoid nonlinearity in a voltage region where the gate voltage is high.

[0215] In addition, the transistors Tr33 and Tr34 of the source follower circuits 63 and 64 are depletion type transistors, and thus the bias voltage becomes 1.0 V. Thus, the minimum voltage of the source voltage (voltage of the output terminals a and b) and the drain voltage (voltage of the pixel electrode PE) of the transistors Tr35 and Tr36 becomes 1.0 V. Therefore, the transistors Tr35 and Tr36, in the case where the gate voltage is off (0 V), can leak 1.0 V between the source and the drain.

[0216] Referring again to Figure 9 , the waveform 84 is a waveform showing the VG-ID characteristic of the transistors Tr35 and Tr36 which are depletion type NMOS transistors.

[0217] The threshold voltage Vth of the transistors Tr5 and Tr6 which are normal NMOS transistors is 0.8 V, and, in contrast, the threshold voltage Vth of the transistors Tr35 and Tr36 which are depletion type NMOS transistors is 0 V.

[0218] In addition, the arrow 86 shows the range of VG (gate voltage) in which the transistors Tr35 and Tr36 can be turned on. A normal NMOS transistor is in an off state if the gate voltage is lower than 0.8 V in the case where the source voltage and the drain voltage are 0 V. On the other hand, the minimum voltage of the source voltage and the drain voltage of the transistors Tr35 and Tr36 which are depletion type NMOS transistors is 1.0 V. Therefore, the transistors Tr35 and Tr36 are in an off state if the gate voltage is lower than -0.2 V (= -1.0 V + 0.8 V) in the case where the source voltage and the drain voltage are converted to 0 V.

[0219] In fact, the substrate effect generated in the transistors Tr35 and Tr36 needs to be taken into consideration. Therefore, the threshold voltage Vth of the transistors Tr35 and Tr36 is set taking the substrate effect into consideration. In the present disclosure, the threshold voltage Vth of the transistors Tr35 and Tr36 is set to 0 V.

[0220] Figure 13 FIG. 7 is a graph showing the relationship between the input voltage and the output voltage of the pixel of the comparative example and the fourth embodiment.

[0221] The waveform 71 is a waveform showing the relationship between the input voltage and the output voltage of the pixel Pix of the comparative example. The waveform 74 is a waveform showing the relationship between the input voltage and the output voltage of the pixel Pix3 of the fourth embodiment.

[0222] In the pixel Pix of the comparative example, the output voltage is in the range of 1.9 V to 4.0 V with respect to the range of the input voltage of 0 V to 3 V. In the pixel Pix3 of the fourth embodiment, the output voltage is in the range of 1.0 V to 4.3 V with respect to the range of the input voltage of 0 V to 4.5 V. Figure 4 In the structure of the pixel Pix shown, the output voltage is the voltage of the pixel electrode PE, but at the same time, it is also the voltage of the output terminal a of the source follower circuit 61 or the output terminal b of the source follower circuit 62. That is, the output voltage of the pixel Pix is nothing but the voltage of the output terminal a or the output terminal b being conducted between the source terminal and the drain terminal of the transistor Tr5 or Tr6 and applied to the pixel electrode PE. Therefore, the output voltage of the pixel Pix is in the range of 1.9 V to 4.0 V, and the dynamic range is 2.1 V.

[0223] On the other hand, in the transistors Tr35 and Tr36 whose threshold voltage Vth is 0 V, in the case where the voltage of the output terminals a and b of the source follower circuits 63 and 64 or the voltage of the pixel electrode PE is high, the threshold voltage Vth becomes 1.2 V including the substrate effect. Therefore, the transistors Tr35 and Tr36 can conduct a voltage of 4.3 V (= 5.5 V - 1.2 V) or less to the pixel electrode PE.

[0224] As shown in the waveform 74, the transistors Tr35 and Tr36 can conduct a voltage in the range of 1.0 V to 4.3 V to the pixel electrode PE with respect to the range of the input voltage of 0 V to 4.5 V. Therefore, the pixel Pix3 can expand the dynamic range to 3.3 V from 1.0 V to 4.3 V with respect to the range of the input voltage of 0 V to 4.5 V.

[0225] The pixel Pix3 can normally perform switching without leaking the output voltage in the range of 1.0 V to 4.3 V and can expand the dynamic range compared to the pixel Pix of the comparative example. Thereby, the pixel Pix3 can suppress the reduction in contrast and can suppress the reduction in brightness. In addition, the pixel Pix3 can increase the reflection angle of the reflected light.

[0226] <5th Embodiment>

[0227] Figure 14 Fig. 6 is a view showing a structure of a pixel of a reflective liquid crystal display device according to the fifth embodiment.

[0228] For the constituent elements of the pixel Pix4 of the reflective liquid crystal display device according to the fifth embodiment that are the same as those of the pixel Pix of the comparative example or the pixels Pix1 to Pix3 according to the second to fourth embodiments, the same reference numerals are attached, and the description is omitted.

[0229] The pixel Pix4 includes the transistors Tr41 and Tr42 in place of the transistors Tr1 and Tr2, as compared with the pixel Pix.

[0230] The transistor Tr41 corresponds to an example of the "first transistor" of the present disclosure. The transistor Tr42 corresponds to an example of the "second transistor" of the present disclosure.

[0231] The transistors Tr41 and Tr42 are LowVth or depletion type NMOS transistors. The threshold voltage Vth of the transistors Tr41 and Tr42 is exemplified as about +0.4 V in the case of LowVth, but the present disclosure is not limited thereto.

[0232] Further, the pixel Pix4 includes the transistors Tr45 and Tr46 in place of the transistors Tr5 and Tr6, as compared with the pixel Pix.

[0233] The transistor Tr45 corresponds to an example of the "fifth transistor" of the present disclosure. The transistor Tr46 corresponds to an example of the "sixth transistor" of the present disclosure.

[0234] The transistors Tr45 and Tr46 are LowVth or depletion type NMOS transistors. The threshold voltage Vth of the transistors Tr45 and Tr46 is exemplified as about +0.4 V in the case of LowVth, but the present disclosure is not limited thereto.

[0235] The lowest voltage of the source voltage (voltage of the output terminals a and b) and the drain voltage (voltage of the pixel electrode PE) of the transistors Tr45 and Tr46 is 1.9 V. Therefore, the transistors Tr45 and Tr46 do not leak 1.9 V between the source and the drain as long as the gate voltage is off (0 V).

[0236] The transistors Tr41 and Tr42 are LowVth or depletion type NMOS transistors. That is, the threshold voltage Vth of the transistors Tr41 and Tr42 is lower than that of the transistors Trl and Tr2. Therefore, the transistors Tr41 and Tr42 can turn on the high voltage supplied to the pixel data line Di+ for positive polarity and the pixel data line Di- for negative polarity, compared with the transistors Trl and Tr2. That is, the transistors Tr41 and Tr42 can turn on the high voltage applied to the source terminal to the drain terminal, in the case where the scan pulse supplied to the row scan line Gj is on (5.5 V).

[0237] On the other hand, in the pixel Pix of the comparative example, the transistors Trl and Tr2 are normal NMOS transistors. The threshold voltage Vth of the transistors Trl and Tr2 rises from 0.8 V by about 0.7 V due to the substrate effect, and becomes 1.5 V. Therefore, the highest voltage that the transistors Trl and Tr2 can turn on between the source terminal and the drain terminal is a voltage obtained by subtracting the threshold voltage 1.5 V from 5.5 V, that is, 4.0 V (= 5.5 V - 1.5 V). That is, even in the case where the high voltage is supplied to the pixel data line Di+ for positive polarity and the pixel data line Di- for negative polarity, the maximum voltage to which the transistors Trl and Tr2 can turn on the hold capacitors Cs 1 and Cs2 becomes 4 V.

[0238] In addition, in the case where the threshold voltage Vth of the transistors Tr45 and Tr46 is set to LowVth + 0.4 V, the threshold voltage Vth of the transistors Tr45 and Tr46 rises from 0.4 V by about 0.7 V due to the substrate effect, and becomes 1.1 V. Therefore, the transistors Tr45 and Tr46 can turn on a voltage of 4.4 V (= 5.5 V - 1.1 V) or less to the pixel electrode PE.

[0239] Figure 15 Fig. 7 is a graph showing the relationship between the input voltage and the output voltage of the pixel of the comparative example and the fifth embodiment.

[0240] The waveform 71 is a waveform showing the relationship between the input voltage and the output voltage of the pixel Pix of the comparative example. The waveform 75 is a waveform showing the relationship between the input voltage and the output voltage of the pixel Pix4 of the fifth embodiment.

[0241] In the case where the threshold voltage Vth of the transistors Tr45 and Tr46 as LowVth transistors is set to +0.4 V, the threshold voltage Vth of the transistors Tr45 and Tr46 rises by about 0.7 V from 0.4 V due to the substrate effect, and becomes 1.1 V. Therefore, the maximum voltage that the transistors Tr45 and Tr46 can turn on from the pixel data line Di+ for positive polarity and the pixel data line Di- for negative polarity to the holding capacitors Cs1 and Cs2 becomes 4.4 V (= 5.5 V - 1.1 V).

[0242] Therefore, in the case where the pixel data line Di+ for positive polarity and the pixel data line Di- for negative polarity are supplied with a voltage of 0 V to 5 V, the voltage that can be turned on to the holding capacitors Cs1 and Cs2 becomes 0 V to 4.4 V. The holding voltage of the holding capacitors Cs1 and Cs2 is level-shifted (a bias voltage is added) by the source follower circuits 61 and 62. Also, the transistors Tr45 and Tr46 can turn on a voltage of 4.4 V or less to the pixel electrode PE. Therefore, the voltage applied to the pixel electrode PE is 1.9 V to 4.4 V.

[0243] The switch provided on the pixel data line drive circuit for supplying the pixel data line Di+ for positive polarity and the pixel data line Di- for negative polarity with a pixel signal is a complementary switch using both an NMOS transistor and a PMOS transistor. Therefore, the switch of the pixel data line drive circuit, unlike the switch using only an NMOS transistor used in the pixel Pix4, can also turn on a high voltage. Therefore, the pixel data line drive circuit can supply the pixel data line Di+ for positive polarity and the pixel data line Di- for negative polarity with a pixel signal of a reference voltage (ground voltage) GND to a power supply voltage VDD (i.e., 0 V to 5.5 V).

[0244] In addition, in the pixel Pix4, since it is necessary to reduce the pixel pitch, the switch becomes one using only an NMOS transistor.

[0245] As described above, the pixel Pix4 can expand the dynamic range compared to the pixel Pix of the comparative example. Thus, the pixel Pix4 can suppress a decrease in contrast, and can suppress a decrease in luminance. In addition, the pixel Pix4 can increase the reflection angle of reflected light.

[0246] In addition, in the fifth embodiment, the case where the transistors Tr41, Tr42, Tr45, and Tr46 are NMOS transistors of LowVth is described. However, the transistors Tr41, Tr42, Tr45, and Tr46 can also be depletion-mode NMOS transistors. In this case, the threshold voltage Vth is set in consideration of the voltage range of the pixel signal input to the pixel Pix and the range in which the switch can be performed.

[0247] Further, in the fifth embodiment, a case where the threshold voltage Vth of the transistors Tr41 and Tr42 is the same as the threshold voltage Vth of the transistors Tr45 and Tr46 is described. However, the threshold voltage Vth of the transistors Tr41 and Tr42 can be different from the threshold voltage Vth of the transistors Tr45 and Tr46. For example, the threshold voltage Vth of the transistors Tr41 and Tr42, which are Low Vth transistors, can be +0.4 V, and the threshold voltage Vth of the transistors Tr45 and Tr46, which are depletion mode transistors, can be -0.9 V. In this case, the pixel Pix4 can further expand the dynamic range. Thus, the pixel Pix4 can further suppress the reduction in contrast, can further suppress the reduction in luminance, and can further increase the reflection angle of the reflected light.

[0248] <Sixth Embodiment>

[0249] Figure 16 Fig. 6 is a view showing the structure of a pixel of a reflective liquid crystal display device according to a sixth embodiment.

[0250] The same reference numerals are assigned to the constituent elements of the pixel Pix5 of the reflective liquid crystal display device according to the sixth embodiment that are the same as those of the pixel Pix of the comparative example or the pixels Pixl to Pix4 of the second to fifth embodiments, and the description thereof is omitted.

[0251] The pixel Pix5 includes the transistors Tr41 and Tr42 in place of the transistors Trl and Tr2, as compared with the pixel Pix3 (see Fig. 4) of the fourth embodiment. Figure 12

[0252] As described in the pixel Pix4 of the fifth embodiment, the transistors Tr41 and Tr42 can turn on the high voltage supplied to the pixel data line Di+ for the positive polarity and the pixel data line Di- for the negative polarity, as compared with the transistors Trl and Tr2.

[0253] The threshold voltage Vth of the transistors Tr41 and Tr42 is lower than the threshold voltage Vth of the transistors Trl and Tr2. Thus, the transistors Tr41 and Tr42 can turn on the high voltage applied to the source terminal to the drain terminal, in a case where the voltage at the gate terminal is on (5.5 V).

[0254] The transistors Tr35 and Tr36 are NMOS transistors, and the threshold voltage Vth becomes large in a case where the source voltage and the drain voltage are higher than the well voltage (0 V) because of the substrate effect.

[0255] ​In the pixel Pix of the comparative example, the transistors Trl and Tr2 are normal NMOS transistors. The threshold voltage Vth of the transistors Trl and Tr2 rises by about 0.7 V from 0.8 V due to the substrate effect, becoming 1.5 V. Therefore, the maximum voltage at which the transistors Trl and Tr2 can turn on between the source terminal and the drain terminal is a voltage obtained by subtracting the threshold voltage 1.5 V from 5.5 V, i.e., 4.0 V (= 5.5 V - 1.5 V). That is, even in the case where a high voltage is supplied to the pixel data line Di+ for the positive polarity and the pixel data line Di- for the negative polarity, the maximum voltage at which the transistors Trl and Tr2 can turn on to the holding capacitors Csl and Cs2 becomes 4 V.

[0256] Figure 17 FIG. 7 is a graph showing the relationship between the input voltage and the output voltage of the pixel of the comparative example and the sixth embodiment.

[0257] The waveform 71 is a waveform showing the relationship between the input voltage and the output voltage of the pixel Pix of the comparative example. The waveform 76 is a waveform showing the relationship between the input voltage and the output voltage of the pixel Pix5 of the sixth embodiment.

[0258] In the pixel Pix of the comparative example, for the range of the input voltage of 0 V to 3 V, the output voltage is in the range of 1.9 V to 4.0 V. In the pixel Pix of the comparative example, for the range of the input voltage of 0 V to 3 V, the output voltage is in the range of 1.9 V to 4.0 V. In the pixel Pix of the comparative example, for the range of the input voltage of 0 V to 3 V, the output voltage is in the range of 1.9 V to 4.0 V. Figure 4 In the structure of the pixel Pix shown in FIG. 6, the output voltage is the voltage of the pixel electrode PE, but at the same time, it is also the voltage of the output terminal a of the source follower circuit 61 or the output terminal b of the source follower circuit 62. That is, the output voltage of the pixel Pix is nothing but the voltage of the output terminal a or the output terminal b turned on between the source terminal and the drain terminal of the transistor Tr5 or Tr6 and applied to the pixel electrode PE. Therefore, the output voltage of the pixel Pix becomes 1.9 V to 4.0 V, and the dynamic range becomes 2.1 V.

[0259] On the other hand, in the transistors Tr35 and Tr36 whose threshold voltage Vth is 0 V, in the case where the voltage of the output terminals a and b of the source follower circuits 63 and 64 or the voltage of the pixel electrode PE is high, the threshold voltage Vth becomes 1.2 V including the substrate effect. Therefore, the transistors Tr35 and Tr36 can turn on a voltage of 4.3 V (= 5.5 V - 1.2 V) or less to the pixel electrode PE.

[0260] As shown in the waveform 76, the transistors Tr35 and Tr36 can turn on a voltage in the range of 1.0 V to 4.3 V to the pixel electrode PE for the range of the input voltage of 0 V to 4.5 V. Therefore, the pixel Pix5 can expand the dynamic range to 3.3 V from 1.0 V to 4.3 V for the range of the input voltage of 0 V to 4.5 V.

[0261] The threshold voltage Vth of transistors Tr33 and Tr34 is set to +0.4 V by ion implantation into the channel portion. Since the threshold voltage Vth of transistors Tr33 and Tr34 is +0.4 V, they are in a normally-on state with conduction between the source and the drain even when the gate voltage is turned off (0 V).

[0262] The gate terminals of transistors Tr33 and Tr34 are connected to holding capacitors Cs1 and Cs2, respectively, and their gate electrodes are fixed to the pixel signal voltage. Therefore, transistors Tr33 and Tr34, which function as signal input transistors, do not use gate voltage to control the source-drain current. The source-drain current of transistors Tr33 and Tr34 is controlled by a gate bias control signal supplied to wiring B connected to the gate terminals of transistors Tr7 and Tr8, which function as constant-current load transistors. Therefore, transistors Tr33 and Tr34 only need to control the source-drain resistance value using the gate voltage, so there is no need to shut off the source-drain current even at a gate voltage of 5.5V.

[0263] Thus, the transistors Tr33 and Tr34 can avoid nonlinearity in a voltage region where the gate voltage is high.

[0264] Furthermore, since the transistors Tr33 and Tr34 of the source follower circuits 63 and 64 are depletion-mode transistors, the bias voltage is 1.0 V. Consequently, the minimum voltage of the source voltage (the voltage of the output terminals a and b) and the drain voltage (the voltage of the pixel electrode PE) of the transistors Tr35 and Tr36 is 1.0 V. Therefore, when the gate voltage of the transistors Tr35 and Tr36 is off (0 V), it is sufficient that 1.0 V does not leak between the source and the drain.

[0265] Refer again Figure 9 A waveform 82 is a waveform showing the VG-ID characteristics of the transistors Tr41 and Tr42, which are low-Vth NMOS transistors, and a waveform 84 is a waveform showing the VG-ID characteristics of the transistors Tr35 and Tr36, which are depletion-mode NMOS transistors.

[0266] The threshold voltage Vth of the transistors Tr1 and Tr2 , which are normal NMOS transistors, is 0.8V. In contrast, the threshold voltage Vth of the transistors Tr41 and Tr42 , which are LowVth NMOS transistors, is 0.4V.

[0267] The threshold voltage Vth of the transistors Tr5 and Tr6 , which are normal NMOS transistors, is 0.8V. In contrast, the threshold voltage Vth of the transistors Tr35 and Tr36 , which are depletion-mode NMOS transistors, is 0V.

[0268] Further, arrow 86 shows the range of VG (gate voltage) at which the transistors Tr35 and Tr36 can be turned on. A typical NMOS transistor becomes in an off state if the gate voltage is lower than 0.8 V when the source voltage and the drain voltage are 0 V. On the other hand, the lowest voltage of the source voltage and the drain voltage of the transistors Tr35 and Tr36, which are depletion-mode NMOS transistors, is 1.0 V. Therefore, the transistors Tr35 and Tr36 become in an off state if the gate voltage is lower than -0.2 V (= -1.0 V + 0.8 V) when the source voltage and the drain voltage are converted to 0 V.

[0269] In fact, the substrate effect generated in the transistors Tr35 and Tr36 needs to be taken into consideration. Therefore, the threshold voltage Vth of the transistors Tr35 and Tr36 is set taking the substrate effect into consideration. In the present disclosure, the threshold voltage Vth of the transistors Tr35 and Tr36 is set to 0 V.

[0270] The switch provided in the pixel data line drive circuit for supplying pixel signals to the pixel data line Di+ for positive polarity and the pixel data line Di- for negative polarity is a complementary switch using both NMOS transistors and PMOS transistors. Therefore, the switch of the pixel data line drive circuit, unlike the switch using only NMOS transistors used in the pixel Pix5, can be turned on also to a high voltage. Therefore, the pixel data line drive circuit can supply pixel signals from the reference voltage GND to the power supply voltage VDD, i.e., from 0 V to 5.5 V, to the pixel data line Di+ for positive polarity and the pixel data line Di- for negative polarity.

[0271] Further, in the pixel Pix5, since it is necessary to reduce the pixel pitch, the switch using only NMOS transistors is used.

[0272] As explained above, the pixel Pix5 can expand the dynamic range compared to the pixel Pix of the comparative example. Thereby, the pixel Pix5 can suppress the reduction in contrast, and can suppress the reduction in brightness. Further, the pixel Pix5 can increase the reflection angle of the reflected light.

[0273] In the sixth embodiment, the case where the transistors Tr41 and Tr42 are Low Vth NMOS transistors and the transistors Tr35 and Tr36 are depletion-mode NMOS transistors is explained. Although the transistors Tr41, Tr42, Tr35, and Tr36 are all NMOS transistors, the threshold voltages Vth are different. In this structure, the manufacturing becomes complicated, and therefore it is also possible to consider that the threshold voltages Vth of the transistors Tr41, Tr42, Tr35, and Tr36 are unified to the same voltage with priority given to cost.

[0274] <Second to sixth embodiments>

[0275] In the second to sixth embodiments, the transistors Trl, Tr2, Tr5, Tr6, Tr15, Tr16, Tr25, Tr26, Tr35, Tr36, Tr41, Tr42, Tr45, and Tr46 are NMOS transistors. In addition, the transistors Tr3, Tr4, Tr7, Tr8, Tr33, and Tr34 are PMOS transistors. However, the polarities of these transistors are not limited to this. Each transistor can be configured with a transistor of opposite polarity. Of course, each transistor can have only a part of opposite polarity. In this case, the polarity of the LowVth threshold voltage Vth and the polarity of the depletion transistor threshold voltage Vth are changed as appropriate in accordance with the polarity of each transistor.

[0276] The use of LowVth or depletion transistors is not limited to the second to sixth embodiments. For example, it can be a combination in which the transistors Trl and Tr2 are LowVth or depletion NMOS transistors and the transistors Tr3 and Tr4 are depletion PMOS transistors. In this case, the threshold voltage Vth is determined taking into account the amplitude of the pixel signal and the voltage at which each transistor starts to leak current, of course.

[0277] Also, in the second to sixth embodiments, the transistors Trl, Tr2, Tr5, Tr6, Tr15, Tr16, Tr25, Tr26, Tr35, Tr36, Tr41, Tr42, Tr45, and Tr46 are configured with NMOS transistors. However, these transistors are not limited to being configured with only NMOS (PMOS) transistors.

[0278] The switch configured with the transistors Trl, Tr2, Tr5, Tr6, Tr15, Tr16, Tr25, Tr26, Tr35, Tr36, Tr41, Tr42, Tr45, and Tr46 can also be a complementary switch. A complementary switch is configured with two transistors, an NMOS transistor and a PMOS transistor. For example, the complementary switch is a switch in which the source terminals of the NMOS transistor and the PMOS transistor are connected to each other as input terminals and the drain terminals of the NMOS transistor and the PMOS transistor are connected to each other as output terminals. When the complementary switch is turned on, the gate terminal of the NMOS transistor is supplied with the power supply voltage VDD and the gate terminal of the PMOS transistor is supplied with the reference voltage GND. When the complementary switch is turned off, the gate terminal of the NMOS transistor is supplied with the reference voltage GND and the gate terminal of the PMOS transistor is supplied with the power supply voltage VDD.

[0279] <Seventh Embodiment>

[0280] Figure 18 is a plan layout of a pixel of the reflective liquid crystal display device of the seventh embodiment. Figure 19 is a cross-sectional view of the pixel of the reflective liquid crystal display device of the seventh embodiment. In detail, Figure 18 is a plan layout of each transistor, the first metal layer 1M, a contact connecting each transistor and the first metal layer 1M, and a via connecting the first metal layer 1M and the second metal layer 2M of the pixel Pixl (the second embodiment). Figure 19 is Figure 18 is a cross-sectional view at the line A-A' in

[0281] For the same constituent elements as those of the pixel Pix of the comparative example or the pixels Pix2 to Pix5 of the third to sixth embodiments among the constituent elements of the pixel Pixl of the seventh (second) embodiment, the same reference numerals are attached, and the description is omitted.

[0282] First, the plan layout of the pixel Pixl will be described with reference to Figure 19 The cross-sectional structure of the pixel Pixl will be described.

[0283] The pixel Pixl is structured such that the first metal layer 1M, the second metal layer 2M, the third metal layer 3M, the fourth metal layer 4M, the fifth metal layer 5M, and the sixth metal layer 6M are stacked with an interlayer film therebetween on the upper layer of each transistor formed on the well 110 of the semiconductor substrate. In addition, the sixth metal layer 6M constitutes the pixel electrode PE, and the common electrode CE is formed at a position opposed to the pixel electrode PE. The liquid crystal display body (liquid crystal layer) LCM is interposed between the pixel electrode PE and the common electrode CE, thereby constituting the liquid crystal display element LC.

[0284] In the pixel Pixl, the circuit constituent elements and the wires of the pixel circuit portion on the positive polarity side and the pixel circuit portion on the negative polarity side are arranged in a line-symmetrical manner. In other words, the circuit constituent elements and the wires of the paired circuits are arranged in a mirror-inverted manner.

[0285] In the pixel Pixl (refer to Figure 8 ), the pixel circuit portion on the positive polarity side includes the transistors Trl, Tr3, Tr7, and Tr15, the holding capacitor Csl, and the pixel data line Di+. In addition, in the pixel Pixl, the pixel circuit portion on the negative polarity side includes the transistors Tr2, Tr4, Tr8, and Tr16, the holding capacitor Cs2, and the pixel data line Di-. However, the transistors Trl to Tr4, Tr7, Tr8, Tr15, and Tr16 are formed on the well as the semiconductor substrate, and the circuit constituent elements and the wires other than these are arranged on the first to sixth metal layers 1M to 6M.

[0286] The gate electrodes of the transistors Tr3 and Tr7 and the gate electrodes of the transistors Tr4 and Tr8 are arranged bilaterally symmetrically in the well 110. These gate electrodes are formed of polysilicon.

[0287] In addition, in the well 110, a diffusion layer 111 is formed between the gate of the transistor Tr3 and the gate of the transistor Tr7, which serves as the source of the transistor Tr3 and the drain of the transistor Tr7. In addition, a diffusion layer 112 is formed between the gate of the transistor Tr4 and the gate of the transistor Tr8, which serves as the source of the transistor Tr4 and the drain of the transistor Tr8. In addition, in the well 110, a diffusion layer 113 is formed as the drain of the transistor Tr3, a diffusion layer 114 is formed as the drain of the transistor Tr4, and a diffusion layer 115 is formed as the source of the transistor Tr7 and the source of the transistor Tr8. Parts of the diffusion layers 111 to 115 are connected to the pixel electrode wiring 138 (see FIG. 14 ) of the first metal layer 1M via contacts and through-holes. Figure 18 Furthermore, another portion within the diffusion layers 111 to 115 is electrically connected to the reference potential wiring VSS of the first metal layer 1M.

[0288] In addition, Figure 19 In the embodiment, an anti-reflection film shown in bold solid lines is formed on the upper and lower surfaces of each of the first metal layer 1M, the second metal layer 2M, the third metal layer 3M, and the fifth metal layer 5M, as well as on the lower surface of the sixth metal layer 6M. The anti-reflection film is formed of a metal film such as Ti or TiN and functions as part of the metal layer. The anti-reflection film absorbs light irradiated from the gap between the pixel electrodes PE and reflects the portion that is not completely absorbed. Therefore, the longer the optical path length of the reflected light (the more repeated reflections), the more attenuated the reflected light is.

[0289] The fourth metal layer 4M includes a positive polarity storage capacitor electrode 121 (high-potential side electrode for storage capacitor Cs1), a negative polarity storage capacitor electrode 122 (high-potential side electrode for storage capacitor Cs2), and a pixel electrode storage capacitor electrode (not shown). The pixel electrode storage capacitor electrode is connected to the sixth metal layer 6M (pixel electrode PE) via vias 104 and 105.

[0290] Next, we will refer to Figure 18 Describe the planar layout of pixel Pix1.

[0291] Each transistor is formed by an active region and layers such as polysilicon, and is connected to the first metal layer 1M via contacts as needed. Figure 18 In FIG, transistor Tr2 is a switching transistor for writing a negative pixel signal, and transistor Tr1 is a switching transistor for writing a positive pixel signal. Transistor Tr1 and transistor Tr2 are formed with left and right mirror images inverted with respect to the center line 131 within one pixel.

[0292] Also, the source follower circuit 61 (composed of the transistor Tr3 and the transistor Tr7) and the source follower circuit 62 (composed of the transistor Tr4 and the transistor Tr8) are formed by left-right mirror inversion with the center line 131 as a reference.

[0293] The connection wiring 133 is connected to the source of the transistor Tr2, the gate of the transistor Tr4, and the hold capacitor Cs2. The connection wiring 132 is connected to the source of the transistor Trl, the gate of the transistor Tr3, and the hold capacitor Csl. The connection wiring 133 and the connection wiring 132 are formed by left-right mirror inversion. The gate electrode of the transistor Tr 15 which performs switching of the pixel signal of positive polarity and the gate electrode of the transistor Tr 16 which performs switching of the pixel signal of negative polarity are independent. Also, the gate electrode of the transistor Tr 15 and the gate electrode of the transistor Tr 16 are respectively connected to the wiring S+ and S- which are arranged in the row direction for the same row of pixels.

[0294] In the through holes illustrated for the gates of the transistors Trl, Tr2, Tr7, Tr8, Tr 15, and Tr 16, and the drains of the transistors Tr7 and Tr8, contacts which are not illustrated are also arranged. Therefore, the gates of the transistors Trl, Tr2, Tr7, Tr8, Tr 15, and Tr 16, and the drains of the transistors Tr7 and Tr8 are connected to the second metal layer 2M via the contacts and the through holes.

[0295] The power supply wirings 134 and 135 which supply the power supply voltage VDD are arranged at both left and right ends within one pixel, in a manner so as to suppress crosstalk from the connection wirings 132 or 133 composed of the first metal layer 1M of the left and right adjacent pixels, and are arranged as a protective pattern. Thereby, the hold capacitors Csl and Cs2 can hold a stable voltage without being affected by unnecessary voltage. Also, the power supply wirings 134 and 135 are also used as wirings which connect the power supply voltage VDD potential in the upper and lower pixels.

[0296] Here, as described above, the transistors Tr 15 and Tr 16 are LowVth NMOS transistors. In the ion implantation regions 136 and 137 of the transistors Tr 15 and Tr 16, ions are implanted in a manner so as to become a threshold voltage Vth which is different from other normal NMOS transistors. Actually, a mask is made in the pattern of the ion implantation regions 136 and 137. Then, ions which pass through the mask are implanted into the active region under the gate of the transistors Tr 15 and Tr 16. Thereby, the transistors Tr 15 and Tr 16 are adjusted to the desired threshold voltage Vth. In the pixel Pixl, ion implantation is performed so as to make the threshold voltage Vth of the transistors Tr 15 and Tr 16 0.4 V.

[0297] Further, the manufacturing method of the pixel Pix2 of the third embodiment is the same as that of the pixel Pixl, and thus the description is omitted. In the pixel Pix2, ions are injected into the ion-implanted regions 136 and 137 of the transistors Tr25 and Tr26 to make them into depletion mode transistors. In the pixel Pix2, ion implantation is performed to make the threshold voltage Vth of the transistors Tr25 and Tr26 -0.9 V.

[0298] <Eighth Embodiment>

[0299] Figure 20 is a plan layout of a pixel of a reflective liquid crystal display device of the eighth embodiment. In detail, Figure 20 is a plan layout showing each transistor, the first metal layer 1M, the contact for connecting each transistor and the first metal layer 1M, and the via for connecting the first metal layer 1M and the second metal layer 2M of the pixel Pix3 (fourth embodiment).

[0300] As for the components common to the pixel Pix3 of the eighth (fourth) embodiment and the components common to the pixel Pix of the comparative example or the pixels Pixl, Pix2, Pix4, and Pix5 of the second, third, fifth through seventh embodiments, the same reference numerals are attached, and the description is omitted.

[0301] Each transistor is formed of an active region and a layer of polysilicon or the like, and is wired-connected to the first metal layer 1M via a contact as necessary. In Figure 20 In the pixel Pix3, the transistor Tr2 is a switching transistor for writing a pixel signal of a negative polarity, and the transistor Trl is a switching transistor for writing a pixel signal of a positive polarity. The transistor Trl and the transistor Tr2 are formed in mirror image with the center line 131 within one pixel as a reference.

[0302] Further, the source follower circuit 63 (composed of the transistor Tr33 and the transistor Tr7) and the source follower circuit 64 (composed of the transistor Tr34 and the transistor Tr8) are formed in mirror image with the center line 131 as a reference.

[0303] The connection wiring 133 is connected to the source of the transistor Tr2, the gate of the transistor Tr4, and the hold capacitor Cs2. The connection wiring 132 is connected to the source of the transistor Trl, the gate of the transistor Tr3, and the hold capacitor Csl. The connection wiring 133 and the connection wiring 132 are formed in mirror image. The gate electrode of the transistor Tr35 which performs switching of a pixel signal of a positive polarity and the gate electrode of the transistor Tr36 which performs switching of a pixel signal of a negative polarity are independent. Further, the gate electrode of the transistor Tr35 and the gate electrode of the transistor Tr36 are respectively connected to the wiring S+ and S- arranged in the row direction for the same row of pixels.

[0304] In the through holes illustrated in the gate of each of the transistors Trl, Tr2, Tr7, Tr8, Tr35, and Tr36, and the drain of each of the transistors Tr7 and Tr8, a contact not illustrated is also provided. Thus, the gate of each of the transistors Trl, Tr2, Tr7, Tr8, Tr35, and Tr36, and the drain of each of the transistors Tr7 and Tr8 are connected to the second metal layer 2M via the contact and the through hole.

[0305] The power supply lines 134 and 135 that supply the power supply voltage VDD are provided at both left and right ends within one pixel, and are provided as a guard pattern in a manner to suppress crosstalk from the connection line 132 or 133 made of the first metal layer 1M of the left and right adjacent pixels. Thus, the holding capacitances Csl and Cs2 can hold a stable voltage without being affected by unnecessary voltage. Further, the power supply lines 134 and 135 are also used as lines that connect the power supply voltage VDD potential in the upper and lower pixels.

[0306] Here, as described above, the transistors Tr35 and Tr36 are depletion type NMOS transistors. In the ion implantation regions 136 and 137 of the transistors Tr35 and Tr36, ions are implanted in a manner to become a threshold voltage Vth different from other normal NMOS transistors. Actually, a mask is made in the pattern of the ion implantation regions 136 and 137. Then, ions that have passed through the mask are implanted into the active region under the gate of the transistors Tr35 and Tr36. Thus, the transistors Tr35 and Tr36 are adjusted to the desired threshold voltage Vth. In the pixel Pix3, ion implantation is performed so that the threshold voltage Vth of the transistors Tr35 and Tr36 becomes 0 V.

[0307] Further, as described above, the transistors Tr33 and Tr34 are depletion type PMOS transistors. In the ion implantation regions 141 and 142 of the transistors Tr33 and Tr34, ions are implanted in a manner to become a threshold voltage Vth different from other normal PMOS transistors. Actually, a mask is made in the pattern of the ion implantation regions 141 and 142. Then, ions that have passed through the mask are implanted into the active region under the gate of the transistors Tr33 and Tr34. Thus, the transistors Tr33 and Tr34 are adjusted to the desired threshold voltage Vth. In the pixel Pix3, ion implantation is performed so that the threshold voltage Vth of the transistors Tr33 and Tr34 becomes +0.4 V.

[0308] Further, the ion implantation regions 136 and 137 are ion implanted using a first mask of a pattern for NMOS transistors, and the ion implantation regions 141 and 142 are ion implanted using a second mask of a pattern for PMOS transistors. Thus, the mask for the ion implantation regions 136 and 137 and the mask for the ion implantation regions 141 and 142 are different masks.

[0309] <SEVENTH EMBODIMENT>

[0310] Figure 21 is a plan layout of a pixel of a reflective liquid crystal display device according to the ninth embodiment. In detail, Figure 21 is a plan layout showing each transistor, the first metal layer 1M, the contact connecting each transistor and the first metal layer 1M, and the via connecting the first metal layer 1M and the second metal layer 2M of the pixel Pix4 (fifth embodiment).

[0311] For the constituent elements of the pixel Pix4 of the ninth (fifth) embodiment that are the same as those of the pixel Pix of the comparative example or the pixels Pixl, Pix2, Pix3, and Pix5 of the second to fourth embodiments and the sixth to eighth embodiments, the same reference numerals are attached, and the description is omitted.

[0312] Each transistor is formed of an active region and a layer of polysilicon or the like, and is wired-connected to the first metal layer 1M via a contact as necessary. In Figure 21 In the pixel Pix4, the transistor Tr42 is a switching transistor for writing a pixel signal of a negative polarity, and the transistor Tr41 is a switching transistor for writing a pixel signal of a positive polarity. The transistor Tr41 and the transistor Tr42 are formed in mirror image with the center line 131 within one pixel as a reference.

[0313] Further, the source follower circuit 61 (constituted of the transistor Tr3 and the transistor Tr7) and the source follower circuit 62 (constituted of the transistor Tr4 and the transistor Tr8) are formed in mirror image with the center line 131 as a reference.

[0314] The connection wiring 133 is connected to the source of the transistor Tr42, the gate of the transistor Tr4, and the hold capacitor Cs2. The connection wiring 132 is connected to the source of the transistor Tr41, the gate of the transistor Tr3, and the hold capacitor Csl. The connection wiring 133 and the connection wiring 132 are formed in mirror image. The gate electrode of the transistor Tr45 that performs switching of a pixel signal of a positive polarity and the gate electrode of the transistor Tr46 that performs switching of a pixel signal of a negative polarity are independent. Further, the gate electrode of the transistor Tr45 and the gate electrode of the transistor Tr46 are respectively connected to the wiring S+ and S- arranged in the row direction for the same row of pixels.

[0315] In the through holes illustrated in the gates of the transistors Tr7, Tr8, Tr41, Tr42, Tr45, and Tr46, and the drains of the transistors Tr7 and Tr8, contacts not illustrated are also provided. Thus, the gates of the transistors Tr7, Tr8, Tr41, Tr42, Tr45, and Tr46, and the drains of the transistors Tr7 and Tr8 are connected to the second metal layer 2M via the contacts and the through holes.

[0316] The power supply lines 134 and 135 for supplying the power supply voltage VDD are provided at both left and right ends within one pixel, and are provided as a guard pattern to suppress crosstalk from the connection lines 132 or 133 formed of the first metal layer 1M of the left and right adjacent pixels. Thus, the holding capacitors Csl and Cs2 can hold a stable voltage without being affected by unnecessary voltage. Further, the power supply lines 134 and 135 are also used as lines for connecting the power supply voltage VDD potential in the upper and lower pixels.

[0317] Here, as described above, the transistors Tr41, Tr42, Tr45, and Tr46 are LowVth NMOS transistors. In the ion implantation regions 136 and 137 of the transistors Tr45 and Tr46, and the ion implantation regions 151 and 152 of the transistors Tr41 and Tr42, ions are implanted in a manner to become a threshold voltage Vth different from that of other normal NMOS transistors. Actually, one mask is made which combines the patterns of the ion implantation regions 136, 137, 151, and 152. Then, ions which have passed through the mask are implanted into the active regions under the gates of the transistors Tr41, Tr42, Tr45, and Tr46. Thus, the transistors Tr41, Tr42, Tr45, and Tr46 are adjusted to the desired threshold voltage Vth. In the pixel Pix4, ion implantation is performed so that the threshold voltage Vth of the transistors Tr41, Tr42, Tr45, and Tr46 becomes +0.4 V.

[0318] In the above description, the case where the threshold voltage Vth of the transistors Tr41 and Tr42 and the threshold voltage Vth of the transistors Tr45 and Tr46 are the same voltage is described. In the case where the threshold voltage Vth of the transistors Tr41 and Tr42 and the threshold voltage Vth of the transistors Tr45 and Tr46 are different, the first mask for the ion implantation regions 136 and 137 and the second mask for the ion implantation regions 151 and 152 are made different masks. Then, ion implantation is performed so that the threshold voltage Vth of the transistors Tr41 and Tr42 and the threshold voltage Vth of the transistors Tr45 and Tr46 respectively reach the desired threshold voltage Vth.

[0319] < TENTH EMBODIMENT >

[0320] Figure 22 is a plan layout of a pixel of the reflective liquid crystal display device of the tenth embodiment. In detail, Figure 22 is a plan layout showing each transistor, the first metal layer 1M, the contact connecting each transistor and the first metal layer 1M, and the via connecting the first metal layer 1M and the second metal layer 2M of the pixel Pix5 (the sixth embodiment).

[0321] Among the constituent elements of the pixel Pix5 of the tenth (sixth) embodiment, the same reference numerals are attached to the constituent elements common to the pixel Pix of the comparative example or the pixels Pix1 to Pix4 of the second to fifth embodiments and the seventh to ninth embodiments, and the explanation is omitted.

[0322] Each transistor is formed of an active region and a layer of polysilicon or the like, and is wired-connected to the first metal layer 1M via a contact as necessary. In Figure 22 In the tenth embodiment, the transistor Tr42 is a switching transistor for writing a pixel signal of a negative polarity, and the transistor Tr41 is a switching transistor for writing a pixel signal of a positive polarity. The transistor Tr41 and the transistor Tr42 are formed in mirror image with the center line 131 within one pixel as a reference.

[0323] Further, the source follower circuit 63 (composed of the transistor Tr33 and the transistor Tr7) and the source follower circuit 64 (composed of the transistor Tr34 and the transistor Tr8) are formed in mirror image with the center line 131 as a reference.

[0324] The connection wiring 133 is connected to the source of the transistor Tr42, the gate of the transistor Tr34, and the hold capacitor Cs2. The connection wiring 132 is connected to the source of the transistor Tr41, the gate of the transistor Tr33, and the hold capacitor Cs1. The connection wiring 133 and the connection wiring 132 are formed in mirror image. The gate electrode of the transistor Tr35 which performs switching of a pixel signal of a positive polarity and the gate electrode of the transistor Tr36 which performs switching of a pixel signal of a negative polarity are independent. Further, the gate electrode of the transistor Tr35 and the gate electrode of the transistor Tr36 are respectively connected to the wiring S+ and S- which are arranged in the row direction for the same row of pixels.

[0325] In the vias illustrated in the gate of each of the transistors Tr7, Tr8, Tr41, Tr42, Tr35, and Tr36, and the drain of each of the transistors Tr7 and Tr8, a contact which is not illustrated is also arranged. Thus, the gate of each of the transistors Tr7, Tr8, Tr41, Tr42, Tr35, and Tr36, and the drain of each of the transistors Tr7 and Tr8 are connected to the second metal layer 2M via the contact and the via.

[0326] The power supply lines 134 and 135 that supply the power supply voltage VDD are arranged at both left and right ends within one pixel, and are arranged as a guard pattern in a manner to suppress crosstalk from the connection lines 132 or 133 made of the first metal layer 1M of the left and right adjacent pixels. Thus, the holding capacitances Cs1 and Cs2 can hold a stable voltage without being affected by unnecessary voltage. Further, the power supply lines 134 and 135 are also used as lines that connect the power supply voltage VDD potential in the upper and lower pixels.

[0327] Here, as described above, the transistors Tr35 and Tr36 are depletion type NMOS transistors. In the ion implantation regions 136 and 137 of the transistors Tr35 and Tr36, ions are implanted in a manner to become a threshold voltage Vth different from other normal NMOS transistors. Actually, a mask is made with the pattern of the ion implantation regions 136 and 137. Then, ions that have passed through the mask are implanted into the active region under the gate of the transistors Tr35 and Tr36. Thus, the transistors Tr35 and Tr36 are adjusted to the desired threshold voltage Vth. In the pixel Pix5, ion implantation is performed so that the threshold voltage Vth of the transistors Tr45 and Tr46 becomes 0 V.

[0328] In addition, as described above, the transistors Tr41 and Tr42 are LowVth NMOS transistors. In the ion implantation regions 151 and 152 of the transistors Tr41 and Tr42, ions are implanted in a manner to become a threshold voltage Vth different from other normal NMOS transistors. Actually, a mask is made with the pattern of the ion implantation regions 151 and 152. Then, ions that have passed through the mask are implanted into the active region under the gate of the transistors Tr41 and Tr42. Thus, the transistors Tr41 and Tr42 are adjusted to the desired threshold voltage Vth. In the pixel Pix5, ion implantation is performed so that the threshold voltage Vth of the transistors Tr41 and Tr42 becomes +0.4 V.

[0329] Further, as described above, the transistors Tr33 and Tr34 are depletion type PMOS transistors. In the ion implantation regions 141 and 142 of the transistors Tr33 and Tr34, ions are implanted in a manner to become a threshold voltage Vth different from other normal PMOS transistors. Actually, a mask is made with the pattern of the ion implantation regions 141 and 142. Then, ions that have passed through the mask are implanted into the active region under the gate of the transistors Tr33 and Tr34. Thus, the transistors Tr33 and Tr34 are adjusted to the desired threshold voltage Vth. In the pixel Pix5, ion implantation is performed so that the threshold voltage Vth of the transistors Tr33 and Tr34 becomes +0.4 V.

[0330] Further, the transistors Tr41 and Tr42 are LowVth NMOS transistors, and the transistors Tr35 and Tr36 are depletion-mode NMOS transistors. Further, the transistors Tr33 and Tr34 are depletion-mode PMOS transistors. Therefore, the first mask of the patterns of the ion implantation regions 136 and 137, the second mask of the patterns of the ion implantation regions 141 and 142, and the third mask of the patterns of the ion implantation regions 151 and 152 are different masks.

[0331] Further, in the pixel Pix5, the transistors Tr41 and Tr42 are LowVth NMOS transistors, and the transistors Tr35 and Tr36 are depletion-mode NMOS transistors. Although the transistors Tr41, Tr42, Tr35, and Tr36 are all NMOS transistors, the threshold voltages Vth are different. In this structure, the manufacturing becomes complicated, and therefore it is also possible to consider that the threshold voltages Vth of the transistors Tr41, Tr42, Tr35, and Tr36 are unified to the same voltage with priority given to cost. In this case, one mask of the patterns of the ion implantation regions 151 and 152 and the ion implantation regions 136 and 137 is fabricated. Then, ion implantation is performed on the active regions under the gates of the transistors Tr41, Tr42, Tr35, and Tr36. Thereby, the transistors Tr41, Tr42, Tr35, and Tr36 are adjusted to the desired threshold voltages Vth.

[0332] <Notes>

[0333] Figure 3 Each transistor in the pixels of the portion (the frame portion) 13a of the reflective liquid crystal display device 13, to which the diffused plurality of wavelength channels are not incident, is preferably a transistor of a normal threshold voltage Vth, rather than a LowVth or depletion-mode transistor. Thereby, the leakage current at the portion 13a of the reflective liquid crystal display device 13 is suppressed, and therefore it is possible to suppress power consumption.

[0334] The technical scope of the present embodiment is not limited to the above-described embodiment, and can be appropriately changed within the scope of the gist of the present embodiment.

[0335] Industrial Applicability

[0336] The optical node device of the present embodiment can be used, for example, for an optical network.

[0337] Explanation of Symbols

[0338] 10 WSS array

[0339] 11 Input / output section

[0340] 12 Optical system

[0341] 13 reflective liquid crystal display device

[0342] 16 collimator lens

[0343] 21, 22, 23 lens

[0344] 24 dispersion element

[0345] 61, 62, 63, 64 source follower circuit

[0346] Pix, Pix1, Pix2, Pix3, Pix4, Pix5 pixel

[0347] Tr1,..., Tr8, Tr15, Tr16, Tr25, Tr26, Tr33, Tr34, Tr35, Tr36, Tr41, Tr42, Tr45, Tr46 transistor Cs1, Cs2 hold capacitor

[0348] LC liquid crystal display element

[0349] LCM liquid crystal display body

[0350] PE pixel electrode

[0351] CE common electrode

Claims

1. An optical node device comprising: liquid crystal display device; An input / output unit having an input port and an output port, wherein the input port receives incident light and the output port emits outgoing light corresponding to each wavelength included in the incident light; a dispersion element that spatially disperses light of each wavelength included in the incident light according to each wavelength and emits the emitted light toward the input / output unit; as well as a lens that focuses the light of each wavelength dispersed by the dispersion element onto the surface of the liquid crystal display device according to each wavelength, and emits the light of each wavelength reflected by the liquid crystal display device toward the dispersion element side, The liquid crystal display device is provided with a plurality of pixels at intersections where a plurality of groups of pixel data lines, each group of which includes a positive polarity pixel data line and a negative polarity pixel data line, intersect a plurality of row scan lines, wherein the positive polarity pixel data lines are supplied with positive polarity pixel signals, the negative polarity pixel data lines are supplied with negative polarity pixel signals, and the row scan lines are supplied with row scan signals, and each of the plurality of pixels includes: A display element having a liquid crystal layer sandwiched between opposing pixel electrodes and a common electrode; A first holding capacitor, configured to hold the positive polarity pixel signal; a first transistor, a source-drain path of which is connected between the positive polarity pixel data line and the first holding capacitor, and a gate of which is supplied with the row scanning signal; a second holding capacitor, configured to hold the pixel signal of negative polarity; a second transistor, a source-drain path of which is connected between the negative polarity pixel data line and the second holding capacitor, and a gate of which is supplied with the row scanning signal; a first source follower circuit comprising a third transistor, wherein the voltage of the first holding capacitor is input to a gate of the third transistor; a second source follower circuit comprising a fourth transistor, wherein the voltage of the second holding capacitor is input to a gate of the fourth transistor; a fifth transistor, a source-drain path of which is connected between the output terminal of the first source follower circuit and the pixel electrode, and a gate of which is supplied with a first control signal; and a sixth transistor, whose source-drain path is connected between the output terminal of the second source follower circuit and the pixel electrode, and whose gate is supplied with a second control signal that is alternately turned on with the first control signal; The first transistor, the second transistor, the fifth transistor, and the sixth transistor are transistors of the first conductivity type. The third transistor and the fourth transistor are transistors of the second conductivity type, The light of each wavelength focused by the lens is reflected in the direction determined by the routing according to each wavelength. The threshold voltages of the fifth transistor and the sixth transistor are different from 0.8V, The fifth transistor and the sixth transistor are low-threshold transistors.

2. The optical node device according to claim 1, wherein: The fifth transistor and the sixth transistor are depletion-mode transistors.

3. The optical node device according to claim 1 or 2, wherein: The fifth transistor and the sixth transistor are transistors into which ions for changing a threshold voltage are implanted.

4. The optical node device according to claim 1 or 2, wherein: The fifth transistor and the sixth transistor are N-channel MOS transistors.

5. The optical node device according to claim 1, wherein: Threshold voltages of the first transistor, the second transistor, the fifth transistor, and the sixth transistor are different from 0.8V.

6. The optical node device according to claim 5, wherein: The first transistor and the second transistor are low-threshold transistors.

7. The optical node device according to claim 5, wherein: The first transistor, the second transistor, the fifth transistor, or the sixth transistor is a depletion-mode transistor.

8. The optical node device according to any one of claims 5 to 7, wherein: A threshold voltage of the first transistor and the second transistor is different from a threshold voltage of the fifth transistor and the sixth transistor.

9. The optical node device according to any one of claims 5 to 7, wherein: The first transistor, the second transistor, the fifth transistor, and the sixth transistor are N-channel MOS transistors.

10. The optical node device according to any one of claims 5 to 7, wherein: The first transistor, the second transistor, the fifth transistor, and the sixth transistor are transistors into which ions for changing a threshold voltage are implanted.

11. The optical node device according to claim 10, wherein: The fifth transistor and the sixth transistor are transistors into which ions are implanted through a first mask, and the first transistor and the second transistor are transistors into which ions are implanted through a second mask different from the first mask.

12. The optical node device according to claim 1, wherein: The threshold voltages of the third transistor and the fourth transistor are different from -0.4V.

13. The optical node device according to claim 12, wherein: The fifth transistor and the sixth transistor are depletion-mode transistors.

14. The optical node device according to claim 12 or 13, wherein: The fifth transistor and the sixth transistor are transistors into which ions for changing a threshold voltage are implanted.

15. The optical node device according to claim 12 or 13, wherein: The third transistor and the fourth transistor are low-threshold transistors.

16. The optical node device according to claim 12 or 13, wherein: The third transistor and the fourth transistor are depletion-mode transistors.

17. The optical node device according to claim 14, wherein: The third transistor and the fourth transistor are transistors into which ions for changing a threshold voltage are implanted.

18. The optical node device according to claim 12 or 13, wherein: The third transistor and the fourth transistor are P-channel MOS transistors, and the fifth transistor and the sixth transistor are N-channel MOS transistors.

19. The optical node device according to claim 17, wherein: The fifth transistor and the sixth transistor are transistors into which ions are implanted through a first mask, and the third transistor and the fourth transistor are transistors into which ions are implanted through a second mask different from the first mask.

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