Display panel, display device

Abstract

A display panel and a display device, wherein the display panel includes a pixel driving circuit, the pixel driving circuit includes a driving transistor (T2) and an eighth transistor (T8), a first electrode of the eighth transistor (T8) connected to the first electrode of the driving transistor (T2), and a second electrode connected to a third initial signal line (Vinit3). The display panel also includes a base substrate (90), a first active layer, a first conductive layer, and a third initial signal line (Vinit3). The first active layer is located on one side of the substrate (90), and the first active layer includes an eighth active portion (78), a second active portion (72), a ninth active portion (79), a tenth active portion (710), and an eleventh active portion (711). The eighth active portion (78) is connected between the ninth active portion (79) and the tenth active portion (710), and the eleventh active portion (711) is connected to one side of the second active portion (72). The eighth active portion (78) is used to form a channel region of the eighth transistor (T8), the second active portion (72) is used to form a channel region of the driving transistor (T2), and the ninth active portion (79) is electrically connected to the eleventh active portion (711). The first conductive layer is located on the first active layer. The first conductive layer is on a side facing away from the base substrate (90), the first conductive layer includes a first reset signal line (Re1) and a first conductive portion (11), the positive projection of the first reset signal line (Re1) on the base substrate extends along a first direction (X) and covers the positive projection of the eighth active portion (78) on the base substrate, a partial structure of the first reset signal line (Re1) is used to form the gate of the eighth transistor (T8), the positive projection of the first conductive portion (11) on the base substrate covers the positive projection of the second active portion (72) on the base substrate, and the first conductive portion (11) is used to form the gate of the driving transistor (T2); and the third initial signal line (Vinit3) is electrically connected to the tenth active portion (710).

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] In related art, parasitic capacitance exists between the gate and source of the driver transistor in the pixel driver circuit. During the reset phase of the pixel driver circuit, the gate voltage of the driver transistor is initialized to an initial voltage. Under the coupling effect of the above-mentioned parasitic capacitance, the source voltage of the driver transistor also changes accordingly. When resetting different grayscales during the reset phase, the change in the gate voltage of the driver transistor varies, and thus the change in the source voltage of the driver transistor also varies. This, in turn, results in different source voltages of the driver transistor after the reset phase is completed, and different Vgs (gate-source voltage difference) of the driver transistor. At the same time, because the Vgs of the driver transistor affects its threshold voltage, the display panel may experience afterimage problems.

[0003] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute prior art known to ordinary technicians in the field. Summary of the Invention

[0004] According to one aspect of the present disclosure, a display panel is provided, wherein the display panel includes a pixel driving circuit, the pixel driving circuit includes a driving transistor and an eighth transistor, the first electrode of the eighth transistor is connected to the first electrode of the driving transistor, and the second electrode is connected to a third initial signal line, the display panel also includes: a base substrate, a first active layer, a first conductive layer, and the third initial signal line. A first active layer is located on one side of the base substrate, the first active layer includes an eighth active portion, a second active portion, a ninth active portion, a tenth active portion, and an eleventh active portion, the eighth active portion is connected between the ninth active portion and the tenth active portion, the eleventh active portion is connected to one side of the second active portion, the eighth active portion is used to form a channel region of the eighth transistor, the second active portion is used to form a channel region of the driving transistor, and the ninth active portion is electrically connected to the eleventh active portion; a first conductive layer is located on a side of the first active layer away from the base substrate, the first conductive layer includes a first reset signal line and a first conductive portion, the orthographic projection of the first reset signal line on the base substrate extends along a first direction and covers the orthographic projection of the eighth active portion on the base substrate, a portion of the first reset signal line is used to form a gate of the eighth transistor, the orthographic projection of the first conductive portion on the base substrate covers the orthographic projection of the second active portion on the base substrate, and the first conductive portion is used to form the gate of the driving transistor; the third initial signal line is electrically connected to the tenth active portion.

[0005] In an exemplary embodiment of the present disclosure, the display panel further includes: a third conductive layer, the third conductive layer is located on a side of the first conductive portion away from the base substrate, and the third conductive layer includes the third initial signal line.

[0006] In an exemplary embodiment of the present disclosure, an orthographic projection of the third initial signal line on the base substrate at least partially overlaps with an orthographic projection of the first reset signal line on the base substrate.

[0007] In an exemplary embodiment of the present disclosure, the display panel further includes: a fourth conductive layer, the fourth conductive layer is located on the side of the third conductive layer away from the base substrate, the fourth conductive layer includes a first bridging portion, and the first bridging portion is connected to the third initial signal line and the tenth active portion through vias respectively.

[0008] In an exemplary embodiment of the present disclosure, the pixel driving circuit further includes a fifth transistor, a first electrode of the fifth transistor being connected to a power line, and a second electrode being connected to the first electrode of the driving transistor, the first active layer further including: a fifth active portion, the fifth active portion being used to form a channel region of the fifth transistor, the fifth active portion being connected to a side of the eleventh active portion away from the second active portion; the first conductive layer further including: an enable signal line, the orthographic projection of the enable signal line on the base substrate extending along the first direction, covering the orthographic projection of the fifth active portion on the base substrate, and being located between the orthographic projection of the eleventh active portion on the base substrate and the orthographic projection of the ninth active portion on the base substrate, a partial structure of the enable signal line being used to form a gate of the fifth transistor; the display panel further including a fourth conductive layer, the fourth conductive layer being located on a side of the first conductive layer away from the base substrate, the fourth conductive layer including: a second bridging portion, the second bridging portion being connected to the ninth active portion and the eleventh active portion through vias, respectively.

[0009] In an exemplary embodiment of the present disclosure, an orthographic projection of the ninth active portion on the base substrate is located between an orthographic projection of the first reset signal line on the base substrate and an orthographic projection of the enable signal line on the base substrate.

[0010] In an exemplary embodiment of the present disclosure, the pixel driving circuit further includes a sixth transistor and a seventh transistor, wherein the first electrode of the sixth transistor is connected to the second electrode of the driving transistor, and the gate is connected to the enable signal line; the first electrode of the seventh transistor is connected to the second initial signal line, the second electrode is connected to the second electrode of the sixth transistor, and the gate is connected to the first reset signal line. The first active layer further includes: a sixth active portion, a seventh active portion, and a twelfth active portion, wherein the sixth active portion is connected to a side of the second active portion away from the eleventh active portion and is used to form a channel region of the sixth transistor; the seventh active portion is connected to a side of the sixth active portion away from the second active portion and is used to form a channel region of the seventh transistor; and the twelfth active portion is connected to a side of the seventh active portion away from the sixth active portion. The first conductive layer further includes an enable signal line, the orthographic projection of the enable signal line on the base substrate extending along the first direction and covering the orthographic projection of the sixth active portion on the base substrate, and a portion of the structure of the enable signal line is used to form the gate of the sixth transistor; the orthographic projection of the first reset signal line on the base substrate covers the orthographic projection of the seventh active portion on the base substrate, and a portion of the structure of the first reset signal line is used to form the gate of the seventh transistor. The display panel further includes a fourth conductive layer, the fourth conductive layer being located on a side of the first conductive layer facing away from the base substrate. The fourth conductive layer includes the second initial signal line, which is connected to the twelfth active portion via a via.

[0011] In an exemplary embodiment of the present disclosure, the pixel driving circuit further includes a third transistor and a fourth transistor, wherein the first electrode of the third transistor is connected to the gate of the driving transistor, the second electrode is connected to the second electrode of the driving transistor, and the gate is connected to a second gate line; the first electrode of the fourth transistor is connected to a first initial signal line, the second electrode is connected to the gate of the driving transistor, and the gate is connected to a second reset signal line. The display panel further includes: a second active layer and a third conductive layer, wherein the second active layer is located on a side of the first conductive layer facing away from the base substrate, and the second active layer includes: a third active portion and a fourth active portion, wherein the third active portion is used to form a channel region of the third transistor; and the fourth active portion is used to form a channel region of the fourth transistor. The third conductive layer is located on the side of the second active layer facing away from the base substrate, and the third conductive layer includes: the second gate line and the second reset signal line, the orthographic projection of the second gate line on the base substrate extends along the first direction and covers the orthographic projection of the third active part on the base substrate, and a partial structure of the second gate line is used to form a top gate of the third transistor; the orthographic projection of the second reset signal line on the base substrate extends along the first direction and covers the orthographic projection of the fourth active part on the base substrate, and a partial structure of the second reset signal line is used to form a top gate of the fourth transistor.

[0012] In an exemplary embodiment of the present disclosure, the display panel further includes: a second conductive layer located between the first conductive layer and the second active layer, the second conductive layer including: a third gate line and a third reset signal line, the orthographic projection of the third gate line on the base substrate extending along the first direction and covering the orthographic projection of the third active portion on the base substrate, a partial structure of the third gate line being used to form a bottom gate of the third transistor, the orthographic projection of the third reset signal line on the base substrate extending along the first direction and covering the orthographic projection of the fourth active portion on the base substrate, and a partial structure of the third reset signal line being used to form a bottom gate of the fourth transistor.

[0013] In an exemplary embodiment of the present disclosure, the orthographic projection of the second gate line on the base substrate is located on a side where the orthographic projection of the first conductive portion on the base substrate is away from the orthographic projection of the first reset signal line on the base substrate; the orthographic projection of the second reset signal line on the base substrate is located on a side where the orthographic projection of the second gate line on the base substrate is away from the orthographic projection of the first conductive portion on the base substrate.

[0014] In an exemplary embodiment of the present disclosure, the pixel driving circuit further includes a sixth transistor and a seventh transistor, wherein a first electrode of the sixth transistor is connected to a second electrode of the driving transistor, a first electrode of the seventh transistor is connected to a second initial signal line, and a second electrode is connected to a second electrode of the sixth transistor. The display panel further includes: a fourth conductive layer, the fourth conductive layer being located on a side of the third conductive layer away from the substrate, the fourth conductive layer including the second initial signal line; the first conductive layer further including the first initial signal line, the orthographic projection of the first initial signal line on the substrate extending along the first direction and being located on a side where the orthographic projection of the second reset signal line on the substrate is away from the orthographic projection of the second gate line on the substrate; the display panel includes a plurality of the pixel driving circuits distributed in the second direction and the first direction, the first direction being a row direction and the second direction being a column direction; the orthographic projection of the first initial signal line in the pixel driving circuit of the current row on the substrate at least partially overlaps with the orthographic projection of the second initial signal line in the pixel driving circuit of the previous row on the substrate.

[0015] In an exemplary embodiment of the present disclosure, the pixel driving circuit further includes a first transistor, wherein a first electrode of the first transistor is connected to a data line, a second electrode is connected to the first electrode of the driving transistor, and a gate is connected to a first gate line; the first active layer further includes: a first active portion, the first active portion is used to form a channel region of the first transistor; the first conductive layer further includes: a first gate line, the orthographic projection of the first gate line on the substrate extends along the first direction and covers the orthographic projection of the first active portion on the substrate, and a partial structure of the first gate line is used to form the gate of the first transistor; wherein the orthographic projection of the first gate line on the substrate is located between the orthographic projection of the second gate line on the substrate and the orthographic projection of the second reset signal line on the substrate; the display panel further includes: a fourth conductive layer and a fifth conductive layer; the fifth conductive layer is located on a side of the fourth conductive layer away from the substrate, the fifth conductive layer includes the data line, the orthographic projection of the data line on the substrate extends along the second direction, and the second direction intersects with the first direction.

[0016] In an exemplary embodiment of the present disclosure, the display panel includes a plurality of pixel driving circuits, and the plurality of pixel driving circuits include a first pixel driving circuit and a second pixel driving circuit adjacently distributed in the first direction; the first pixel driving circuit and the second pixel driving circuit are at least partially mirror-symmetrical.

[0017] In an exemplary embodiment of the present disclosure, the display panel also includes: a fourth conductive layer, the fourth conductive layer is located on the side of the first conductive layer away from the base substrate, the fourth conductive layer includes a first bridging portion, the first bridging portion is connected to the third initial signal line and the tenth active portion through vias respectively; the first active layer also includes: a thirteenth active portion, the thirteenth active portion is connected between the tenth active portion in the first pixel driving circuit and the tenth active portion in the second pixel driving circuit; the first bridging portion in the first pixel driving circuit is reused as the first bridging portion in the second pixel driving circuit.

[0018] In an exemplary embodiment of the present disclosure, the eighth transistor in the first pixel driving circuit is multiplexed as the eighth transistor in the second pixel driving circuit.

[0019] In an exemplary embodiment of the present disclosure, the fourth conductive layer further includes: a second bridging portion, the second bridging portion being connected to the ninth active portion and the eleventh active portion through vias; the eighth active portion in the first pixel driving circuit being multiplexed as the eighth active portion in the second pixel driving circuit; the ninth active portion in the first pixel driving circuit being multiplexed as the ninth active portion in the second pixel driving circuit; and the tenth active portion in the first pixel driving circuit being multiplexed as the tenth active portion in the second pixel driving circuit. The display panel further includes: a ninth bridging portion; the second bridging portion in the first pixel driving circuit being further connected to the ninth bridging portion through a via, and the second bridging portion in the second pixel driving circuit being connected to the ninth bridging portion through a via to connect the ninth active portion in the first pixel driving circuit.

[0020] In an exemplary embodiment of the present disclosure, the display panel further includes: a second conductive layer, the second conductive layer is located on a side of the first conductive layer away from the base substrate, and the second conductive layer includes the ninth bridge portion.

[0021] In an exemplary embodiment of the present disclosure, the pixel driving circuit further includes a capacitor and a fifth transistor, wherein a first electrode of the fifth transistor is connected to a power line and a second electrode is connected to the first electrode of the driving transistor. The first electrode of the capacitor is connected to the gate of the driving transistor, and the second electrode is connected to the power line. The first active layer further includes: a fifth active portion and a fourteenth active portion. The fifth active portion is connected to a side of the eleventh active portion away from the second active portion and is used to form a channel region of the fifth transistor. The fourteenth active portion is connected between the fifth active portion in the first pixel driving circuit and the fifth active portion in the second pixel driving circuit. The display panel further includes: a second conductive layer, a fourth conductive layer, and a fifth conductive layer. The second conductive layer is located on a side of the first conductive layer facing away from the base substrate. The second conductive layer includes: a second conductive portion and a first connecting portion. The orthographic projection of the second conductive portion on the base substrate at least partially overlaps with the orthographic projection of the first conductive portion on the base substrate. The first conductive portion also forms the first electrode of the capacitor, and the second conductive portion forms the second electrode of the capacitor. The first connecting portion is connected between the second conductive portion in the first pixel driving circuit and the second conductive portion in the second pixel driving circuit. The fourth conductive layer is located on a side of the second conductive layer facing away from the base substrate, and includes a third bridging portion, the third bridging portion being connected to the fourteenth active portion and the first connecting portion via vias. A fifth conductive layer is located on a side of the fourth conductive layer facing away from the base substrate, and includes the power line, the orthographic projection of the power line on the base substrate extending along a second direction, the second direction intersecting the first direction; and a power line in the first pixel driving circuit and a power line in the second pixel driving circuit being connected to the third bridging portion via vias.

[0022] In an exemplary embodiment of the present disclosure, the display panel further includes: a light shielding layer located between the first active layer and the base substrate, wherein the orthographic projection of the light shielding layer on the base substrate covers the orthographic projection of the second active portion on the base substrate.

[0023] In an exemplary embodiment of the present disclosure, the display panel also includes: a fourth conductive layer, the fourth conductive layer is located on the side of the first conductive layer away from the base substrate, the fourth conductive layer includes a first bridging portion, the first bridging portion is connected to the third initial signal line and the tenth active portion through vias respectively; the first bridging portion in the first pixel driving circuit and the first bridging portion in the second pixel driving circuit share part of the structure with each other, and are connected to the third initial signal line through the same via.

[0024] In an exemplary embodiment of the present disclosure, the pixel driving circuit is used to drive a light-emitting unit, and the pixel driving circuit further includes: a first transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and a capacitor; the first electrode of the first transistor is connected to a data line, the second electrode is connected to the first electrode of the driving transistor, and the gate is connected to the first gate line; the first electrode of the third transistor is connected to the gate of the driving transistor, the second electrode is connected to the second electrode of the driving transistor, and the gate is connected to the second gate line; the first electrode of the fourth transistor is connected to a first initial signal line, the second electrode is connected to the gate of the driving transistor, and the gate is connected to a second reset signal line; the first electrode of the fifth transistor is connected to a power line, the second electrode is connected to the first electrode of the driving transistor, and the gate is connected to an enable signal line; the first electrode of the sixth transistor is connected to the second electrode of the driving transistor, the second electrode is connected to the first electrode of the light-emitting unit, and the gate is connected to the enable signal line; the first electrode of the seventh transistor is connected to the second initial signal line, the second electrode is connected to the second electrode of the sixth transistor, and the gate is connected to the first reset signal line; the capacitor is connected between the power line and the gate of the driving transistor. Wherein, the driving transistor, the first transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor are P-type transistors, and the third transistor and the fourth transistor are N-type transistors.

[0025] According to one aspect of the present disclosure, a display device is provided, comprising the above-mentioned display panel.

[0026] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0028] Figure 1 This is a schematic structural diagram of a pixel driving circuit in an exemplary embodiment of a display panel disclosed herein;

[0029] Figure 2 for Figure 1 A timing diagram of each node in a driving method of a pixel driving circuit;

[0030] Figure 3 A structural diagram of an exemplary embodiment of a display panel disclosed herein;

[0031] Figure 4 for Figure 3 Structural layout of the middle light-shielding layer;

[0032] Figure 5 for Figure 3 The structural layout of the first active layer;

[0033] Figure 6 for Figure 3 The structural layout of the first conductive layer;

[0034] Figure 7 for Figure 3 The structural layout of the second conductive layer;

[0035] Figure 8 for Figure 3 The structural layout of the second active layer;

[0036] Figure 9 for Figure 3 The structural layout of the third conductive layer;

[0037] Figure 10 for Figure 3 The structural layout of the fourth conductive layer;

[0038] Figure 11 for Figure 3 The structural layout of the fifth conductive layer;

[0039] Figure 12 for Figure 3 Structural layout of the middle light-shielding layer and the first active layer;

[0040] Figure 13 for Figure 3 Structural layout of the middle light-shielding layer, the first active layer, and the first conductive layer;

[0041] Figure 14 for Figure 3 Structural layout of the middle light-shielding layer, the first active layer, the first conductive layer, and the second conductive layer;

[0042] Figure 15 for Figure 3 Structural layout of the middle light-shielding layer, the first active layer, the first conductive layer, the second conductive layer, and the second active layer;

[0043] Figure 16 for Figure 3 Structural layout of the middle light-shielding layer, the first active layer, the first conductive layer, the second conductive layer, the second active layer, and the third conductive layer;

[0044] Figure 17 for Figure 3 Structural layout of the middle light-shielding layer, the first active layer, the first conductive layer, the second conductive layer, the second active layer, the third conductive layer, and the fourth conductive layer;

[0045] Figure 18 for Figure 3 A partial cross-sectional view along the dotted line AA;

[0046] Figure 19 A structural diagram of another exemplary embodiment of a display panel disclosed herein;

[0047] Figure 20 for Figure 19 The structural layout of the first active layer;

[0048] Figure 21 for Figure 19 The structural layout of the fourth conductive layer;

[0049] Figure 22 for Figure 19 Structural layout of the middle light-shielding layer, the first active layer, and the first conductive layer;

[0050] Figure 23 for Figure 19 Structural layout of the middle light-shielding layer, the first active layer, the first conductive layer, and the second conductive layer;

[0051] Figure 24 for Figure 19 Structural layout of the middle light-shielding layer, the first active layer, the first conductive layer, the second conductive layer, and the second active layer;

[0052] Figure 25 for Figure 19 Structural layout of the middle light-shielding layer, the first active layer, the first conductive layer, the second conductive layer, the second active layer, and the third conductive layer;

[0053] Figure 26 for Figure 19 Structural layout of the middle light-shielding layer, the first active layer, the first conductive layer, the second conductive layer, the second active layer, the third conductive layer, and the fourth conductive layer;

[0054] Figure 27 A structural diagram of another exemplary embodiment of a display panel disclosed herein;

[0055] Figure 28 for Figure 27 The structural layout of the first active layer;

[0056] Figure 29 for Figure 27 The structural layout of the second conductive layer;

[0057] Figure 30 for Figure 27 The structural layout of the fourth conductive layer;

[0058] Figure 31 for Figure 27Structural layout of the middle light-shielding layer, the first active layer, and the first conductive layer;

[0059] Figure 32 for Figure 27 Structural layout of the middle light-shielding layer, the first active layer, the first conductive layer, and the second conductive layer;

[0060] Figure 33 for Figure 27 Structural layout of the middle light-shielding layer, the first active layer, the first conductive layer, the second conductive layer, and the second active layer;

[0061] Figure 34 for Figure 27 Structural layout of the middle light-shielding layer, the first active layer, the first conductive layer, the second conductive layer, the second active layer, and the third conductive layer;

[0062] Figure 35 for Figure 27 Structural layout of the middle light-shielding layer, the first active layer, the first conductive layer, the second conductive layer, the second active layer, the third conductive layer, and the fourth conductive layer;

[0063] Figure 36 A structural diagram of another exemplary embodiment of a display panel disclosed herein;

[0064] Figure 37 A structural diagram of another exemplary embodiment of a display panel disclosed herein;

[0065] Figure 38 for Figure 37 The structure layout of the fifth conductive layer in the display panel is shown;

[0066] Figure 39 A structural layout diagram of a light shielding layer, a first active layer, a first conductive layer, a second conductive layer, a second active layer, a third conductive layer, and a fourth conductive layer in another exemplary embodiment of a display panel disclosed herein;

[0067] Figure 40 for Figure 39 The structure layout of the fourth conductive layer in the display panel is shown;

[0068] Figure 41 This is a structural diagram of another exemplary embodiment of the display panel disclosed herein.

[0069] Figure 42 A structural layout diagram of a light shielding layer, a first active layer, a first conductive layer, a second conductive layer, a second active layer, a third conductive layer, and a fourth conductive layer in another exemplary embodiment of a display panel disclosed herein;

[0070] Figure 43 for Figure 42 The structure layout of the fourth conductive layer in the display panel is shown;

[0071] Figure 44 A structural layout diagram of a light shielding layer, a first active layer, a first conductive layer, a second conductive layer, a second active layer, a third conductive layer, and a fourth conductive layer in another exemplary embodiment of a display panel disclosed herein;

[0072] Figure 45 for Figure 44 The structural layout of the second conductive layer;

[0073] Figure 46 for Figure 44 The structural layout of the fourth conductive layer;

[0074] Figure 47 A structural layout diagram of a light shielding layer, a first active layer, a first conductive layer, a second conductive layer, a second active layer, a third conductive layer, and a fourth conductive layer in another exemplary embodiment of a display panel disclosed herein;

[0075] Figure 48 for Figure 47 The structural layout of the second conductive layer;

[0076] Figure 49 for Figure 47 The structural layout of the fourth conductive layer;

[0077] Figure 50 A structural diagram of another exemplary embodiment of a display panel disclosed herein;

[0078] Figure 51 for Figure 50 The structural layout of the fifth conductive layer;

[0079] Figure 52 A structural diagram of another exemplary embodiment of a display panel disclosed herein;

[0080] Figure 53 for Figure 52 The structural layout of the fifth conductive layer. DETAILED DESCRIPTION

[0081] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art. Like reference numerals in the figures represent like or similar structures, and thus their detailed description will be omitted.

[0082] The terms "a", "an", and "said" are used to indicate that there are one or more elements / components / etc.; the terms "including" and "having" are used to express an open-ended inclusive meaning and mean that there may be additional elements / components / etc. in addition to the listed elements / components / etc.

[0083] like Figure 1 FIG. 1 is a schematic diagram of a pixel driving circuit in an exemplary embodiment of a display panel of the present disclosure. The pixel driving circuit may include a first transistor T1, a driving transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and a capacitor C. Among them, the first electrode of the driving transistor T2 is connected to the second node N2, the second electrode is connected to the third node N3, and the gate is connected to the first node N1; the first electrode of the first transistor T1 is connected to the data signal terminal Da, the second electrode is connected to the second node N2, and the gate is connected to the first gate driving signal terminal G1; the first electrode of the third transistor T3 is connected to the first node N1, the second electrode is connected to the third node N3, and the gate is connected to the second gate driving signal terminal G2; the first electrode of the fourth transistor T4 is connected to the first initial signal terminal Vinit1, the second electrode is connected to the first node N1, and the gate is connected to the second reset signal terminal Re2; the first electrode of the fifth transistor T5 is connected to the first power supply terminal VDD, the second electrode is connected to the second node N2, and the gate is connected to the enable signal terminal EM; the first electrode of the sixth transistor T6 is connected to the third node N3, the second electrode is connected to the fourth node N4, and the gate is connected to the enable signal terminal EM; the first electrode of the seventh transistor T7 is connected to the second initial signal terminal Vinit2, the second electrode is connected to the fourth node N4, and the gate is connected to the first reset signal terminal Re1; the first electrode of the eighth transistor T8 is connected to the third initial signal terminal Vinit3, the second electrode is connected to the second node N2, and the gate is connected to the first reset signal terminal Re1. The second electrode of the seventh transistor T7 can be used to connect to the first electrode of the light-emitting unit OLED, and the other electrode of the light-emitting unit OLED can be used to connect to the second power supply terminal VSS. The first transistor T1, the driving transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 can be P-type transistors, and the third transistor T3 and the fourth transistor T4 can be N-type transistors. Furthermore, in other exemplary embodiments, the third initial signal terminal can also share stable signal terminals such as the first initial signal terminal, the second initial signal terminal, the first power supply terminal, and the second power supply terminal. When the third initial signal terminal Vinit3 shares the first power supply terminal VDD, the voltage of the third initial signal terminal Vinit3 can be 0.5 to 1.5 times the voltage of the first power supply terminal VDD. For example, the voltage of the third initial signal terminal Vinit3 can be 0.5 times, 1 times, 1.5 times, etc., of the voltage of the first power supply terminal VDD.

[0084] like Figure 2As shown, Figure 1 A timing diagram of each node in a driving method for a pixel driving circuit, wherein G1 represents the timing of the first gate driving signal terminal, G2 represents the timing of the second gate driving signal terminal, Re1 represents the timing of the first reset signal terminal, Re2 represents the timing of the second reset signal terminal, and EM represents the timing of the enable signal terminal. The driving method for the pixel driving circuit may include four stages: a reset stage t1, a threshold compensation stage t2, a buffer stage t3, and a light-emitting stage t4. In the reset stage t1, the enable signal terminal EM, the second reset signal terminal Re2, and the first gate driving signal terminal G1 output high-level signals, the second gate driving signal terminal G2 and the first reset signal terminal Re1 output low-level signals, the fourth transistor T4, the seventh transistor T7, and the eighth transistor T8 are turned on, the first initial signal terminal Vinit1 inputs the first initial signal to the first node N1, the third initial signal terminal Vinit3 inputs the third initial signal to the second node N2, and the second initial signal terminal Vinit2 inputs the second initial signal to the fourth node. During the threshold compensation phase t2, the enable signal terminal EM, the second gate drive signal terminal G2, and the first reset signal terminal Re1 output high-level signals, while the second reset signal terminal Re2 and the first gate drive signal terminal G1 output low-level signals. The third transistor T3 and the first transistor T1 are turned on, and the data signal terminal Da writes the compensation voltage Vdata+Vth to the first node N1, where Vdata is the voltage of the data signal terminal and Vth is the threshold voltage of the drive transistor. During the buffering phase t3, the enable signal terminal EM, the first reset signal terminal Re1, and the first gate drive signal terminal G1 output high-level signals, while the second gate drive signal terminal G2 and the second reset signal terminal Re2 output low-level signals, and all transistors are turned off. During the light-emitting phase t4, the first reset signal terminal Re1 and the first gate drive signal terminal G1 output high-level signals, while the enable signal terminal EM, the second gate drive signal terminal G2, and the second reset signal terminal Re2 output low-level signals. The fifth transistor T5 and the sixth transistor T6 are turned on, and the drive transistor T2 emits light under the action of the voltage Vdata+Vth stored in the capacitor C. It should be understood that in other exemplary embodiments, the driving method may not include the buffer stage; the fourth transistor T4 and the seventh transistor T7 may be turned on at different stages. During the threshold compensation stage t2, the duration of the effective level (low level) of the first gate drive signal terminal G1 may be shorter than the duration of the effective level (high level) of the second gate drive signal terminal G2. During the threshold compensation stage t2, the first gate drive signal terminal G1 may scan a row of pixel drive circuits, and the second gate drive signal terminal G2 may scan multiple rows of pixel drive circuits, for example, two rows of pixel drive circuits, row by row.

[0085] In the related art, the pixel driving circuit does not have an eighth transistor. There is parasitic capacitance between the gate and source of the driving transistor in the pixel driving circuit. During the reset phase of the pixel driving circuit, the gate voltage of the driving transistor is initialized to the initial voltage. Under the above-mentioned parasitic capacitance coupling, the source voltage of the driving transistor also changes accordingly. When resetting different grayscales during the reset phase, the change in the gate voltage of the driving transistor is different, and thus the change in the source voltage of the driving transistor is also different, which in turn leads to different Vgs (gate-source voltage difference) of the driving transistor after the reset phase is completed. At the same time, because the Vgs of the driving transistor affects its threshold voltage, the display panel may have an afterimage problem. In this exemplary embodiment, the pixel driving circuit can use the fourth transistor T4 to reset the first node N1 and the eighth transistor T8 to reset the second node N2 during the reset phase, so that under different data signals, the pixel driving circuit can reset the gate-source voltage difference of the driving transistor to the same value, thereby improving the problem of afterimage on the display panel.

[0086] In this exemplary embodiment, the display panel may further include a base substrate, a light shielding layer, a first active layer, a first conductive layer, a second conductive layer, a second active layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer stacked in sequence, and an insulating layer may be provided between the above layers. Figure 3-17 As shown, Figure 3 This is a structural diagram of an exemplary embodiment of the display panel disclosed herein. Figure 4 for Figure 3 The structural layout of the middle shading layer, Figure 5 for Figure 3 The structural layout of the first active layer, Figure 6 for Figure 3 The structural layout of the first conductive layer, Figure 7 for Figure 3 The structural layout of the second conductive layer, Figure 8 for Figure 3 The structural layout of the second active layer, Figure 9 for Figure 3 The structural layout of the third conductive layer, Figure 10 for Figure 3 The structural layout of the fourth conductive layer, Figure 11 for Figure 3 The structural layout of the fifth conductive layer, Figure 12 for Figure 3 The structural layout of the middle light-shielding layer and the first active layer, Figure 13 for Figure 3 The structural layout of the middle light-shielding layer, the first active layer, and the first conductive layer, Figure 14 for Figure 3 The structural layout of the middle light-shielding layer, the first active layer, the first conductive layer, and the second conductive layer, Figure 15 for Figure 3 The structural layout of the middle light-shielding layer, the first active layer, the first conductive layer, the second conductive layer, and the second active layer, Figure 16 for Figure 3 The structural layout of the middle light-shielding layer, the first active layer, the first conductive layer, the second conductive layer, the second active layer, and the third conductive layer, Figure 17 for Figure 3 The display panel may include multiple Figure 1 The pixel driving circuit shown in FIG. Figure 3 As shown, the plurality of pixel driving circuits may include a first pixel driving circuit P1 and a second pixel driving circuit P2 adjacently distributed in a first direction X, and the first pixel driving circuit P1 and the second pixel driving circuit P2 may be arranged in a mirror-symmetrical manner. Figure 3 The repeating units shown, multiple repeating units can be distributed in an array.

[0087] like Figure 3 、 4 As shown in FIG. 12 , the light shielding layer may include two light shielding portions 61 distributed in the first direction X, and a connecting portion 62 connected between the light shielding portions 61. The light shielding layer may be a conductor structure, for example, the light shielding layer may be a light shielding metal layer.

[0088] like Figure 3 、 5As shown in Figures 12 and 13, the first active layer may include a first active portion 71, a second active portion 72, a fifth active portion 75, a sixth active portion 76, a seventh active portion 77, an eighth active portion 78, a ninth active portion 79, a tenth active portion 710, an eleventh active portion 711, a twelfth active portion 712, a thirteenth active portion 713, and a fourteenth active portion 714. The first active portion 71 may be used to form a channel region of the first transistor T1; the second active portion 72 may be used to form a channel region of the driving transistor T2; the fifth active portion 75 may be used to form a channel region of the fifth transistor T5; the sixth active portion 76 may be used to form a channel region of the sixth transistor; the seventh active portion 77 may be used to form a channel region of the seventh transistor T7; and the eighth active portion 78 may be used to form a channel region of the eighth transistor T8. The ninth active portion 79 and the tenth active portion 710 are respectively connected to the two sides of the eighth active portion 78; the eleventh active portion 711 is connected to one side of the second active portion 72; the twelfth active portion 712 is connected to the side of the seventh active portion 77 away from the sixth active portion 76; the thirteenth active portion 713 is connected between the tenth active portion 710 in the first pixel driving circuit P1 and the tenth active portion 710 in the second pixel driving circuit P2; the fourteenth active portion 714 is connected between the fifth active portion 75 in the first pixel driving circuit P1 and the fifth active portion 75 in the second pixel driving circuit P2. The first active layer can be formed of polysilicon, and accordingly, the first transistor T1, the driving transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 can be P-type low-temperature polycrystalline silicon thin film transistors. Figure 12 As shown, the orthographic projection of the light shielding portion 61 on the base substrate can cover the orthographic projection of the second active portion 72 on the base substrate. The light shielding portion 61 can shield the second active portion 72, thereby reducing the influence of light on the characteristics of the driving transistor T2.

[0089] like Figure 3 、 6 As shown in FIG. 13 , the first conductive layer may include a first initial signal line Vinit1, a first gate line G1, a first conductive portion 11, an enable signal line EM, and a first reset signal line Re1. The orthographic projection of the first initial signal line Vinit1 on the base substrate, the orthographic projection of the first gate line G1 on the base substrate, the orthographic projection of the enable signal line EM on the base substrate, and the orthographic projection of the first reset signal line Re1 on the base substrate all extend along the first direction X. The first initial signal line Vinit1 may be used to provide Figure 1 The first initial signal terminal. The orthographic projection of the first gate line G1 on the substrate covers the orthographic projection of the first active portion 71 on the substrate. Part of the structure of the first gate line G1 can be used to form the gate of the first transistor. The enable signal line EM can be used to provide Figure 1The enable signal end in the middle, the orthographic projection of the enable signal line EM on the substrate can cover the orthographic projection of the fifth active portion 75 on the substrate and the orthographic projection of the sixth active portion 76 on the substrate, and a portion of the structure of the enable signal line EM can be used to form the gate of the fifth transistor and the gate of the sixth transistor respectively. The first reset signal line Re1 can be used to provide Figure 1 The first reset signal terminal in the circuit board, the orthographic projection of the first reset signal line Re1 on the substrate can cover the orthographic projection of the seventh active portion 77 on the substrate, and the orthographic projection of the eighth active portion 78 on the substrate. Part of the structure of the first reset signal line Re1 can be used to form the gate of the seventh transistor and the gate of the eighth transistor, respectively. The orthographic projection of the first conductive portion 11 on the substrate can cover the orthographic projection of the second active portion 72 on the substrate. The first conductive portion 11 can be used to form the gate of the driving transistor T2 and the first electrode of the capacitor C. The light shielding layer can be connected to a stable power supply terminal, for example, Figure 1 The first power supply terminal, the first initial signal terminal, the second initial signal terminal, the third initial signal terminal, etc., the light shielding layer can be connected to the stable voltage terminals located in other conductive layers through vias located around the display area of ​​the display panel. For example, the light shielding layer can be connected to the power line of the fifth conductive layer through vias located around the display area of ​​the display panel. The light shielding portion 61 can stabilize the voltage of the first conductive portion 11, thereby reducing the voltage fluctuation of the gate of the driving transistor T2 during the light-emitting stage. Figure 6 、 13 As shown, the orthographic projection of the enable signal line EM on the substrate can be located between the orthographic projection of the eleventh active portion 711 on the substrate and the orthographic projection of the ninth active portion 79 on the substrate. The orthographic projection of the ninth active portion 79 on the substrate is located between the orthographic projection of the first reset signal line Re1 on the substrate and the orthographic projection of the enable signal line EM on the substrate. In addition, the display panel can use the first conductive layer as a mask to perform a conductorization process on the first active layer, that is, the area of ​​the first active layer covered by the first conductive layer can form the channel region of the transistor, and the area not covered by the first conductive layer forms a conductor structure. In addition, in this exemplary embodiment, the orthographic projection of a structure on the substrate extends along a certain direction, which can be understood as the orthographic projection of the structure on the substrate extends along the direction as a whole, that is, the orthographic projection of the structure on the substrate can extend straight or bend along the direction.

[0090] like Figure 3 、 7 As shown in FIG. 14 , the second conductive layer may include a third gate line 2G2, a third reset signal line 2Re2, a second conductive portion 22, and a first connecting portion 21. The third gate line 2G2 may be used to provide Figure 1The second gate drive signal terminal, the third reset signal line 2Re2 can be used to provide Figure 1 The second reset signal terminal in the substrate. The orthographic projection of the third gate line 2G2 on the substrate and the orthographic projection of the third reset signal line 2Re2 on the substrate can both extend along the first direction X. The orthographic projection of the second conductive portion 22 on the substrate can at least partially overlap with the orthographic projection of the first conductive portion on the substrate, and the second conductive portion 22 can be used to form a second electrode of the capacitor. The first connecting portion 21 can be connected between adjacent second conductive portions 22. In a plurality of repeating units spaced apart in the first direction X, the second conductive portions 22 can be connected to each other in sequence. The second conductive portion 22 can be provided with an opening 221.

[0091] like Figure 3 、 8 As shown in Figures 1 and 15 , the second active layer may include an active portion 81, and the active portion 81 may include a third active portion 813 and a fourth active portion 814. The third active portion 813 may be used to form the channel region of the third transistor T3, and the fourth active portion 814 may be used to form the channel region of the fourth transistor T4. The orthographic projection of the third reset signal line 2Re2 on the substrate may overlap the orthographic projection of the fourth active portion 814 on the substrate, and a portion of the structure of the third reset signal line 2Re2 may be used to form the bottom gate of the fourth transistor T4. The orthographic projection of the third gate line 2G2 on the substrate may overlap the orthographic projection of the third active portion 813 on the substrate, and a portion of the structure of the third gate line 2G2 may be used to form the bottom gate of the third transistor T3. The second active layer may be formed of indium gallium zinc oxide, and accordingly, the third and fourth transistors may be N-type oxide thin film transistors.

[0092] like Figure 3 、 9 As shown in FIG. 16 , the third conductive layer may include a third initial signal line Vinit3, a second reset signal line 3Re2, and a second gate line 3G2. The orthographic projection of the third initial signal line Vinit3 on the substrate, the orthographic projection of the second reset signal line 3Re2 on the substrate, and the orthographic projection of the second gate line 3G2 on the substrate may all extend along the first direction X. The third initial signal line Vinit3 may be used to provide Figure 1 The second reset signal line 3Re2 can be used to provide Figure 1The second reset signal end in the second reset signal line 3Re2 can be connected to the third reset signal line 2Re2 through a via hole, and the via hole connecting the second reset signal line 3Re2 and the third reset signal line 2Re2 can be located in the edge wiring area of ​​the display panel. The orthographic projection of the second reset signal line 3Re2 on the base substrate can cover the orthographic projection of the fourth active portion 814 on the base substrate, and a part of the structure of the second reset signal line 3Re2 can be used to form the top gate of the fourth transistor T4. The second gate line 3G2 can be used to provide Figure 1 The second gate drive signal terminal in the second gate line 3G2 can be connected to the third gate line 2G2 through a via hole. The via hole connecting the second gate line 3G2 and the third gate line 2G2 can be located in the edge wiring area of ​​the display panel. The orthographic projection of the second gate line 3G2 on the base substrate can cover the orthographic projection of the third active portion 813 on the base substrate. Part of the structure of the second gate line 3G2 can be used to form the top gate of the third transistor T3. Figure 3 、 16 As shown, the orthographic projection of the third initial signal line Vinit3 on the substrate can at least partially overlap with the orthographic projection of the first reset signal line Re1 on the substrate. This arrangement can improve the integration of the pixel driving circuit and reduce the layout area of ​​the pixel driving circuit. The orthographic projection of the second reset signal line 3Re2 on the substrate can be located on the side of the orthographic projection of the second gate line 3G2 on the substrate away from the orthographic projection of the first conductive part 11 on the substrate. The orthographic projection of the first gate line G1 on the substrate can be located between the orthographic projection of the second gate line 3G2 on the substrate and the orthographic projection of the second reset signal line 3Re2 on the substrate. In addition, the display panel can use the third conductive layer as a mask to perform conductor processing on the second active layer, that is, the area covered by the third conductive layer in the second active layer can form the channel region of the transistor, and the area not covered by the third conductive layer forms a conductor structure.

[0093] like Figure 3 、 10 As shown in FIG. 17 , the fourth conductive layer may include a second initial signal line Vinit2, a first bridge portion 41, a second bridge portion 42, a third bridge portion 43, a fourth bridge portion 44, a fifth bridge portion 45, a sixth bridge portion 46, a seventh bridge portion 47, and an eighth bridge portion 48. The orthographic projection of the second initial signal line Vinit2 on the substrate may extend along the first direction X. The second initial signal line Vinit2 may be used to provide Figure 1The second initial signal end in. The first bridge portion 41 can be connected to the tenth active portion 710 and the third initial signal line Vinit3 through the via H, respectively, to connect the first electrode of the eighth transistor T8 to the third initial signal end, wherein the first bridge portion 41 in the first pixel driving circuit P1 and the first bridge portion 41 in the second pixel driving circuit reuse part of the structure and share the same via to connect the third initial signal line Vinit3. It should be noted that the black squares in this exemplary embodiment represent vias, and this exemplary embodiment only annotates the positions of some vias. The second bridge portion 42 can be connected to the ninth active portion 79 and the eleventh active portion 711 through vias, respectively, to connect the second electrode of the eighth transistor T8 and the first electrode of the driving transistor T2. The third bridge portion 43 can be connected to the fourteenth active portion 714 and the first connection portion 21 through vias, respectively, to connect the second electrode of the capacitor and the first electrode of the fifth transistor. Wherein, the third bridge portion 43 can be mirror-symmetrical with the mirror-symmetrical plane of the first pixel driving circuit P1 and the second pixel driving circuit P2. The fourth bridge portion 44 can connect the first active layer between the sixth active portion 76 and the second active portion 72, and the second active layer of the third active portion 813 on the side away from the fourth active portion 814, through vias, to connect the second electrode of the driving transistor T2, the second electrode of the third transistor T3, and the first electrode of the sixth transistor T6. The fifth bridge portion 45 can connect the second active layer between the third active portion 813 and the fourth active portion 814, and the first conductive portion 11 through vias, to connect the first electrode of the third transistor T3, the second electrode of the fourth transistor T4, and the gate of the driving transistor T2. The orthographic projection of the via connecting between the fifth bridge portion 55 and the first conductive portion 11 on the substrate is located within the orthographic projection of the opening 221 on the substrate, so as to prevent the conductive structure within the via from being electrically connected to the second conductive portion 22. The sixth bridge portion 46 can be connected to the second active layer of the fourth active portion 814 away from the third active portion 813 and the first initial signal line Vinit1 through vias, thereby connecting the first electrode of the fourth transistor T4 and the first initial signal terminal. The seventh bridge portion 47 can be connected to the first active layer between the sixth active portion 76 and the seventh active portion 77 through vias to connect the second electrode of the seventh transistor. The seventh bridge portion 47 can be used to connect the first electrode of the light-emitting unit. The eighth bridge portion 48 can be connected to the first active layer of the first active portion 71 away from the second active portion 72 through vias to connect the first electrode of the first transistor. The display panel can also include a plurality of pixel driving circuits distributed in an array along a first direction X and a second direction Y. The first direction X and the second direction Y can intersect. For example, the first direction X can be a row direction and the second direction Y can be a column direction.Among them, the orthographic projection of the first initial signal line Vinit1 in the pixel driving circuit of this row on the substrate can at least partially overlap with the orthographic projection of the second initial signal line Vinit2 in the pixel driving circuit of the previous row on the substrate. This setting can improve the integration of the pixel driving circuit and reduce the layout area of ​​the pixel driving circuit.

[0094] In other exemplary embodiments, when the third initial signal terminal Vinit3 shares the first power supply terminal VDD, as shown in FIG. Figure 3 、 17 As shown, the power line VDD can be directly connected to the first bridge portion 41 through a via, thereby connecting the first electrode of the eighth transistor and the first power supply terminal VDD. The via connected between the power line VDD and the first bridge portion 41 can be located at the position of the via originally connected between the third initial signal line Vinit3 and the first bridge portion 41. In this case, the display panel can retain the third initial signal line Vinit3 or remove the third initial signal line Vinit3.

[0095] like Figure 3 、 11 As shown, the fifth conductive layer may include a power line VDD, a data line Da, and a bridge portion 51. The power line VDD may be used to provide Figure 1 The first power supply terminal in the data line Da can be used to provide Figure 1 The data signal end in. The orthographic projection of the power line VDD on the base substrate and the orthographic projection of the data line Da on the base substrate can both extend along the second direction Y. The data line Da can be connected to the eighth bridge portion 48 through a via to connect the first electrode of the first transistor. The power line VDD in the first pixel driving circuit and the power line VDD in the second pixel driving circuit are respectively connected to the third bridge portion 43 through vias to connect the first power supply terminal, the second electrode of the capacitor C, and the first electrode of the fifth transistor T5. The bridge portion 51 can be connected to the seventh bridge portion 47 through a via, and the bridge portion 51 can be used to connect the first electrode of the light-emitting unit. The second conductive portion 22 and the power line VDD connected in the first direction X can form a grid structure, so that the power line impedance load (IR loading) can be reduced, such as Figure 3 As shown, the orthographic projection of the power line VDD on the substrate can also cover the orthographic projection of the fourth active portion 814 on the substrate, thereby reducing the impact of light on the characteristics of the fourth transistor T4. At the same time, the orthographic projection of the power line VDD on the substrate can also at least partially overlap with the orthographic projection of the third active portion 813 on the substrate. Similarly, the power line VDD can reduce the impact of light on the characteristics of the third transistor T3.

[0096] like Figure 18 As shown, Figure 3Partial cross-sectional view along dotted line AA in FIG. The display panel may further include a first insulating layer 91, a second insulating layer 92, a third insulating layer 93, a fourth insulating layer 94, a fifth insulating layer 95, a dielectric layer 96, a passivation layer 97, and a planarization layer 98, wherein the base substrate 90, the light shielding layer, the first insulating layer 91, the first active layer, the second insulating layer 92, the first conductive layer, the third insulating layer 93, the second conductive layer, the fourth insulating layer 94, the second active layer, the fifth insulating layer 95, the third conductive layer, the dielectric layer 96, the fourth conductive layer, the passivation layer 97, the planarization layer 98, and the fifth conductive layer are stacked in sequence. The first insulating layer 91, the second insulating layer 92, the third insulating layer 93, the fourth insulating layer 94, and the fifth insulating layer 95 can be silicon oxide layers; the dielectric layer 96 and the passivation layer 97 can be silicon nitride layers; the material of the planar layer 98 can be an organic material, such as polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), silicon-glass bonding structure (SOG), etc. The base substrate 90 can include a glass substrate, a barrier layer, and a polyimide layer stacked in sequence, and the barrier layer can be an inorganic material. The material of the first conductive layer, the second conductive layer, and the third conductive layer can be molybdenum, aluminum, copper, titanium, niobium, or an alloy thereof, or a molybdenum / titanium alloy or a laminate, etc. The material of the fourth conductive layer and the fifth conductive layer can be a metal material, such as molybdenum, aluminum, copper, titanium, niobium, or an alloy thereof, or a molybdenum / titanium alloy or a laminate, etc., or a titanium / aluminum / titanium laminate.

[0097] like Figure 19 As shown, Figure 19 This is a structural diagram of another exemplary embodiment of a display panel disclosed herein. The display panel may include multiple Figure 1 The pixel driving circuits shown include a first pixel driving circuit P1 and a second pixel driving circuit P2 adjacently arranged in a first direction X. At least portions of the first pixel driving circuit P1 and the second pixel driving circuit P2 may be arranged in mirror-symmetric configurations. The display panel may also include a base substrate, a light shielding layer, a first active layer, a first conductive layer, a second conductive layer, a second active layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer stacked in sequence.

[0098] Figure 19 The light shielding layer in the display panel is shown Figure 3 The light shielding layer layout structure in the display panel shown is the same. The light shielding layer may include a plurality of light shielding portions 61 distributed in the first direction X, and connecting portions 62 connected between the light shielding portions 61 .

[0099] Figure 19 The first conductive layer in the display panel is Figure 3The layout structure of the first conductive layer in the display panel shown is the same. The first conductive layer may include a first initial signal line Vinit1, a first gate line G1, a first conductive portion 11, an enable signal line EM, and a first reset signal line Re1.

[0100] Figure 19 The second conductive layer in the display panel is Figure 3 The second conductive layer in the display panel shown has the same layout structure. The second conductive layer may include a third gate line 2G2 , a third reset signal line 2Re2 , a second conductive portion 22 , and a first connecting portion 21 .

[0101] Figure 19 The second active layer in the display panel is Figure 3 The second active layer layout structure in the display panel shown is the same. The second active layer may include an active portion 81 . The active portion 81 may include a third active portion 813 and a fourth active portion 814 .

[0102] Figure 19 The third conductive layer in the display panel is Figure 3 The layout structure of the third conductive layer in the display panel shown is the same, and the third conductive layer may include a third initial signal line Vinit3, a second reset signal line 3Re2, and a second gate line 3G2.

[0103] Figure 19 The fifth conductive layer in the display panel is Figure 3 The fifth conductive layer in the display panel shown has the same layout structure. The fifth conductive layer may include a power line VDD, a data line Da, and a bridge portion 51 .

[0104] Figure 19 The display panel shown is Figure 3 The display panel shown in FIG. 1 is different only in the structures of the first active layer and the fourth conductive layer. Figure 20-26 As shown, Figure 20 for Figure 19 The structural layout of the first active layer, Figure 21 for Figure 19 The structural layout of the fourth conductive layer, Figure 22 for Figure 19 The structural layout of the middle light-shielding layer, the first active layer, and the first conductive layer, Figure 23 for Figure 19 The structural layout of the middle light-shielding layer, the first active layer, the first conductive layer, and the second conductive layer, Figure 24 for Figure 19 The structural layout of the middle light-shielding layer, the first active layer, the first conductive layer, the second conductive layer, and the second active layer, Figure 25 for Figure 19 The structural layout of the middle light-shielding layer, the first active layer, the first conductive layer, the second conductive layer, the second active layer, and the third conductive layer, Figure 26 for Figure 19 Structural layout of the middle light-shielding layer, the first active layer, the first conductive layer, the second conductive layer, the second active layer, the third conductive layer, and the fourth conductive layer.

[0105] like Figure 19 、 20 As shown in Figures 22, 23, 24 and 25, the first active layer also includes a first active portion 71, a second active portion 72, a fifth active portion 75, a sixth active portion 76, a seventh active portion 77, an eighth active portion 78, a ninth active portion 79, a tenth active portion 710, an eleventh active portion 711, a twelfth active portion 712, a thirteenth active portion 713 and a fourteenth active portion 714. Figure 20 The first active layer and Figure 4 The first active layer shown is different in that Figure 20 In the first active layer shown, the tenth active portion 710 in the second pixel driving circuit P2 is not mirror-symmetrically arranged with the tenth active portion 710 in the first pixel driving circuit P1, and the area of ​​the tenth active portion 710 in the second pixel driving circuit P2 projected on the substrate is slightly smaller than the area of ​​the tenth active portion 710 in the first pixel driving circuit P1 projected on the substrate.

[0106] like Figure 19 、 21 As shown in Figures 25 and 26 , the fourth conductive portion may also include a second initial signal line Vinit2, a first bridge portion 41, a second bridge portion 42, a third bridge portion 43, a fourth bridge portion 44, a fifth bridge portion 45, a sixth bridge portion 46, a seventh bridge portion 47, and an eighth bridge portion 48. The first bridge portion 41 in the first pixel driving circuit P1 may be reused as the first bridge portion in the second pixel driving circuit P2. That is, the second pixel driving circuit does not include the first bridge portion 41, and the tenth active portion 710 in the second pixel driving circuit is connected to the third initial signal line Vinit3 via the first bridge portion 41 in the first pixel driving circuit.

[0107] Figure 19 The display panel shown can leave a large space at the location of the tenth active portion 710 in the second pixel driving circuit to facilitate layout arrangement of other structures. Figure 22-24 As shown, Figure 19 Other structures of the display panel shown are similar to Figure 3 The display panel is the same as shown. Figure 19 As shown, Figure 19 The cross-sectional view along the dotted line AA Figure 18 same.

[0108] like Figure 27 The structure of another exemplary embodiment of the display panel disclosed in the present invention is shown in FIG. The display panel may include multiple Figure 1 The pixel driving circuit shown includes a first pixel driving circuit P1 and a second pixel driving circuit P2 adjacently arranged in a first direction X. At least portions of the structures of the first pixel driving circuit P1 and the second pixel driving circuit P2 may be arranged in mirror symmetry. The display panel may also include a base substrate, a light shielding layer, a first active layer, a first conductive layer, a second conductive layer, a second active layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer stacked in sequence. In this exemplary embodiment, the eighth transistor in the first pixel driving circuit may be reused as the eighth transistor in the second pixel driving circuit.

[0109] Figure 27 The light shielding layer in the display panel is shown Figure 3 The light shielding layer layout structure in the display panel shown is the same. The light shielding layer may include a plurality of light shielding portions 61 distributed in the first direction X, and connecting portions 62 connected between the light shielding portions 61 .

[0110] Figure 27 The first conductive layer in the display panel is Figure 3 The layout structure of the first conductive layer in the display panel shown is the same. The first conductive layer may include a first initial signal line Vinit1, a first gate line G1, a first conductive portion 11, an enable signal line EM, and a first reset signal line Re1.

[0111] Figure 27 The second active layer in the display panel is Figure 3 The second active layer layout structure in the display panel shown is the same. The second active layer may include an active portion 81 . The active portion 81 may include a third active portion 813 and a fourth active portion 814 .

[0112] Figure 27 The third conductive layer in the display panel is Figure 3 The layout structure of the third conductive layer in the display panel shown is the same, and the third conductive layer may include a third initial signal line Vinit3, a second reset signal line 3Re2, and a second gate line 3G2.

[0113] Figure 27 The fifth conductive layer in the display panel is Figure 3 The fifth conductive layer in the display panel shown has the same layout structure. The fifth conductive layer may include a power line VDD, a data line Da, and a bridge portion 51 .

[0114] Figure 27 The display panel shown is Figure 3 The display panels shown are different only in the structures of the first active layer, the second conductive layer, and the fourth conductive layer. Figure 28-35 As shown, Figure 28 for Figure 27The structural layout of the first active layer, Figure 29 for Figure 27 The structural layout of the second conductive layer, Figure 30 for Figure 27 The structural layout of the fourth conductive layer, Figure 31 for Figure 27 The structural layout of the middle light-shielding layer, the first active layer, and the first conductive layer, Figure 32 for Figure 27 The structural layout of the middle light-shielding layer, the first active layer, the first conductive layer, and the second conductive layer, Figure 33 for Figure 27 The structural layout of the middle light-shielding layer, the first active layer, the first conductive layer, the second conductive layer, and the second active layer, Figure 34 for Figure 27 The structural layout of the middle light-shielding layer, the first active layer, the first conductive layer, the second conductive layer, the second active layer, and the third conductive layer, Figure 35 for Figure 27 Structural layout of the middle light-shielding layer, the first active layer, the first conductive layer, the second conductive layer, the second active layer, the third conductive layer, and the fourth conductive layer.

[0115] like Figure 27 、 28 As shown, the first active layer also includes a first active portion 71 , a second active portion 72 , a fifth active portion 75 , a sixth active portion 76 , a seventh active portion 77 , an eighth active portion 78 , a ninth active portion 79 , a tenth active portion 710 , an eleventh active portion 711 , a twelfth active portion 712 , and a fourteenth active portion 714 . Figure 28 The first active layer and Figure 4 The first active layer shown is different in that Figure 28 In the first active layer shown, the eighth active portion 78 in the first pixel driving circuit P1 is multiplexed into the eighth active portion 78 in the second pixel driving circuit P2, the ninth active portion 79 in the first pixel driving circuit P1 is multiplexed into the ninth active portion 79 in the second pixel driving circuit P2, the tenth active portion 710 in the first pixel driving circuit P1 is multiplexed into the tenth active portion 710 in the second pixel driving circuit P2, and Figure 28 The first active layer shown does not have the thirteenth active portion 713. That is, the second pixel driving circuit P2 does not have the eighth active portion 78, the ninth active portion 79, and the tenth active portion 710.

[0116] like Figure 27 、 29 , 32-35, Figure 27The second conductive layer in the display panel shown may also include a third gate line 2G2, a third reset signal line 2Re2, a second conductive portion 22, and a first connecting portion 21. Furthermore, the second conductive layer may further include a ninth bridge portion 29. The ninth bridge portion 29 may be mirror-symmetric about the mirror-symmetric plane of the first pixel driving circuit P1 and the second pixel driving circuit P2. Furthermore, the ninth bridge portion 29 may also be located in other conductive layers, such as the first conductive layer, the third conductive layer, or other additional conductive layers.

[0117] like Figure 27 、 30 , 35, the fourth conductive portion may also include a second initial signal line Vinit2, a first bridge portion 41, a second bridge portion 42, a third bridge portion 43, a fourth bridge portion 44, a fifth bridge portion 45, a sixth bridge portion 46, a seventh bridge portion 47, and an eighth bridge portion 48. Among them, the first bridge portion 41 in the first pixel driving circuit P1 can be reused as the first bridge portion in the second pixel driving circuit P2. That is, the first bridge portion 41 is not provided in the second pixel driving circuit. In addition, the second bridge portion 42 in the first pixel driving circuit P1 includes three via-hole connecting portions, and the second bridge portion 42 in the first pixel driving circuit P1 is respectively connected to the ninth active portion 79, the eleventh active portion 711, and the ninth bridge portion 29 in the first pixel driving circuit P1 through the three via-hole connecting portions. The second bridge portion 42 in the second pixel driving circuit P2 includes two via connection portions, and the second bridge portion 42 in the second pixel driving circuit P2 is via-connected to the eleventh active portion 711 and the ninth bridge portion 29 in the second pixel driving circuit P2 through the two via connection portions.

[0118] Figure 27 The display panel shown can leave a large space at the location of the original eighth transistor in the second pixel driving circuit to facilitate layout arrangement of other structures. Figures 31-35 As shown, Figure 27 Other structures of the display panel shown are similar to Figure 3 The display panel is the same as shown. Figure 27 As shown, Figure 27 The cross-sectional view along the dotted line AA Figure 18 same.

[0119] like Figure 36 The figure shows the structure of another exemplary embodiment of the display panel disclosed herein. Figure 36 The structure shown includes two adjacent Figure 3The repeating unit shown. In these two repeating units, adjacent power lines VDD are connected. The orthographic projection of the power line VDD on the substrate can at least partially overlap with the orthographic projection of the second active layer connected between the third active portion 813 and the fourth active portion 814 on the substrate. The area of ​​overlap between the orthographic projection of the power line VDD on the substrate and the orthographic projection of the second active layer connected between the third active portion 813 and the fourth active portion 814 on the substrate is S1, and the area of ​​the orthographic projection of the second active layer connected between the third active portion 813 and the fourth active portion 814 on the substrate is S2. S1 / S2 can be greater than or equal to 90%, for example, S1 / S2 can be 90%, 95%, 100%, etc. This arrangement can stabilize the voltage of the second active layer connected between the third active portion 813 and the fourth active portion 814 via the power line VDD, thereby reducing voltage fluctuations on the gate of the driving transistor during the light-emitting phase.

[0120] like Figure 37 FIG. 1 is a structural diagram of another exemplary embodiment of the display panel disclosed herein. Figure 38 for Figure 37 The structure layout of the fifth conductive layer in the display panel is shown. Figure 37 The display panel shown is Figure 36 The display panel shown is different only in the structure of the power line VDD in the fifth conductive layer. Figure 37 As shown, the orthographic projection of the power line VDD on the substrate at least partially overlaps with the orthographic projection of the fifth bridge portion 45 on the substrate. The overlapping area of ​​the orthographic projection of the power line VDD on the substrate and the fifth bridge portion 45 on the substrate is S3, and the orthographic projection area of ​​the fifth bridge portion 45 on the substrate is S4. S3 / S4 can be greater than or equal to 80%, for example, 80%, 90%, 95%, etc. This arrangement stabilizes the voltage of the fifth bridge portion 45 via the power line VDD, thereby reducing voltage fluctuations on the gate of the driving transistor during the light-emitting phase.

[0121] like Figure 39 、 40 As shown, Figure 39 This is a structural layout diagram of a light shielding layer, a first active layer, a first conductive layer, a second conductive layer, a second active layer, a third conductive layer, and a fourth conductive layer in another exemplary embodiment of the display panel disclosed herein. Figure 40 for Figure 39 The structure layout of the fourth conductive layer in the display panel is shown. Figure 39 The hierarchical structures in the display panel are shown as follows Figure 36 The corresponding hierarchical structure in the display panel shown only differs in that Figure 39 The third bridge portion 43 in the fourth conductive layer of the display panel shown has a different structure. Figure 39 、 40As shown, the third bridge portion 43 may have a hollow portion 431, which may be located in the light-transmitting area of ​​the display panel. The light-transmitting area of ​​the display panel can be understood as the area not covered by the light-shielding layer, the first active layer, the first conductive layer, the second conductive layer, the second active layer, the third conductive layer, the fourth conductive layer, and the fifth conductive layer. This arrangement can improve the transmittance of the display panel.

[0122] like Figure 41 FIG. 1 is a structural diagram of another exemplary embodiment of a display panel disclosed herein. The display panel may include Figure 39 The structure of the display panel shown in FIG. 1 is a diagram illustrating a structure of a display panel. In addition, the display panel further includes a fifth conductive layer located on the side of the fourth conductive layer facing away from the base substrate. The fifth conductive layer may include a power line VDD and a data line Da. The orthographic projection of the hollow portion 431 on the third bridge portion 43 on the base substrate may intersect with the orthographic projection of the data line Da on the base substrate. Providing the hollow portion 431 on the third bridge portion 43 may further reduce the coupling effect of the third bridge portion 43 on the data line Da.

[0123] like Figure 39 、 40 As shown, the hollow portion 431 is a non-closed figure. It should be understood that the hollow portion can also be a closed figure, for example, Figure 42 、 43 As shown, Figure 42 This is a structural layout diagram of a light shielding layer, a first active layer, a first conductive layer, a second conductive layer, a second active layer, a third conductive layer, and a fourth conductive layer in another exemplary embodiment of the display panel disclosed herein. Figure 43 for Figure 42 The structure layout of the fourth conductive layer in the display panel is shown. Figure 42 The structure of the display panel shown is similar to Figure 39 The structure of the display panel shown only differs in the shape of the hollow portion 431 . The closed-loop hollow portion 431 can also improve the transmittance of the display panel and reduce the coupling effect of the third bridge portion 43 on the data line Da.

[0124] like Figure 44 、 45 , 46, Figure 44 This is a structural layout diagram of a light shielding layer, a first active layer, a first conductive layer, a second conductive layer, a second active layer, a third conductive layer, and a fourth conductive layer in another exemplary embodiment of the display panel disclosed herein. Figure 45 for Figure 44 The structural layout of the second conductive layer, Figure 46 for Figure 44 The structural layout of the fourth conductive layer. Figure 44 The hierarchical structures in the display panel are shown as follows Figure 36The difference between the corresponding hierarchical structures in the display panel shown is that the second conductive layer and the fourth conductive layer have different structures. Figure 45 As shown, the second initial signal line Vinit2 can be set in the second conductive layer, and the second conductive layer is close to the first active layer, so as to improve the yield rate of the via hole between the second initial signal line Vinit2 and the twelfth active portion. Figure 46 As shown, the fourth conductive layer may further include a connecting line 49, the orthographic projection of the connecting line 49 on the base substrate extending along the second direction Y, the connecting line 49 being connected between two sixth bridge portions 46 in the repeating units adjacent in the first direction X, and being connected between two sixth bridge portions 46 in the pixel driving circuits adjacent in the second direction Y. The connecting line 49 may connect the first initial signal line Vinit1 into a grid structure, thereby reducing the self-voltage drop of the first initial signal line Vinit1 and improving the reset effect of the gate of the driving transistor.

[0125] like Figure 44As shown, in the region of the dotted box B, the first reset signal line Re1, the second initial signal line Vinit2, and the third initial signal line Vinit3 extending along the first direction X are stacked in sequence. This results in a protrusion in the insulating layer between the third and fourth conductive layers, facing the fourth conductive layer, at the location of the dotted box B. This protrusion may cause the connecting line 49 to break at the location of the dotted box B. In this exemplary embodiment, at the location of the dotted box B, the orthographic projections of at least two of the three sides of the first reset signal line Re1, the second initial signal line Vinit2, and the third initial signal line Vinit3 on the same side in the second direction Y on the substrate may not overlap. This arrangement allows the protrusion to form a stepped structure, thereby reducing the risk of breaking the connecting line 49. For example, at the position of the dotted box B, the size of the orthogonal projection of the first reset signal line Re1 on the substrate in the second direction Y, the size of the orthogonal projection of the second initial signal line Vinit2 on the substrate in the second direction Y, and the size of the orthogonal projection of the third initial signal line Vinit3 on the substrate in the second direction Y increase successively, and the orthogonal projection of the third initial signal line Vinit3 on the substrate can cover the orthogonal projection of the first reset signal line Re1 on the substrate and the orthogonal projection of the second initial signal line Vinit2 on the substrate; for another example, at the position of the dotted box B, the size of the orthogonal projection of the first reset signal line Re1 on the substrate in the second direction Y, the size of the orthogonal projection of the second initial signal line Vinit2 on the substrate in the second direction Y, and the size of the orthogonal projection of the third initial signal line Vinit3 on the substrate in the second direction Y can be approximately the same, and the orthogonal projection of the first reset signal line Re1 on the substrate, the orthogonal projection of the second initial signal line Vinit2 on the substrate, and the orthogonal projection of the third initial signal line Vinit3 on the substrate are staggered with each other in the second direction Y.

[0126] like Figure 47 、 48 ,49, Figure 47 This is a structural layout diagram of a light shielding layer, a first active layer, a first conductive layer, a second conductive layer, a second active layer, a third conductive layer, and a fourth conductive layer in another exemplary embodiment of the display panel disclosed herein. Figure 48 for Figure 47 The structural layout of the second conductive layer, Figure 49 for Figure 47 The structural layout of the fourth conductive layer. Figure 47 The hierarchical structures in the display panel are shown as follows Figure 36 The difference between the corresponding hierarchical structures in the display panel shown is that the second conductive layer and the fourth conductive layer have different structures. Figure 48As shown, the second initial signal line Vinit2 can be set in the second conductive layer, and the second conductive layer is close to the first active layer, so as to improve the yield rate of the via hole between the second initial signal line Vinit2 and the twelfth active portion 712. Figure 49 As shown, the fourth conductive layer may further include a connecting line 410 and a bridge portion 411. In the same pixel driving circuit, the bridge portion 411 is connected to the second initial signal line Vinit2 and the twelfth active portion 712 through vias, respectively. The orthographic projection of the connecting line 410 on the base substrate extends along the second direction Y. The connecting line 410 is connected between two bridge portions 411 in adjacent repeating units in the first direction X, and is connected between two bridge portions 411 in adjacent pixel driving circuits in the second direction Y. The connecting line 410 can connect the second initial signal line Vinit2 into a grid structure, thereby reducing the voltage drop of the second initial signal line Vinit2 itself.

[0127] In the same display panel of other exemplary embodiments, the first initial signal line Vinit1 may be Figure 44 The structure shown is gridded, and the second initial signal line Vinit2 can be Figure 47 The structure shown is gridded. The connecting lines 49 and the connecting lines 410 can be arranged between different repeating units. For example, the connecting lines 49 and the connecting lines 410 can be alternately arranged in the first direction X.

[0128] like Figure 50 、 51 As shown, Figure 50 This is a structural diagram of another exemplary embodiment of the display panel disclosed herein. Figure 51 for Figure 50 The structural layout of the fifth conductive layer. Figure 50 The display panel shown includes Figure 44 The structure of the display panel is shown, and Figure 50 The display panel shown has a fifth conductive layer formed on the side of the fourth conductive layer facing away from the base substrate. Figure 51 The fifth conductive layer and Figure 36 The only difference between the fifth conductive layer and the adjacent repeating units is that a hollow portion 52 can be provided on the connected power line VDD. The hollow portion 52 can be located in the light-transmitting area of ​​the display panel. This arrangement can increase the transmittance of the display panel. In addition, the orthographic projection of the hollow portion 52 on the base substrate can overlap with the orthographic projection of the connecting line 49 on the base substrate. This arrangement can reduce the coupling effect between the power line VDD and the first initial signal line Vinit1. Figure 51As shown, the connected power lines VDD can be connected through two connecting portions 53. Accordingly, the hollow portion 52 can include a closed-loop hollow portion 522 and a non-closed-loop hollow portion 521. In addition, the hollow portion 52 can also include only a non-closed-loop hollow portion. For example, the connected power lines VDD can be connected through only one connecting portion 53.

[0129] like Figure 52 、 53 As shown, Figure 52 This is a structural diagram of another exemplary embodiment of the display panel disclosed herein. Figure 53 for Figure 52 The structural layout of the fifth conductive layer. Figure 52 The display panel shown includes Figure 47 The structure of the display panel is shown, and Figure 52 The display panel shown has a fifth conductive layer formed on the side of the fourth conductive layer facing away from the base substrate. Figure 52 The fifth conductive layer and Figure 37 The only difference between the fifth conductive layer and the adjacent repeating units is that a hollow portion 52 can be provided on the connected power line VDD. This hollow portion 52 can be located in the light-transmitting area of ​​the display panel, which can increase the transmittance of the display panel. In addition, the orthographic projection of the hollow portion 52 on the base substrate can overlap with the orthographic projection of the connecting line 410 on the base substrate, which can reduce the coupling between the power line VDD and the second initial signal line Vinit2. The hollow portion 52 can include a closed-loop hollow portion 522 and a non-closed-loop hollow portion 521.

[0130] This exemplary embodiment also provides a display device, which includes the above-mentioned display panel. The display device can be a mobile phone, a tablet computer, a television, or other display device.

[0131] Other embodiments of the present disclosure will readily occur to those skilled in the art after considering the specification and practicing what is disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the claims.

[0132] It should be understood that the present disclosure is not limited to the exact structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A display panel, wherein: The display panel includes a pixel driving circuit, the pixel driving circuit includes a driving transistor and an eighth transistor, a first electrode of the eighth transistor is connected to the first electrode of the driving transistor, and a second electrode is connected to a third initial signal line, and the display panel further includes: substrate; a first active layer located on one side of the base substrate, the first active layer comprising an eighth active portion, a second active portion, a ninth active portion, a tenth active portion, and an eleventh active portion, the eighth active portion being connected between the ninth active portion and the tenth active portion, the eleventh active portion being connected to one side of the second active portion, the eighth active portion being used to form a channel region of the eighth transistor, the second active portion being used to form a channel region of the driving transistor, and the ninth active portion being electrically connected to the eleventh active portion; a first conductive layer, located on a side of the first active layer facing away from the base substrate, the first conductive layer comprising a first reset signal line and a first conductive portion, an orthographic projection of the first reset signal line on the base substrate extending along a first direction and covering an orthographic projection of the eighth active portion on the base substrate, a portion of the first reset signal line being used to form a gate of the eighth transistor, an orthographic projection of the first conductive portion on the base substrate covering an orthographic projection of the second active portion on the base substrate, and the first conductive portion being used to form a gate of the driving transistor; The third initial signal line is electrically connected to the tenth active portion; The pixel driving circuit is used to drive the light-emitting unit, and the pixel driving circuit further includes a seventh transistor, a first electrode of the seventh transistor is connected to the second initial signal line, a second electrode is connected to the first electrode of the light-emitting unit, and a gate is connected to the first reset signal line; The first active layer further comprises: a seventh active portion, configured to form a channel region of the seventh transistor; An orthographic projection of the first reset signal line on the base substrate covers an orthographic projection of the seventh active portion on the base substrate, and a portion of the first reset signal line is used to form a gate of the seventh transistor; The display panel includes a plurality of pixel driving circuits, wherein the plurality of pixel driving circuits include a first pixel driving circuit and a second pixel driving circuit adjacently distributed in the first direction; The first pixel driving circuit and the second pixel driving circuit are at least partially mirror-symmetrical; In the first pixel driving circuit and the second pixel driving circuit that are at least partially mirror-symmetrical, the eighth active portion is located between the two seventh active portions; The display panel further includes: a third conductive layer, located on a side of the first conductive portion facing away from the base substrate, the third conductive layer including the third initial signal line; The orthographic projection of the third initial signal line on the base substrate at least partially overlaps with the orthographic projection of the first reset signal line on the base substrate; The pixel driving circuit further includes a fifth transistor, a first electrode of the fifth transistor being connected to a power line, and a second electrode being connected to the first electrode of the driving transistor, and the first active layer further includes: a fifth active portion, configured to form a channel region of the fifth transistor, the fifth active portion being connected to a side of the eleventh active portion away from the second active portion; The first conductive layer further comprises: an enable signal line, an orthographic projection of the enable signal line on the base substrate extending along the first direction, covering the orthographic projection of the fifth active portion on the base substrate, and located between the orthographic projection of the eleventh active portion on the base substrate and the orthographic projection of the ninth active portion on the base substrate, wherein a portion of the enable signal line is configured to form a gate of the fifth transistor; The display panel further includes a fourth conductive layer, the fourth conductive layer being located on a side of the third conductive layer away from the base substrate, and the fourth conductive layer including: a second bridging portion, connected to the ninth active portion and the eleventh active portion through via holes; An orthographic projection of the ninth active portion on the base substrate is located between an orthographic projection of the first reset signal line on the base substrate and an orthographic projection of the enable signal line on the base substrate.

2. The display panel according to claim 1, wherein The fourth conductive layer includes a first bridge portion, and the first bridge portion is connected to the third initial signal line and the tenth active portion through via holes.

3. The display panel according to claim 1, wherein: The pixel driving circuit further includes a sixth transistor, a first electrode of the sixth transistor being connected to the second electrode of the driving transistor, a gate of the sixth transistor being connected to the enable signal line, and a second electrode of the seventh transistor being connected to the second electrode of the sixth transistor; The first active layer further comprises: a sixth active portion connected to a side of the second active portion away from the eleventh active portion, and configured to form a channel region of the sixth transistor; and the seventh active portion connected to a side of the sixth active portion away from the second active portion. a twelfth active portion connected to a side of the seventh active portion away from the sixth active portion; The orthographic projection of the enable signal line on the base substrate covers the orthographic projection of the sixth active portion on the base substrate, and a partial structure of the enable signal line is used to form a gate of the sixth transistor; The fourth conductive layer includes the second initial signal line, and the second initial signal line is connected to the twelfth active portion through a via hole.

4. The display panel according to claim 1, wherein: The pixel driving circuit further includes a third transistor and a fourth transistor, wherein a first electrode of the third transistor is connected to the gate of the driving transistor, a second electrode is connected to the second electrode of the driving transistor, and the gate is connected to the second gate line; a first electrode of the fourth transistor is connected to the first initial signal line, a second electrode is connected to the gate of the driving transistor, and the gate is connected to the second reset signal line; The display panel further includes: a second active layer, located between the first conductive layer and the third conductive layer, wherein the second active layer comprises: a third active portion, configured to form a channel region of the third transistor; a fourth active portion, configured to form a channel region of the fourth transistor; The third conductive layer further comprises: The orthographic projection of the second gate line on the base substrate extends along the first direction and covers the orthographic projection of the third active portion on the base substrate, and a portion of the second gate line is used to form a top gate of the third transistor; The orthographic projection of the second reset signal line on the base substrate extends along the first direction and covers the orthographic projection of the fourth active portion on the base substrate. A partial structure of the second reset signal line is used to form a top gate of the fourth transistor.

5. The display panel according to claim 4, wherein: The display panel further includes: a second conductive layer located between the first conductive layer and the second active layer, the second conductive layer including: a third gate line, an orthographic projection of the third active portion on the substrate extending along the first direction and covering the orthographic projection of the third active portion on the substrate, wherein a portion of the third gate line is used to form a bottom gate of the third transistor; The orthographic projection of the third reset signal line on the base substrate extends along the first direction and covers the orthographic projection of the fourth active portion on the base substrate. Part of the structure of the third reset signal line is used to form the bottom gate of the fourth transistor. The display panel according to claim 4 , wherein: The orthographic projection of the second gate line on the base substrate is located on a side of the orthographic projection of the first conductive portion on the base substrate away from the orthographic projection of the first reset signal line on the base substrate; The orthographic projection of the second reset signal line on the base substrate is located on a side of the orthographic projection of the second gate line on the base substrate away from the orthographic projection of the first conductive portion on the base substrate.

7. The display panel according to claim 6, wherein: The pixel driving circuit further includes a sixth transistor, a first electrode of the sixth transistor is connected to the second electrode of the driving transistor, and a second electrode of the seventh transistor is connected to the second electrode of the sixth transistor; The fourth conductive layer includes the second initial signal line; The first conductive layer further includes a first initial signal line, an orthographic projection of the first initial signal line on the base substrate extending along the first direction and located on a side of the orthographic projection of the second reset signal line on the base substrate away from an orthographic projection of the second gate line on the base substrate; The display panel includes a plurality of pixel driving circuits distributed in a second direction and a first direction, the first direction is a row direction, and the second direction is a column direction; The orthographic projection of the first initial signal line in the pixel driving circuit of the current row on the substrate at least partially overlaps with the orthographic projection of the second initial signal line in the pixel driving circuit of the previous row on the substrate.

8. The display panel according to claim 4, wherein: The pixel driving circuit further includes a first transistor, wherein a first electrode of the first transistor is connected to the data line, a second electrode is connected to the first electrode of the driving transistor, and a gate is connected to the first gate line; The first active layer further comprises: a first active portion, configured to form a channel region of the first transistor; The first conductive layer further comprises: The first gate line, wherein an orthographic projection of the first gate line on the base substrate extends along the first direction and covers an orthographic projection of the first active portion on the base substrate, and a portion of the first gate line is used to form a gate of the first transistor; The orthographic projection of the first gate line on the base substrate is located between the orthographic projection of the second gate line on the base substrate and the orthographic projection of the second reset signal line on the base substrate.

9. The display panel according to claim 8, wherein: The display panel further includes: The fifth conductive layer is located on a side of the fourth conductive layer away from the base substrate. The fifth conductive layer includes the data line. The orthographic projection of the data line on the base substrate extends along a second direction that intersects the first direction.

10. The display panel according to claim 1, wherein The display panel further includes: The fourth conductive layer includes a first bridge portion, wherein the first bridge portion is connected to the third initial signal line and the tenth active portion through via holes; The first active layer further comprises: a thirteenth active portion connected between the tenth active portion in the first pixel driving circuit and the tenth active portion in the second pixel driving circuit; The first bridge portion in the first pixel driving circuit is multiplexed as the first bridge portion in the second pixel driving circuit.

11. The display panel according to claim 10, wherein: The eighth transistor in the first pixel driving circuit is multiplexed as the eighth transistor in the second pixel driving circuit.

12. The display panel according to claim 11, wherein: The second bridge portion is connected to the ninth active portion and the eleventh active portion through via holes respectively; The eighth active portion in the first pixel driving circuit is multiplexed as the eighth active portion in the second pixel driving circuit; The ninth active portion in the first pixel driving circuit is multiplexed as the ninth active portion in the second pixel driving circuit; The tenth active portion in the first pixel driving circuit is multiplexed as the tenth active portion in the second pixel driving circuit; The display panel further includes: a ninth bridging portion; The second bridge portion in the first pixel driving circuit is further connected to the ninth bridge portion through a via hole, and the second bridge portion in the second pixel driving circuit is connected to the ninth bridge portion through a via hole to connect to the ninth active portion in the first pixel driving circuit.

13. The display panel according to claim 12, wherein: The display panel further includes a second conductive layer, the second conductive layer is located between the first conductive layer and the third conductive layer, and the second conductive layer includes the ninth bridge portion.

14. The display panel according to claim 1, wherein: The pixel driving circuit further comprises a capacitor, wherein a first electrode of the capacitor is connected to the gate of the driving transistor, and a second electrode of the capacitor is connected to the power line; The first active layer further comprises: a fourteenth active portion connected between the fifth active portion in the first pixel driving circuit and the fifth active portion in the second pixel driving circuit; The display panel further includes: A second conductive layer, located between the first conductive layer and the third conductive layer, includes: a second conductive portion, wherein an orthographic projection of the second conductive portion on the base substrate at least partially overlaps with an orthographic projection of the first conductive portion on the base substrate, the first conductive portion is further configured to form a first electrode of the capacitor, and the second conductive portion is configured to form a second electrode of the capacitor; a first connecting portion connected between the second conductive portion in the first pixel driving circuit and the second conductive portion in the second pixel driving circuit; a fifth conductive layer, located on a side of the fourth conductive layer facing away from the base substrate, the fifth conductive layer comprising: The power line, an orthographic projection on the base substrate, extends along a second direction, and the second direction intersects the first direction; The fourth conductive layer includes: a third bridging portion, connected to the fourteenth active portion and the first connecting portion through via holes; The power line in the first pixel driving circuit and the power line in the second pixel driving circuit are respectively connected to the third bridge portion through via holes.

15. The display panel according to claim 1, wherein The display panel further includes: A light shielding layer is located between the first active layer and the base substrate, and the orthographic projection of the light shielding layer on the base substrate covers the orthographic projection of the second active portion on the base substrate.

16. The display panel according to claim 1, wherein The fourth conductive layer includes a first bridge portion, wherein the first bridge portion is connected to the third initial signal line and the tenth active portion through via holes; The first bridge portion in the first pixel driving circuit and the first bridge portion in the second pixel driving circuit share a portion of their structure and are connected to the third initial signal line through the same via hole.

17. The display panel according to claim 1, wherein: The pixel driving circuit further includes: a first transistor, a third transistor, a fourth transistor, a sixth transistor, and a capacitor C; The first electrode of the first transistor is connected to the data line, the second electrode is connected to the first electrode of the driving transistor, and the gate is connected to the first gate line; The first electrode of the third transistor is connected to the gate of the driving transistor, the second electrode is connected to the second electrode of the driving transistor, and the gate is connected to the second gate line; A first electrode of the fourth transistor is connected to the first initial signal line, a second electrode is connected to the gate of the driving transistor, and the gate is connected to the second reset signal line; A first electrode of the sixth transistor is connected to the second electrode of the driving transistor, a second electrode is connected to the first electrode of the light emitting unit, and a gate is connected to the enable signal line; The capacitor is connected between the power line and the gate of the driving transistor; The driving transistor, the first transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor are P-type transistors, and the third transistor and the fourth transistor are N-type transistors.

18. A display device, wherein: The display panel comprises the display panel according to any one of claims 1 to 17.

Images