A solar array simulator and a method for improving its dynamic performance

Abstract

The invention discloses a solar array simulator and a method for improving its dynamic performance, which relates to the field of programmable power supply. In a simulation mode, a voltage control loop is shielded, an output terminal voltage feedback signal is sampled, and an IV curve current programming reference value is obtained by looking up a table with the output terminal voltage as an index, and the output of the IV curve is completed with a current control loop. In order to increase the output operating point switching speed, a differential feedback signal of the dynamic change of the output terminal voltage is added to the current control loop to improve the dynamic adjustment performance of the simulator, and a voltage clamping circuit is combined with an FPGA programming control method to limit the feedback amount of the dynamic change of the voltage, so as to ensure the loop stability and effectively improve the dynamic response performance of the simulator when switching between different operating points.

Description

Technical Field

[0001] The invention relates to the field of programmable power supplies, and in particular to a solar array simulator and a method for improving its dynamic performance. Background Art

[0002] The solar array simulator is a key component of the satellite power ground test and evaluation system. During ground testing, it can simulate the DC output characteristics of a solar cell array in a close to real space environment, and replace solar cell panels to provide energy input for the satellite power ground test system. Its performance directly affects the accuracy and reliability of the satellite power system test results, and is of great significance to the life assessment and working status of the entire satellite power system.

[0003] The main task of the solar array simulator is to simulate the output IV characteristic curve of the solar cell array under various load conditions, replace the real solar cell panels to provide test energy for each subsystem of the satellite power supply, and complete the ground test of the satellite power supply system. According to the ground test characteristics of the satellite power supply system, the solar array simulator must have the high-speed dynamic response capability of the solar cell panels, be able to quickly respond to any changes in the back-end load, and achieve high dynamic and stable switching of the IV characteristic output. Since the IV curve has serious nonlinear problems on the right side of the maximum power point, the traditional IV outer loop control method requires simultaneous control of the voltage control unit and the current control unit. The control is complex and the bandwidth is limited, which cannot meet the high-frequency dynamic load shedding. It is necessary to shield the voltage control loop, add the voltage feedback signal differential term in the current control loop and clamp it, improve the circuit dynamic performance, and achieve accurate simulation of the output characteristic curve of the solar array. Summary of the invention

[0004] In view of the above-mentioned technical problems existing in the prior art, the present invention provides a solar array simulator and a method for improving its dynamic performance, which has a reasonable design, solves the shortcomings of the prior art and has good effects.

[0005] In order to achieve the purpose 1 of the invention, the following technical solutions are adopted:

[0006] A solar array simulator comprises an analog control unit and a digital processing unit;

[0007] The analog control unit is used to complete signal acquisition and power output control, including a switch gating circuit, a dynamic performance improvement and clamping circuit, a power adjustment circuit, a total current limiting circuit, a current control loop, an output current detection circuit, a voltage control loop, an output voltage detection circuit, a control op amp circuit and a voltage clamping circuit;

[0008] The switch gating circuit is used to complete the switching between the fixed mode and the simulation mode;

[0009] The dynamic performance improvement and clamping circuit is used to introduce the output voltage signal into the current control loop as a differential term in the simulation mode, and clamp the differential term through the clamping circuit, thereby improving the dynamic adjustment speed and stability of the simulator load operating point.

[0010] The power adjustment circuit is used to complete the power adjustment of the output voltage / current, including a multi-channel power MOSFET adjustment circuit, which uses a current-sharing method to evenly distribute the output current in parallel for output;

[0011] The total current limiting circuit is used to control the maximum operating current of each power MOSFET;

[0012] The output current detection circuit is used to convert the output current into a voltage signal through the sampling resistor R1, perform differential amplification, and output a current feedback signal;

[0013] The current control loop is used to perform error calculation and compensation correction on the current detection signal and the current programming reference signal, thereby controlling the current output and realizing constant current control;

[0014] The output voltage detection circuit is used to differentially amplify the output voltage and output a voltage feedback signal;

[0015] The voltage control loop is used to perform error calculation and compensation correction on the output voltage detection signal and the voltage programming reference signal, thereby controlling the voltage output and achieving constant voltage control;

[0016] The control operational amplifier circuit is used to convert the error signal output by the total current limiting circuit, the current control loop, and the voltage control loop into a control signal for controlling / driving the power series adjustment tube;

[0017] The voltage clamping circuit is used for clamping the total loop error signal;

[0018] The digital processing unit is used to realize the programming of output voltage / current and the table lookup and measurement readback functions of voltage / current, and includes a DAC module, an ADC module, an FPGA and a memory;

[0019] The DAC module is used to convert the programmed value of the output voltage / current into a reference signal of the voltage / current;

[0020] The ADC module is used to convert the sampled value of voltage / current into the measured value of voltage / current;

[0021] The FPGA is used to complete the voltage / current measurement readback function for the voltage / current measurement value output by the ADC module;

[0022] The memory is used to store the signal processed by the digital processor.

[0023] The digital processing unit outputs the programmed value of the voltage / current, which is then passed through the DAC module to generate a voltage / current reference signal, which is then error-amplified with the sampling signal to control the power adjustment circuit and complete the programmable adjustment of the output voltage / current. At the same time, after the output voltage / current is sampled and detected, the ADC module outputs the voltage / current measurement value and sends it to the digital processor to complete the voltage / current table lookup and measurement readback functions.

[0024] Further, the current control loop includes an operational amplifier N5B, diodes V2-1, V2-2 and V3, resistors R2, R3, R7, R12, R15-R18, R20 and R22, and capacitors C5-C7;

[0025] One end of the resistor R2 is connected to 5VA, and the other end of the resistor R2 is connected to the dynamic performance improvement and clamping circuit, one end of the resistor R16, one end of the resistor R20, one end of the capacitor C7, the negative input end of the operational amplifier N5B, the anode of the diode V2-1, and the cathode of the diode V2-2; the other end of the resistor R16 is connected to one end of the capacitor C5, and the other end of the capacitor C5 is connected to the DAC module and one end of the resistor R17, and the other end of the resistor R17 is connected to one end of the resistor R18, and the other end of the resistor R18 is connected to one end of the capacitor C6; the other end of the resistor R20 is connected to the output current detection circuit; The other end of capacitor C7 is connected to one end of resistor R22 and the positive input end of operational amplifier N5B, and the other end of resistor R22 is connected to ground; the cathode of diode V2-1 is connected to one end of resistor R3 and one end of resistor R7, and the other end of resistor R3 is connected to 15VA, the other end of resistor R7 is connected to one end of resistor R12, the other end of capacitor C6, the output end of operational amplifier N5B, and the cathode of diode V3, and the anode of diode V3 is connected to Vea end; the anode of diode V2-2 is connected to the other end of resistor R12 and one end of resistor R15, and the other end of resistor R15 is connected to -15VA.

[0026] Further, the dynamic performance enhancement and clamping circuit includes operational amplifiers N1B and N4B, transistors V1A, V1B, V1C and V1D, N-channel field effect transistor V4, resistors R1, R4, R5, R6, R8-R11, R13, R14, R19 and R21, and capacitors C1-C4;

[0027] One end of the resistor R14 is connected to the negative input and output of the operational amplifier N1B, the other end of the resistor R14 is connected to one end of the resistor R9 and one end of the capacitor C2, the positive input of the operational amplifier N1B is connected to one end of the resistor R19 and the drain of the field effect tube V4, the other end of the resistor R19 is connected to the output voltage detection circuit, the gate of the field effect tube V4 is connected to one end of the resistor R21, the other end of R21 is connected to the FPGA, and the source of the field effect tube V4 is connected to the ground; one end of the resistor R4 is connected to the VMPDAC end, the other end of the resistor R4 is connected to one end of the capacitor C1, one end of the resistor R5, and the negative input of the operational amplifier N4B, the other end of the capacitor C1 is connected to the other end of the resistor R5, the output of the operational amplifier N4B, one end of the resistor R8, and one end of the capacitor C4, the positive input of the operational amplifier N4B is connected to one end of the resistor R11 and one end of the resistor R13, The other end of resistor R11 is connected to 2V5R, the other end of resistor R13 is connected to the RG end, the other end of capacitor C4 is connected to ground, the other end of resistor R8 is connected to the collector of transistor V1C, the base of transistor V1C is connected to the collector of transistor V1B, the emitter of transistor V1C is connected to one end of resistor R1, the emitter and base of transistor V1B, and the base of transistor V1A, the other end of resistor R1 is connected to 15VA, the emitter of transistor V1A is connected to 15VA and the emitter of transistor V1D, the collector of transistor V1A is connected to the base of transistor V1D, and the collector of transistor V1D is connected to the other end of resistor R9; the other end of capacitor C2 is connected to one end of capacitor C3 and one end of resistor R6, the other end of capacitor C3 is connected to one end of resistor R10, and the other end of resistor R6 and the other end of resistor R10 are commonly connected to the other end of resistor R2 in the current control loop.

[0028] Further, the FPGA is connected to the input end of the inverter D1C, and its output end is connected to one end of the resistor R23D, the other end of the resistor R23D is connected to one end of the capacitor C41 and one end of the resistor R23C, the other end of the resistor C41 is connected to the AG end, the other end of the resistor R23C is connected to one end of the capacitor C40 and the positive input end of the operational amplifier D2C, the other end of the capacitor C40 is connected to the AG end, the negative input end of the operational amplifier is connected to its output end and one end of the magnetic bead L10B, and the other end of the magnetic bead L10B is connected to the VMPDAC end.

[0029] Further, the voltage control loop includes operational amplifiers N2B, N3B and peripheral devices, and the peripheral devices include resistors R23-R38, capacitors C8-C15, transistor V8, diodes V5-1, V5-2, V6, V7 and V9;

[0030] One end of the resistor R30 is connected to the DAC module, and the other end is connected to one end of the capacitor C9 and the positive input end of the operational amplifier N2B. The negative input end of the operational amplifier N2B is connected to its output end and one end of the resistor R28. The other end of the circuit R28 is connected to one end of the resistor R23, the anode of the diode V5-1, the cathode of the diode V5-2, one end of the resistor R29, one end of the resistor R32, one end of the resistor R31, one end of the resistor R34, one end of the capacitor C13 and the negative input end of the operational amplifier N3B; the resistor R23 The other end of the diode V5-1 is connected to 5VA; the cathode of the diode V5-1 is connected to one end of the resistor R24 ​​and one end of the resistor R25, the other end of the resistor R24 ​​is connected to 15VA, the other end of the resistor R25 is connected to one end of the resistor R26, one end of the capacitor C8, one end of the capacitor C10, one end of the capacitor C12, the output end of the operational amplifier N3B and the cathode of the diode V7, the anode of the diode V7 is connected to the Vea end; the anode of the diode V5-2 is connected to the other end of the resistor R26 and one end of the resistor R27, the other end of the resistor R27 is connected -15VA; the other end of resistor R29 is connected to the other end of capacitor C8; the other end of resistor R32 is connected to one end of resistor R33, the other end of resistor R33 is connected to the other end of capacitor C12, the other end of capacitor C10 and the cathode of diode V6, and the anode of diode V6 is connected to the VG end; the other end of resistor R31 is connected to one end of capacitor C11, the other end of capacitor C11 is connected to the output voltage detection circuit and the other end of resistor R34; the other end of capacitor C13 is connected to the positive input end of operational amplifier N3B and resistor R38 One end of the resistor R38 is connected to the VG end, the other end of the capacitor C15 is connected to the VG end, the anode of the diode V9 is connected to one end of the resistor R37, the emitter of the transistor V8, and one end of the capacitor C14, the other end of the capacitor C14 is connected to one end of the resistor R36, one end of the resistor R35, and the base of the transistor V8, the other end of the resistor R35 is connected to the collector of the transistor V8 and 5VD, the other end of the resistor R36 is connected to the FPGA, and the other end of R37 is connected to the GG end.

[0031] In order to achieve the second object of the invention, the following technical solutions are adopted:

[0032] A method for improving dynamic performance, using the above solar array simulator, comprises the following steps:

[0033] S1. When the simulator works in fixed mode, the control signals of field effect tube V4 and transistor V8 are set high by FPGA, transistor V8 is cut off, the positive input terminal of operational amplifier N3B is grounded, the voltage programming signal and the voltage feedback signal generate a voltage error signal at the negative input terminal of operational amplifier N3B, and the voltage error adjustment signal is obtained through the operation of operational amplifier N3B, and the voltage control loop is effective; field effect tube V4 is turned on, and the output voltage feedback signal in the current control loop is clamped to 0;

[0034] S2. When the simulator works in simulation mode, the control signals of field effect tube V4 and transistor V8 are set low by FPGA, transistor V8 is turned on, and the positive input terminal of operational amplifier N3B is clamped to 5VD. At this time, the voltage error signal generated by the voltage programming signal and the voltage feedback signal is shielded, that is, the voltage control loop fails; field effect tube V4 is cut off, and the voltage feedback signal is followed and isolated by operational amplifier N1B, and the output voltage feedback signal is introduced into the current control loop as a differential term, and the dynamic change of the output voltage signal is effectively controlled in the current control loop;

[0035] When the simulator is under stable load conditions, the voltage feedback signal has no effect on the error calculation of the current control loop because the differential network attenuates the low-frequency signal. The FPGA uses the voltage feedback signal as an index to look up the table to obtain the current programming reference value of the IV curve. At this time, the current programming reference value and the current feedback signal perform error calculation and compensation correction, and the obtained error adjustment signal controls the power amplifier circuit. When the simulator is under dynamic load shedding conditions, the dynamically changing voltage feedback signal participates in the error calculation of the current control loop through the differential network. At this time, the voltage feedback signal is followed by the operational amplifier N1B for isolation, and then passes through the circuit R6, R10 and R14, and the capacitors C2 and C3 become the voltage differential feedback signal. The voltage differential feedback signal participates in the calculation of the current error signal, and the obtained error adjustment signal controls the power amplifier circuit to complete the output of the voltage-controlled current source. The clamping circuit controlled by the FPGA programming is used to clamp the dynamically changing voltage feedback signal. Only when the voltage feedback signal is higher than the clamping point voltage can the voltage feedback signal pass through the differential network to achieve a rapid adjustment effect.

[0036] Furthermore, the FPGA outputs pulse signals of different frequencies and widths according to the maximum power point voltage of different curves. The pulse signal is inverted by D1C, filtered by two stages of RC, and followed by D2C operational amplifier to obtain a stable DC voltage programming value, which is then calculated by operational amplifier N4B to obtain the clamping voltage. The voltage following function is realized by a mirror circuit to complete the voltage clamping.

[0037] Furthermore, the mirror circuit is composed of two groups of Darlington transistors V1A, V1D and V1B, V1C, and the Darlington transistors are composed of four NPN transistors with consistent parameters and integrated on the same chip.

[0038] The present invention has the following beneficial effects:

[0039] 1. The SAS simulation function of the solar array simulator is to sample the output voltage signal under the condition of shielding the voltage control loop, use the output voltage as the index to look up the table to obtain the IV curve current programming reference value, and complete the output of the IV curve with the current control loop; in order to increase the output operating point switching speed, the differential feedback signal of the dynamic change of the output voltage is added to the current control loop, thereby improving the dynamic adjustment performance of the simulator.

[0040] 2. Dynamic performance improvement and clamping circuits are combined with FPGA programming control to limit the feedback amount of dynamic voltage changes. The clamping voltage reference signal is controlled according to the maximum power point voltage programming of different IV curves to achieve programmable control of the clamping voltage, ensure stable switching of the output operating point, and avoid oscillation caused by external voltage during high-frequency series / parallel switching adjustment of the simulator. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 It is a circuit principle block diagram of the solar array simulator in the present invention;

[0042] Figure 2 It is a schematic diagram of the current control loop and the dynamic performance improvement and clamping circuit in the present invention;

[0043] Figure 3 is a schematic diagram of a voltage control loop in the present invention;

[0044] Figure 4 The schematic diagram of the clamping voltage digital-to-analog conversion circuit of the FPGA programming in the present invention; DETAILED DESCRIPTION

[0045] The specific implementation of the present invention is further described below in conjunction with specific embodiments:

[0046] Example 1

[0047] A solar array simulator, such as Figure 1 As shown, it includes an analog control unit and a digital processing unit;

[0048] The analog control unit is used to complete signal acquisition and power output control, including switch gating circuit, dynamic performance improvement and clamping circuit, power adjustment circuit, total current limiting circuit, current control loop, output current detection circuit, voltage control loop, output voltage detection circuit, control op amp circuit and voltage clamping circuit;

[0049] The switch gating circuit is used to complete the switching between the fixed mode and the simulation mode;

[0050] Dynamic performance improvement and clamping circuits are used to introduce the output voltage signal into the current control loop as a differential term in simulation mode, and clamp the differential term through the clamping circuit to improve the dynamic adjustment speed and stability of the simulator load operating point;

[0051] The power adjustment circuit is used to complete the power adjustment of the output voltage / current, including a multi-channel power MOSFET adjustment circuit, which uses a current-sharing method to evenly distribute the output current in parallel;

[0052] The total current limiting circuit is used to control the maximum operating current of each power MOSFET;

[0053] The output current detection circuit is used to convert the output current into a voltage signal through the sampling resistor R1, perform differential amplification, and output a current feedback signal;

[0054] The current control loop is used to perform error calculation and compensation correction between the current detection signal and the current programming reference signal, thereby controlling the current output and achieving constant current control;

[0055] The output voltage detection circuit is used to differentially amplify the output voltage and output a voltage feedback signal;

[0056] The voltage control loop is used to perform error calculation and compensation correction on the output voltage detection signal and the voltage programming reference signal, thereby controlling the voltage output and achieving constant voltage control;

[0057] The control operational amplifier circuit is used to convert the error signal output by the total current limiting circuit, the current control loop, and the voltage control loop into a control signal for controlling / driving the power series adjustment tube;

[0058] The voltage clamping circuit is used for clamping the total error signal of the loop; the digital processing unit is used for realizing the programming value of the output voltage / current and the measurement and reading back function of the voltage / current, including a DAC module, an ADC module, an FPGA and a memory;

[0059] The DAC module is used to convert the programmed value of the output voltage / current into a reference signal of the voltage / current;

[0060] The ADC module is used to convert the sampled value of voltage / current into the measured value of voltage / current;

[0061] FPGA is used to complete the voltage / current measurement readback function for the voltage / current measurement value output by the ADC module;

[0062] The memory is used to store the signal processed by the digital processor.

[0063] The digital processing unit outputs the programmed value of the voltage / current, which is then passed through the DAC module to generate a voltage / current reference signal, which is then error-amplified with the sampling signal to control the power adjustment circuit and complete the programmable adjustment of the output voltage / current. At the same time, after the output voltage / current is sampled and detected, the ADC module outputs the voltage / current measurement value and sends it to the digital processor to complete the voltage / current table lookup and measurement readback functions.

[0064] The solar array simulator has two working modes: fixed (FIXED) mode and simulation (SAS) mode. In the fixed mode, the simulator realizes the constant voltage and constant current output function through the voltage and current dual closed-loop control scheme. In the simulation mode, the voltage control loop is shielded, and the output voltage signal is sampled. The FPGA digital table lookup method is used to obtain the IV curve current programming reference value according to the sampled voltage, and the error calculation is performed with the current feedback signal. The calculation result controls the power amplifier circuit to realize the output characteristics of the voltage-controlled current source, thereby completing the SAS simulation output of the IV characteristic curve. The key to realizing the simulator's SAS output function is that when the simulator switches between different operating points, it can quickly adjust the current control loop error signal to stabilize the simulator at the new operating point. The key to completing the high dynamic and stable switching of the operating point lies in how to effectively respond to and control the dynamic changes of the output voltage in the current loop to ensure the stable dynamic performance of the simulator.

[0065] The simulator dynamic performance improvement circuit and clamping method of the present invention are to add a differential feedback circuit of the output voltage signal and a voltage clamping circuit controlled by FPGA programming in the simulator current control loop. The output voltage feedback signal is isolated by a first-stage op amp in-phase follower and then fed into the current control loop by the differential circuit; a MOSFET selection switch controlled by FPGA is added to the op amp in-phase input end, and when the simulator works in a fixed mode, the in-phase end of the follower op amp is grounded through the MOSFET switch to shield the influence of the dynamically changing voltage signal. In addition, a voltage clamping circuit controlled by FPGA programming is added to the output end of the op amp follower circuit, and when the simulator works in the SAS mode, the dynamic change of the output voltage can be fed back differently according to the maximum power point voltage of different curves, so as to ensure the high-speed and stable switching of the output working point, and avoid the simulator output oscillation caused by external voltage when the simulator is switched and adjusted in high-frequency series / parallel connection.

[0066] like Figure 2 As shown, the current control loop includes an operational amplifier N5B, diodes V2-1, V2-2, V3, resistors R2, R3, R7, R12, R15-R18, R20 and R22, and capacitors C5-C7;

[0067] One end of the resistor R2 is connected to 5VA, and the other end of the resistor R2 is connected to the dynamic performance improvement and clamping circuit, one end of the resistor R16, one end of the resistor R20, one end of the capacitor C7, the negative input end of the operational amplifier N5B, the anode of the diode V2-1, and the cathode of the diode V2-2; the other end of the resistor R16 is connected to one end of the capacitor C5, and the other end of the capacitor C5 is connected to the DAC module and one end of the resistor R17, and the other end of the resistor R17 is connected to one end of the resistor R18, and the other end of the resistor R18 is connected to one end of the capacitor C6; the other end of the resistor R20 is connected to the output current detection circuit; The other end of capacitor C7 is connected to one end of resistor R22 and the positive input end of operational amplifier N5B, and the other end of resistor R22 is connected to ground; the cathode of diode V2-1 is connected to one end of resistor R3 and one end of resistor R7, and the other end of resistor R3 is connected to 15VA, the other end of resistor R7 is connected to one end of resistor R12, the other end of capacitor C6, the output end of operational amplifier N5B, and the cathode of diode V3, and the anode of diode V3 is connected to Vea end; the anode of diode V2-2 is connected to the other end of resistor R12 and one end of resistor R15, and the other end of resistor R15 is connected to -15VA.

[0068] like Figure 2 As shown, the dynamic performance improvement and clamping circuit includes operational amplifiers N1B and N4B, transistors V1A, V1B, V1C and V1D, N-channel field effect transistor V4, resistors R1, R4, R5, R6, R8-R11, R13, R14, R19 and R21, and capacitors C1-C4;

[0069] One end of the resistor R14 is connected to the negative input and output of the operational amplifier N1B, the other end of the resistor R14 is connected to one end of the resistor R9 and one end of the capacitor C2, the positive input of the operational amplifier N1B is connected to one end of the resistor R19 and the drain of the field effect tube V4, the other end of the resistor R19 is connected to the output voltage detection circuit, the gate of the field effect tube V4 is connected to one end of the resistor R21, the other end of R21 is connected to the FPGA, and the source of the field effect tube V4 is connected to the ground; one end of the resistor R4 is connected to the VMPDAC end, the other end of the resistor R4 is connected to one end of the capacitor C1, one end of the resistor R5, and the negative input of the operational amplifier N4B, the other end of the capacitor C1 is connected to the other end of the resistor R5, the output of the operational amplifier N4B, one end of the resistor R8, and one end of the capacitor C4, the positive input of the operational amplifier N4B is connected to one end of the resistor R11 and one end of the resistor R13, The other end of resistor R11 is connected to 2V5R, the other end of resistor R13 is connected to the RG end, the other end of capacitor C4 is connected to ground, the other end of resistor R8 is connected to the collector of transistor V1C, the base of transistor V1C is connected to the collector of transistor V1B, the emitter of transistor V1C is connected to one end of resistor R1, the emitter and base of transistor V1B, and the base of transistor V1A, the other end of resistor R1 is connected to 15VA, the emitter of transistor V1A is connected to 15VA and the emitter of transistor V1D, the collector of transistor V1A is connected to the base of transistor V1D, and the collector of transistor V1D is connected to the other end of resistor R9; the other end of capacitor C2 is connected to one end of capacitor C3 and one end of resistor R6, the other end of capacitor C3 is connected to one end of resistor R10, and the other end of resistor R6 and the other end of resistor R10 are commonly connected to the other end of resistor R2 in the current control loop.

[0070] The FPGA is connected to the input end of the inverter D1C, and its output end is connected to one end of the resistor R23D. The other end of the resistor R23D is connected to one end of the capacitor C41 and one end of the resistor R23C. The other end of the resistor C41 is connected to the AG end. The other end of the resistor R23C is connected to one end of the capacitor C40 and the positive input end of the operational amplifier D2C. The other end of the capacitor C40 is connected to the AG end. The negative input end of the operational amplifier is connected to its output end and one end of the magnetic bead L10B. The other end of the magnetic bead L10B is connected to the VMPDAC end.

[0071] like Figure 3 As shown, the voltage control loop includes operational amplifiers N2B and N3B, resistors R23-R38, capacitors C8-C15, transistor V8, diodes V5-1, V5-2, V6, V7 and V9;

[0072] One end of the resistor R30 is connected to the DAC module, and the other end is connected to one end of the capacitor C9 and the positive input end of the operational amplifier N2B. The negative input end of the operational amplifier N2B is connected to its output end and one end of the resistor R28. The other end of the circuit R28 is connected to one end of the resistor R23, the anode of the diode V5-1, the cathode of the diode V5-2, one end of the resistor R29, one end of the resistor R32, one end of the resistor R31, one end of the resistor R34, one end of the capacitor C13 and the negative input end of the operational amplifier N3B; the resistor R23 The other end of the diode V5-1 is connected to 5VA; the cathode of the diode V5-1 is connected to one end of the resistor R24 ​​and one end of the resistor R25, the other end of the resistor R24 ​​is connected to 15VA, the other end of the resistor R25 is connected to one end of the resistor R26, one end of the capacitor C8, one end of the capacitor C10, one end of the capacitor C12, the output end of the operational amplifier N3B and the cathode of the diode V7, the anode of the diode V7 is connected to the Vea end; the anode of the diode V5-2 is connected to the other end of the resistor R26 and one end of the resistor R27, the other end of the resistor R27 is connected -15VA; the other end of resistor R29 is connected to the other end of capacitor C8; the other end of resistor R32 is connected to one end of resistor R33, the other end of resistor R33 is connected to the other end of capacitor C12, the other end of capacitor C10 and the cathode of diode V6, and the anode of diode V6 is connected to the VG end; the other end of resistor R31 is connected to one end of capacitor C11, the other end of capacitor C11 is connected to the output voltage detection circuit and the other end of resistor R34; the other end of capacitor C13 is connected to the positive input end of operational amplifier N3B and resistor R38 One end of the resistor R38 is connected to the VG end, the other end of the capacitor C15 is connected to the VG end, the anode of the diode V9 is connected to one end of the resistor R37, the emitter of the transistor V8, and one end of the capacitor C14, the other end of the capacitor C14 is connected to one end of the resistor R36, one end of the resistor R35, and the base of the transistor V8, the other end of the resistor R35 is connected to the collector of the transistor V8 and 5VD, the other end of the resistor R36 is connected to the FPGA, and the other end of R37 is connected to the GG end.

[0073] Embodiment 2:

[0074] A method for improving dynamic performance, using the above-mentioned solar array simulator, comprises the following steps:

[0075] S1. When the simulator works in fixed mode, the control signals of field effect tube V4 and transistor V8 are set high by FPGA, transistor V8 is cut off, the positive input terminal of operational amplifier N3B is grounded, the voltage programming signal and the voltage feedback signal generate a voltage error signal at the negative input terminal of operational amplifier N3B, and the voltage error adjustment signal is obtained through compensation and correction by operational amplifier N3B, and the voltage control loop is effective; field effect tube V4 is turned on, and the output voltage feedback signal in the current control loop is clamped to 0;

[0076] S2. When the simulator works in simulation mode, the control signals of field effect tube V4 and transistor V8 are set low by FPGA, transistor V8 is turned on, and the positive input terminal of operational amplifier N3B is clamped to 5VD. At this time, the voltage error signal generated by the voltage programming signal and the voltage feedback signal is shielded, that is, the voltage control loop fails; field effect tube V4 is cut off, and the voltage feedback signal is followed and isolated by operational amplifier N1B, and the output voltage feedback signal is introduced into the current control loop as a differential term, and the dynamic change of the output voltage signal is effectively controlled in the current control loop;

[0077] When the simulator is under stable load conditions, the voltage feedback signal has no effect on the error calculation of the current control loop because the differential network attenuates the low-frequency signal. The FPGA uses the voltage feedback signal as an index to look up the table to obtain the current programming reference value of the IV curve. At this time, the current programming reference value and the current feedback signal perform error calculation and compensation correction, and the obtained error adjustment signal controls the power amplifier circuit. When the simulator is under dynamic load shedding conditions, the dynamically changing voltage feedback signal participates in the error calculation of the current control loop through the differential network. At this time, the voltage feedback signal is followed by the operational amplifier N1B for isolation, and then passes through the circuit R6, R10 and R14, and the capacitors C2 and C3 become the voltage differential feedback signal. The voltage differential feedback signal participates in the calculation of the current error signal, and the obtained error adjustment signal controls the power amplifier circuit to complete the output of the voltage-controlled current source. The clamping circuit controlled by the FPGA programming is used to clamp the dynamically changing voltage feedback signal. Only when the voltage feedback signal is higher than the clamping point voltage can the voltage feedback signal pass through the differential network to achieve a rapid adjustment effect.

[0078] FPGA outputs pulse signals of different frequencies and widths according to the maximum power point voltage of different curves, such as Figure 4 As shown, the pulse signal is inverted by D1C, filtered by two stages of RC and followed by D2C operational amplifier to obtain a stable DC voltage programming value, and then the clamping voltage is obtained by operation of operational amplifier N4B. The voltage following function is realized by using a mirror circuit to complete the voltage clamping.

[0079] The mirror circuit is composed of two groups of Darlington tubes V1A, V1D and V1B, V1C. The Darlington tubes are composed of four NPN transistors with consistent parameters and integrated on the same chip. The use of Darlington tubes can effectively improve the load capacity of the clamping circuit and suppress interference signals.

[0080] Of course, the above description is not a limitation of the present invention, and the present invention is not limited to the above examples. Changes, modifications, additions or substitutions made by technicians in this technical field within the essential scope of the present invention should also fall within the protection scope of the present invention.

Claims

1. A method for improving the dynamic performance of a solar array simulator, characterized in that: The solar array simulator includes an analog control unit and a digital processing unit; The analog control unit is used to complete signal acquisition and power output control, including a switch gating circuit, a dynamic performance improvement and clamping circuit, a power adjustment circuit, a total current limiting circuit, a current control loop, an output current detection circuit, a voltage control loop, an output voltage detection circuit, a control op amp circuit and a voltage clamping circuit; The switch gating circuit is used to complete the switching between the fixed mode and the simulation mode; The dynamic performance improvement and clamping circuit is used to introduce the output voltage signal into the current control loop as a differential term in the simulation mode, and to clamp the differential term through the clamping circuit, thereby improving the dynamic adjustment speed and stability of the simulator load operating point; The power adjustment circuit is used to complete the power adjustment of the output voltage / current, including a multi-channel power MOSFET adjustment circuit, which uses a current-sharing method to evenly distribute the output current in parallel for output; The total current limiting circuit is used to control the maximum operating current of each power MOSFET; The output current detection circuit is used to convert the output current into a voltage signal through the sampling resistor R1, perform differential amplification, and output a current feedback signal; The current control loop is used to perform error calculation and compensation correction on the current detection signal and the current programming reference signal, thereby controlling the current output and realizing constant current control; The output voltage detection circuit is used to differentially amplify the output voltage and output a voltage feedback signal; The voltage control loop is used to perform error calculation and compensation correction on the output voltage detection signal and the voltage programming reference signal, thereby controlling the voltage output and achieving constant voltage control; The control operational amplifier circuit is used to convert the error signal output by the total current limiting circuit, the current control loop, and the voltage control loop into a control signal for controlling / driving the power series adjustment tube; The voltage clamping circuit is used for clamping the total loop error signal; The digital processing unit is used to realize the programming of output voltage / current and the table lookup and measurement readback functions of voltage / current, and includes a DAC module, an ADC module, an FPGA and a memory; The DAC module is used to convert the programmed value of the output voltage / current into a reference signal of the voltage / current; The ADC module is used to convert the sampled value of voltage / current into the measured value of voltage / current; The FPGA is used to complete the voltage / current measurement readback function for the voltage / current measurement value output by the ADC module; The memory is used to store the signal processed by the digital processor; The digital processing unit outputs the programmed value of the voltage / current, which is then passed through the DAC module to generate a reference signal for the voltage / current, which is then error-amplified with the sampling signal to control the power adjustment circuit and complete the program-controlled adjustment of the output voltage / current. At the same time, after the output voltage / current is sampled and detected, the ADC module outputs the voltage / current measurement value and sends it to the digital processor to complete the voltage / current table lookup and measurement readback functions. The method comprises the following steps: S1. When the simulator works in fixed mode, the control signals of field effect tube V4 and transistor V8 are set high by FPGA, transistor V8 is cut off, the positive input terminal of operational amplifier N3B is grounded, the voltage programming signal and the voltage feedback signal generate a voltage error signal at the negative input terminal of operational amplifier N3B, and the voltage error adjustment signal is obtained through compensation and correction by operational amplifier N3B, and the voltage control loop is effective; field effect tube V4 is turned on, and the output voltage feedback signal in the current control loop is clamped to 0; S2. When the simulator works in simulation mode, the control signals of field effect tube V4 and transistor V8 are set low by FPGA, transistor V8 is turned on, and the positive input terminal of operational amplifier N3B is clamped to 5VD. At this time, the voltage error signal generated by the voltage programming signal and the voltage feedback signal is shielded, that is, the voltage control loop fails; field effect tube V4 is cut off, and the voltage feedback signal is followed and isolated by operational amplifier N1B, and the output voltage feedback signal is introduced into the current control loop as a differential term, and the dynamic change of the output voltage signal is effectively controlled in the current control loop; When the simulator is under stable load conditions, since the differential network attenuates the low-frequency signal, the voltage feedback signal has no effect on the error calculation of the current control loop. The FPGA uses the voltage feedback signal as an index to look up the table to obtain the current programming reference value of the IV curve. At this time, the current programming reference value and the current feedback signal perform error calculation and compensation correction, and the obtained error adjustment signal controls the power amplifier circuit; when the simulator is under dynamic load shedding conditions, the dynamically changing voltage feedback signal participates in the current control loop error calculation through the differential network. At this time, the voltage feedback signal passes through the operational amplifier N1B follower isolation, and then passes through the circuit R6, R10 and R14, and the capacitors C2 and C3 become the voltage differential feedback signal. The voltage differential feedback signal participates in the calculation of the current error signal, and the obtained error adjustment signal controls the power amplifier circuit to complete the output of the voltage-controlled current source; The clamping circuit controlled by FPGA programming is used to clamp the dynamically changing voltage feedback signal. Only when the voltage feedback signal is higher than the clamping point voltage, the voltage feedback signal can pass through the differential network to achieve rapid adjustment. The FPGA outputs pulse signals of different frequencies and widths according to the maximum power point voltage of different curves. The pulse signal is inverted by D1C, filtered by two stages of RC, and followed by D2C operational amplifier to obtain a stable DC voltage programming value. The clamping voltage is then obtained by operational amplifier N4B. The voltage following function is realized by using a mirror circuit to complete the voltage clamping. The mirror circuit is composed of two groups of Darlington tubes V1A, V1D and V1B, V1C, and the Darlington tubes are composed of four NPN triodes with consistent parameters and integrated on the same chip.

2. The method for improving the dynamic performance of a solar array simulator according to claim 1, characterized in that: The current control loop includes an operational amplifier N5B, diodes V2-1, V2-2, V3, resistors R2, R3, R7, R12, R15-R18, R20 and R22, and capacitors C5-C7; One end of the resistor R2 is connected to 5VA, and the other end of the resistor R2 is connected to the dynamic performance improvement and clamping circuit, one end of the resistor R16, one end of the resistor R20, one end of the capacitor C7, the negative input end of the operational amplifier N5B, the anode of the diode V2-1, and the cathode of the diode V2-2; the other end of the resistor R16 is connected to one end of the capacitor C5, and the other end of the capacitor C5 is connected to the DAC module and one end of the resistor R17, and the other end of the resistor R17 is connected to one end of the resistor R18, and the other end of the resistor R18 is connected to one end of the capacitor C6; the other end of the resistor R20 is connected to the output current detection circuit; The other end of capacitor C7 is connected to one end of resistor R22 and the positive input end of operational amplifier N5B, and the other end of resistor R22 is connected to ground; the cathode of diode V2-1 is connected to one end of resistor R3 and one end of resistor R7, and the other end of resistor R3 is connected to 15VA, the other end of resistor R7 is connected to one end of resistor R12, the other end of capacitor C6, the output end of operational amplifier N5B, and the cathode of diode V3, and the anode of diode V3 is connected to Vea end; the anode of diode V2-2 is connected to the other end of resistor R12 and one end of resistor R15, and the other end of resistor R15 is connected to -15VA.

3. The method for improving the dynamic performance of a solar array simulator according to claim 2, characterized in that: The dynamic performance improvement and clamping circuit includes operational amplifiers N1B and N4B, transistors V1A, V1B, V1C and V1D, N-channel field effect transistor V4, resistors R1, R4, R5, R6, R8-R11, R13, R14, R19 and R21, and capacitors C1-C4; One end of the resistor R14 is connected to the negative input and output of the operational amplifier N1B, the other end of the resistor R14 is connected to one end of the resistor R9 and one end of the capacitor C2, the positive input of the operational amplifier N1B is connected to one end of the resistor R19 and the drain of the field effect tube V4, the other end of the resistor R19 is connected to the output voltage detection circuit, the gate of the field effect tube V4 is connected to one end of the resistor R21, the other end of R21 is connected to the FPGA, and the source of the field effect tube V4 is connected to the ground; one end of the resistor R4 is connected to the VMPDAC end, the other end of the resistor R4 is connected to one end of the capacitor C1, one end of the resistor R5, and the negative input of the operational amplifier N4B, the other end of the capacitor C1 is connected to the other end of the resistor R5, the output of the operational amplifier N4B, one end of the resistor R8, and one end of the capacitor C4, the positive input of the operational amplifier N4B is connected to one end of the resistor R11 and one end of the resistor R13, The other end of resistor R11 is connected to 2V5R, the other end of resistor R13 is connected to the RG end, the other end of capacitor C4 is connected to ground, the other end of resistor R8 is connected to the collector of transistor V1C, the base of transistor V1C is connected to the collector of transistor V1B, the emitter of transistor V1C is connected to one end of resistor R1, the emitter and base of transistor V1B, and the base of transistor V1A, the other end of resistor R1 is connected to 15VA, the emitter of transistor V1A is connected to 15VA and the emitter of transistor V1D, the collector of transistor V1A is connected to the base of transistor V1D, and the collector of transistor V1D is connected to the other end of resistor R9; the other end of capacitor C2 is connected to one end of capacitor C3 and one end of resistor R6, the other end of capacitor C3 is connected to one end of resistor R10, and the other end of resistor R6 and the other end of resistor R10 are commonly connected to the other end of resistor R2 in the current control loop.

4. The method for improving the dynamic performance of a solar array simulator according to claim 3, characterized in that: The FPGA is connected to the input end of the inverter D1C, and its output end is connected to one end of the resistor R23D. The other end of the resistor R23D is connected to one end of the capacitor C41 and one end of the resistor R23C. The other end of the resistor C41 is connected to the AG end. The other end of the resistor R23C is connected to one end of the capacitor C40 and the positive input end of the operational amplifier D2C. The other end of the capacitor C40 is connected to the AG end. The negative input end of the operational amplifier is connected to its output end and one end of the magnetic bead L10B. The other end of the magnetic bead L10B is connected to the VMPDAC end.

5. The method for improving the dynamic performance of a solar array simulator according to claim 1, characterized in that: The voltage control loop includes operational amplifiers N2B, N3B and peripheral devices, and the peripheral devices include resistors R23-R38, capacitors C8-C15, transistor V8, diodes V5-1, V5-2, V6, V7 and V9; One end of the resistor R30 is connected to the DAC module, and the other end is connected to one end of the capacitor C9 and the positive input end of the operational amplifier N2B. The negative input end of the operational amplifier N2B is connected to its output end and one end of the resistor R28. The other end of the circuit R28 is connected to one end of the resistor R23, the anode of the diode V5-1, the cathode of the diode V5-2, one end of the resistor R29, one end of the resistor R32, one end of the resistor R31, one end of the resistor R34, one end of the capacitor C13 and the negative input end of the operational amplifier N3B; the resistor R23 The other end of the diode V5-1 is connected to 5VA; the cathode of the diode V5-1 is connected to one end of the resistor R24 ​​and one end of the resistor R25, the other end of the resistor R24 ​​is connected to 15VA, the other end of the resistor R25 is connected to one end of the resistor R26, one end of the capacitor C8, one end of the capacitor C10, one end of the capacitor C12, the output end of the operational amplifier N3B and the cathode of the diode V7, the anode of the diode V7 is connected to the Vea end; the anode of the diode V5-2 is connected to the other end of the resistor R26 and one end of the resistor R27, the other end of the resistor R27 is connected -15VA; the other end of resistor R29 is connected to the other end of capacitor C8; the other end of resistor R32 is connected to one end of resistor R33, the other end of resistor R33 is connected to the other end of capacitor C12, the other end of capacitor C10 and the cathode of diode V6, and the anode of diode V6 is connected to the VG end; the other end of resistor R31 is connected to one end of capacitor C11, the other end of capacitor C11 is connected to the output voltage detection circuit and the other end of resistor R34; the other end of capacitor C13 is connected to the positive input end of operational amplifier N3B and resistor R38 One end of the resistor R38 is connected to the VG end, the other end of the capacitor C15 is connected to the VG end, the anode of the diode V9 is connected to one end of the resistor R37, the emitter of the transistor V8, and one end of the capacitor C14, the other end of the capacitor C14 is connected to one end of the resistor R36, one end of the resistor R35, and the base of the transistor V8, the other end of the resistor R35 is connected to the collector of the transistor V8 and 5VD, the other end of the resistor R36 is connected to the FPGA, and the other end of R37 is connected to the GG end.

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