Basic memory cell management circuit and basic memory cell management method

Abstract

A basic memory cell management circuit and a basic memory cell management method are disclosed. The basic memory cell management circuit includes a receiving circuit, a transmitting circuit, a first buffer, and an idle basic memory cell controller. The first buffer stores a bit table, wherein the bit table includes a plurality of first bits, each corresponding to a plurality of basic memory cells, and each of the plurality of first bits is used to indicate whether a corresponding basic memory cell is an idle basic memory cell. The idle basic memory cell controller is coupled to the receiving circuit, the transmitting circuit, and the first buffer, and is used to manage the bit table stored in the first buffer, and to process at least one basic memory cell corresponding to at least one packet received by the receiving circuit or transmitted by the transmitting circuit according to the bit table.

Description

Technical Field

[0001] This invention relates to data management, and more particularly to a basic storage unit management circuit and a basic storage unit management method for idle basic storage units. Background Technology

[0002] In traditional switches, routers, or media access control (MAC) systems, a memory, such as static random access memory (SRAM), is typically divided into multiple basic storage units. A multi-bit link list of idle basic storage units is used to manage these idle units. However, several problems can arise. Since the address of an idle basic storage unit in the multi-bit link list is stored in the address of the previous idle basic storage unit, the size of a memory (e.g., SRAM) with such a link list can increase with the number of basic storage units, potentially increasing cost and read time. Furthermore, the throughput for getting / releasing idle basic storage units can be limited by the memory's bandwidth. Therefore, a novel architecture is needed to replace the idle basic storage unit link list. Summary of the Invention

[0003] Therefore, one of the objectives of this invention is to provide a basic memory cell management circuit and a related basic memory cell management method to solve the above-mentioned problems.

[0004] At least one embodiment of the present invention provides a basic memory cell management circuit, wherein the basic memory cell management circuit may include a receiving circuit, a transmitting circuit, a first buffer, and an idle basic memory cell controller. The first buffer can be used to store a bit table, wherein the bit table includes a plurality of first bits, each corresponding to a plurality of basic memory cells, and each of the plurality of first bits is used to indicate whether a corresponding basic memory cell is an idle basic memory cell. The idle basic memory cell controller may be coupled to the receiving circuit, the transmitting circuit, and the first buffer, and can be used to manage the bit table stored in the first buffer, and to process at least one basic memory cell of at least one packet received by the receiving circuit or transmitted by the transmitting circuit according to the bit table, wherein when a basic memory cell of the plurality of basic memory cells is an idle basic memory cell, the idle basic memory cell controller sets a first bit corresponding to that basic memory cell to a first logic value; and when the basic memory cell of the plurality of basic memory cells is not an idle basic memory cell, the idle basic memory cell controller sets a first bit corresponding to that basic memory cell to a second logic value.

[0005] At least one embodiment of the present invention provides a basic storage unit management method. The basic storage unit management method may include: storing a bit table, wherein the bit table includes a plurality of first bits, each corresponding to a plurality of basic storage units, and each of the plurality of first bits is used to indicate whether a corresponding basic storage unit is an idle basic storage unit; and using an idle basic storage unit controller to process at least one basic storage unit corresponding to at least one packet received by a receiving circuit or transmitted by a transmitting circuit according to the bit table, and managing the bit table, wherein when a basic storage unit of the plurality of basic storage units is an idle basic storage unit, the idle basic storage unit controller sets a first bit corresponding to that basic storage unit to a first logic value, and when the basic storage unit of the plurality of basic storage units is not an idle basic storage unit, the idle basic storage unit controller sets a first bit corresponding to that basic storage unit to a second logic value.

[0006] One advantage of this invention is that the basic memory cell management circuit provided by this invention can manage idle basic memory cells using a memory buffer storing a bit table and a temporary register buffer. The idle basic memory cell controller of the basic memory cell management circuit first finds a target second bit with a first logic value (e.g., 1) from a plurality of second bits in the temporary register buffer to obtain a read address, and reads a target valid idle memory cell identifier field in the bit table of the memory buffer according to the read address, and finds at least one target first bit with a first logic value (e.g., 1) from the target valid idle memory cell identifier field to obtain at least one idle basic memory cell. In this way, the time for reading the memory buffer can be greatly reduced. In addition, in order to reduce the power consumption of the memory buffer and save the bandwidth of the memory buffer, this invention also provides a basic memory cell management circuit, which includes a release basic memory cell buffer, wherein releasing the basic memory cell buffer can be used to reduce the number of accesses to the memory buffer. Attached Figure Description

[0007] Figure 1 This is a schematic diagram showing the correspondence between bits in a memory buffer and bits in a temporary register buffer according to an embodiment of the present invention.

[0008] Figure 2 This is a schematic diagram of a basic memory cell management circuit according to an embodiment of the present invention.

[0009] Figure 3 This is a schematic diagram of a basic memory cell management circuit according to another embodiment of the present invention.

[0010] Figure 4 This is a flowchart of a basic storage unit management method according to an embodiment of the present invention.

[0011] Symbol Explanation

[0012] 100, 200, 300: Static Random Access Memory Buffers

[0013] 101, 201, 301: Bit table

[0014] 110, 210, 310: Temporary register buffers

[0015] a~d: Fields indicating available idle storage units

[0016] e~h: Second digit

[0017] 20, 30: Basic memory cell management circuit

[0018] 220, 320: Idle Basic Storage Unit Controller

[0019] 230, 330: Receiving circuit

[0020] 240, 340: Transmission circuit

[0021] 350: Release the basic memory unit buffer

[0022] B10, B21, B22, B27: First element

[0023] S400, S402: Steps Detailed Implementation

[0024] Figure 1 This is a schematic diagram illustrating the correspondence between bits in a memory buffer and bits in a temporary register buffer according to an embodiment of the present invention. Figure 1 As shown, a memory buffer (e.g., static random access memory buffer 100; for simplicity, in) Figure 1 The SRAM buffer (labeled as "SRAM buffer") can be used to store a bit table 101, which may contain 32 bit bits (each corresponding to one of 32 basic storage units). Each of the 32 bit bits can be used to indicate whether a corresponding basic storage unit is an idle basic storage unit. For example, when a basic storage unit is an idle basic storage unit, the bit bit corresponding to that basic storage unit is a first logic value (e.g., 1); and when a basic storage unit is not an idle basic storage unit, the bit bit corresponding to that basic storage unit is a second logic value (e.g., 0). Furthermore, in order to save time reading the memory buffer and find idle basic memory units more quickly, the bit table can be divided into multiple effective idle memory unit identification fields in units of multiple bits. For example, the M x N (e.g., M x N = 32) first bits in bit table 101 can be divided into N (e.g., N = 4) effective idle memory unit identification fields (e.g., effective idle memory unit identification field a to effective idle memory unit identification field d) in units of M (e.g., M = 8).

[0025] The register buffer 110 can be used to store four second bits (e.g., second bits e to second bits h, which correspond to valid idle memory cell identifier fields a to d in bit table 101, respectively), wherein each of the four second bits can be used to indicate whether a corresponding valid idle memory cell identifier field contains at least one first bit with a first logic value (e.g., 1) (that is, to indicate whether the eight basic memory cells corresponding to the eight first bits in the corresponding valid idle memory cell identifier field contain at least one idle basic memory cell). When one of the four valid free storage cell identifier fields contains at least one first bit with a first logical value (e.g., 1), the second bit corresponding to that valid free storage cell identifier field is the first logical value (e.g., 1); and when all the first bits contained in one of the four valid free storage cell identifier fields have a second logical value (e.g., 0) (that is, there are no free basic storage cells among the eight basic storage cells corresponding to the eight first bits in that valid free storage cell identifier field), the second bit corresponding to that valid free storage cell identifier field is the second logical value (e.g., 0). For example, since valid free storage cell identifier field a in bit table 101 contains four first bits with a first logical value (e.g., 1), the second bit e corresponding to valid free storage cell identifier field a is the first logical value (e.g., 1). For example, since all the first bits in the valid free storage cell identifier field c in bit table 101 have a second logic value (e.g., 0), the second bit g corresponding to the valid free storage cell identifier field c is a second logic value (e.g., 0).

[0026] Figure 2 This is a schematic diagram of a basic memory cell management circuit 20 according to an embodiment of the present invention. Figure 2 As shown, the basic memory cell management circuit 20 may include a memory buffer (e.g., a static random access memory buffer 200; for simplicity, in...). Figure 2 The system includes a static random access memory buffer (SRAM buffer), a temporary register buffer 210, an idle basic memory cell controller 220, a receiving circuit 230, and a transmission circuit 240. The static random access memory buffer 200 and the temporary register buffer 210 can be respectively... Figure 1The static random access memory buffer 100 and the temporary register buffer 110 shown are used to implement this. The static random access memory buffer 200 can be used to store a bit table 201. In this embodiment, the bit table 201 may contain 32 first bits (each corresponding to one of the 32 basic storage units), and the 32 first bits in the bit table 201 can be divided into 4 effective free storage unit indicator fields in units of 8 bits (e.g., effective free storage unit indicator fields a to d). However, this is only an example and not a limitation of the present invention. In practice, the size of the bit table 201 and the division of the effective free storage unit indicator fields can be adjusted according to the requirements. The temporary register buffer 210 can be used to store four second bits (e.g., second bits e to second bits h, which correspond to valid free storage cell identifier fields a to d in the bit table 201, respectively). However, this is only an example and not a limitation of the invention. In practice, the number of second bits stored in the temporary register buffer 210 depends on the number of valid free storage cell identifier fields in the bit table 201. For the sake of brevity, similar descriptions of the static random access memory buffer 200 and the temporary register buffer 210 in this embodiment will not be repeated here.

[0027] The idle basic storage unit controller 220 can be coupled to the static random access memory buffer 200, the receiving circuit 230, and the transmitting circuit 240. It can be used to manage the bit table 201 stored in the static random access memory buffer 200, and to process at least one basic storage unit of at least one packet received by the receiving circuit 230 or transmitted by the transmitting circuit 240 according to the bit table 201. When one of the 32 basic storage units corresponding to the first bit of the 32 bits of the bit table 201 is an idle basic storage unit, the idle basic storage unit controller 220 can set the first bit corresponding to the basic storage unit to a first logic value (e.g., 1); and when one of the 32 basic storage units corresponding to the first bit of the 32 bits of the bit table 201 is not an idle basic storage unit, the idle basic storage unit controller 220 can set the first bit corresponding to the basic storage unit to a second logic value (e.g., 0). Furthermore, the idle basic storage unit controller 220 may also be coupled to the register buffer 210, wherein when one of the four valid idle storage unit indicator fields of the bit table 201 contains at least one first bit with a first logic value (e.g., 1), the idle basic storage unit controller 220 may set the second bit corresponding to the valid idle storage unit indicator field to the first logic value (e.g., 1); and when all the first bits contained in one of the four valid idle storage unit indicator fields of the bit table 201 have a second logic value (e.g., 0), the idle basic storage unit controller 220 may set the second bit corresponding to the valid idle storage unit indicator field to the second logic value (e.g., 0).

[0028] When the receiving circuit 230 receives a received packet, the idle basic storage unit controller 220 can obtain at least one idle basic storage unit through the static random access memory buffer 200 and the register buffer 210 to temporarily store the received packet. For example, the idle basic storage unit controller 220 will first find a target second bit (e.g., second bit e, second bit f, or second bit h) with a first logic value (e.g., 1) from the four second bits (e.g., second bits e to second bits h) of the register buffer 210 to obtain a read. The address is retrieved, and a target valid free memory cell identifier field (e.g., valid free memory cell identifier field a corresponding to the second bit e, valid free memory cell identifier field b corresponding to the second bit f, or valid free memory cell identifier field d corresponding to the second bit h) is read from the bit table 201 of the static random access memory buffer 200 according to the read address. Finally, at least one target first bit with a first logic value (e.g., 1) is found from the target valid free memory cell identifier field to obtain at least one free basic memory cell.

[0029] It should be noted that after at least one idle basic storage unit is used to temporarily store the received packet, the idle basic storage unit controller 220 can also update the at least one target first bit corresponding to the at least one idle basic storage unit from a first logic value (e.g., 1) to a second logic value (e.g., 0). Furthermore, after the idle basic storage unit controller 220 updates the at least one target first bit corresponding to the at least one idle basic storage unit, when all the first bits in the target valid idle storage unit identifier field containing the at least one target first bit have a second logic value (e.g., 0), the idle basic storage unit controller 220 can also be used to temporarily store the packet. The second bit in buffer 210 corresponding to the target valid idle memory cell identifier field is updated from a first logical value (e.g., 1) to a second logical value (e.g., 0). On the other hand, after the idle basic memory cell controller 220 updates the at least one target first bit corresponding to the at least one idle basic memory cell, if the target valid idle memory cell identifier field containing the at least one target first bit still contains at least one first bit with a first logical value (e.g., 1), the idle basic memory cell controller 220 can further maintain the second bit in the register buffer 210 corresponding to the target valid idle memory cell identifier field at the first logical value (e.g., 1). The idle basic memory cell controller 220 can implement the updating of 32 first bits in the bit table of the static random access memory buffer 200 and 4 second bits of the register buffer 210 through a pipeline, but the present invention is not limited thereto.

[0030] When the transmission circuit 240 finishes transmitting a transmission packet, the transmission circuit 240 releases at least one basic storage unit corresponding to the transmission packet to the idle basic storage unit controller 220. The idle basic storage unit controller 220 can update at least one target first bit in at least one target valid idle storage unit indicator field in the bit table 201 of the static random access memory buffer 200 from a second logic value (e.g., 0) to a first logic value (e.g., 1) according to the at least one target first bit. That is, at least one basic storage unit corresponding to the at least one target first bit is at least one idle basic storage unit. Furthermore, when at least one target first bit in the original at least one target valid idle storage unit identifier field all has a second logic value (e.g., 0) (i.e., the original at least one target valid idle storage unit identifier field does not have an idle basic storage unit), after the idle basic storage unit controller 220 updates the at least one target first bit, when the at least one target valid idle storage unit identifier field containing the at least one target first bit contains at least one first bit with a first logic value (e.g., 1), the idle basic storage unit controller 220 can also be used to add a corresponding first bit to the register buffer 210. At least one second bit of a target valid idle memory cell identifier field is updated from a second logic value (e.g., 0) to a first logic value (e.g., 1). On the other hand, if the original target valid idle memory cell identifier field already contains at least one first bit with a first logic value (e.g., 1) (i.e., the original target valid idle memory cell identifier field already contains idle basic memory cells), the idle basic memory cell controller 220 may also be used to maintain at least one second bit in the register buffer 210 corresponding to the at least one target valid idle memory cell identifier field as the first logic value (e.g., 1).

[0031] Furthermore, to reduce the power consumption of the memory buffer and save its bandwidth, a basic memory cell buffer can be used to reduce the number of memory buffer accesses. Figure 3 This is a schematic diagram of a basic memory cell management circuit 30 according to another embodiment of the present invention. Figure 3 As shown, the basic memory cell management circuit 30 may include a memory buffer (e.g., a static random access memory buffer 300; for simplicity, in...). Figure 3 The system includes an SRAM buffer (labeled as "SRAM buffer"), a temporary register buffer 310, an idle basic memory cell controller 320, a receiving circuit 330, a transmitting circuit 340, and a basic memory cell release buffer 350. Figure 3 The basic memory cell management circuit 30 shown is... Figure 2The difference in the shown basic memory management circuit 20 is that the basic memory management circuit 30 may also include a release basic memory buffer 350. The release basic memory buffer 350 may be coupled to the idle basic memory controller 320 and the transmission circuit 340, and can be used to temporarily store at least one basic memory corresponding to a transmission packet released when the transmission circuit 340 completes the transmission of a transmission packet. The idle basic memory controller 320 can obtain at least one basic memory corresponding to a transmission packet from the release basic memory buffer 350 as an idle basic memory. In this way, when the receiving circuit 330 receives a receive packet, the idle basic memory controller 320 can pre-read the at least one basic memory corresponding to a transmission packet temporarily stored in the release basic memory buffer 350 for use in receiving the packet, without needing to obtain an idle basic memory through the static random access memory buffer 300 and the register buffer 310 (which reduces the number of accesses to the static random access memory buffer 300).

[0032] In this embodiment, the idle basic memory cell corresponding to the first bit B10 in the static random access memory buffer 300 is temporarily stored in the basic memory cell buffer 350 (it is temporarily stored in the basic memory cell buffer 350 with a decimal value of 10 as 5 bits), and... Figure 3 The idle basic memory unit corresponding to the first bit B21 (marked as "5'd10") is temporarily stored in the free basic memory unit buffer 350 with a decimal value of 21 (5 bits). Figure 3 The idle basic memory unit corresponding to the first bit B22 (marked as "5'd21") is temporarily stored in the free basic memory unit buffer 350 with a decimal value of 22 (5 bits). Figure 3 The idle basic memory unit corresponding to the first bit B27 (marked as "5'd22") and the 5 bits of the free basic memory unit (which are temporarily stored in the free basic memory unit buffer 350 with a decimal value of 27) are also temporarily stored in the free basic memory unit buffer 350. Figure 3(marked as "5'd27" in the text). It should be noted that when at least one basic storage unit corresponding to the transmission packet temporarily stored in the basic storage unit buffer 350 is occupied (i.e., there is no idle basic storage unit in the basic storage unit buffer 350), the idle basic storage unit controller 320 can find a target second bit with a first logic value (e.g., 1) from the four second bits of the register buffer 310 to obtain a read address, and read a target valid idle storage unit identifier field in the bit table 301 of the static random access memory buffer 300 according to the read address, and find at least one target first bit with a first logic value (e.g., 1) from the target valid idle storage unit identifier field to obtain at least one idle basic storage unit for use in receiving packets. In other words, if the release basic storage unit buffer 350 has an idle basic storage unit available for use, the idle basic storage unit controller 320 will first read the release basic storage unit buffer 350. If it cannot obtain the required idle basic storage unit from the release basic storage unit buffer 350, the idle basic storage unit controller 320 will then obtain the idle basic storage unit through the temporary register buffer 310 and the static random access memory buffer 300.

[0033] In the above embodiments, the idle basic storage unit controller 220 (or idle basic storage unit controller 320) can quickly find the first bit indicating the idle basic storage unit from the bit table of the static random access memory buffer 200 (or static random access memory buffer 300) by using the second bit stored in the register buffer 210 (or register buffer 310). However, the register buffer can be an optional element. For example, in some embodiments of the present invention, the data management circuit 20 (or data management circuit 30) can omit the register buffer 210 (or register buffer 310) and directly search the bit table of the static random access memory buffer 200 (or static random access memory buffer 300) to find the first bit indicating the idle basic storage unit. In summary, any data management circuit that uses bits recorded in a bit table to indicate whether a corresponding basic storage unit is an idle basic storage unit falls within the scope of the present invention.

[0034] Figure 4 This is a flowchart of a basic memory unit management method according to an embodiment of the present invention. If the same result can be obtained, the steps do not necessarily need to be followed exactly. Figure 4 The process shown is executed sequentially. For example, at... Figure 4 The basic storage unit management method shown can be derived from... Figure 2 The data management circuit 20 shown or Figure 3 The data management circuit 30 shown is used to implement this.

[0035] In step S400, the static random access memory buffer can store a bit table, wherein the bit table can contain multiple first bits, which correspond to multiple basic storage units respectively, and each of the multiple first bits can be used to indicate whether the corresponding basic storage unit is an idle basic storage unit.

[0036] In step S402, an idle basic storage unit controller can be used to manage the bit table and process at least one basic storage unit corresponding to at least one packet received by a receiving circuit or transmitted by a transmitting circuit according to the bit table. When one of the basic storage units of the plurality of basic storage units is an idle basic storage unit, the idle basic storage unit controller can set the first bit corresponding to the basic storage unit to a first logic value. When the basic storage unit of the plurality of basic storage units is not an idle basic storage unit, the idle basic storage unit controller can set the first bit corresponding to the basic storage unit to a second logic value.

[0037] Because technicians can easily understand the contents of the above instruction manual. Figure 4 For the sake of brevity, the operations shown in each step will not be repeated here in this embodiment.

[0038] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

Claims

1. A basic memory cell management circuit, comprising: A receiving circuit; A transmission circuit; A first buffer is used to store a bit table, wherein the bit table contains a plurality of first bits, each corresponding to a plurality of basic storage units, and each of the plurality of first bits is used to indicate whether a corresponding basic storage unit is an idle basic storage unit. An idle basic storage unit controller, coupled to the receiving circuit, the transmitting circuit, and the first buffer, is used to manage the bit table stored in the first buffer and to process at least one basic storage unit corresponding to at least one packet received by the receiving circuit or transmitted by the transmitting circuit according to the bit table. When a basic storage unit among the plurality of basic storage units is an idle basic storage unit, the idle basic storage unit controller sets a first bit corresponding to that basic storage unit to a first logic value; and when the basic storage unit among the plurality of basic storage units is not an idle basic storage unit, the idle basic storage unit controller sets the first bit corresponding to that basic storage unit to a second logic value. The plurality of first bits in the bit table are divided into a plurality of valid idle storage unit indicator fields. The basic storage unit management circuit further includes: A second buffer, coupled to the idle basic memory cell controller, is used to store a plurality of second bits, each corresponding to a plurality of valid idle memory cell label fields, wherein each of the plurality of second bits is used to indicate whether a corresponding valid idle memory cell label field contains at least one first bit having the first logic value. When one of the multiple valid idle storage unit indicator fields contains at least one first bit with the first logic value, the idle basic storage unit controller sets a second bit corresponding to the valid idle storage unit indicator field to one of the first logic value and the second logic value; and when all the first bits contained in the valid idle storage unit indicator field of the multiple valid idle storage unit indicator fields have the second logic value, the idle basic storage unit controller sets the second bit corresponding to the valid idle storage unit indicator field to the other of the first logic value and the second logic value.

2. The basic storage unit management circuit as claimed in claim 1, wherein when the receiving circuit receives a receive packet, the idle basic storage unit controller first finds a target second bit with the logic value from the plurality of second bits of the second buffer to obtain a read address, and reads a target valid idle storage unit identifier field in the bit table of the first buffer according to the read address, and finds at least one target first bit with the first logic value from the target valid idle storage unit identifier field to obtain at least one idle basic storage unit.

3. The basic memory cell management circuit as described in claim 2, wherein the idle basic memory cell controller is further configured to update the at least one target bit from the first logic value to the second logic value.

4. The basic storage unit management circuit as claimed in claim 1, wherein when the transmission circuit finishes transmitting a transmission packet, the transmission circuit releases at least one basic storage unit corresponding to the transmission packet to the idle basic storage unit controller.

5. The basic storage unit management circuit as claimed in claim 4, wherein the idle basic storage unit controller is further configured to update at least one target first bit in the target valid idle storage unit identifier field of the bit table of the first buffer from the second logic value to the first logic value according to the at least one basic storage unit of the transmission packet.

6. The basic memory cell management circuit as described in claim 1 further comprises: A release basic storage unit buffer is coupled to the transmission circuit and the idle basic storage unit controller, and is used to temporarily store at least one basic storage unit corresponding to the transmission packet released when the transmission circuit finishes transmitting a transmission packet, wherein the idle basic storage unit controller obtains the at least one basic storage unit corresponding to the transmission packet from the release basic storage unit buffer as an idle basic storage unit.

7. The basic storage unit management circuit as claimed in claim 6, wherein when the receiving circuit receives a receive packet, the idle basic storage unit controller reads the at least one basic storage unit corresponding to the transmission packet temporarily stored in the release basic storage unit buffer for use by the receive packet.

8. The basic storage unit management circuit as claimed in claim 7, wherein when all at least one basic storage unit corresponding to the transmission packet temporarily stored in the release basic storage unit buffer is occupied, the idle basic storage unit controller finds a target second bit with the logic value from the plurality of second bits of the second buffer to obtain a read address, and reads a target valid idle storage unit identifier field in the bit table of the first buffer according to the read address, and finds at least one target first bit with the first logic value from the target valid idle storage unit identifier field to obtain at least one idle basic storage unit for use by the received packet.

9. A basic storage unit management method, comprising: Store a bit table, wherein the bit table contains a plurality of first bits, each corresponding to a plurality of basic storage units, and each of the plurality of first bits is used to indicate whether a corresponding basic storage unit is an idle basic storage unit. An idle basic storage unit controller is used to manage the bit table and process at least one basic storage unit corresponding to at least one packet received by a receiving circuit or transmitted by a transmitting circuit according to the bit table, wherein when a basic storage unit of the plurality of basic storage units is an idle basic storage unit, the idle basic storage unit controller sets a first bit corresponding to the basic storage unit to a first logic value, and when the basic storage unit of the plurality of basic storage units is not the idle basic storage unit, the idle basic storage unit controller sets the first bit corresponding to the basic storage unit to a second logic value; The first bit in the bit table is divided into multiple valid free storage unit indicator fields; and The system stores a plurality of second bits, each corresponding to a plurality of valid idle storage unit indicator fields. Each of the plurality of second bits is used to indicate whether a corresponding valid idle storage unit indicator field contains at least one first bit having the first logic value. When a valid idle storage unit indicator field contains the at least one first bit having the first logic value, the idle basic storage unit controller sets the second bit corresponding to the valid idle storage unit indicator field to one of the first logic value and the second logic value. And when all the first bits contained in the valid idle storage unit indicator field have the second logic value, the idle basic storage unit controller sets the second bit corresponding to the valid idle storage unit indicator field to the other of the first logic value and the second logic value.

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