An efficient data checking system and method thereof

Abstract

An efficient data check system and method thereof. The efficient data check system comprises a storage module, an IO register, an IO port, a comparator, and an interrupt port. The IO register comprises a first GPIO register and a second GPIO register. The first and second GPIO registers are used to control the output and input of the IO port and to realize digital-to-analog conversion. The IO port comprises a first GPIO port and a second GPIO port. The comparator has two input terminals connected with the first and second GPIO ports respectively. The first and second GPIO ports read the converted analog quantity of the IO register and determine the high and low of the potential according to the analog quantity. The comparator receives the high potential or the low potential and compares them. The interrupt port judges whether the data is the same according to the output of the comparator, adopts the method of byte-by-byte comparison, and realizes the check. Thus, the process of temporarily storing the compared data is saved, and the process of calculating CRC is also saved. The speed is faster and the efficiency is higher.

Description

Technical Field

[0001] This invention relates to the field of data verification technology, and in particular to an efficient data verification system and method. Background Technology

[0002] Electronic paper, also known as digital paper, is an ultra-thin, ultra-light display screen—essentially a paper-thin, flexible, and erasable display. In existing technologies, firmware programming for electronic paper modules is performed using a test board. Operators need to transmit the information of the module to be programmed to the test board via a data input device. The test board then programs the information into the product, as disclosed in patent number CN202110997958.2, which describes a firmware programming method, apparatus, and related equipment.

[0003] However, since different module models require different firmware to be downloaded to the test board, the issue of firmware compatibility arises. Manually verifying each module individually is too tedious, and errors are prone to occur during batch firmware flashing, making it difficult to quickly locate damaged hardware and hindering repair. Furthermore, verifying the flashed data typically involves reading the data for CRC checks after flashing, requiring data rereading, increasing flashing time and impacting efficiency. Summary of the Invention

[0004] In view of this, the present invention provides an efficient data verification system and method to solve the above-mentioned technical problems.

[0005] A high-efficiency data verification system includes two storage modules, two I / O registers connected to the storage modules respectively, multiple I / O ports connected to the I / O registers, multiple comparators connected to the I / O ports, and an interrupt port connected to the comparators. The two storage modules respectively store first and second data to be compared. The I / O registers include a first GPIO register and a second GPIO register, which are used to control the output and input of the I / O ports and implement digital-to-analog conversion. The I / O ports include multiple first GPIO ports connected to the first GPIO registers and multiple second GPIO ports connected to the second GPIO registers. The first and second GPIO ports read the analog signal converted by the I / O registers and determine the high or low potential based on the analog signal, while simultaneously outputting a high or low potential to the comparators. The comparators have two input terminals connected to the first and second GPIO ports respectively, capable of receiving high or low potentials and comparing them. The interrupt port determines whether the data is the same based on the output of the comparators.

[0006] Furthermore, the first and second GPIO registers are 8-bit, 16-bit, and 32-bit. 8-bit corresponds to 1 byte of data for simultaneous digital-to-analog conversion, 16-bit corresponds to 2 bytes of data, and 32-bit corresponds to 4 bytes of data. The number of bits in the first and second GPIO registers matches the number of comparators: 8 bits for 8 comparators, 16 bits for 16 comparators, and 32 bits for 32 comparators.

[0007] Furthermore, the number of the first and second GPIO ports is the same as the number of bits in the first and second GPIO registers.

[0008] Furthermore, when the voltages at the two input terminals of the comparator are the same, it means that the two data to be compared are the same, and the comparator outputs a high level; when the voltages at the two input terminals of the comparator are different, it means that the two data to be compared are different, and the comparator outputs a low level.

[0009] Furthermore, the comparator is also connected to a diode to prevent backflow of the signal output by the comparator.

[0010] Furthermore, the interrupt port is set to a falling edge interrupt, so a falling edge will occur when the comparator outputs a low level.

[0011] An efficient data validation method includes the following steps:

[0012] Step S1: Provide two storage modules, two I / O registers connected to the storage modules respectively, multiple I / O ports connected to the I / O registers, multiple comparators connected to the I / O ports, and an interrupt port connected to the comparators. Create two RAM areas in the microcontroller's RAM region, including RAM1 for storing the first data to be compared and RAM2 for storing the second data to be compared. Set parameters i1, i2, and k in the microcontroller. i1 is used to count the number of bytes compared, i2 is used to store the positions where different data occurs, and k is used to count the frequency of different comparisons.

[0013] Step S2: The I / O register includes a first GPIO register and a second GPIO register. The number of bytes compared in a single operation is determined based on the bit width of the first GPIO register and the second GPIO register.

[0014] Step S3: The first GPIO register reads n bytes of RAM1 data, and then sends it to the I / O port after digital-to-analog conversion. The second GPIO register reads n bytes of RAM2 data, and then sends it to the I / O port after digital-to-analog conversion.

[0015] Step S4: The I / O port determines the potential level based on the analog signal, and then sends the high or low potential to the comparator.

[0016] Step S5: If the voltages received at the two input terminals of the comparator are the same, it means that the data is the same, and the comparator outputs a high level. If the voltages at the two input terminals of the comparator are different, it means that the data is different, and the comparator outputs a low level.

[0017] Step S6: The interrupt port is a falling edge interrupt. When the interrupt port receives a low level, a falling edge will occur and an interrupt will occur. The interrupt port determines whether an interrupt has occurred. If an interrupt has occurred, proceed to step S7. If no interrupt has occurred, proceed to step S8. Record the amount of data i1 that has been compared for each byte transmitted in the first GPIO register and the second GPIO register.

[0018] Step S7: Statistically compare the different positions of the data and record them in i2.

[0019] Step S8: Determine if i1 is equal to the total amount of data. If i1 is less than the total amount of data, return to step S3 and continue to compare the remaining data. When i2 is equal to the total amount of data, the verification ends.

[0020] Furthermore, in step S7 above, based on the number of bytes being transmitted in the first GPIO register and the second GPIO register, the different locations where data occurs are determined and recorded in i2. At the same time, the number of interrupts K is counted, and K is incremented by 1 for each interrupt.

[0021] Furthermore, in step S4 above, the I / O port determines the voltage level based on the analog signal, where 1 represents a high level and 0 represents a low level.

[0022] Compared with existing technologies, the efficient data verification system provided by this invention uses the first and second GPIO registers to send n bytes of data from the first and second comparison data to the first and second GPIO ports after digital-to-analog conversion. The analog signals from the first and second GPIO ports determine the voltage levels (1 for high level, 0 for low level) and are sent to the comparator. When the voltages at the two input terminals of the comparator are different, it indicates that the two comparison data are different, and the comparator outputs a low level, causing an interrupt to occur at the interrupt port. This verifies whether the data are the same, and also determines the location of the data difference and counts the number of interrupts for subsequent work. This invention uses a byte-by-byte comparison method for verification, which eliminates the process of temporarily storing the comparison data and avoids the CRC calculation process, resulting in faster speed and higher efficiency. Attached Figure Description

[0023] Figure 1This is a schematic diagram of the structure of an efficient data verification system provided by the present invention.

[0024] Figure 2 for Figure 1 The flowchart shows an efficient data verification method. Detailed Implementation

[0025] The following provides a more detailed description of specific embodiments of the present invention. It should be understood that the description of the embodiments of the present invention herein is not intended to limit the scope of protection of the present invention.

[0026] like Figures 1 to 2 The diagram shown is a structural schematic of the efficient data verification system and method provided by this invention. The efficient data verification system includes two storage modules 10, two I / O registers 20 respectively connected to the storage modules 10, multiple I / O ports 30 connected to the I / O registers 20, multiple comparators 40 connected to the I / O ports 30, and an interrupt port 50 connected to the comparators 40. It is conceivable that the efficient data verification system is for data verification of a microcontroller system, and therefore also includes other functional modules of the microcontroller, such as control modules, circuit conversion modules, and transmission modules, etc., which are technologies well known to those skilled in the art and will not be described in detail here.

[0027] The two storage modules 10 respectively store the first data to be compared and the second data to be compared. The data to be compared can be directly stored in the microcontroller's ROM space or transmitted to the microcontroller through other communication methods.

[0028] The I / O register 20 includes a first GPIO register 21 and a second GPIO register 22. The first and second GPIO registers 21 and 22 are used to control the output and input of the I / O port 30 and to implement digital-to-analog conversion. The first and second GPIO registers 21 and 22 have 8 bits, 16 bits, and 32 bits, therefore the number of data bytes transmitted simultaneously varies with the bit depth, and the speed also varies, which can be set as needed. 8 bits correspond to simultaneous digital-to-analog conversion of 1 byte of data, with a speed of 5-10 Mbyte / s. 16 bits correspond to 2 bytes of data, with a speed of 10-20 Mbyte / s. 32 bits correspond to 4 bytes of data, with a speed of 20-40 Mbyte / s. The number of comparators 40 also needs to be matched with the bit depth of the first and second GPIO registers 21 and 22: 8 bits for 8 comparators, 16 bits for 16 comparators, and 32 bits for 32 comparators.

[0029] The I / O port 30 includes a plurality of first GPIO ports 31 connected to the first GPIO register 21, and a plurality of second GPIO ports 32 connected to the second GPIO register 22.

[0030] The number of the first and second GPIO ports 31 and 32 is the same as the number of bits in the first and second GPIO registers 21 and 22. The first and second GPIO ports 31 and 32 are used to read the analog signals converted from the registers and determine the voltage level based on the analog signals (1 for high level, 0 for low level). Simultaneously, they output a high or low voltage level to the comparator 40, thereby receiving the data to be compared, converting the data into a high or low voltage level, and sending it to the comparator 40 for comparison.

[0031] The comparator 40 has two input terminals connected to the first and second GPIO ports 31 and 32 respectively, enabling it to receive high or low voltage levels for comparison. When the voltages at the two input terminals of the comparator 40 are the same, it indicates that the two data to be compared are identical, and the comparator 40 outputs a high level. When the voltages at the two input terminals of the comparator 40 are different, it indicates that the two data to be compared are different, and the comparator 40 outputs a low level. This allows for byte-by-byte comparison, and multiple comparators 40 can perform the comparison simultaneously, resulting in faster speed and higher efficiency. The comparator 40 is also connected to a diode 41, which prevents the signal output of the comparator 40 from backflowing and affecting other comparators, thus ensuring the correctness of the verification.

[0032] The interrupt port 50 is configured to interrupt on the falling edge. Therefore, when the two input terminals of the comparator 40 have different data and voltages, resulting in a low output level, a falling edge will occur, causing the interrupt port 50 to be interrupted. This verifies whether the data is the same, and also determines the location where the data is different and counts the number of interrupts for subsequent work.

[0033] This invention provides an efficient data verification method, comprising the following steps:

[0034] Step S1: Provide two storage modules 10, two I / O registers 20 connected to the storage modules 10 respectively, multiple I / O ports 30 connected to the I / O registers 20, multiple comparators 40 connected to the I / O ports 30, and an interrupt port 50 connected to the comparators 40. Create two RAM areas in the microcontroller's RAM region, including RAM1 for storing the first data to be compared and RAM2 for storing the second data to be compared. Set parameters i1, i2, and k in the microcontroller. i1 is used to count the number of bytes compared, i2 is used to store the location where different data occurs, and k is used to count the frequency of different comparisons.

[0035] Step S2: The io register 20 includes a first GPIO register 21 and a second GPIO register 22. The number of bytes compared in a single operation is determined based on the number of bits in the first GPIO register 21 and the second GPIO register 22.

[0036] Step S3: The first GPIO register 21 reads n bytes of RAM1 data, and then sends it to the I / O port 30 after digital-to-analog conversion. The second GPIO register 22 reads n bytes of RAM2 data, and then sends it to the I / O port 30 after digital-to-analog conversion.

[0037] Step S4: The I / O port 30 determines the high or low potential based on the analog signal, where 1 represents a high level and 0 represents a low level, and then sends the high or low potential to the comparator 40.

[0038] Step S5: If the voltages received at the two input terminals of the comparator 40 are the same, it means the data is the same, and the comparator 40 outputs a high level. If the voltages at the two input terminals of the comparator 40 are different, it means the data is different, and the comparator 40 outputs a low level.

[0039] Step S6: The interrupt port 50 is a falling edge interrupt, so as long as the data is different, an interrupt will occur when the interrupt port 50 receives a low level. The interrupt port 50 determines whether an interrupt has occurred. If an interrupt has occurred, proceed to step S7; otherwise, proceed to step S8. For each byte transmitted in the first GPIO register 21 and the second GPIO register 22, the amount of data compared, i1, is recorded.

[0040] Step S7: Statistically compare the different positions of the data. Based on the number of bytes being transmitted in the first GPIO register 21 and the second GPIO register 22, determine the different positions of the data and record them in i2. At the same time, count the number of interrupts K, and increment K by 1 for each interrupt.

[0041] Step S8: Determine if i1 is equal to the total data volume. If i1 is less than the total data volume, return to step S3 and continue comparing the remaining data. If i1 is equal to the total data volume, the verification ends.

[0042] Compared with existing technologies, the efficient data verification system provided by this invention uses the first and second GPIO registers 21 and 22 to convert n bytes of data from the first and second data to be compared into analog data and send them to the first and second GPIO ports 31 and 32 respectively. The analog signals from the first and second GPIO ports 31 and 32 determine the voltage level (1 for high level, 0 for low level) and are sent to the comparator 40. When the voltages at the two input terminals of the comparator 40 are different, it indicates that the two data to be compared are different, and the comparator 40 outputs a low level, causing an interrupt to occur at the interrupt port 50. This verifies whether the data are the same, and also determines the location of the data difference and counts the number of interrupts for subsequent work. This invention uses a byte-by-byte comparison method for verification, which eliminates the process of temporarily storing the comparison data and avoids the CRC calculation process, resulting in faster speed and higher efficiency.

[0043] The above are merely preferred embodiments of the present invention and are not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions or improvements within the spirit of the present invention are covered within the scope of the claims of the present invention.

Claims

1. An efficient data verification method, comprising the following steps: Step S1: Provide two storage modules, two I / O registers connected to the storage modules respectively, multiple I / O ports connected to the I / O registers, multiple comparators connected to the I / O ports, and an interrupt port connected to the comparators. In the RAM area of ​​the microcontroller, two RAM areas are opened, including RAM1 for storing the first data to be compared and RAM2 for storing the second data to be compared. In the microcontroller, set parameters i1, i2, and K. i1 is used to count the number of bytes compared, i2 is used to store the location where the different data occurs, and K is used to count the frequency of different comparisons. Step S2: The I / O register includes a first GPIO register and a second GPIO register. The number of bytes compared in a single operation is determined based on the bit width of the first GPIO register and the second GPIO register. Step S3: The first GPIO register reads n bytes of RAM1 data, and then sends it to the I / O port after digital-to-analog conversion; the second GPIO register reads n bytes of RAM2 data, and then sends it to the I / O port after digital-to-analog conversion. Step S4: The I / O port determines the potential level based on the analog signal, and then sends the high or low potential to the comparator; Step S5: If the voltages received at the two input terminals of the comparator are the same, it means that the data is the same, and the comparator outputs a high level. If the voltages at the two input terminals of the comparator are different, it means that the data is different, and the comparator outputs a low level. Step S6: The interrupt port is a falling edge interrupt. When the interrupt port receives a low level, a falling edge will occur and an interrupt will occur. The interrupt port determines whether an interrupt has occurred. If an interrupt has occurred, proceed to step S7. If no interrupt has occurred, proceed to step S8. Record the amount of data i1 that has been compared for each byte transmitted in the first GPIO register and the second GPIO register. Step S7: Statistically compare the different positions of the data and record them in i2; Step S8: Determine if i1 is equal to the total amount of data. If i1 is less than the total amount of data, return to step S3 and continue to compare the remaining data. When i2 is equal to the total amount of data, the verification ends.

2. The efficient data verification method as described in claim 1, characterized in that: In step S7 above, based on the number of bytes being transmitted in the first GPIO register and the second GPIO register, the different locations where data occurs are determined and recorded in i2. At the same time, the number of interrupts K is counted, and K is incremented by 1 for each interrupt.

3. The efficient data verification method as described in claim 1, characterized in that: In step S4 above, the I / O port determines the voltage level based on the analog signal, with 1 representing a high level and 0 representing a low level.

4. A high-efficiency data verification system for implementing the high-efficiency data verification method as described in any one of claims 1 to 3, characterized in that: The high-efficiency data verification system includes two storage modules, two I / O registers connected to the storage modules respectively, multiple I / O ports connected to the I / O registers, multiple comparators connected to the I / O ports, and an interrupt port connected to the comparators. The two storage modules respectively store a first data to be compared and a second data to be compared. The I / O registers include a first GPIO register and a second GPIO register. The first and second GPIO registers are used to control the output and input of the I / O ports and realize digital-to-analog conversion. The I / O ports include multiple first GPIO ports connected to the first GPIO registers and multiple second GPIO ports connected to the second GPIO registers. The first and second GPIO ports read the analog quantity converted by the I / O registers and determine the high or low potential based on the analog quantity. At the same time, they output a high or low potential to the comparators. The comparators have two input terminals connected to the first and second GPIO ports respectively, and can receive high or low potentials and compare them. The interrupt port determines whether the data is the same based on the output of the comparators.

5. The high-efficiency data verification system as described in claim 4, characterized in that: The first and second GPIO registers are 8-bit, 16-bit, and 32-bit. 8-bit corresponds to 1 byte of data for simultaneous digital-to-analog conversion, 16-bit corresponds to 2 bytes of data, and 32-bit corresponds to 4 bytes of data. The number of bits in the first and second GPIO registers matches the number of comparators: 8 bits for 8 comparators, 16 bits for 16 comparators, and 32 bits for 32 comparators.

6. The high-efficiency data verification system as described in claim 5, characterized in that: The number of the first and second GPIO ports is the same as the number of bits in the first and second GPIO registers.

7. The high-efficiency data verification system as described in claim 4, characterized in that: When the voltages at the two input terminals of the comparator are the same, it means that the two data to be compared are the same, and the comparator outputs a high level. When the voltages at the two input terminals of the comparator are different, it means that the two data to be compared are different, and the comparator outputs a low level.

8. The high-efficiency data verification system as described in claim 4, characterized in that: The comparator is also connected to a diode, which prevents the signal output by the comparator from flowing back.

9. The high-efficiency data verification system as described in claim 4, characterized in that: The interrupt port is set to fall-edge interrupt, so a fall-edge will occur when the comparator outputs a low level.

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