Circuit simulation method and apparatus

Abstract

The present disclosure provides a circuit simulation method and device, relates to the technical field of semiconductors, and is applied to a to-be-simulated circuit. The to-be-simulated circuit comprises a first power bus, a second power bus, a first load connected to the first power bus, and a second load connected to the second power bus. The first power bus is connected to the second power bus through a switch, and the second power bus is connected to an external power supply. The method comprises the following steps: obtaining a netlist corresponding to the to-be-simulated circuit and an SPF file according to a design database of the to-be-simulated circuit. The SPF file comprises parameters corresponding to the first power bus, parameters corresponding to the second power bus, device parameters of the first load, device parameters of the second load, and device parameters of the switch. The to-be-simulated circuit is simulated based on the netlist and the standard parasitic parameter format file. According to the simulation result, it is determined whether the performance of the first power bus and the second power bus meets the performance requirement of the to-be-simulated circuit.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a circuit simulation method and apparatus. Background Technology

[0002] The design process for integrated circuits typically includes circuit design, pre-simulation, layout design, and post-simulation. Post-simulation refers to performing simulations after the layout design is completed, taking into account the circuit's parasitic parameters and the interconnections between various circuit units. The simulation results are then used to analyze the circuit to ensure it meets design requirements.

[0003] Currently, as memory chips become increasingly faster and smaller in size, accurately evaluating the performance of the power bus to ensure it meets the performance requirements of the memory chips is a pressing technical problem that needs to be solved. Summary of the Invention

[0004] This disclosure provides a circuit simulation method and apparatus that can accurately evaluate the performance of a power bus, enabling the power bus to meet the performance requirements of the circuit to be simulated.

[0005] In a first aspect, embodiments of this disclosure provide a circuit simulation method applied to a circuit to be simulated. The circuit to be simulated includes a first power bus, a second power bus, at least one first load connected to the first power bus, and at least one second load connected to the second power bus. The first power bus is connected to the second power bus via a switch, and the second power bus is connected to an external power source. The method includes:

[0006] Based on the design database of the circuit to be simulated, obtain the netlist and standard parasitic parameter format file corresponding to the circuit to be simulated. The standard parasitic parameter format file includes the parameters corresponding to the first power bus, the parameters corresponding to the second power bus, the device parameters of all the first loads, the device parameters of all the second loads, and the device parameters of the switch.

[0007] The circuit to be simulated is simulated based on the netlist and the standard parasitic parameter format file.

[0008] Based on the simulation results of the circuit to be simulated, determine whether the performance of the first power bus and the second power bus meets the performance requirements of the circuit to be simulated.

[0009] In some feasible implementations, the parameters corresponding to the first power bus include the self-resistance and / or parasitic capacitance of the first power bus; the parameters corresponding to the second power bus include the self-resistance and / or parasitic capacitance of the second power bus.

[0010] In some feasible implementations, the first power bus includes a first sub-power bus, the second power bus includes a second sub-power bus, the external power supply includes a first power supply, and the switch includes at least one first transistor.

[0011] Each of the first transistors has its first terminal connected to the second sub-power bus, its second terminal connected to the first sub-power bus, and its gate receiving the first drive signal in the circuit to be simulated.

[0012] The device parameters of the switch include all the feature size parameters of the first transistor.

[0013] In some feasible implementations, the first power bus further includes a third sub-power bus, the second power bus further includes a fourth sub-power bus, the external power supply further includes a second power supply, and the switch further includes at least one second transistor;

[0014] The first terminal of each second transistor is connected to the fourth sub-power bus, the second terminal is connected to the third sub-power bus, and the gate receives the second drive signal in the circuit to be simulated.

[0015] The device parameters of the switch also include the characteristic dimension parameters of all the second transistors.

[0016] In some feasible implementations, the circuit to be simulated also includes at least one pad connected to the second power bus;

[0017] The standard parasitic parameter format file also includes input voltage information at all the connections between the pads and the second power bus.

[0018] In some feasible implementations, the pads include a first pad and a second pad, the first pad being connected to the second sub-power bus and the second pad being connected to the fourth sub-power bus;

[0019] The standard parasitic parameter format file also includes first input voltage information at the connection between the first pad and the second sub-power bus, and second input voltage information at the connection between the second pad and the fourth sub-power bus.

[0020] In some feasible implementations, the circuit to be simulated further includes a first capacitor connected between the second sub-power bus and the fourth sub-power bus, and / or a second capacitor connected between the first sub-power bus and the third sub-power bus;

[0021] The standard parasitic parameter format file also includes parameter information for the first capacitor and / or the second capacitor.

[0022] In some feasible implementations, the device parameters of the first load include the resistance and capacitance of the devices in the first load; the device parameters of the second load include the resistance and capacitance of the devices in the second load.

[0023] In some feasible implementations, determining whether the performance of the first power bus and the second power bus meets the performance requirements of the circuit to be simulated based on the simulation results of the circuit to be simulated includes:

[0024] Based on the simulation results of the circuit to be simulated, determine the first voltage value at the node where the first load and the first power bus are connected, and the second voltage value at the node where the second load and the second power bus are connected.

[0025] Based on the first voltage value and the second voltage value, determine whether the performance of the first power bus and the second power bus meets the performance requirements of the circuit to be simulated.

[0026] In some feasible implementations, determining whether the performance of the first power bus and the second power bus meets the performance requirements of the circuit to be simulated based on the first voltage value and the second voltage value includes:

[0027] Based on the first voltage value and the second voltage value, determine whether the width of the first power bus and the second power bus in the layout meets the performance requirements of the circuit to be simulated.

[0028] In some feasible implementations, determining whether the performance of the first power bus and the second power bus meets the performance requirements of the circuit to be simulated based on the first voltage value and the second voltage value includes:

[0029] Based on the first voltage value and the second voltage value, determine whether the number of switches connected on the first power bus meets the performance requirements of the circuit to be simulated.

[0030] In some feasible implementations, determining whether the performance of the first power bus and the second power bus meets the performance requirements of the circuit to be simulated based on the first voltage value and the second voltage value includes:

[0031] Based on the first voltage value and the second voltage value, determine whether the number of capacitors connected on the first power bus and the second power bus meets the performance requirements of the circuit to be simulated.

[0032] In some feasible implementations, determining whether the performance of the first power bus and the second power bus meets the performance requirements of the circuit to be simulated based on the first voltage value and the second voltage value includes:

[0033] Based on the impact of the changes in the first voltage value and the second voltage value on the signal timing of the circuit to be simulated, a first voltage threshold and a second voltage threshold are determined at the node where the first load and the first power bus are connected. Based on the first voltage value, the second voltage value, the first voltage threshold, and the second voltage threshold, it is determined whether the performance of the first power bus and the second power bus meets the performance requirements of the circuit to be simulated.

[0034] In some feasible implementations, it also includes:

[0035] If the performance of the first power bus does not meet the performance requirements of the circuit to be simulated, then increase the width of the first power bus in the layout.

[0036] If the performance of the second power bus does not meet the performance requirements of the circuit to be simulated, then the width of the second power bus in the layout is increased.

[0037] In some feasible implementations, it also includes:

[0038] If the performance of the first power bus does not meet the performance requirements of the circuit to be simulated, then increase the number of switches connected to the first power bus.

[0039] In some feasible implementations, it also includes:

[0040] If the performance of the first power bus does not meet the performance requirements of the circuit to be simulated, then increase the number of capacitors connected to the first power bus, or adjust the capacitance value of the capacitors connected to the first power bus, or adjust the distribution position of the capacitors connected to the first power bus.

[0041] If the performance of the second power bus does not meet the performance requirements of the circuit to be simulated, then increase the number of capacitors connected to the second power bus, or adjust the capacitance value of the capacitors connected to the second power bus, or adjust the distribution position of the capacitors connected to the second power bus.

[0042] Secondly, embodiments of this disclosure provide a circuit simulation apparatus applied to a circuit to be simulated. The circuit to be simulated includes a first power bus, a second power bus, at least one first load connected to the first power bus, and at least one second load connected to the second power bus. The first power bus is connected to the second power bus via a switch, and the second power bus is connected to an external power source. The apparatus includes:

[0043] The acquisition module is used to acquire the netlist and standard parasitic parameter format file corresponding to the circuit to be simulated based on the design database of the circuit to be simulated. The standard parasitic parameter format file includes parameters corresponding to the first power bus, parameters corresponding to the second power bus, device parameters of all first loads, device parameters of all second loads, and device parameters of the switch.

[0044] The simulation module is used to simulate the circuit to be simulated based on the netlist and the standard parasitic parameter format file.

[0045] The processing module is used to determine, based on the simulation results of the circuit to be simulated, whether the performance of the first power bus and the second power bus meets the performance requirements of the circuit to be simulated.

[0046] Thirdly, embodiments of this disclosure provide an electronic device, including: at least one processor and a memory;

[0047] The memory stores computer-executed instructions;

[0048] The at least one processor executes computer execution instructions stored in the memory, causing the at least one processor to perform the circuit simulation method as provided in the first aspect.

[0049] Fourthly, embodiments of this disclosure provide a computer-readable storage medium storing computer-executable instructions, which, when executed by a computer, implement the circuit simulation method provided in the first aspect.

[0050] The circuit simulation method and apparatus provided in this disclosure, during post-simulation, obtain the netlist and standard parasitic parameter format file corresponding to the circuit to be simulated from the design database of the circuit to be simulated. The standard parasitic parameter format file includes parameters corresponding to each power bus, device parameters of each load, and device parameters of each switch. Based on the above netlist and standard parasitic parameter format file, the circuit to be simulated is simulated, which makes the simulation process closer to the actual working condition of the circuit to be simulated. Furthermore, based on the simulation results, the performance of the power bus can be accurately evaluated, so that the power bus can meet the performance requirements of the circuit to be simulated. Attached Figure Description

[0051] Figure 1 This is a schematic diagram of the structure of a circuit to be simulated provided in an embodiment of this disclosure. Figure 1 ;

[0052] Figure 2 This is a flowchart illustrating the steps of a circuit simulation method provided in an embodiment of this disclosure;

[0053] Figure 3 This is a schematic diagram of the structure of a circuit to be simulated provided in an embodiment of this disclosure. Figure 2 ;

[0054] Figure 4 and Figure 5 This is a schematic diagram showing the pin positions of the two power buses provided in the embodiments of this disclosure;

[0055] Figure 6 This is a schematic flowchart of another step of a circuit simulation method provided in this embodiment of the disclosure;

[0056] Figure 7 This is a schematic diagram of the program modules of a circuit simulation device provided in an embodiment of the present disclosure;

[0057] Figure 8 This is a schematic diagram of the hardware structure of an electronic device provided in an embodiment of this disclosure. Detailed Implementation

[0058] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure. Furthermore, although the disclosure in this disclosure is based on one or several exemplary examples, it should be understood that each aspect of these disclosures can also constitute a complete implementation method on its own.

[0059] It should be noted that the brief descriptions of terms in this disclosure are only for the convenience of understanding the embodiments described below, and are not intended to limit the embodiments of this disclosure. Unless otherwise stated, these terms should be understood in their ordinary and common meaning.

[0060] The terms "first," "second," etc., used in this disclosure, the specification, claims, and the accompanying drawings are used to distinguish similar or related objects or entities and do not necessarily imply a specific order or sequence, unless otherwise specified. It should be understood that such terms can be used interchangeably where appropriate, for example, in situations where implementation can proceed in an order other than those given in the illustrations or description of embodiments of this disclosure.

[0061] Furthermore, the terms “comprising” and “having”, and any variations thereof, are intended to cover but not exclude inclusion, for example, a product or device that includes a series of components is not necessarily limited to those that are clearly listed, but may include other components that are not clearly listed or that are inherent to such product or device.

[0062] When an element is referred to as being “connected” to another element in this disclosure, it may be directly connected to the other element, or there may be an intermediate element through which it is connected to the other element.

[0063] The term "module" as used in the embodiments of this disclosure refers to any known or subsequently developed hardware, software, firmware, artificial intelligence, fuzzy logic, or combination of hardware and / or software code capable of performing the functions associated with that element.

[0064] The embodiments disclosed herein can be applied to the field of semiconductor technology, for example, to the design process of integrated circuits.

[0065] In some implementations, the design flow of integrated circuits typically includes circuit design, pre-simulation, layout design, and post-simulation. Circuit design involves designing the circuit based on its function; pre-simulation simulates the circuit's function, including parameters such as power consumption, current, voltage, temperature, and input / output characteristics; layout design generates the circuit layout based on the designed circuit; and post-simulation, after the layout design is completed, extracts parasitic parameters from the circuit and adds these parameters to the circuit for simulation.

[0066] Currently, post-simulation using the Standard Parasitic Format (SPF) file does not include parasitic parameters of the power bus. All power supply output voltages use ideal voltage values, meaning that the power supply is assumed to have no internal resistance or parasitic impedance. As a result, the power supply terminal of the simulation device cannot obtain the voltage drop (IRdrop) of the power bus, and therefore cannot accurately evaluate the performance of the power bus.

[0067] The parasitic parameters mentioned above can include parasitic capacitance, parasitic resistance, and parasitic inductance. Parasitic capacitance itself is not a capacitor; the term "parasitic" means that no capacitor was originally designed into that location, but due to the presence of many adjacent metal conductors at different potentials, a certain capacitance inevitably exists between them. Since these conductors were not intentionally created to generate such capacitance, these accidentally appearing capacitors are called "parasitic capacitances." Such capacitances have no independent value; they are "parasitic" on the metal conductors that perform other functions. According to the principle of capacitance, a capacitor consists of two plates and an insulating medium. Therefore, parasitic capacitance is unavoidable. For example, in a circuit with many wires, parasitic capacitance will form between the wires. Parasitic capacitance affects the circuit's ability to operate at high speeds, sometimes causing circuit instability, parasitic oscillations, or even unwanted AC signal short circuits.

[0068] Parasitic resistance is an excess resistance generated in integrated circuit design. Moreover, parasitic resistance is cumulative. As the integration density increases, the parasitic resistance will increase, which will lead to a decrease in the performance of integrated circuits.

[0069] Parasitic inductance is inductance that is generated in wires or other components. Generally speaking, parasitic inductance will exist wherever there are wires. The magnitude of parasitic inductance not only affects the transient voltage and current of integrated circuits, but also affects the losses of integrated circuits.

[0070] In this context, an SPF file refers to a file with the ".spf" extension used during simulation. An SPF file can contain information such as interconnect resistances, parasitic capacitances, and interconnect logic relationships between circuit units.

[0071] IR drop refers to the phenomenon of voltage drop and rise on the power and ground networks in integrated circuits. With the continuous evolution of semiconductor technology, the width of metal interconnects is becoming narrower, and the resistance is increasing (while the supply voltage is decreasing), making the IR drop effect more and more pronounced. IR drop is mainly divided into two types: static IR drop and dynamic IR drop. Static IR drop is mainly caused by voltage division in the metal interconnects of the power network, due to the inherent resistance of the interconnects themselves. Current flowing through the internal power interconnects generates a voltage drop, so static IR drop is primarily related to the structure and wiring details of the power network. Dynamic IR drop is caused by voltage drop due to current fluctuations during circuit switching. This phenomenon occurs at the clock edge. The clock edge transition not only triggers a large number of transistor switching but also causes transitions in combinational logic circuits, often generating a large current across the entire chip in a short period. This instantaneous large current causes the IR drop phenomenon. Furthermore, the more transistors that switch, the easier it is to trigger dynamic IR drop.

[0072] In the existing technology, taking Dynamic Random Access Memory (DRAM) as an example, as the clock frequency of DRAM becomes higher and the area becomes smaller, how to accurately evaluate the performance of the power bus so that the power bus can meet the performance requirements of the memory chip is a technical problem that urgently needs to be solved.

[0073] To address the aforementioned technical problems, this disclosure provides a circuit simulation method and apparatus. During post-simulation, all power bus parameters, device parameters of switches connected to the power bus, and device parameters of the load are included. This allows the post-simulation process to more closely approximate the actual operating conditions of the circuit to be simulated, thereby facilitating accurate evaluation of the power bus performance and ensuring that the power bus meets the performance requirements of the memory chip. Detailed procedures can be found in the following embodiments.

[0074] The circuit simulation method provided in this embodiment is applied to the circuit to be simulated, which can be understood as the aforementioned memory chip, or as a circuit module within the aforementioned memory chip.

[0075] In some embodiments, the circuit to be simulated may include various components, wires, power buses, etc. The power bus employs power bus technology, with each component suspended on the power bus; this is also known as a suspended bus.

[0076] Reference Figure 1 , Figure 1 This is a schematic diagram of the structure of a circuit to be simulated provided in an embodiment of this disclosure. Figure 1 .

[0077] In some embodiments, the circuit to be simulated includes a first power bus 100, a second power bus 200, at least one first load 101 connected to the first power bus 100, and at least one second load 201 connected to the second power bus 200. The first power bus 100 is connected to the second power bus 200 via a switch 102, and the second power bus 200 is connected to an external power supply V1.

[0078] The first power bus 100 is a power bus controlled by switch 102. For example, the first power bus 100 is turned off when the circuit to be simulated is in sleep mode (otherwise the leakage current of the power bus will be large), and the first power bus 100 is turned on when the circuit to be simulated is working normally. This can save power when the circuit to be simulated is in sleep mode and ensure the circuit running speed when it is working normally.

[0079] In some embodiments, capacitors may not be connected to the first power bus 100 and the second power bus 200, thereby enabling the first power bus 100 and the second power bus 200 to power on quickly enough after a power outage; alternatively, capacitors may be connected to the first power bus 100 and / or the second power bus 200, thereby reducing the IR drop of the first power bus 100 and / or the second power bus 200 and improving their performance.

[0080] Reference Figure 2 , Figure 2 This is a schematic flowchart illustrating the steps of a circuit simulation method provided in an embodiment of this disclosure. In some embodiments of this disclosure, the above-described circuit simulation method can be applied to... Figure 1 The circuit to be simulated shown includes:

[0081] S201. Based on the design database of the circuit to be simulated, obtain the netlist and SPF file corresponding to the circuit to be simulated. The SPF file includes the parameters corresponding to the first power bus, the parameters corresponding to the second power bus, the device parameters of all first loads, the device parameters of all second loads, and the device parameters of the switches.

[0082] In circuit design, netlists are typically used to describe the interconnections between circuit components. Generally, they are text files that follow a certain tagging syntax.

[0083] Optionally, the netlist may include circuit description statements of the circuit to be simulated, such as the circuit connection method, the attributes, parameters, and identification information of the components, devices, power nodes, etc. that make up the circuit.

[0084] In some embodiments of this disclosure, the netlist may also include information that needs to be output during simulation (i.e., which nodes in the circuit to be simulated should be output as output terminals to output simulation results), as well as information about the circuit to be simulated that needs to be input during simulation.

[0085] In some embodiments of this disclosure, the parameters corresponding to the first power bus include the self-resistance and / or parasitic capacitance of the first power bus; the parameters corresponding to the second power bus include the self-resistance and / or parasitic capacitance of the second power bus.

[0086] The inherent resistance and parasitic capacitance of the first power bus are related to its width and length. In some embodiments, the parameters corresponding to the first power bus may be its width, length, etc., and the simulation equipment determines the inherent resistance and / or parasitic capacitance of the first power bus based on these parameters during simulation.

[0087] Similarly, the self-resistance and parasitic capacitance corresponding to the second power bus are related to the width and length of the second power bus. In some embodiments, the parameters corresponding to the second power bus can be the width, length, etc. of the second power bus, and the simulation equipment determines the self-resistance and / or parasitic capacitance of the second power bus based on these parameters during the simulation process.

[0088] In some implementations, the SPF file includes parameters of each complete power bus in the circuit to be simulated. That is, the power buses in the circuit to be simulated are not segmented, and the self-resistance and / or parasitic capacitance of each power bus are the self-resistance and / or parasitic capacitance of each complete power bus. This ensures that the parameters corresponding to each power bus are accurate.

[0089] In some embodiments of this disclosure, the device parameters of the switch may refer to the feature size information of the switch, which may be the smallest dimension in a semiconductor device. For example, in CMOS technology, the feature size typically represents the width of the "gate," that is, the channel length of a MOS device.

[0090] Similarly, the device parameters of the above load can also refer to the characteristic size information of each device in the above load.

[0091] S202. Based on the above netlist and SPF file, simulate the circuit to be simulated.

[0092] In some implementations, after generating the circuit layout based on the circuit to be simulated, post-simulation is performed based on the acquired netlist and SPF file to obtain the simulation results of the circuit to be simulated.

[0093] S203. Based on the simulation results of the circuit to be simulated, determine whether the performance of the first power bus and the second power bus meets the performance requirements of the circuit to be simulated.

[0094] The number of first loads and second loads in the circuit to be simulated is unlimited. In some embodiments, it is assumed that the circuit to be simulated includes multiple first loads and multiple second loads. The voltage value at the node where each first load and the first power bus are connected can be determined based on the simulation results of the circuit to be simulated. Then, based on the voltage value and the output voltage of the external power supply V1, the IR drop at the node where each first load and the first power bus are connected can be calculated. Based on the calculated IR drop, it can be determined whether the performance of the first power bus meets the performance requirements of the circuit to be simulated.

[0095] Similarly, the voltage value at each node connecting the second load and the second power bus in the circuit to be simulated can be determined based on the simulation results of the circuit to be simulated. Then, based on the voltage value and the output voltage of the external power supply V1, the IR drop at each node connecting the second load and the second power bus can be calculated. Based on the calculated IR drop, it can be determined whether the performance of the second power bus meets the performance requirements of the circuit to be simulated.

[0096] In some embodiments of this disclosure, the IR drop described above may be a dynamic IR drop.

[0097] Understandably, a decrease in the power bus voltage slows down the switching speed of transistors in the circuit, leading to a degraded circuit performance. Therefore, for high-performance circuit designs, IR drop must be kept within a very small range. If the global IR drop is too high, logic gates will malfunction, causing the circuit to fail completely, even if logic simulation shows the design is correct. Local IR drop is more sensitive and only occurs under specific conditions, such as when all bus data is synchronously toggling; therefore, the circuit will intermittently exhibit some functional failures.

[0098] In some implementations, taking the first power bus as an example, if the calculated IR drop is greater than a preset threshold, it can be determined that the performance of the first power bus cannot meet the performance requirements of the circuit to be simulated; if the calculated IR drop is less than or equal to the preset threshold, it can be determined that the performance of the first power bus can meet the performance requirements of the circuit to be simulated.

[0099] The circuit simulation method provided in this disclosure, during post-simulation, obtains the netlist and SPF file corresponding to the circuit to be simulated from the design database of the circuit to be simulated. The SPF file includes parameters corresponding to each power bus, device parameters of the switches connected on each power bus, and device parameters of the load. Based on the above netlist and SPF file, the circuit to be simulated is simulated, which makes the simulation process closer to the actual working condition of the circuit to be simulated. Furthermore, based on the simulation results, the performance of the power bus can be accurately evaluated, so that the power bus can meet the performance requirements of the circuit to be simulated.

[0100] Based on the description in the above embodiments, in some embodiments of this disclosure, the first power bus includes a first sub-power bus, the second power bus includes a second sub-power bus, the external power supply includes a first power supply, and the switch includes at least one first transistor. Each first transistor has its first terminal connected to the second sub-power bus, its second terminal connected to the first sub-power bus, and its gate receiving a first drive signal from the circuit to be simulated.

[0101] The device parameters of the aforementioned switch include the feature size parameters of all the first transistors.

[0102] Optionally, in some embodiments of this disclosure, the first power bus further includes a third sub-power bus, the second power bus further includes a fourth sub-power bus, the external power supply further includes a second power supply, and the switch further includes at least one second transistor. Each second transistor has its first terminal connected to the fourth sub-power bus, its second terminal connected to the third sub-power bus, and its gate receiving a second drive signal from the circuit to be simulated.

[0103] The device parameters of the aforementioned switch also include the characteristic dimension parameters of all the second transistors.

[0104] In some embodiments of this disclosure, the characteristic size parameters of the first transistor and the second transistor may be the gate width W of the first transistor and the second transistor. The larger the W of the transistor, the larger the parasitic capacitance.

[0105] For example, refer to Figure 3 , Figure 3 This is a schematic diagram of the structure of a circuit to be simulated provided in an embodiment of this disclosure. Figure 2 .

[0106] In some embodiments of this disclosure, the first power bus in the circuit to be simulated includes a first sub-power bus VCCZ and a third sub-power bus VSSZ; the second power bus includes a second sub-power bus VCCG and a fourth sub-power bus VSSG; the external power supply includes a first power supply VCC and a second power supply VSS; and the switch includes at least one first transistor M1 and at least one second transistor M2.

[0107] In this circuit, the first terminal of each first transistor M1 is connected to the second sub-power bus VCCG, the second terminal is connected to the first sub-power bus VCCZ, and the gate receives the first drive signal EnN from the circuit to be simulated; the first terminal of each second transistor M2 is connected to the fourth sub-power bus VSSG, the second terminal is connected to the third sub-power bus VSSZ, and the gate receives the second drive signal En from the circuit to be simulated.

[0108] Optionally, the channel type of the first transistor M1 is different from that of the second transistor M2. For example, in some embodiments, the first transistor M1 can be a PMOS and the second transistor M2 can be an NMOS.

[0109] In some implementations, when the circuit under test is in sleep mode, the first drive signal EnN and the second drive signal En are used to control the first transistor M1 and the second transistor M2 to be turned off, respectively, thereby shutting down the first sub-power bus VCCZ and the third sub-power bus VSSZ. When the circuit under test is operating normally, the first drive signal EnN and the second drive signal En are used to control the first transistor M1 and the second transistor M2 to be turned on, thereby turning on the first sub-power bus VCCZ and the third sub-power bus VSSZ.

[0110] In some embodiments of this disclosure, the circuit to be simulated further includes at least one load 101 connected between the first sub-power bus VCCZ and the third sub-power bus VSSZ, and at least one load 201 connected between the second sub-power bus VCCG and the fourth sub-power bus VSSG.

[0111] Optionally, loads 101 and 201 may include devices such as inverters and NAND gates. The SPF file includes device parameters for all loads 101 and 201. Optionally, the device parameters for load 101 include the resistance and capacitance of each device in load 101, and the device parameters for load 201 include the resistance and capacitance of each device in load 201.

[0112] Optionally, the SPF file may also include the characteristic size information of the remaining effective devices in the circuit to be simulated, excluding the first transistor M1 and the second transistor M2, as well as the self-resistance and / or parasitic capacitance of the remaining wires in the circuit to be simulated, excluding the power bus.

[0113] In some embodiments of this disclosure, to improve the performance of the power bus, the circuit to be simulated may further include a first capacitor Cap1 connected between the second sub-power bus VCCG and the fourth sub-power bus VSSG, and / or a second capacitor Cap2 connected between the first sub-power bus VCCZ and the third sub-power bus VSSZ. The SPF file also includes parameter information for the first capacitor Cap1 and / or the second capacitor Cap2.

[0114] In some embodiments of this disclosure, the circuit to be simulated further includes at least one pad connected to the second power bus; the SPF file also includes input voltage information at the connection point between each pad and the second power bus.

[0115] PADs are typically composed of the top metal layer of an integrated circuit, with openings of a specific size. Different manufacturing companies have their own specific opening specifications. The PAD is generally located at the edge of the entire chip.

[0116] Optionally, the aforementioned pads include a first pad VDD PAD and a second pad VSS PAD. The first pad VDD PAD is connected to the second sub-power bus VCCG, and the second pad VSS PAD is connected to the fourth sub-power bus VSSG. The aforementioned SPF file also includes first input voltage information at the connection point between the first pad VDD PAD and the second sub-power bus VCCG, and second input voltage information at the connection point between the second pad VSS PAD and the fourth sub-power bus VSSG.

[0117] It is understandable that during the simulation of the circuit under test, the voltage in the second power bus is provided by the pins of the second power bus. Therefore, the input voltage of the second power bus extracted from the SPF file is also extracted from the pins of the second power bus. However, when the circuit under test is actually working, the voltage in the second power bus is provided by the pads connected to the second power bus.

[0118] To better understand the embodiments of this disclosure, please refer to... Figure 4 and Figure 5 , Figure 4 and Figure 5 This is a schematic diagram showing the pin locations of the two power buses provided in the embodiments of this disclosure.

[0119] exist Figure 4In the simulation, one location on the second sub-power bus VCCG was selected as the pin of the second sub-power bus VCCG, and one location on the fourth sub-power bus VSSG was selected as the pin of the fourth sub-power bus VSSG. During the simulation, the input voltages of VSSG and VCCG extracted from the SPF file are the voltages of the VCCG pin and the VSSG pin, while in actual operation of the circuit under simulation, the power supply to VSSG and VCCG is supplied through VDD PAD and VSS PAD, therefore... Figure 4 The power bus shown cannot guarantee that the circuit under simulation will behave the same as the actual circuit under operation.

[0120] exist Figure 5 In the simulation, the connection point between the second sub-power bus VCCG and the first pad VDD PAD was selected as the pin of the second sub-power bus VCCG, and the connection point between the fourth sub-power bus VSSG and the second pad VSS PAD was selected as the pin of the fourth sub-power bus VSSG. During simulation, the first input voltage information of the second sub-power bus VCCG extracted from the above SPF file is the voltage provided by VDD PAD, and the second input voltage information of the fourth sub-power bus VSSG is the voltage provided by VSS PAD. This ensures that the simulated circuit behaves consistently in simulation and actual operation, making the simulation process closer to the actual working condition of the simulated circuit.

[0121] Reference Figure 6 , Figure 6 This is a schematic flowchart illustrating another step of a circuit simulation method provided in an embodiment of this disclosure. In some embodiments of this disclosure, the circuit simulation method includes:

[0122] S601. Obtain the design database of the circuit to be simulated.

[0123] The structure of the circuit to be simulated can be referred to as follows. Figure 1 or Figure 3 The circuit to be simulated will not be described in detail here.

[0124] In some implementations, the design database described above is a design database based on LVS clean.

[0125] In the integrated circuit design process, the verification work after the layout design is completed includes Design Rule Check (DRC), layout and schematic verification. Figure 1Consistency checks (LVS), etc. DRC's main purpose is to check the physical verification process of all potential open circuits, short circuits, or adverse effects caused by violations of design rules in the layout. It uses graphical operation functions to identify those violations. LVS's main purpose is to verify whether the circuit structure of the layout is consistent with the circuit schematic, including whether the electrical connections of all signals are consistent, whether the device types and sizes are consistent, etc. It compares the netlist of the original circuit schematic with the netlist of the circuit schematic extracted from the layout.

[0126] In some embodiments of this disclosure, the design database can be obtained after the designed layout has passed through DRC and LVS.

[0127] S602. Obtain the netlist corresponding to the circuit to be simulated based on the above design database.

[0128] S603. Obtain the SPF file corresponding to the circuit to be simulated based on the above design database.

[0129] The SPF file includes parameters corresponding to the first power bus, parameters corresponding to the second power bus, device parameters for all first loads, device parameters for all second loads, and device parameters for all switches.

[0130] Optionally, the parameters corresponding to the first power bus include the self-resistance and / or parasitic capacitance of the first power bus; the parameters corresponding to the second power bus include the self-resistance and / or parasitic capacitance of the second power bus.

[0131] In some embodiments, the device parameters of the first load include the resistance and capacitance of the devices in the first load; the device parameters of the second load include the resistance and capacitance of the devices in the second load.

[0132] In some embodiments, the circuit to be simulated further includes a capacitor connected to a first power bus and / or a capacitor connected to a second power bus; the SPF file also includes parameter information of the capacitor.

[0133] S604. Based on the above netlist and SPF file, simulate the circuit to be simulated.

[0134] After generating the circuit layout based on the circuit to be simulated, post-simulation is performed based on the netlist and SPF file mentioned above to obtain the simulation results of the circuit to be simulated.

[0135] S605. Based on the simulation results of the circuit to be simulated, determine whether the performance of the first power bus and the second power bus meets the performance requirements of the circuit to be simulated. If yes, end the process; otherwise, the first power bus and / or the second power bus need to be improved, and return to modify the design database.

[0136] In some embodiments of this disclosure, a first voltage value at the node where the first load and the first power bus are connected, and a second voltage value at the node where the second load and the second power bus are connected, can be determined based on the simulation results of the circuit to be simulated; and based on the first voltage value and the second voltage value, it can be determined whether the performance of the first power bus and the second power bus meets the performance requirements of the circuit to be simulated.

[0137] Optionally, the IR drop at the node connecting the first load and the first power bus can be calculated based on the first voltage value at the node and the voltage value provided by the external power supply; or, the IR drop at the node connecting the first load and the first power bus can be calculated based on the first voltage value at the node connecting the first load and the first power bus, and the second voltage value at the node connecting the second load and the second power bus; or, the IR drop at the node connecting the first load and the first power bus can be calculated based on the first voltage value at the node connecting the first load and the first power bus, and the voltage value at the node connecting the switch and the first power bus. Based on the calculated IR drop, it can be determined whether the performance of the first power bus meets the performance requirements of the circuit to be simulated. For example, when the calculated IR drop is greater than a certain threshold, it can be determined that the performance of the first power bus does not meet the performance requirements of the circuit to be simulated; when the calculated IR drop is less than or equal to the threshold, it can be determined that the performance of the first power bus meets the performance requirements of the circuit to be simulated.

[0138] Similarly, the IR drop at the node connecting the second load and the second power bus can be calculated based on the first voltage value at the node and the voltage value provided by the external power supply. Based on the calculated IR drop, it can be determined whether the performance of the second power bus meets the performance requirements of the circuit to be simulated. For example, if the calculated IR drop is greater than a certain threshold, it can be determined that the performance of the second power bus does not meet the performance requirements of the circuit to be simulated; if the calculated IR drop is less than or equal to the threshold, it can be determined that the performance of the second power bus meets the performance requirements of the circuit to be simulated.

[0139] Optionally, in some embodiments of this disclosure, the width of the first power bus in the layout can be determined based on the IR drop at the node where the first load and the first power bus are connected; and / or the width of the second power bus in the layout can be determined based on the IR drop at the node where the second load and the second power bus are connected.

[0140] It is understandable that the wider the power bus is in the layout, the smaller the IR drop generated by the power bus. Therefore, when the calculated IR drop is greater than a certain threshold, it can be determined that the width of the power bus in the layout does not meet the performance requirements of the circuit to be simulated; when the calculated IR drop is less than or equal to the above threshold, it can be determined that the width of the power bus in the layout meets the performance requirements of the circuit to be simulated.

[0141] Optionally, in some embodiments of this disclosure, the number of switches connected on the first power bus can be determined based on the IR drop at the node where the first load and the first power bus are connected to, to determine whether the number of switches connected on the first power bus meets the performance requirements of the circuit to be simulated.

[0142] It is understandable that the more switches connected to the power bus, the smaller the IR drop generated by the power bus. Therefore, when the calculated IR drop is greater than a certain threshold, it can be determined that the number of switches does not meet the performance requirements of the circuit to be simulated; when the calculated IR drop is less than or equal to the threshold, it can be determined that the number of switches meets the performance requirements of the circuit to be simulated.

[0143] Optionally, in some embodiments of this disclosure, the number of capacitors connected on the first power bus can be determined based on the IR drop at the node where the first load and the first power bus are connected; and / or the number of capacitors connected on the second power bus can be determined based on the IR drop at the node where the second load and the second power bus are connected.

[0144] It is understandable that the more capacitors connected to the power bus, the smaller the IR drop generated by the power bus. Therefore, when the calculated IR drop is greater than a certain threshold, it can be determined that the number of capacitors does not meet the performance requirements of the circuit to be simulated; when the calculated IR drop is less than or equal to the threshold, it can be determined that the number of capacitors meets the performance requirements of the circuit to be simulated.

[0145] Optionally, in some embodiments of this disclosure, a first voltage threshold at the node connecting the first load and the first power bus, and a second voltage threshold at the node connecting the second load and the second power bus, can be determined based on the impact of the changes in the first voltage value and the second voltage value on the signal timing of the circuit to be simulated. Based on the first voltage value, the second voltage value, the first voltage threshold, and the second voltage threshold, it can be determined whether the performance of the first power bus and the second power bus meets the performance requirements of the circuit to be simulated.

[0146] Understandably, the delay of a standard cell in an integrated circuit depends on the actual input voltage of that cell; if the voltage decreases, the delay increases. This increase in standard cell delay can impact chip design performance. If the available voltage for a standard cell falls below a certain level, the cell may stop working entirely, potentially causing the chip design to malfunction. Even when the IR drop is within limits, an increase in cell delay can still affect the chip design's setup and hold timing, sometimes leading to setup and hold timing failures.

[0147] For example, in some implementations, the impact of voltage changes at the node connecting the first load and the first power bus on the signal timing of the circuit to be simulated can be analyzed to determine the voltage threshold at the node connecting the first load and the first power bus. Then, based on the voltage values ​​at the node connecting the first load and the first power bus in the simulation results and the voltage threshold, it can be determined whether the performance of the first power bus meets the performance requirements of the circuit to be simulated. For example, when the voltage value at the node connecting the first load and the first power bus in the simulation results is greater than or equal to the voltage threshold, it is determined that the performance of the first power bus meets the performance requirements of the circuit to be simulated; when the voltage value at the node connecting the first load and the first power bus in the simulation results is less than the voltage threshold, it is determined that the performance of the first power bus does not meet the performance requirements of the circuit to be simulated.

[0148] Similarly, the impact of voltage changes at the node connecting the second load and the second power bus on the signal timing of the circuit to be simulated can be analyzed to determine the voltage threshold at the node. Then, based on the voltage values ​​at the node and the voltage threshold in the simulation results, it can be determined whether the performance of the second power bus meets the performance requirements of the circuit to be simulated. For example, if the voltage value at the node is greater than or equal to the voltage threshold, the performance of the second power bus meets the performance requirements of the circuit to be simulated; if the voltage value is less than the voltage threshold, the performance of the second power bus does not meet the performance requirements of the circuit to be simulated.

[0149] In some implementations, if the performance of the first power bus or the second power bus does not meet the performance requirements of the circuit to be simulated, the circuit to be simulated can be improved, and after the circuit to be simulated is improved, the design database of the circuit to be simulated is updated according to the improvement scheme.

[0150] Optionally, if the performance of the first power bus does not meet the performance requirements of the circuit to be simulated, the ways to improve the circuit to be simulated include, but are not limited to:

[0151] Increase the width of the first power bus in the layout.

[0152] Increase the number of switches connected to the first power bus.

[0153] Increase the number of capacitors connected to the first power bus; or adjust the capacitance value of the capacitors connected to the first power bus; or adjust the distribution of the capacitors connected to the first power bus.

[0154] If the performance of the first power bus does not meet the performance requirements of the circuit to be simulated, the ways to improve the circuit to be simulated include, but are not limited to:

[0155] Increase the width of the second power bus in the layout.

[0156] Increase the number of capacitors connected to the second power bus; or adjust the capacitance value of the capacitors connected to the second power bus; or adjust the distribution of the capacitors connected to the second power bus.

[0157] The circuit simulation method provided in this disclosure, during post-simulation, obtains the netlist and SPF file corresponding to the circuit to be simulated from the design database of the circuit to be simulated. The SPF file includes parameters corresponding to each power bus, device parameters of the switches connected on each power bus, and device parameters of the load. Based on the above netlist and SPF file, the circuit to be simulated is simulated, which makes the simulation process closer to the actual working condition of the circuit to be simulated. Furthermore, based on the simulation results, the performance of the power bus can be accurately evaluated. When the performance of the power bus does not meet the performance requirements of the circuit to be simulated, the power bus can be made to meet the performance requirements of the circuit to be simulated by improving the circuit to be simulated.

[0158] Based on the content described in the above embodiments, this disclosure also provides a circuit simulation device applied to a circuit to be simulated. The circuit to be simulated includes a first power bus, a second power bus, at least one first load connected to the first power bus, and at least one second load connected to the second power bus. The first power bus is connected to the second power bus via a switch, and the second power bus is connected to an external power source.

[0159] Reference Figure 7 , Figure 7 This is a schematic diagram of the program modules of a circuit simulation device provided in an embodiment of this disclosure. In some embodiments of this disclosure, the circuit simulation device includes:

[0160] The acquisition module 701 is used to acquire the netlist and SPF file corresponding to the circuit to be simulated based on the design database of the circuit to be simulated. The SPF file includes parameters corresponding to the first power bus, parameters corresponding to the second power bus, device parameters of all first loads, device parameters of all second loads, and device parameters of the switch.

[0161] The simulation module 702 is used to simulate the circuit to be simulated based on the netlist and the SPF file.

[0162] The processing module 703 is used to determine, based on the simulation results of the circuit to be simulated, whether the performance of the first power bus and the second power bus meets the performance requirements of the circuit to be simulated.

[0163] The circuit simulation apparatus provided in this embodiment obtains the netlist and SPF file corresponding to the circuit to be simulated from the design database of the circuit to be simulated during post-simulation. The SPF file includes parameters corresponding to each power bus, device parameters of switches, and device parameters of loads. Based on the netlist and SPF file, the circuit to be simulated is simulated, which makes the simulation process closer to the actual working condition of the circuit to be simulated. Then, based on the simulation results, the performance of the power bus can be accurately evaluated, so that the power bus can meet the performance requirements of the circuit to be simulated.

[0164] It should be noted that the specific execution of the acquisition module 701, simulation module 702, and processing module 703 in this embodiment can be found in the [reference needed]. Figures 1 to 6 The relevant content in the illustrated embodiments will not be repeated here.

[0165] Furthermore, based on the content described in the above embodiments, this disclosure also provides an electronic device, which includes at least one processor and a memory; wherein the memory stores computer execution instructions; the at least one processor executes the computer execution instructions stored in the memory to implement the various steps in the circuit simulation method described in the above embodiments, which will not be repeated here.

[0166] To better understand the embodiments of this disclosure, please refer to... Figure 8 , Figure 8 This is a schematic diagram of the hardware structure of an electronic device provided in an embodiment of this disclosure.

[0167] like Figure 8 As shown, the electronic device 80 of this embodiment includes: a processor 801 and a memory 802; wherein:

[0168] Memory 802 is used to store instructions executed by the computer;

[0169] The processor 801 is used to execute computer execution instructions stored in the memory to implement the various steps in the circuit simulation method described in the above embodiments. For details, please refer to the relevant descriptions in the foregoing method embodiments.

[0170] Alternatively, the memory 802 can be either standalone or integrated with the processor 801.

[0171] When the memory 802 is set up independently, the device also includes a bus 803 for connecting the memory 802 and the processor 801.

[0172] Furthermore, based on the content described in the above embodiments, this disclosure also provides a computer-readable storage medium storing computer-executable instructions. When the processor executes the computer-executable instructions, it implements the various steps in the circuit simulation method described in the above embodiments. This embodiment will not repeat the details here.

[0173] In the several embodiments provided in this disclosure, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative; for instance, the division of modules described above is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple modules may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be indirect coupling or communication connection through some interfaces, devices, or modules, and may be electrical, mechanical, or other forms.

[0174] The modules described above as separate components may or may not be physically separate. The components shown as modules may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0175] Furthermore, the functional modules in the various embodiments of this disclosure can be integrated into one processing unit, or each module can exist physically separately, or two or more modules can be integrated into one unit. The unit integrating the above modules can be implemented in hardware or in the form of hardware plus software functional units.

[0176] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this disclosure.

Claims

1. A circuit simulation method, characterized by, The application is applied to a to-be-simulated circuit, wherein the to-be-simulated circuit comprises a first power bus, a second power bus, at least one first load connected to the first power bus, and at least one second load connected to the second power bus; The first power bus is connected to the second power bus through a switch, and the second power bus is connected to an external power supply; the method comprises: According to a design database of the to-be-simulated circuit, a netlist corresponding to the to-be-simulated circuit and a standard parasitic parameter format file are obtained, wherein the standard parasitic parameter format file comprises parameters corresponding to the first power bus, parameters corresponding to the second power bus, device parameters of all the first loads, device parameters of all the second loads, and device parameters of the switch; The to-be-simulated circuit is simulated based on the netlist and the standard parasitic parameter format file; According to a simulation result of the to-be-simulated circuit, whether the performance of the first power bus and the second power bus meets the performance requirement of the to-be-simulated circuit is determined; The first power bus comprises a first sub-power bus, the second power bus comprises a second sub-power bus, the external power supply comprises a first power supply, and the switch comprises at least one first transistor; A first electrode of each first transistor is connected to the second sub-power bus, a second electrode is connected to the first sub-power bus, and a gate electrode receives a first driving signal in the to-be-simulated circuit; The device parameters of the switch comprise characteristic size parameters of all the first transistors.

2. The method of claim 1, wherein, The parameters corresponding to the first power bus comprise self-resistance and / or parasitic capacitance of the first power bus, and the parameters corresponding to the second power bus comprise self-resistance and / or parasitic capacitance of the second power bus.

3. The method of claim 1, wherein, The first power bus further comprises a third sub-power bus, the second power bus further comprises a fourth sub-power bus, the external power supply further comprises a second power supply, and the switch further comprises at least one second transistor; A first electrode of each second transistor is connected to the fourth sub-power bus, a second electrode is connected to the third sub-power bus, and a gate electrode receives a second driving signal in the to-be-simulated circuit; The device parameters of the switch further comprise characteristic size parameters of all the second transistors.

4. The method of claim 3, wherein, The to-be-simulated circuit further comprises at least one pad connected to the second power bus; The standard parasitic parameter format file further comprises input voltage information of a connection between all the pads and the second power bus.

5. The method of claim 4, wherein, The pad comprises a first pad and a second pad, the first pad is connected to the second sub-power bus, and the second pad is connected to the fourth sub-power bus; The standard parasitic parameter format file further comprises first input voltage information of a connection between the first pad and the second sub-power bus, and second input voltage information of a connection between the second pad and the fourth sub-power bus.

6. The method of claim 3, wherein, The to-be-simulated circuit further includes a first capacitor connected between the second sub-power bus and the fourth sub-power bus, and / or a second capacitor connected between the first sub-power bus and the third sub-power bus. The standard parasitic parameter format file further includes parameter information of the first capacitor and / or the second capacitor.

7. The method of claim 1, wherein, The device parameters of the first load include resistance and capacitance of devices in the first load; and the device parameters of the second load include resistance and capacitance of devices in the second load.

8. A circuit simulation method, characterized by, The to-be-simulated circuit includes a first power bus, a second power bus, at least one first load connected to the first power bus, and at least one second load connected to the second power bus; The first power bus is connected to the second power bus through a switch, and the second power bus is connected to an external power supply; the method comprises: According to a design database of the to-be-simulated circuit, a netlist corresponding to the to-be-simulated circuit and a standard parasitic parameter format file are obtained, the standard parasitic parameter format file including parameters corresponding to the first power bus, parameters corresponding to the second power bus, device parameters of all the first loads, device parameters of all the second loads, and device parameters of the switch; Based on the netlist and the standard parasitic parameter format file, the to-be-simulated circuit is simulated; According to a simulation result of the to-be-simulated circuit, it is determined whether the performance of the first power bus and the second power bus meets the performance requirement of the to-be-simulated circuit; According to the simulation result of the to-be-simulated circuit, a first voltage value at a node where the first load and the first power bus are connected, and a second voltage value at a node where the second load and the second power bus are connected are determined; According to the first voltage value and the second voltage value, it is determined whether the performance of the first power bus and the second power bus meets the performance requirement of the to-be-simulated circuit. According to the first voltage value and the second voltage value, it is determined whether the width of the first power bus and the second power bus in the layout meets the performance requirement of the to-be-simulated circuit.

9. The method of claim 8, wherein, According to the first voltage value and the second voltage value, it is determined whether the number of the switch connected to the first power bus meets the performance requirement of the to-be-simulated circuit. ​ 10. The method of claim 8, wherein, ​ ​ 11. The method of claim 8, wherein, The determining whether the performance of the first power bus and the second power bus meets the performance requirement of the circuit to be simulated according to the first voltage value and the second voltage value comprises: The determining whether the performance of the first power bus and the second power bus meets the performance requirement of the circuit to be simulated according to the first voltage value and the second voltage value comprises:

12. The method of claim 8, wherein, The determining whether the performance of the first power bus and the second power bus meets the performance requirement of the circuit to be simulated according to the first voltage value and the second voltage value comprises: The determining whether the performance of the first power bus and the second power bus meets the performance requirement of the circuit to be simulated according to the first voltage value and the second voltage value comprises:

13. The method according to any one of claims 8 to 12, characterized in that, The determining whether the performance of the first power bus and the second power bus meets the performance requirement of the circuit to be simulated according to the first voltage value and the second voltage value comprises: The method further comprises: If the performance of the first power bus does not meet the performance requirement of the circuit to be simulated, increasing the width of the first power bus in the layout; 14. The method according to any one of claims 8 to 12, characterized in that, If the performance of the second power bus does not meet the performance requirement of the circuit to be simulated, increasing the width of the second power bus in the layout. The method further comprises:

15. The method according to any one of claims 8 to 12, characterized in that, If the performance of the first power bus does not meet the performance requirement of the circuit to be simulated, increasing the number of switches connected to the first power bus. The method further comprises: If the performance of the first power bus does not meet the performance requirement of the circuit to be simulated, increasing the number of capacitors connected to the first power bus, or adjusting the capacitance value of the capacitors connected to the first power bus, or adjusting the distribution position of the capacitors connected to the first power bus; 16. A circuit emulation device, comprising: If the performance of the second power bus does not meet the performance requirement of the circuit to be simulated, increasing the number of capacitors connected to the second power bus, or adjusting the capacitance value of the capacitors connected to the second power bus, or adjusting the distribution position of the capacitors connected to the second power bus. The method is applied to a circuit to be simulated, and the circuit to be simulated comprises a first power bus, a second power bus, at least one first load connected to the first power bus, and at least one second load connected to the second power bus. The first power bus is connected to the second power bus through a switch, and the second power bus is connected to an external power supply. The device comprises: The device comprises: The device comprises: The device comprises: The simulation module is configured to simulate the to-be-simulated circuit based on the netlist and the standard parasitic parameter format file. The processing module is configured to determine whether the performance of the first power bus and the second power bus meets the performance requirement of the to-be-simulated circuit according to the simulation result of the to-be-simulated circuit. The first power bus includes a first sub-power bus, the second power bus includes a second sub-power bus, the external power supply includes a first power supply, and the switch includes at least one first transistor. The first electrode of each first transistor is connected with the second sub-power bus, the second electrode is connected with the first sub-power bus, and the gate electrode receives a first driving signal in the to-be-simulated circuit. The device parameters of the switch include characteristic size parameters of all the first transistors. Alternatively, The determination of whether the performance of the first power bus and the second power bus meets the performance requirement of the to-be-simulated circuit according to the simulation result of the to-be-simulated circuit includes: determining a first voltage value at a node connected with the first load and the first power bus and a second voltage value at a node connected with the second load and the second power bus according to the simulation result of the to-be-simulated circuit; and determining whether the performance of the first power bus and the second power bus meets the performance requirement of the to-be-simulated circuit according to the first voltage value and the second voltage value.

17. An electronic device, comprising: The circuit simulation method includes: at least one processor and a memory; the memory stores computer-executable instructions; the at least one processor executes the computer-executable instructions stored in the memory, so that the at least one processor executes the circuit simulation method according to any one of claims 1 to 15.

18. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions, and when the computer executes the computer-executable instructions, the circuit simulation method according to any one of claims 1 to 15 is realized.

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