Clock tree synthesis method and apparatus, electronic device, and computer-readable storage medium

Abstract

The present application provides a clock tree synthesis method, device, electronic device and computer-readable storage medium, the method comprising: dividing the clock nodes into multiple skew groups based on the physical location and naming of each clock node that needs to undergo clock tree synthesis in a chip; wherein the clock nodes are nodes in the chip that are controlled by a clock signal; each of the skew groups includes one or more different clock nodes; balancing the time delays between the skew groups to obtain a target design structure; and using the target design structure in the chip. The present application can automatically divide the skew groups without relying on the experience of IC design engineers for manual grouping, thereby reducing the subjectivity of grouping and also reducing the time consumption of grouping, thereby improving efficiency.

Description

TECHNICAL FIELD

[0001] The present application relates to the chip design field, in particular, to a clock tree synthesis method and device, electronic equipment and computer readable storage medium. BACKGROUND

[0002] With the continuous development of integration technology, the integration level of chips such as CPU (Central Processing Unit) and GPU (Graphics Processing Unit) has also been significantly improved. How to balance the clock tree in the chip is one of the biggest challenges in chip design. The step of ensuring clock quality in the back end of chip design is called CTS (Clock tree synthesis). When CTS needs to balance a large number of clock-controlled elements (i.e. elements controlled by clock signals, such as flip-flops, etc.) in a large block in the chip, directly using EDA (Electronic Design Automation) tools for CTS design will increase the clock delay of the entire block (usually achieved by inserting a logic gate unit, so it is also called insertion delay) in order to take into account the delay between all clock-controlled elements, which will increase the OCV (On Chip Variation) derating on the data path, making the high-performance design of the chip more challenging.

[0003] Therefore, IC (Integrated Circuit) design engineers will manually check CTS, and then based on experience, the entire block (usually a physical area corresponding to a clock domain) is divided into multiple skew groups. By balancing the time delay between skew groups, a design structure with less insertion delay can be obtained under the condition that the clock-controlled elements in each skew group meet the design requirements.

[0004] However, this approach relies heavily on the experience of IC design engineers and is highly subjective, making it difficult to ensure that the effect of the design structure after each split is good. In addition, since this approach must rely on the experience of IC design engineers to complete manually, it also has the problems of long time-consuming and low efficiency. SUMMARY

[0005] The purpose of the embodiments of the present application is to provide a clock tree synthesis method, device, electronic equipment and computer readable storage medium to solve the above problems.

[0006] The embodiment of the present application provides a clock tree synthesis method, comprising: dividing clock nodes needing clock tree synthesis in a chip into a plurality of skew groups based on physical positions and naming names of the clock nodes; wherein the clock nodes are nodes controlled by clock signals in the chip; each skew group comprises one or more different clock nodes; balancing time delays between the skew groups to obtain a target design structure; and using the target design structure in the chip.

[0007] Through the above implementation process, the skew groups can be automatically divided based on the physical positions and naming names of the clock nodes needing clock tree synthesis in the chip, without relying on experience of IC design engineers to manually group, thereby reducing subjectivity of grouping and time-consuming of grouping, and improving efficiency. In addition, since the time delay between clock nodes is positively correlated with the distance between the clock nodes, and since timing requirements between different logic groups can be different, and the naming name of the clock node can reflect which logic group the clock node belongs to, therefore, the clock nodes in the same skew group can have smaller clock skew by dividing the clock nodes into skew groups based on the physical positions and naming names of the clock nodes, the CTS tool can work more on balancing the time delays between the skew groups, so that only a smaller physical area needs to be balanced in the CTS design process, thereby making the delay in the clock tree smaller, and ensuring that the effect of the design structure obtained by splitting the block (i.e. the region where the clock nodes are located) is good compared with not splitting.

[0008] Further, the clock nodes needing clock tree synthesis in the chip are divided into a plurality of skew groups based on the physical positions and naming names of the clock nodes, comprising: dividing the clock nodes into a plurality of skew groups according to different grouping manners based on the physical positions and naming names of the clock nodes needing clock tree synthesis in the chip, to obtain a skew group set corresponding to each grouping manner; and balancing time delays between the skew groups to obtain a target design structure, comprising: for each skew group set, balancing time delays between the skew groups in the skew group set to obtain a design structure corresponding to the skew group set; determining chip costs when each design structure is used in the chip; and determining a target design structure from each design structure according to chip costs corresponding to the design structures.

[0009] In the above implementation process, the clock nodes are divided into a plurality of skew groups by using different grouping manners, and the chip cost corresponding to the design structure obtained by each grouping manner is determined, and then the target design structure most meeting the requirements can be obtained based on the chip costs corresponding to the design structures, so that the use of the target design structure can meet the actual requirements while the chip cost is optimal.

[0010] Further, the clock nodes are divided into a plurality of skew groups according to different grouping manners based on the physical positions and naming names of the clock nodes in the chip, including: determining distances between the clock nodes based on the physical positions of the clock nodes, and determining clock nodes belonging to the same logical group among the clock nodes based on the naming names of the clock nodes; clock nodes belonging to the same logical group and having distances less than or equal to a preset distance threshold are divided into the same skew group.

[0011] In the above implementation process, by dividing clock nodes belonging to the same logical group and having distances less than or equal to a preset distance threshold into the same skew group, the clock nodes in the same skew group can have smaller clock skew, so that the CTS tool can invest more work in balancing the delay between skew groups, so that only fewer physical regions need to be balanced in the CTS design process, so that the delay in the clock tree is smaller, and it is ensured that the design structure obtained after the block is split can bring good results.

[0012] Further, the clock nodes are divided into a plurality of skew groups according to different grouping manners based on the physical positions and naming names of the clock nodes in the chip, including: determining clock nodes belonging to the same logical group among the clock nodes based on the naming names of the clock nodes; determining a position center of the clock nodes belonging to the same logical group based on the physical positions of the clock nodes belonging to the same logical group; and dividing target clock nodes within a preset range from the position center into the same skew group; wherein the target clock nodes are clock nodes belonging to the logical group corresponding to the position center.

[0013] In the above implementation process, since the clock nodes in a skew group are all input clock nodes of the same logical group, by dividing target clock nodes within a preset range from the position center of the clock nodes belonging to the same logical group into the same skew group, the clock nodes in the same skew group can have smaller clock skew, so that the CTS tool can invest more work in balancing the delay between skew groups, so that only fewer physical regions need to be balanced in the CTS design process, so that the delay in the clock tree is smaller, and it is ensured that the design structure obtained after the block is split can bring good results.

[0014] Further, the preset range is determined according to a preset area threshold, or the preset range is determined according to a preset number threshold of the target clock nodes divided into the skew group.

[0015] It can be understood that in the chip design process, the chip cost per unit area is different for different process angles. Therefore, based on the preliminary basic research, the optimal area or clock node number of the CTS design effect under each process angle can be initially obtained. In the above implementation process, the preset range is determined by setting the area threshold, or the preset range is determined by setting the number threshold, so the preset range can be determined according to the optimal area or clock node number of the CTS design effect under the current process angle initially determined in the basic research, so that the finally selected target design structure meets the current process angle requirement, and good timing constraint effect can be obtained after using the target design structure in the chip.

[0016] Further, the clock skew between each clock node in each of the skew groups is within a preset skew range.

[0017] In the above implementation process, since the clock skew between each clock node in each skew group is within a preset skew range, as long as the skew range is within the clock skew range specified by the chip, the skew group does not need to balance the delay between the clock nodes, thereby reducing the physical area that needs to be balanced in the CTS design process, reducing the delay in the clock tree, and reducing the power consumption.

[0018] Further, when the clock nodes are divided into a plurality of skew groups according to each grouping manner to obtain a skew group set corresponding to each grouping manner, the method further comprises: recording the skew group to which each clock node belongs and the grouping manner; for each skew group set, balancing the delay between each skew group in the skew group set to obtain a design structure corresponding to the skew group set, comprising: according to the recorded skew group to which each clock node belongs and the grouping manner, sequentially balancing the delay between each skew group in the same grouping manner to obtain a design structure corresponding to the skew group set under the grouping manner; repeating the above process to obtain a design structure corresponding to the skew group set under each grouping manner.

[0019] In the above implementation process, by recording the skew group to which each clock node belongs and the grouping manner, the information basis is clear in the subsequent process of obtaining the design structure corresponding to each skew group set and determining the chip cost of each design structure, so that the situation that the design structure cannot be accurately determined due to information confusion when obtaining the design structure does not occur.

[0020] Further, the chip cost when each of the design structures is used in the chip is determined by: obtaining values of cost parameters of the chip when each of the design structures is used in the chip; the cost parameters include at least one of power consumption, area, and frequency of the chip; and determining the chip cost when each of the design structures is used in the chip according to the values of the cost parameters of the chip when each of the design structures is used.

[0021] In the implementation process, the chip cost when each of the design structures is determined based on values of cost parameters including at least one of power consumption, area, and frequency of the chip, so that the design structures can be evaluated from at least one dimension affecting the performance of the chip, thereby effectively judging the advantages and disadvantages of each of the design structures, and making the selection of the target design structure more objective.

[0022] The embodiment of the present application further provides a CTS design device, which comprises: a grouping module, configured to divide clock nodes in a chip into a plurality of skew groups based on physical positions and naming names of the clock nodes; wherein the clock nodes are nodes controlled by clock signals in the chip; each of the skew groups comprises one or more different clock nodes; a balancing module, configured to balance time delays between the skew groups to obtain a target design structure; and a processing module, configured to use the target design structure in the chip.

[0023] Further, the grouping module is specifically configured to: determine distances between the clock nodes based on the physical positions of the clock nodes, and determine clock nodes belonging to the same logical group among the clock nodes based on the naming names of the clock nodes; and divide clock nodes belonging to the same logical group and having distances less than or equal to a preset distance threshold to the same skew group.

[0024] Further, the grouping module is specifically configured to: determine clock nodes belonging to the same logical group among the clock nodes based on the naming names of the clock nodes; determine a position center of the clock nodes belonging to the same logical group based on the physical positions of the clock nodes belonging to the same logical group; and divide target clock nodes within a preset range from the position center to the same skew group; wherein the target clock nodes are clock nodes belonging to the logical group corresponding to the position center.

[0025] The embodiment of the present application further provides an electronic device, which comprises a processor and a memory; the processor is configured to execute one or more programs stored in the memory to implement any of the clock tree synthesis methods.

[0026] The embodiment of the present application further provides a computer readable storage medium, the computer readable storage medium stores one or more programs, the one or more programs can be executed by one or more processors to implement the clock tree synthesis method. BRIEF DESCRIPTION OF DRAWINGS

[0027] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the embodiments of the present application will be briefly introduced as follows, and it should be understood that the following drawings only show some embodiments of the present application, and therefore should not be regarded as a limitation to the scope, and for those skilled in the art, other related drawings can also be obtained without creative labor on the basis of these drawings.

[0028] Figure 1 A flowchart of a clock tree synthesis method provided by the embodiment of the present application is shown in the figure.

[0029] Figure 2 A clock node grouping diagram provided by the embodiment of the present application is shown in the figure.

[0030] Figure 3 Another clock node grouping diagram provided by the embodiment of the present application is shown in the figure.

[0031] Figure 4 A structural diagram of a clock tree synthesis device provided by the embodiment of the present application is shown in the figure.

[0032] Figure 5 A structural diagram of an electronic device provided by the embodiment of the present application is shown in the figure. DETAILED DESCRIPTION

[0033] The technical solutions in the embodiments of the present application will be described in detail below with reference to the drawings in the embodiments of the present application.

[0034] It should be understood that the disclosed devices and methods in the embodiments provided by the present application can be implemented in other ways, and the subsequently described embodiments are merely illustrative. For example, the division of units in the device embodiments is only a logical function division, and actual implementation can have another division manner, and for example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed.

[0035] In this document, the relationship terms such as first and second are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between these entities or operations.

[0036] In this document, plural means two or more.

[0037] In order to solve the problem that in the current CTS design process, the division of the skew group must be manually performed by an IC design engineer, so that the division result is seriously dependent on the experience of the IC design engineer, the subjectivity is strong, it is difficult to guarantee that the effect brought by the design structure after each time of division is good, and there is also the problem of long time consumption and low efficiency, the embodiment of the present application provides a clock tree synthesis method. It can be seen from Figure 1 As shown in the figure, Figure 1 The flowchart of the clock tree synthesis method provided in the embodiment of the present application comprises:

[0038] S101: Based on the physical positions and naming names of each clock node in the chip that needs to perform clock tree synthesis, the clock nodes are divided into skew groups.

[0039] It should be noted that the chip in the embodiment of the present application should be understood in a broad sense, which can be a chip layout in the chip design stage, or a chip entity that has been produced.

[0040] In the embodiment of the present application, the clock node is a node in the chip controlled by a clock signal, such as a flip-flop, a register, a latch, etc. It can be understood that the node in the embodiment of the present application refers to an electronic element or a standard cell arranged in the chip.

[0041] In the embodiment of the present application, each skew group includes one or more different clock nodes. It can be understood that the embodiment of the present application allows only one skew group to exist, at this time all clock nodes are located in the skew group, at this time the case is consistent with the case without division.

[0042] In the embodiment of the present application, each clock node that needs to perform clock tree synthesis can be set or specified by an engineer, or can be determined by a chip design tool such as an EDA tool. Correspondingly, the physical positions and naming names of each clock node that needs to perform clock tree synthesis can be input by an engineer or automatically obtained from a chip design tool such as an EDA tool.

[0043] It can be understood that in the chip design process, the naming of the node is performed according to the set logic naming rule, for example, the naming name can sequentially include the belonging logic group, the node type (such as register, latch, flip-flop, etc.), the identification, etc. but not as a limitation, so that the logic group to which the node belongs can be parsed from the naming name of the node. The so-called logic group refers to different logic circuits built in the chip design process to realize different functions, and the standard cells or electronic elements constituting these logic circuits are called logic groups.

[0044] In an optional implementation of the embodiments of the present application, to implement the division of skew groups, the distance between each clock node can be determined based on the physical location of each clock node, and the clock nodes belonging to the same logical group can be determined based on the naming of each clock node. Then, the clock nodes belonging to the same logical group and having a distance less than or equal to the preset distance threshold can be divided into the same skew group.

[0045] In the above optional implementation, to divide the clock nodes belonging to the same logical group and having a distance less than or equal to the preset distance threshold into the same skew group, the clock nodes can be first classified according to the logical groups. Then, for each classified clock node: an optional clock node in the classified clock nodes is taken as a starting node, all clock nodes having a distance less than or equal to the preset distance threshold are found, and clock nodes having a distance greater than the preset distance threshold with any other clock node are removed from the clock nodes, so that the remaining clock nodes have a distance less than or equal to the preset distance threshold, and a skew group is obtained. The above process is repeated for the remaining clock nodes in the classified clock nodes until all clock nodes are divided into skew groups.

[0046] It can be understood that the preset distance threshold can be set according to actual needs, for example, can be set according to the maximum clock skew allowed by the logical group.

[0047] It can be understood that the above is only one way to divide the clock nodes belonging to the same logical group and having a distance less than or equal to the preset distance threshold into the same skew group, and is not limited. For example, after the clock nodes are classified according to the logical groups, a pre-trained grouping model (such as a neural network model) can be used to divide the skew groups for each classified clock node, but is not limited.

[0048] In another alternative implementation of the embodiments of the present application, in order to implement the division of the skew group, the clock nodes belonging to the same logical group can be determined based on the naming of the clock nodes, and then the position center of the clock nodes belonging to the same logical group can be determined based on the physical positions of the clock nodes belonging to the same logical group. Then, the target clock nodes within a preset range from the position center, wherein the target clock nodes are the clock nodes belonging to the logical group corresponding to the position center, are divided into the same skew group. It can be understood that for the remaining clock nodes in the logical group corresponding to the position center, the position center of the remaining clock nodes can be determined again, and then the target clock nodes within a preset range from the new position center (it should be noted that the target clock nodes do not include the clock nodes that have been divided into skew groups, so as to ensure that there is no same clock node between skew groups) are divided into the same skew group. The above process is repeated until all clock nodes belonging to the logical group are divided into skew groups.

[0049] It can be understood that the position center can be obtained by calculating the average or weighted average of the position coordinates of the clock nodes, but is not limited thereto.

[0050] For example, as shown in Figure 2 , it is assumed that the clock nodes A, B, C and D belong to the same logical group, it is assumed that the position center calculated based on the clock nodes A, B, C and D is a, and it is assumed that A and B are within a preset range from a, then A and B are divided into a skew group 1. The position center calculated based on the clock nodes C and D is b, and it is assumed that C and D are within a preset range from b, then C and D are divided into a skew group 2, and at this time, since A and B have been divided into the skew group 1, A and B do not participate in the division of the skew group 2 regardless of whether A and B are within the preset range from b.

[0051] In the above implementation, the preset range can be determined according to a preset area threshold, or the preset range can be determined according to a preset number threshold of the target clock nodes divided into the skew group. When the preset range is determined according to the preset number threshold of the target clock nodes divided into the skew group, the preset range is not a fixed value, and the range size is related to the physical positions of the clock nodes. For example, in the above example, the number threshold of the target clock nodes divided into the skew group is 3, as shown in Figure 3 , the position center a is extended outward, and it is assumed that the clock nodes A, B and C are sequentially included in the extended area, and the number threshold 3 is reached when the clock node C is included, at which time the extension is ended, and the range at this time is recorded as the preset range. Thereafter, the remaining clock node D is separately divided into another skew group.

[0052] It can be understood that the above are only two possible implementations provided by the present application, and are not intended to limit the manner of skew group division in the present application.

[0053] It can also be understood that in the embodiments of the present application, the skew groups can also be divided according to different grouping manners based on the physical positions and naming names of the clock nodes in the chip that need to be clock tree synthesized, to obtain a skew group set corresponding to each grouping manner.

[0054] At this time, a plurality of skew group sets are obtained, so that in the subsequent step S102, a design structure of each skew group set is obtained, so that an optimal design structure can be selected from a plurality of design structures as a target design structure, so that the target design structure used in the chip finally has a better effect.

[0055] It can be understood that when a plurality of skew group sets are obtained by dividing the skew groups according to different grouping manners, the skew group division manner under each grouping manner can be implemented by using any one of the two possible implementations described above, the difference being that when the first possible implementation is used for skew group division, different grouping manners should have different preset distance thresholds to ensure that different grouping manners can obtain different skew group sets; when the second possible implementation is used for skew group division, different grouping manners should have different preset ranges to ensure that different grouping manners can obtain different skew group sets.

[0056] It can be understood that in the chip design process, the chip cost per unit area is not the same for different process angles. Therefore, based on preliminary basic research, the area or clock node number with the optimal CTS design effect under each process angle can be initially obtained. In an optional embodiment of the embodiments of the present application, when the second possible implementation is used for skew group division, the preset range of different grouping manners can be determined based on the area or clock node number with the optimal CTS design effect under each process angle initially determined in the basic research, so that the target design structure finally selected is in line with the current process angle requirement, so that good timing constraint effect can be obtained after the target design structure is used in the chip.

[0057] S102: Balance the time delay between the skew groups to obtain a target design structure.

[0058] It can be understood that in the embodiments of the present application, the balance of the time delay between the skew groups can be achieved by adding logic gates and the like between the skew groups through the CTS tool, but this is not a limitation.

[0059] It can also be understood that when the clock nodes are divided into skew groups in multiple different grouping manners to obtain multiple skew group sets, the time delay between the skew groups in each skew group set can be balanced by adding logical gates and the like between the skew groups in the skew group set through the CTS tool, but this is also not as a limitation.

[0060] It can also be understood that if the time delay between the clock nodes in a skew group does not meet the timing requirements of the design, the time delay between the clock nodes in the skew group also needs to be balanced through the design structure. Therefore, in order to reduce the physical area that needs to be balanced in the CTS design process and reduce the delay and power consumption in the clock tree, the clock skew between the clock nodes in each skew group can be configured to be within a preset skew range. The preset skew range can be within the clock skew range specified in the chip design. In this way, the time delay between the clock nodes in the skew group can be balanced, thereby achieving the effect of reducing the physical area that needs to be balanced in the CTS design process and reducing the delay and power consumption in the clock tree.

[0061] In order to make the clock skew between the clock nodes in each skew group within the preset skew range, in an optional embodiment of the present application, a reasonable distance threshold or a preset range can be set to ensure that the clock skew between the clock nodes divided into the skew group is within the preset skew range. In another optional embodiment of the present application, the clock skew between the clock nodes in the skew group can also be detected by an EDA tool after the skew group is divided, and the clock node with a clock skew exceeding the preset skew range is removed from the skew group and added to another skew group or separately as a skew group, thereby ensuring that the clock skew between the clock nodes in each skew group is within the preset skew range.

[0062] It can be understood that the structure after the time delay is balanced by the CTS tool is the design structure described in the present application. In the scheme with only one skew group set, the design structure obtained is the target design structure. In the scheme with multiple skew group sets obtained by using multiple different grouping manners, multiple design structures are obtained, and a target design structure needs to be selected from the multiple design structures.

[0063] Therefore, in the present application, the chip cost when each design structure is used in the chip can be determined first, and then the target design structure is determined from the design structures according to the chip cost corresponding to each design structure.

[0064] Optionally, a manner of determining the chip cost when each design structure is used in the chip is that, values of the cost parameters of the chip when each design structure is used in the chip are acquired, and then the chip cost when each design structure is used in the chip is determined according to the values of the cost parameters of the chip when each design structure is used in the chip respectively.

[0065] In the embodiment of the present application, the cost parameters can include at least one of the power consumption, the area and the frequency of the chip.

[0066] It can be understood that the cost of the chip in the embodiment of the present application is not the generation cost of the chip, but an evaluation value representing the performance of the chip. Among them, the power consumption value of the chip, the area of the chip and the cost of the chip are positively correlated, that is, the greater the power consumption value of the chip, the higher the chip cost, the greater the area of the chip, the higher the chip cost. The frequency value of the chip and the cost of the chip are negatively correlated, the higher the frequency value of the chip, the lower the chip cost.

[0067] In the embodiment of the present application, the values of the cost parameters of the chip can be directly fed back to the engineers for selection.

[0068] In addition, a total chip cost can also be obtained by converting the parameter values into scores and then performing weighted summation, and then the selection of the target design structure is performed based on the chip cost. For example, the design structure with the lowest chip cost is selected as the target design structure.

[0069] In this way, the design structure can be evaluated from at least one dimension affecting the performance of the chip, so as to effectively judge the advantages and disadvantages of each design structure, and make the subsequent selection of the target design structure more objective.

[0070] In the embodiment of the present application, the manner of converting the parameter values into scores can be but not limited to dimensionless processing, normalization processing, etc. The related processing manners please refer to the known technologies, which are not described in detail in the embodiment of the present application.

[0071] In the embodiment of the present application, the values of the cost parameters of the chip when each design structure is used in the chip can be obtained through EDA tool testing.

[0072] It can also be understood that, in the embodiments of the present application, when the clock nodes are divided into skew groups in multiple different grouping manners to obtain multiple skew group sets, since each grouping manner is for the division of the same clock nodes, in order to ensure the accuracy of subsequent processing, when the clock nodes are divided into multiple skew groups according to each grouping manner to obtain the skew group set corresponding to each grouping manner, the skew groups to which the clock nodes belong and the grouping manners can be associated and recorded. Then, for each skew group set: according to the recorded skew groups to which the clock nodes belong and the grouping manners, the delays between the skew groups in the same grouping manner are balanced in turn to obtain the design structure corresponding to the skew group set under the grouping manner. The above process is repeatedly performed, and the design structure corresponding to the skew group set under each grouping manner can be obtained.

[0073] In the embodiments of the present application, a record table can be constructed by software to associate and record the clock nodes, the skew groups to which the clock nodes belong and the grouping manners. In addition, since the clock nodes are mostly elements such as registers having data storage capability, the skew groups to which the clock nodes belong and the grouping manners can also be associated and recorded in the clock nodes in the form of attribute information. That is, the clock nodes can record the skew groups to which they belong and the grouping manners. For example, the clock node K records A1B2C1, indicating that the clock node K belongs to skew group 1 in grouping manner A, belongs to skew group 2 in grouping manner B, and belongs to skew group 1 in grouping manner C.

[0074] S103: using the target design structure in the chip.

[0075] It can be understood that, in actual application, there can be many skew groups divided, resulting in that although many physical regions to be balanced have been reduced in the CTS design process, there are still many regions to be balanced, and the insertion delay to be introduced is still large. Therefore, the skew groups can be abstracted as the clock nodes in the foregoing (at this time, the center coordinates of the skew groups can be taken as the physical positions, and the logical groups to which the skew groups belong are already clear, and do not need to be determined again), and the foregoing method is re-executed to divide and balance the skew groups, so as to attempt to further reduce the insertion delay to be introduced.

[0076] The scheme of the embodiments of the present application can be applied to the timing design of clock synchronization networks, asynchronous reset logic design, multi-point CTS structure, separate latches, and and / OR clock structure in chip design, but is not limited thereto.

[0077] The clock tree synthesis method provided by the embodiments of the present application can automatically perform skew group division based on the physical positions and naming names of clock nodes in a chip that need to perform clock tree synthesis, without relying on the experience of IC design engineers to manually perform grouping, thereby reducing the subjectivity of grouping and the long time-consuming of grouping, and improving the efficiency. In addition, since the delay between clock nodes is positively correlated with the distance between clock nodes, and since the timing requirements between different logic groups can be different, and the naming name of a clock node can reflect which logic group the clock node belongs to, therefore, based on the physical positions and naming names of the clock nodes, the clock nodes are divided into skew groups, so that the clock nodes in the same skew group have smaller clock skew, and the CTS tool works more on balancing the delay between skew groups, so that only fewer physical regions need to be balanced in the CTS design process, thereby making the delay in the clock tree smaller, and ensuring that the effect of the design structure obtained after splitting the block (i.e., the region where the clock nodes are located) is good compared with not splitting.

[0078] In addition, the embodiments of the present application can also divide the clock nodes into multiple skew groups by using different grouping methods, and determine the chip cost corresponding to the design structure obtained by each grouping method, and then based on the chip cost corresponding to each design structure, the target design structure that best meets the requirements can be obtained, so that the use of the target design structure can meet the actual requirements while the chip cost is optimal.

[0079] Reference Figure 4 In some other embodiments of the present application, a CTS design device 400 is also provided. The device 400 can be used to implement the method shown in Figure 1 It should be understood that the specific functions of the device 400 can be referred to the description in the above, and the detailed description is appropriately omitted here. The device 400 includes at least one software function module that can be stored in the form of software or firmware in the memory or solidified in the operating system of the device 400. Specifically:

[0080] Referring to Figure 4 The device 400 can include:

[0081] The grouping module 401 is configured to divide the clock nodes into multiple skew groups based on the physical positions and naming names of the clock nodes in a chip that need to perform clock tree synthesis; wherein the clock nodes are nodes in the chip controlled by a clock signal; each skew group includes one or more different clock nodes;

[0082] The balancing module 402 is configured to balance the delay between each skew group to obtain a target design structure;

[0083] The processing module 403 is configured to use the target design structure in the chip.

[0084] In an optional embodiment of the present application, the grouping module 401 is specifically configured to divide the clock nodes into a plurality of skew groups according to different grouping manners based on the physical positions and naming names of the clock nodes in the chip that need to perform clock tree synthesis, to obtain a skew group set corresponding to each grouping manner.

[0085] Correspondingly, the balancing module 402 is specifically configured to balance the time delays between the skew groups in each skew group set, to obtain a clock tree synthesis design structure corresponding to the skew group set; determine the chip cost when each design structure is used in the chip; and determine a target design structure from the design structures according to the chip cost corresponding to each design structure.

[0086] In an optional embodiment of the present application, the grouping module 401 is specifically configured to determine the distances between the clock nodes based on the physical positions of the clock nodes, and determine the clock nodes belonging to the same logical group among the clock nodes based on the naming names of the clock nodes; and divide the clock nodes, which are within a preset distance threshold and belong to the same logical group, into the same skew group.

[0087] In another optional embodiment of the present application, the grouping module 401 is specifically configured to determine the clock nodes belonging to the same logical group among the clock nodes based on the naming names of the clock nodes; determine the position center of the clock nodes belonging to the same logical group based on the physical positions of the clock nodes belonging to the same logical group; and divide the target clock nodes within a preset range from the position center into the same skew group; wherein the target clock nodes are the clock nodes belonging to the logical group corresponding to the position center.

[0088] In the above optional embodiment, the preset range is determined according to a preset area threshold, or the preset range is determined according to a preset quantity threshold of the target clock nodes divided into the skew group.

[0089] In the present application, the clock skew between the clock nodes in each skew group is within a preset skew range.

[0090] In the present application, the processing module 403 is further configured to record the skew groups to which the clock nodes belong and the grouping manners when the grouping module 401 divides the clock nodes into a plurality of skew groups according to each grouping manner, to obtain a skew group set corresponding to each grouping manner.

[0091] The balancing module 402 is specifically configured to: sequentially balance time delays between each skew group in the same grouping manner according to the recorded skew groups to which each clock node belongs and the grouping manner, to obtain a design structure corresponding to a skew group set in the grouping manner; and repeat the above process to obtain a design structure corresponding to a skew group set in each grouping manner.

[0092] In the embodiment of the application, the processing module 403 is specifically configured to: obtain a value of a cost parameter of the chip when each design structure is used in the chip; the cost parameter includes at least one of power consumption, area, and frequency of the chip; and determine a chip cost when each design structure is used in the chip according to the value of the cost parameter of the chip when each design structure is used.

[0093] It should be understood that, for the sake of brevity of description, some of the content described in the first embodiment is not repeated in the embodiment.

[0094] Some other embodiments of the application further provide an electronic device, as shown in Figure 5 The electronic device includes a processor 501 and a memory 502. Wherein:

[0095] The processor 501 is configured to execute one or more programs stored in the memory 502 to implement the clock tree synthesis method described in the first embodiment.

[0096] It should be understood that, Figure 5 The structure shown is only schematic, and the electronic device can further include more or less components than those shown in Figure 5 , or have a different configuration from Figure 5 .

[0097] For example, the processor 501 and the memory 502 can be connected through a communication bus. For another example, the electronic device can further include components such as a display, a mouse, a keyboard, etc.

[0098] In the embodiment of the application, the processor 501 can be a central processing unit, a microprocessor, a single-chip microcomputer, etc., but is not limited thereto. The memory 502 can be a random access memory, a read-only memory, a programmable read-only memory, an erasable programmable read-only memory, an electrically erasable programmable read-only memory, etc., but is not limited thereto.

[0099] In the embodiment of the application, the electronic device can be, but is not limited to, a physical device such as a desktop computer, a notebook computer, a server, etc., and can also be a virtual device such as a virtual machine. In addition, the electronic device is not necessarily a single device, but can also be a combination of multiple devices, such as a server cluster, etc.

[0100] The embodiment also provides a computer readable storage medium, such as a floppy disk, an optical disk, a hard disk, a flash memory, a U disk, an SD (Secure Digital Memory Card) card, an MMC (Multimedia Card) card, and the like, in which one or more programs for implementing the above steps are stored, and the one or more programs can be executed by one or more processors to implement the clock tree synthesis method of the above embodiment one. Details are not described herein.

[0101] The above merely provides an embodiment of the present application, and is not used to limit the protection scope of the present application. For those skilled in the art, the present application can have various modifications and changes. Any modification, equivalent replacement, improvement, and the like within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A clock tree synthesis method, characterized in that: include: Based on the physical location and name of each clock node that requires clock tree synthesis in the chip, the clock nodes are divided into multiple skew groups; wherein the clock nodes are nodes in the chip that are controlled by clock signals; each of the skew groups includes one or more different clock nodes; the names of the clock nodes represent the logic groups to which the clock nodes belong; the chip includes different logic circuits built to achieve different functions, and the logic groups are standard units or electronic components that constitute the logic circuits; Balancing the time delays between the skew groups to obtain a target design structure; The target design structure is used in the chip.

2. The clock tree synthesis method according to claim 1, wherein: Based on the physical location and naming of each clock node in the chip that needs clock tree synthesis, the clock nodes are divided into multiple skew groups, including: Based on the physical location and name of each clock node that needs to be subjected to clock tree synthesis in the chip, the clock nodes are divided into a plurality of skew groups according to different grouping methods, and a skew group set corresponding to each grouping method is obtained; and Balancing the delays between the skew groups to obtain a target design structure includes: For each of the skew group sets, balancing the delays between the skew groups in the skew group set to obtain a design structure corresponding to the skew group set; determining a chip cost when each of the design structures is used in the chip; A target design structure is determined from the design structures according to chip costs corresponding to the design structures.

3. The clock tree synthesis method according to claim 1, wherein: Based on the physical location and name of each clock node that needs to be synthesized for clock tree in the chip, the clock nodes are divided into multiple skew groups according to different grouping methods, including: Determining a distance between the clock nodes based on the physical locations of the clock nodes, and determining clock nodes belonging to the same logical group among the clock nodes based on the names of the clock nodes; The clock nodes whose distances to each other are less than or equal to a preset distance threshold and which belong to the same logical group are divided into the same skew group.

4. The clock tree synthesis method according to claim 1, wherein: Based on the physical location and name of each clock node that needs to be synthesized for clock tree in the chip, the clock nodes are divided into multiple skew groups according to different grouping methods, including: Determining clock nodes belonging to the same logical group among the clock nodes based on the names of the clock nodes; Determining the location center of each clock node belonging to the same logical group based on the physical location of each clock node belonging to the same logical group; The target clock nodes within a preset range from the location center are divided into the same skew group; wherein the target clock nodes are clock nodes belonging to the logical group corresponding to the location center.

5. The clock tree synthesis method according to claim 4, wherein: The preset range is determined according to a preset area threshold, or the preset range is determined according to a preset threshold of the number of the target clock nodes included in the skew group.

6. The clock tree synthesis method according to claim 2, wherein: When the clock nodes are divided into a plurality of skew groups according to each grouping mode to obtain a skew group set corresponding to each grouping mode, the method further comprises: associating and recording the skew group and the grouping mode to which each clock node belongs; For each skew group set, balancing the delays between the skew groups in the skew group set to obtain a design structure corresponding to the skew group set includes: According to the recorded skew groups and grouping modes to which the clock nodes belong, delays between the skew groups in the same grouping mode are balanced in turn, to obtain a design structure corresponding to the skew group set under the grouping mode; The above process is repeated to obtain the design structure corresponding to the skew group set under each grouping method.

7. The clock tree synthesis method according to claim 2, wherein: Determining a chip cost when each of the design structures is used in the chip, including: Obtaining a value of a cost parameter of the chip when each of the design structures is used in the chip; the cost parameter includes at least one of power consumption, area, and frequency of the chip; The chip cost when each of the design structures is used in the chip is determined according to the value of the cost parameter of the chip when each of the design structures is used.

8. The clock tree synthesis method according to any one of claims 1 to 7, wherein: The clock skews between the clock nodes in each skew group are within a preset skew range.

9. A clock tree synthesis device, characterized in that: include: A grouping module, configured to divide clock nodes in a chip requiring clock tree synthesis into a plurality of skew groups based on the physical location and name of each clock node in the chip; wherein the clock nodes are nodes in the chip controlled by a clock signal; each skew group includes one or more different clock nodes; the names of the clock nodes represent the logical groups to which the clock nodes belong; the chip includes different logic circuits constructed to implement different functions, and the logical groups are standard units or electronic components that constitute the logic circuits; a balancing module, configured to balance the time delays between the skew groups to obtain a target design structure; A processing module is configured to use the target design structure in the chip.

10. The clock tree synthesis device according to claim 9, wherein: The grouping module is specifically used for: Determining a distance between the clock nodes based on the physical locations of the clock nodes, and determining clock nodes belonging to the same logical group among the clock nodes based on the names of the clock nodes; The clock nodes whose distances to each other are less than or equal to a preset distance threshold and which belong to the same logical group are divided into the same skew group.

11. The clock tree synthesis device according to claim 9, wherein: The grouping module is specifically used for: Determining clock nodes belonging to the same logical group among the clock nodes based on the names of the clock nodes; Determining the location center of each clock node belonging to the same logical group based on the physical location of each clock node belonging to the same logical group; The target clock nodes within a preset range from the location center are divided into the same skew group; wherein the target clock nodes are clock nodes belonging to the logical group corresponding to the location center.

12. An electronic device, characterized in that: include: processor and memory; The processor is configured to execute the program stored in the memory to implement the clock tree synthesis method according to any one of claims 1 to 8.

13. A computer-readable storage medium, characterized in that The computer-readable storage medium stores one or more programs, and the one or more programs can be executed by one or more processors to implement the clock tree synthesis method according to any one of claims 1 to 8.

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