Ramp signal generation circuit and gamma correction circuit

Abstract

The present application discloses a ramp signal generation circuit and a gamma correction circuit. The ramp signal generation circuit includes: a first capacitor, a first end of the first capacitor is connected to an initial voltage via a first input switch and is connected to a termination voltage via a second input switch; a second capacitor, a first end of the second capacitor is grounded; and a first branch and a second branch connected in parallel between a second end of the first capacitor and a second end of the second capacitor, the first branch includes a first path switch, the second branch includes a second path switch and a voltage follower connected in series, wherein, in a pre-charge stage, the first input switch and the second path switch are turned on, in a step signal generation stage, the second input switch and the first path switch are turned on, so that the voltage on the second end of the second capacitor undergoes a step, and the pre-charge stage and the step signal generation stage are alternately executed to generate a ramp signal with a step change from the initial voltage to the termination voltage on the second end of the second capacitor.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit technologies, and more particularly, to a ramp signal generation circuit and a gamma correction circuit. Background Art

[0002] With the continuous development of display technologies and semiconductor processes, organic light-emitting diodes (OLEDs) have been widely used in display fields such as mobile phones, home appliances, and automobiles. Since the human eye's perception of light intensity is non-linear, a gamma correction circuit needs to be provided in the OLED driving chip so that the display gray levels and brightness meet the requirements of the gamma curve.

[0003] The mainstream gamma correction circuit is implemented by a resistor string digital-to-analog converter (DAC), which converts digital codes into analog voltage signals to drive OLED devices and display gray-scale images that conform to the linearity of the human eye. However, with the increase in display resolution, the area and power consumption of the traditional resistor string DAC structure far exceed the acceptable range of chip size and power consumption. Therefore, a gamma correction circuit architecture suitable for high-resolution displays needs to be proposed. Among them, the single-slope digital-to-analog conversion circuit has the advantages of small area and low power consumption and is widely used in high-resolution display driving circuits.

[0004] For the generation of traditional ramp signals, there are two most commonly used structures. One is the current steering structure, which generates a ramp signal by controlling the current flowing through a fixed resistor. The other method is the integrating structure, which uses a fixed current to charge a fixed capacitor to generate a continuous ramp signal. Both of these methods require precise current setting to achieve precise ramp steps, and are easily affected by process, temperature, voltage fluctuations (corners), etc., resulting in low accuracy of the gamma voltage and long signal establishment time in high-speed applications.

[0005] It is desired to provide an improved ramp signal generation circuit to solve the above problems. Summary of the Invention

[0006] In view of the above problems, an object of the present invention is to provide a ramp signal generation circuit and a gamma correction circuit, which take into account the accuracy and stability of the ramp signal and reduce the design difficulty of the circuit.

[0007] According to a first aspect of the present invention, there is provided a ramp signal generation circuit, comprising:

[0008] A first capacitor, a first end of the first capacitor is connected to an initial voltage via a first input switch and is connected to a termination voltage via a second input switch;

[0009] A second capacitor, a first end of the second capacitor is grounded; and

[0010] A first branch and a second branch connected in parallel between a second end of the first capacitor and a second end of the second capacitor, the first branch includes a first path switch, and the second branch includes a second path switch and a voltage follower connected in series.

[0011] Wherein, in a pre-charging stage, the first input switch and the second path switch are turned on, and the initial voltage charges the first capacitor.

[0012] In a step signal generation stage, the second input switch and the first path switch are turned on, and the termination voltage drives charges to flow between the first capacitor and the second capacitor, so that the voltage on the second end of the second capacitor undergoes a step change.

[0013] The pre-charging stage and the step signal generation stage are alternately executed to generate a ramp signal with a step change from the initial voltage to the termination voltage on the second end of the second capacitor.

[0014] Optionally, further comprising:

[0015] An initialization switch, a second end of the second capacitor is connected to the initial voltage via the initialization switch.

[0016] In an initialization stage, the initialization switch, the first input switch and the second path switch are turned on to initialize the voltages everywhere in the circuit.

[0017] Optionally, further comprising:

[0018] A timing controller for generating clock signals respectively controlling the initialization switch, the first input switch, the second input switch, the first path switch and the second path switch.

[0019] Optionally, the timing controller is configured to generate a first clock valid in the initialization stage, a second clock and a third clock alternately valid in the pre-charging stage and the step signal generation stage, and send the first clock to the initialization switch, send the second clock to the second input switch and the first path switch, and send the third clock to the first input switch and the second path switch.

[0020] Optionally, the periods of the second clock and the third clock are T, and the duty cycle is 1 / 2.

[0021] Optionally, when the number and frequency of the second clock and the third clock are both fixed values, the slope of the ramp signal is adjusted by adjusting the initial voltage and / or the termination voltage; and / or

[0022] When the initial voltage and the termination voltage are fixed values, the slope of the ramp signal is adjusted by adjusting the frequencies of the second clock and the third clock.

[0023] Optionally, each time the pre-charge stage and the step signal generation stage are executed, the change amount of the voltage on the second terminal of the second capacitor is:[[]]

[0024]

[0025] where ΔVramp is the change amount, Vstart is the voltage value of the initial voltage, Vend is the voltage value of the termination voltage, C1 is the capacitance value of the first capacitor, and C2 is the capacitance value of the second capacitor.

[0026] Optionally, the pre-charge stage and the step signal generation stage are each executed N times, and the capacitance values of the first capacitor and the second capacitor satisfy:[[]]

[0027]

[0028] Optionally, when the voltage value of the initial voltage is greater than the voltage value of the termination voltage, the slope of the ramp signal is negative;

[0029] When the voltage value of the initial voltage is less than the voltage value of the termination voltage, the slope of the ramp signal is positive;

[0030] When the voltage value of the initial voltage is equal to the voltage value of the termination voltage, the slope of the ramp signal is zero.

[0031] According to a second aspect of the present invention, a gamma correction circuit is provided, including:

[0032] The ramp generation circuit as described above, which provides a ramp signal; and

[0033] A processing unit that performs gamma correction on the display device according to the ramp signal.

[0034] The ramp signal generation circuit of the present application uses a first capacitor to be alternately connected to an initial voltage and a termination voltage, generating a ramp signal with a step change between the first capacitor and the second capacitor, taking into account the accuracy and stability of the ramp signal, and reducing the circuit design difficulty.

[0035] Furthermore, when the size ratio of the first capacitor and the second capacitor is fixed, the initial voltage and the termination voltage of the ramp signal can be flexibly set, and the unit step of the ramp signal can automatically adapt to the initial voltage and the termination voltage, that is, the slope of the ramp signal can be flexibly controlled.

[0036] In the ramp signal generation circuit of the present application, the unit step of the ramp signal is adaptive. When the capacitance values of the first capacitor and the second capacitor are fixed values and the voltage values of the initial voltage and the termination voltage are both determined values, the slope of the ramp signal can still be adjusted by controlling parameters such as the frequency of the clock signal. Therefore, it can be flexibly applied to various scenarios.

[0037] The gamma correction circuit of the present application has the advantage of an adaptive step. At a fixed clock frequency, each time gamma correction is performed, only the initial voltage and the ramp termination voltage need to be set. The ramp unit step automatically adjusts to different termination voltages, and a ramp signal with different slopes can be easily generated. The gamma curve correction can be efficiently completed without complex calculations and timing switching, which greatly improves the efficiency of chip mass production. Moreover, the circuit design has lower timing requirements, the circuit implementation is simpler, and the area and power consumption can be significantly saved. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Through the following description of the embodiments of the present invention with reference to the drawings, the above and other objects, features and advantages of the present invention will become clearer. In the drawings:

[0039] Figure 1 The circuit schematic diagram of the ramp signal generation circuit according to the embodiment of the present invention is shown;

[0040] Figure 2 The working timing diagram of the ramp signal generation circuit according to the embodiment of the present invention is shown;

[0041] Figure 3 The equivalent circuit diagram of the ramp signal generation circuit according to the embodiment of the present invention in the first stage is shown;

[0042] Figure 4 The equivalent circuit diagram of the ramp signal generation circuit according to the embodiment of the present invention in the second stage is shown;

[0043] Figure 5 The equivalent circuit diagram of the ramp signal generation circuit according to the embodiment of the present invention in the third stage is shown;

[0044] Figure 6 The waveform diagram of the ramp signal according to the embodiment of the present invention is shown. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0045] The present invention will be described in more detail below with reference to the accompanying drawings. In the respective drawings, like elements are denoted by like reference numerals. For the sake of clarity, the various parts in the drawings are not drawn to scale. In addition, some well-known parts may not be shown in the figures.

[0046] It should be understood that in the embodiments of the present application, the connection / coupling of A and B means that A and B can be connected in series or in parallel, or A and B are connected through other devices, and the embodiments of the present application do not limit this.

[0047] The term "unit step (ΔV)" used in the present application refers to the minimum step voltage amplitude of the ramp signal.

[0048] The main function of the ramp signal generation circuit is to generate a ramp signal, which can be used in circuits where the voltage needs to change linearly, and is usually used as a reference signal, a slope compensation signal, or for a scan voltage generation circuit, etc.

[0049] The ramp signal generation circuit provided by the present application can be applied to various systems, such as being applied to a display system, a communication system, a power transmission system, a detection system, etc. More specifically, for example, it is utilized in the gamma correction circuit of a display system. Among them, the display system is, for example but not limited to: a Light Emitting Diode (LED) display system, an Organic Light Emitting Diode (OLED) display system, a mini LED display system, a micro OLED display system, etc., a Liquid Crystal Display (LCD) display system, etc.

[0050] The ramp signal generation circuit provided by the present invention realizes the adaptive adjustment of the unit step of the ramp signal according to the initial voltage and the termination voltage of the ramp signal by configuring the ratio of the capacitors and the conduction state of the circuit, thereby reducing the circuit complexity while ensuring the accuracy of the ramp signal.

[0051] Next, embodiments of the ramp signal generation circuit and the gamma correction circuit provided by the present application will be described with reference to the accompanying drawings.

[0052] Figure 1 A circuit schematic diagram of the ramp signal generation circuit according to an embodiment of the present invention is shown. Based on an exemplary configuration method, Figure 2 A working timing diagram of the ramp signal generation circuit according to an embodiment of the present invention is shown. Figure 3 An equivalent circuit diagram of the ramp signal generation circuit according to an embodiment of the present invention in the first stage is shown. Figure 4 An equivalent circuit diagram of the ramp signal generation circuit according to an embodiment of the present invention in the second stage is shown. Figure 5The equivalent circuit diagram of the ramp signal generation circuit according to an embodiment of the present invention in the third stage is shown. Based on an exemplary configuration method, Figure 6 The waveform diagram of the ramp signal according to an embodiment of the present invention is shown.

[0053] As Figure 1 shown, the ramp signal generation circuit 100 includes: a first input terminal P1, a second input terminal P2, an initialization switch sw1, a first input switch sw3a, a second input switch sw3b, a first path switch sw2a, a second path switch sw2b, a first capacitor C1, a second capacitor C2, and an operational amplifier Opamp.

[0054] The first input terminal P1 receives an initial voltage Vstart, and the second input terminal P2 receives a termination voltage Vend. The first input terminal P1 is connected to the first end (i.e., the lower plate) of the first capacitor C1 via the first input switch sw3a, and the second input terminal P2 is connected to the first end of the first capacitor C1 via the second input switch sw3b.

[0055] The second end (i.e., the upper plate) of the first capacitor C1 and the second end (i.e., the upper plate) of the second capacitor C2 are connected to each other via the first path switch sw2a, and the first end (i.e., the lower plate) of the second capacitor C2 is grounded.

[0056] The second end of the first capacitor C1 and the second end of the second capacitor C2 are also connected to each other via the second path switch sw2b and a voltage follower. Specifically, the first input terminal P1 is connected to the non-inverting input terminal of the operational amplifier Opamp via the initialization switch sw1, the second end of the second capacitor C2 is connected to the non-inverting input terminal of the operational amplifier Opamp, the inverting input terminal of the operational amplifier Opamp is directly connected to its output terminal to form the voltage follower, and the output terminal of the operational amplifier Opamp is connected to the second end of the first capacitor C1 via the second path switch sw2b.

[0057] The second end of the second capacitor C2 serves as the output terminal P3 of the ramp signal generation circuit 100 to output a ramp signal Vramp.

[0058] Under the clock control of the ramp signal generation circuit 100, the initialization switch sw1, the first input switch sw3a, the second input switch sw3b, the first path switch sw2a, and the second path switch sw2b are respectively configured in different states, so that the lower plate (i.e., the first end) of the first capacitor C1 is alternately connected to the set initial voltage Vstart and the termination voltage Vend, and by using charge sharing, a step voltage is realized according to the size ratio of the first capacitor and the second capacitor, and a stepped ramp signal close to the full swing is generated.

[0059] The operation of the ramp signal generation circuit 100 can be divided into an initialization phase and a ramp signal generation phase. In the initialization phase, the lower plate of the first capacitor C1 and the upper plate of the second capacitor C2 are connected to the initial voltage Vstart of the ramp signal to be generated. In the ramp signal generation phase, the lower plate of the first capacitor C1 is alternately connected to the initial voltage Vstart and the termination voltage Vend of the ramp signal to be generated, so that the level of the upper plate of the second capacitor C2 changes stepwise from the initial voltage Vstart to the termination voltage Vend according to the proportional relationship between the capacitance value of the first capacitor C1 and the capacitance value of the second capacitor C2.

[0060] Specifically, the ramp signal generation phase includes a pre-charge phase and a step signal generation phase that are alternately performed. That is, after the initialization phase is completed, the initialization switch sw1 is turned off, and the first input switch sw3a, the second input switch sw3b, the first path switch sw2a, and the second path switch sw2b are controlled by a clock signal with a period of T and a duty cycle of 50%. Among them, when the first input switch sw3a and the second path switch sw2b are turned on, the second input switch sw3b and the first path switch sw2a are turned off; when the first input switch sw3a and the second path switch sw2b are turned off, the second input switch sw3b and the first path switch sw2a are turned on.

[0061] In the ramp signal generation phase, the time for each switch to maintain conduction / turn-off is T / 2. An exemplary clock signal for controlling the initialization switch sw1, the first input switch sw3a, the second input switch sw3b, the first path switch sw2a, and the second path switch sw2b can be referred to Figure 2 . It should be understood that the frequency and duty cycle of the clock signal can be freely set according to actual needs, so as to generate a ramp signal different from Figure 6 shown. The present application does not limit parameters such as the frequency and duty cycle of the clock signal. In the ramp signal generation circuit provided by the present invention, the duty cycle of the clock signal does not affect the generation of the ramp signal. Therefore, a clock signal with any duty cycle can be selected, thereby expanding the applicable range of the ramp signal generation circuit.

[0062] Optionally, a timing controller (not shown) is used to generate clock signals for respectively controlling the initialization switch, the first input switch, the second input switch, the first path switch, and the second path switch. Specifically, please refer to Figure 2, the timing controller is configured to generate a first clock sw1 that is valid during the initialization phase, a second clock sw2a / sw3b and a third clock sw2b / sw3a that are alternately valid during the precharge phase and the step signal generation phase, and send the first clock to the initialization switch, send the second clock sw2a / sw3b to the second input switch and the first path switch, and send the third clock sw2b / sw3a to the first input switch and the second path switch.

[0063] In some embodiments, the periods of the second clock and the third clock are T, and the duty cycle is 1 / 2.

[0064] In other embodiments, when the number and frequency of the second clock and the third clock are both fixed values, the slope of the ramp signal is adjusted by adjusting the initial voltage and / or the termination voltage; and / or when the initial voltage and the termination voltage are both fixed values, the slope of the ramp signal is adjusted by adjusting the frequency of the second clock and the third clock.

[0065] The following will be combined with the attached Figure 2-5 The specific working principle of the ramp signal generation circuit of the embodiment of the present application will be described in detail.

[0066] In the first stage t1, that is, the initialization stage: Figure 2 The shown clock signal controls the initialization switch sw1, the first input switch sw3a, and the second path switch sw2b to conduct, and the second input switch sw3b and the first path switch sw2a are turned off. The equivalent circuit diagram of the ramp signal generation circuit in the first stage is as Figure 3 shown. The initial voltage Vstart charges the ramp signal Vramp, the lower plate of the first capacitor C1, and the upper plate of the second capacitor C2 to the initial voltage Vstart. Driven by the operational amplifier Opamp, the output voltage of the operational amplifier Opamp and the upper plate of the first capacitor C1 are also initialized to the initial voltage Vstart.

[0067] In the second stage t2, that is, the precharge stage: Compared with the first stage, Figure 2 The shown clock signal turns off the initialization switch sw1. At this time, the clock signal controls the first input switch sw3a and the second path switch sw2b to conduct, and the second input switch sw3b, the first path switch sw2a, and the initialization switch sw1 are turned off. The equivalent circuit diagram of the ramp signal generation circuit in the second stage is as Figure 4 shown. The lower plate of the first capacitor C1 is still connected to the initial voltage Vstart, and the upper plate of the second capacitor C2 is in a holding state for a holding time of T / 2. At this time, the ramp signal is Vramp(n). According to the capacitance charge calculation formula Q = C*U, the charge Q1 on the first capacitor C1 C1= (Vramp(n) - Vstart) * C1, the charge Q1 on the second capacitor C2 C2 = Vramp(n) * C2, then the total charge on the first capacitor C1 and the second capacitor C2 is as shown in formula (1):

[0068] Q1 = Q1 C1 + Q1 C2 = (Vramp(n) - Vstart) * C1 + Vramp(n) * C2 (1)

[0069] In the third stage t3, that is, the step signal generation stage: Compared with the second stage, Figure 2 the clock signal shown controls the initialization switch sw1 to remain off. At this time, the clock signal controls the second input switch sw3b and the first path switch sw2a to conduct, and the first input switch sw3a, the second path switch sw2b, and the initialization switch sw1 are off. The equivalent circuit diagram of the ramp signal generation circuit in the second stage is as shown Figure 5 The lower plate of the first capacitor C1 is connected to the termination voltage Vend, and the upper plates of the first capacitor C1 and the second capacitor C2 are electrically connected, and the holding time is T / 2. At this time, the charge Q2 on the first capacitor C1 C1 = (Vramp(n + 1) - Vend) * C1, the charge Q2 on the second capacitor C2 C2 = Vramp(n + 1) * C2, then the total charge on the first capacitor C1 and the second capacitor C2 is as shown in formula (2):

[0070] Q2 = Q2 C1 + Q2 C2 = (Vramp(n + 1) - Vend) * C1 + Vramp(n + 1) * C2 (2)

[0071] In the fourth stage t4, that is, the complete ramp generation stage, Figure 2 the clock signal shown is configured to repeat the second and third stages N - 1 times with a fixed period T until the initialization switch sw1 conducts again, that is, enters the initialization stage again and starts to generate the next ramp signal.

[0072] A complete ramp signal is generated from the second stage to the fourth stage, and the voltage change of each step signal is as shown in formula (3):

[0073] ΔVramp = Vramp(n + 1) - Vramp(n) (3)

[0074] It is known that the law of conservation of charge is:

[0075] Q1 = Q2 (4)

[0076] Combined with formulas (1)-(4), the voltage change Δ of each step signal can be obtained That is, every time the pre-charge stage and the step signal generation stage are performed, the voltage value of the ramp signal changes

[0077] Therefore, the final voltage of the complete ramp signal is:

[0078]

[0079] If the capacitance value ratio of the first capacitor and the second capacitor is set to satisfy Then Vramp(end) = Vend, and the finally formed ramp signal is as shown in the ramp signal waveform diagram Figure 6 shown. The capacitance value ratio of the first capacitor and the second capacitor and the number of steps N have a specific ratio, which is 1:1 but not limited to 1:1. It should be understood that both the ratio of the first capacitor to the second capacitor and the number of step signals N of the ramp signal can be freely set according to actual needs, so as to generate a ramp signal different from Figure 6 shown. The present application does not limit the specific ratio of the first capacitor to the second capacitor and the number of step signals N of the ramp signal

[0080] The present application also provides a gamma correction circuit (not shown), including a ramp signal generation circuit and a processing unit as shown Figure 1 shown. The processing unit uses the ramp signal provided by the ramp signal generation circuit as the gamma voltage to perform gamma correction on the display device. The present application does not limit the specific circuit structure of the gamma correction circuit

[0081] The ramp signal generation circuit provided by the present application has the following advantages:

[0082] 1) For the ramp signal generation circuit of the present application, when the size ratio of the first capacitor and the second capacitor is fixed, the initial voltage Vstart and the termination voltage Vend of the ramp signal can be flexibly set. The unit step of the ramp signal can automatically adapt to the initial voltage Vstart and the termination voltage Vend, that is, the slope of the ramp signal can be flexibly controlled. In the traditional technology, when the size ratio of the first capacitor and the second capacitor is fixed, the unit step of the ramp signal is fixed, that is, the slope is fixed and cannot be changed. Therefore, the ramp signal generation circuit of this solution can be applied to circuits with different slope requirements, and the application range is wider

[0083] 2) The ramp signal generation circuit of the present application has an adaptive unit step of the ramp signal and can generate a ramp signal from the initial voltage Vstart to the termination voltage Vend without complex calculations. In the traditional technology, only the initial voltage Vstart and the number of steps of the ramp signal can be set. To achieve different termination voltages Vend, complex calculations need to be combined with the initial voltage Vstart and the unit step, and the number of step signals needs to be controlled to achieve it. In some applications, the number of step signals of the ramp signal is fixed, so only by increasing multiple sets of capacitors with different ratios can the step change be achieved. This undoubtedly increases the area and power consumption of the chip, improves the complexity of the chip, and is not conducive to the mass production of the chip.

[0084] 3) The ramp signal generation circuit of the present application can achieve a positive slope ramp signal, that is, a ramp signal that gradually increases with time, by controlling the initial voltage Vstart to be less than the termination voltage Vend, or can also control the initial voltage Vstart to be greater than the termination voltage Vend to achieve a negative slope ramp signal, that is, a ramp signal that gradually decreases with time. The traditional technical solution can only generate a positive slope ramp signal. Therefore, the ramp signal generated by the technical solution of the present invention has a more comprehensive function and a wider application range.

[0085] 4) The ramp signal generation circuit of the present application has an adaptive unit step of the ramp signal. When the capacitance values of the first capacitor and the second capacitor are fixed values, and the voltage values of the initial voltage Vstart and the termination voltage Vend are both determined values, the slope of the ramp signal can still be adjusted by controlling parameters such as the frequency and duty cycle of the clock signal. Therefore, it can be flexibly applied to various scenarios.

[0086] Some examples of the ramp signal generation circuit of the embodiments of the present invention are described above. However, the embodiments of the present invention are not limited to this, and there may be other ways of expansion and deformation.

[0087] For example, it should be understood that the reference ground potential in the foregoing embodiments can be replaced with other non-zero reference potentials (with positive or negative voltage amplitudes) or a controlled variable reference signal in alternative embodiments.

[0088] For another example, the capacitor provided in the embodiments of the present application can be a lumped parameter capacitor element, or additional identical or similar capacitor groups can be added, or other equivalent elements with functions similar to those of a capacitor. The equivalent structures described here include, but are not limited to, microstrip lines, varactor diodes, conductor structures with a certain pattern, etc., which can provide capacitive impedance. For still another example, the voltage follower provided in the embodiments of the present application can be composed of an operational amplifier or can be composed of components such as transistors.

[0089] For another example, the foregoing ramp signal generation circuit may be discrete devices or may be a circuit unit. In some other implementation manners, the foregoing ramp signal generation circuit may be encapsulated in a certain device.

[0090] Meanwhile, those of ordinary skill in the art can realize that, for the structures and methods of each example described in combination with the embodiments disclosed in this article, different configuration methods or adjustment methods can be used to implement the described functions for each structure or a reasonable deformation of the structure, but such implementation should not be considered to exceed the scope of this application. Moreover, it should be understood that the connection relationships between the various components of the amplifier in the foregoing figures in the embodiments of this application are illustrative examples and do not impose any limitations on the embodiments of this application.

[0091] It should be noted that in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the phrase "including an..." does not exclude the existence of additional identical elements in the process, method, article or device including the said element.

[0092] As described above in the embodiments according to the present invention, these embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and variations can be made according to the above description. The present specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can make good use of the present invention and its modifications based on the present invention. The present invention is only limited by the claims and their full scope and equivalents.

Claims

1. A ramp signal generation circuit, characterized in that, Comprising: A first capacitor, the first end of the first capacitor is connected to an initial voltage via a first input switch and to a termination voltage via a second input switch; A second capacitor, the first end of the second capacitor is grounded; And A first branch and a second branch connected in parallel between the second end of the first capacitor and the second end of the second capacitor, the first branch includes a first path switch, and the second branch includes a second path switch and a voltage follower connected in series, Wherein, in the pre-charging stage, the first input switch and the second path switch are turned on, the second input switch and the first path switch are turned off, and the initial voltage charges the first capacitor, In the step signal generation stage, the second input switch and the first path switch are turned on, the first input switch and the second path switch are turned off, and the termination voltage drives charge to flow between the first capacitor and the second capacitor, so that the voltage on the second end of the second capacitor undergoes a step change, The pre-charging stage and the step signal generation stage are alternately executed to generate a ramp signal with a step change from the initial voltage to the termination voltage on the second end of the second capacitor, The number of times of executing the pre-charging stage and the step signal generation stage is N times respectively, and the capacitance values of the first capacitor and the second capacitor satisfy: ， C1 is the capacitance value of the first capacitor, and C2 is the capacitance value of the second capacitor.

2. The ramp signal generation circuit according to claim 1, wherein, Further comprising: An initialization switch, the second end of the second capacitor is connected to the initial voltage via the initialization switch, In the initialization stage, the initialization switch, the first input switch and the second path switch are turned on, so as to initialize the voltages at various parts of the circuit.

3. The ramp signal generation circuit according to claim 2, wherein Further comprising: A timing controller for generating clock signals respectively controlling the initialization switch, the first input switch, the second input switch, the first path switch and the second path switch.

4. The ramp signal generation circuit according to claim 3, wherein The timing controller is configured to generate a first clock valid in the initialization stage, a second clock and a third clock alternately valid in the pre-charging stage and the step signal generation stage, and send the first clock to the initialization switch, send the second clock to the second input switch and the first path switch, and send the third clock to the first input switch and the second path switch.

5. The ramp signal generation circuit according to claim 4, wherein The periods of the second clock and the third clock are T, and the duty cycle is 1 / 2.

6. The ramp signal generation circuit according to claim 4, wherein, When the number and frequency of the second clock and the third clock are both fixed values, by adjusting the initial voltage and / or the termination voltage, the slope of the ramp signal is adjusted; and / or When the initial voltage and the termination voltage are fixed values, by adjusting the frequencies of the second clock and the third clock, the slope of the ramp signal is adjusted.

7. The ramp signal generation circuit according to claim 1, wherein Each time the pre-charging stage and the step signal generation stage are executed, the change amount of the voltage on the second end of the second capacitor is: ΔVramp = (Vstart - Vend) * , Wherein, ΔVramp is the change amount, Vstart is the voltage value of the initial voltage, Vend is the voltage value of the termination voltage, C1 is the capacitance value of the first capacitor, and C2 is the capacitance value of the second capacitor.

8. The ramp signal generation circuit according to claim 1, wherein when the voltage value of the initial voltage is greater than the voltage value of the termination voltage, the slope of the ramp signal is negative; when the voltage value of the initial voltage is less than the voltage value of the termination voltage, the slope of the ramp signal is positive; when the voltage value of the initial voltage is equal to the voltage value of the termination voltage, the slope of the ramp signal is zero.

9. A gamma correction circuit, characterized in that, Comprising: a ramp signal generation circuit according to any one of claims 1 to 8, providing a ramp signal; and a processing unit for performing gamma correction on the display device according to the ramp signal.

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