A memory having multiple memory planes and a method of operation thereof

Abstract

A memory having multiple memory planes and a method of operation thereof is disclosed. Each memory plane includes at least one corresponding memory array. The method includes, for each memory plane of a plurality of memory planes, generating (i) a corresponding plane ready (PRDY) signal indicative of a busy or ready state of the corresponding memory plane and (ii) a corresponding plane array ready (PARDY) signal indicative of a busy or ready state of a corresponding memory array of the corresponding memory plane, thereby generating a plurality of PRDY signals and a plurality of PARDY signals corresponding to the plurality of memory planes. Execution of a memory command for a memory plane of the plurality of memory planes is selectively allowed or denied based on a state of one or more of the plurality of PRDY signals and the plurality of PARDY signals.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to memory systems, and particularly to a memory having multiple memory planes supporting various types of memory operations and methods of operation thereof. BACKGROUND

[0002] In recent years, memory arrays, such as non-volatile memory arrays, have become increasingly dense and can store relatively large amounts of data. Typically, the memory (e.g., relatively high density memory) is divided into multiple physical segments, which can be referred to as memory planes. Thus, such memory has multiple memory planes. Data stored in different planes can or can not be related.

[0003] A challenge in such multi-plane memory is to provide overlapping access to different planes to a host. However, conventional memory operation command protocols typically prohibit issuing new embedded operation commands to non-operating planes, e.g., until a current embedded operation is completed or operating in the background in the operating plane. SUMMARY

[0004] The present disclosure provides a memory including multiple memory planes. In an example, each memory plane includes (i) at least one corresponding memory array and (ii) one or more peripheral circuits dedicated to read and write operations associated with the at least one corresponding memory array and the corresponding memory plane. The memory also includes an input / output (I / O) interface for receiving memory commands and data from a host and outputting data to the host. The memory further includes one or more storage units configured to store, for each memory plane of the multiple memory planes, (i) a corresponding plane ready (PRDY) signal indicative of a busy or ready status of the corresponding memory plane and (ii) a corresponding plane array ready (PARDY) signal indicative of a busy or ready status of a corresponding memory array of the corresponding memory plane, thereby storing a plurality of PRDY signals and a plurality of PARDY signals corresponding to the multiple memory planes.

[0005] The present disclosure also provides a method of operating a memory including a plurality of memory planes, each memory plane including at least one corresponding memory array and one or more peripheral circuits configured to support operation of the corresponding memory array and the corresponding memory plane. In an example, the method includes generating, for each memory plane of the plurality of memory planes, (i) a corresponding PRDY signal indicative of a busy or ready state of the corresponding memory plane and (ii) a corresponding PARDY signal indicative of a busy or ready state of the corresponding memory array of the corresponding memory plane, thereby generating a plurality of PRDY signals and a plurality of PARDY signals corresponding to the plurality of memory planes. Depending on the plane ready and array ready signals, acceptable memory commands to an array in a particular plane can be determined by a host. In an example, the method further includes selectively allowing or denying execution of a memory command of a memory plane of the plurality of memory planes based on a state of one or more of the plurality of PRDY signals and the plurality of PARDY signals.

[0006] The present disclosure also provides a method of operating a memory including a plurality of memory planes, each memory plane including (i) at least one corresponding memory array and (ii) one or more peripheral circuits dedicated to read and write operations associated with the at least one corresponding memory array and the corresponding memory plane. In an example, the method includes generating, for each memory plane of the plurality of memory planes, (i) a corresponding plane ready (PRDY) signal and (ii) a corresponding plane array ready (PARDY) signal; and executing, in the memory, (i) synchronous chip operation (SCO) memory commands that set a plurality of PARDY signals associated with the plurality of memory planes to indicate a busy state during a SCO background operation phase of execution of a SCO memory command and (ii) asynchronous independent plane operation (AIPO) memory commands that set at most one PARDY signal associated with a corresponding memory plane of the plurality of memory planes to a busy state during an AIPO background operation phase of execution of an AIPO memory command.

[0007] Other situations and advantages of the application will become apparent on review of the following drawings, detailed description, and appended claims. BRIEF DESCRIPTION OF DRAWINGS

[0008] Figure 1 A diagram of a memory system including a memory.

[0009] Figure 2A1 And Figure 2A2An example SCO operation is shown for accessing data from a memory array between two memory planes.

[0010] Figure 2B The example shows the SCO operation of type 1, and Figure 2C This illustrates the second type of SCO operation.

[0011] Figure 3A1 and Figure 3A2 An example AIPO operation is shown for accessing data from a memory array of two memory planes.

[0012] Figure 3B Example AIPO operation is shown.

[0013] Figure 3C1 The timing diagram is shown in relation to the "cache read end" command supported by a conventional memory system.

[0014] Figure 3C2 Shown with Figure 1 The timing diagram associated with the "Cache Read End Random" command supported by the memory system.

[0015] Figure 3D1 The timing diagram is shown in relation to the reset command supported by a conventional memory system.

[0016] Figure 3D2 A timing diagram is shown that is associated with a reset command supported by the memory system discussed in this invention.

[0017] Figure 4 Shown by Figure 1 Examples of background and foreground memory operations performed by the memory system.

[0018] Figure 5 Symbolically showing various memory planes and Figure 1 The memory plane ready state signal (PxRDY) and memory array ready state signal (PxARDY) of various memory arrays in the system's memory.

[0019] Figure 6A The diagram shows an example timing diagram of the plane ready signal and array ready signal in response to the received AIPO command.

[0020] Figure 6B The diagram shows an example timing diagram of the plane ready signal and array ready signal in response to the received AIPO command.

[0021] Figure 7 The diagram shows an example timing diagram of the plane ready signal and array ready signal in response to the received SCO command.

[0022] Figure 8A An example timing diagram depicting the issuance of an AIPO memory command to a non-operational plane while another operational plane has a background operation in progress is shown, where Figure 8A The AIPO memory command of

[0023] Figure 8B Another example timing diagram depicting the issuance of an AIPO memory command to a non-operational plane while another plane has a background operation in progress is shown, where Figure 8B The AIPO memory command of

[0024] Figure 9A and Figure 9B An example timing diagram depicting the issuance of an AIPO memory command to a plane that has a background array operation in progress is shown.

[0025] Figure 10 A timing diagram depicting the issuance of a SCO memory command and the resulting SCO background operation is shown.

[0026] Figure 11 An example timing diagram depicting an ongoing SCO background array operation as well as the issuance of an AIPO command and the issuance of a SCO command is shown.

[0027] Figure 11A1 and Figure 11A2 Various steps associated with a cache read operation are shown.

[0028] Figure 11B and Figure 11C1 , Figure 11C2 A timing diagram and various steps associated with a cache program operation are shown.

[0029] Figure 11D A table outlining the use of PxRDY and PxARDY for various memory operations is shown.

[0030] Figure 12A Bits of a read plane busy status (RPBS) register for a four-plane memory are shown.

[0031] Figure 12B The issuance of an RPBS command and the RPBS output containing the contents of the corresponding status register SR are shown.

[0032] Figure 13A Bits of a read status enhanced (RSE) command register for a particular memory plane are shown.

[0033] Figure 13BIssuing of RSE signals and RSE command waveforms are shown.

[0034] Figure 14A Circuits for generating a plane ready notice (PRN or PRN#) pin for a memory of Figure 1

[0035] Figure 14B Various alternative configurations of the circuit of Figure 14A

[0036] Figure 15 Timing diagrams depicting the generation of the PRN# signal of Figure 14A

[0037] Figure 16 Configurations of reset plane commands (e.g., periodic type) are shown.

[0038] Figure 17A and Figure 17B Timing diagrams depicting scenarios in which AIPO memory commands are issued to a memory plane that does not have a background operation in progress, while one or more other memory planes can have an AIPO background array operation in progress are shown.

[0039] Figure 18A and Figure 18B Timing diagrams depicting various example scenarios for issuing AIPO commands are shown.

[0040] Figure 19A Timing diagrams depicting examples of SCO commands are shown.

[0041] Figure 19B Another timing diagram depicting examples of SCO commands is shown.

[0042] Figure 20 Timing diagrams depicting other examples of SCO commands are shown, and also show that some AIPO memory commands can not be issued while a plane is performing a SCO background array operation.

[0043] Figure 21A and Figure 21B Timing diagrams describing other examples of SCO commands are shown, and also describe that some AIPO memory commands can be issued and performed simultaneously with a plane performing a SCO background array operation.

[0044] Figures 22A to 22H Example timing diagrams of plane ready signals PxRDY of planes P0 through P3 in response to receiving commands of different categories and array ready signals PxARDY of planes P0 through P3 are shown.

[0045] Figure 23 ​​​An example is shown where a second SCO command is issued during the operation of the first SCO command.

[0046] Figure 24 This example shows an AIPO command that can issue a temporary suspension of the operation of a previous SCO command.

[0047] Explanation of reference numerals in the attached figures

[0048] 0, 1, 2, 3, 4, 5, 6, 7: bits

[0049] 102a, 102b, 102c, 102d, ..., 102N: Memory planes

[0050] 10h, 15h: Command codes

[0051] 100: Memory System

[0052] 101: Memory

[0053] 104a, 104b, 104d, 104N: Memory arrays

[0054] 108a, 108b, 108N: Page buffer

[0055] 110a, 110b, ..., 110N: Word line selection circuit

[0056] 112a, 112b, ..., 112N: Cache

[0057] 116, 118: Input / output interfaces

[0058] 119: Communication Link

[0059] 120: Control Circuit

[0060] 130: Host

[0061] 140: Status Register

[0062] 142: Hardware pin

[0063] 404a: Background Array Operation

[0064] 404b: Background Operations

[0065] 408: Foreground Memory Operations

[0066] 604a, 604b, 804, 904, 1104a, 1704a, 1804a, 1804b, 1804c, 1904a, 1904d, 2004b, 2104b: AIPO Order

[0067] 704a, 704b, 1004, 1104b, 1704b, 1904b, 1904c, 2004a, 2004c, 2104a: SCO command

[0068] 1190: table

[0069] 1400: circuit

[0070] 1401a, 1401b, 1401c, 1401d: PRN circuit module

[0071] 1402a: PRN register

[0072] 1406a: AND gate

[0073] 1426: OR gate

[0074] 1427: PRN

[0075] 1428: transistor

[0076] 1429: PRN# signal

[0077] 1430: PRN# plate

[0078] 1480, 1481, 1482, 1483: configuration

[0079] 1500, 1700a, 1700b, 1800a, 1800b, 1900a, 1900b, 2000, 2100a, 2100b: timing diagram

[0080] 1502: memory command

[0081] A, B: data

[0082] P0,..., P3: plane

[0083] PaARDY, PbARDY, PcARDY, PdARDY, PxARDY: array ready signal

[0084] PaPRN, PbPRN, PcPRN, PdPRN: plane PRN signal

[0085] PaRDY, PbRDY, PcRDY, PdRDY, PxRDY: plane ready signal

[0086] PNARDY: memory array ready status signal

[0087] PNRDY: memory plane ready status signal

[0088] R1,..., R3: column address

[0089] SR: status register

[0090] t0, t1, t2, t3, t4, t2B1, t2B2, t2B3, t2C1, t2C2, t2C3, t601a, t602a, t603a, t601b,..., t604b, t702,..., t706, t708, t802a, t803a, t902a, t903a, t902b, t1001, t1002, t1003, t1104, t1702a, t1702b, t1703a, t1801a, t1802a, t1803a, t184a, t1805a, t1806a, t1807a, t1901a, t1902a, t1903a, t1904a, t1905a, t1905a1, t1906a, t1907a, t2001, t2002, t2003, t2004, t2101a, t2102a, t2103a, t2104a, t2106a: time

[0091] tWHR: time period DETAILED DESCRIPTION

[0092] A detailed description of embodiments of the application is provided with reference to the drawings.

[0093] Memory architecture

[0094] Figure 1 For a schematic diagram of a memory system 100 comprising a memory 101 including a plurality of memory planes 102a, memory plane 102b,..., memory plane 102N, wherein the memory 101 supports (i) Asynchronous Independent Plane Operation (AIPO) (also referred to as Overlapping Independent Plane Operation) and (ii) Synchronous Chip Operation (SCO) (also referred to as Parallel Multi-Plane Operation in the present disclosure). It is noted that these memory operations are discussed later in the present disclosure with respect to other figures of the present disclosure.

[0095] Elements mentioned in the present disclosure having a common reference sign followed by a number or letter can be referred to collectively by the reference sign alone. For example, the memory planes 102a, memory plane 102b,..., memory plane 102N can be referred to collectively in plural form and generally as memory planes 102 (or collectively as memory planes 102(a-N)) and in singular form and generally as memory plane 102.

[0096] In one example, memory 101 resides within a single integrated circuit (IC) chip. The IC chip for memory 101 may differ from another IC chip that includes host 130. In another embodiment, host 103 and memory 101 reside on the same single IC chip.

[0097] As shown, the memory 101 is physically and / or logically divided into memory planes 102a, ..., 102N, where N is a suitable positive integer, such as 2, 3, 4, or higher. Memory plane 102 is also simply referred to as a "plane" in this invention. It should be noted that some of the examples discussed in this invention are later assumed to include four memory planes—memory plane 102a, memory plane 102b, memory plane 102c, and memory plane 102d. However, as discussed, memory 101 may include any other suitable number of memory planes, such as 2, 3, 5, or higher.

[0098] Memory 101 may be of any suitable type, such as, for example, non-volatile NAND memory, non-volatile NOR memory, or the like. In an example, memory 101 is a three-dimensional (3D) memory comprising vertically stacked memory cells in individual planes. As an example, memory 101 may be NAND flash memory.

[0099] Each memory plane 102 includes (i) a corresponding memory array 104 and (ii) corresponding peripheral circuitry, wherein the corresponding memory array 104 includes a plurality of corresponding memory cells configured to store data, and the corresponding peripheral circuitry is dedicated to memory operations of the memory plane. For example, memory plane 102a includes memory array 104a, memory plane 102b includes memory array 104b, memory plane 102N includes memory array 104N, and so on. For example, the memory cells of individual memory arrays 104 may be configured, for example, in a NAND configuration or a NOR configuration (or another suitable configuration) based on the type of memory 101.

[0100] For each memory plane 102, memory 101 further includes peripheral circuitry dedicated to memory operations of the memory plane, such as a corresponding page buffer 108 and a corresponding cache 112. For example, memory plane 102a has a corresponding page buffer 108a and a corresponding cache 112a; memory plane 102b has a corresponding page buffer 108b and a corresponding cache 112b, and so on.

[0101] In the example, and as Figure 1As shown in FIG. 1, page buffers 108 include sensing circuitry and associated data buffers for storing write and / or read data, and thus, the sensing circuitry and data buffers are combined in page buffers 108. However, in another example and although not shown in FIG. 1, the sensing circuitry and data buffers can be separate components. Figure 1

[0102] The page buffers 108 of memory planes 102 include a plurality of corresponding sense amplifiers and data buffers. During a memory read operation, the page buffers 108 of a memory plane 102 read data from the corresponding memory array 104 of the memory plane 102 and write the data to the corresponding data buffer of the page buffer 108. The data from the data buffer of the page buffer 108 is then written to the corresponding cache 112. Thus, for example, during a read operation, an entire page of data is read from the memory array 104 to the corresponding page buffer 108 and then from the page buffer 108 to the corresponding cache 112. Similarly, during a write operation, data (e.g., an entire page of data) is written from the corresponding cache 112 to the corresponding page buffer 108 and then from the page buffer 108 to the corresponding memory array 104 of the corresponding memory plane 102.

[0103] The memory 101 also includes word line selection circuitry 110a, word line selection circuitry 110b, word line selection circuitry 110N for selecting word lines during read and / or write operations. In an example, individual memory planes can have corresponding separate and dedicated word line selection circuitry (e.g., memory plane 102a including word line selection circuitry 110a, memory plane 102b including word line selection circuitry 110b, and so on). In other examples and contrary to the description of FIG. 1, some or all of the memory planes 102a, 102b, 102N can share the same word line selection circuitry 110. Figure 1

[0104] The memory 101 further includes one or more status registers 140, e.g., to store values of one or more status signals for each plane (plane x, x can be from 0 to N-1 for a memory having N planes), such as plane ready (PxRDY), plane array ready (PxARDY), and so on, as will be discussed later in this disclosure.

[0105] The memory 101 further includes one or more hardware pins 142 that specifically output a status of one or more signals. One example of this hardware pin 142 is discussed with respect to Figure 14A (e.g., Figure 14A the output PRN# 1430 of the tablet 1430 of FIG. 1 3).

[0106] ​​The memory 101 further includes an input / output (I / O) interface 116 coupled to caches 112a, ..., caches 112N. Each cache 112 receives data from the I / O interface 116 and writes the data to the corresponding page buffer 108, and receives data from the corresponding page buffer 108 and writes the data to the I / O interface 116.

[0107] In this example, host 130 generates memory commands and transmits them to memory 101, stores data sent to memory 101, and receives data from memory 101. In this example, host 130 also receives one or more status signals (e.g., PxRDY, PxARDY, etc.) from memory 130 (e.g., from a status register), as will be discussed later in this invention. In this example, host 130 may also be connected to hardware pin 142. For example, the host may be a memory controller implementing a flash translation layer.

[0108] In this example, memory 101 communicates with host 130, for example, via communication link 119. Communication link 119 can be any suitable communication link, such as a link on a wired connection. Host 130 includes an I / O interface 118, which is coupled to I / O interface 116 of memory 101 via communication link 119. Thus, host 130 stores data destined for and reads data from the memory array of the memory plane via I / O interface 118, communication link 119, I / O interface 116, corresponding cache 112, and corresponding page buffer 108 associated with the memory plane.

[0109] In an embodiment, memory 101 also includes control circuitry 120 that controls various aspects of the operation of memory 101. In an embodiment, control circuitry 120 issues various memory state commands, as will be discussed subsequently throughout this invention. Memory 101 has many other components, which are not listed here for illustrative purposes and to avoid obscuring the teachings of this disclosure. Figure 1 As shown in the image.

[0110] The memory described in this invention can be configured to perform operations that engage multiple memory planes of the memory during at least a portion of the execution, examples of which include synchronous chip operation (SCO) as described in this invention; and can be configured to perform operations that engage an owner of one memory plane rather than multiple memory planes during at least a portion of the execution, examples of which include asynchronous independent plane operation (AIPO) as described in this invention.

[0111] Synchronous chip operation (SCO) or parallel multiplane operation

[0112] Figure 2A1 and Figure 2A2Example synchronous chip operations (SCOs) are shown for accessing data from memory arrays 104b, 104d of two example memory planes 102b, 102d, respectively. In examples, SCO operations are not limited to a particular memory plane or memory array, and can engage multiple (such as all) memory planes and / or memory arrays.

[0113] In Figure 2A1 and Figure 2A2 In an example, four memory planes 102a,..., 102d (Pa to Pd) are assumed to exist in the memory 101, where the memory array 104b of the memory plane 102b stores data A, and the memory array 104d of the memory plane 102d stores data B. Data A and data B can be any suitable type of data.

[0114] From time to, data A is being accessed from the memory plane 102b. At time ti, a request is issued to access data B from the memory plane 102d. However, Figure 2A1 and Figure 2A2 SCO operations performed in one memory plane depend on the state of other memory planes, for example, due to one or more shared resources in the memory 101. For example, if an SCO is being performed in one memory plane, operations on one or more other planes cannot be performed. Some SCO operations in all selected planes within the memory chip start or operate simultaneously in the sense that they are performed during the same time interval (e.g., parallel operations), and the operations can not be the same for all selected planes. After an SCO command is issued, the memory chip becomes busy and cannot accept new embedded operation commands during the busy period. Depending on the command, the memory chip will return to the ready state after the current embedded operation is completed or the cache is ready for data input / output for all planes. Only when the chip is ready after completing the SCO (i.e., all planes are ready) or the cache is ready in the case of a cached SCO, can the host 130 issue a new embedded operation command that can be performed by the memory chip. To determine whether to issue a command that invokes an SCO, the host 130 needs to check the chip busy status PRDY and the chip busy status PARDY for the operation. Because SCOs engage multiple planes in parallel, SCOs are also referred to as parallel multi-plane operations.

[0115] Thus, although data B is requested at time ti, the request cannot be performed immediately, for example, because an SCO (e.g., accessing data A) is currently being performed in the memory plane 102b. Once accessing data A from the memory plane 102b is completed at time t2, accessing data B from the memory plane 102d starts at time t2.

[0116] Figure 2B An example first type of SCO is shown, and Figure 2C An example second type of SCO is shown. In the example, the SCO operations of each plane start at the same time, i.e., are synchronous.

[0117] For example, in the Type 1 SCO shown in Figure 2B , only the same type of operation is allowed in the various memory planes. For example, memory plane 0, memory plane 1, memory plane 2, and memory plane 3 perform corresponding Triple Level Cell (TLC) read operations. Thus, in the example Type 1 SCO of Figure 2B , memory plane 0 cannot perform a TLC read in parallel with another memory plane 1 to perform a Single Level Cell (SLC) read operation. Moreover, the SCO operations of each plane start at the same time, i.e., are synchronous. For example, the TLC read operations of plane 0, plane 1, and plane 3 start at time t2B1, the TLC read operations of plane 0 and plane 2 start at time t2B2, and the TLC read operation of plane 0 starts at time t2B3.

[0118] In contrast, in the Type 2 SCO shown in Figure 2C , different types of operations are allowed in different memory planes. For example, example memory plane 0, example memory plane 1, example memory plane 2, and example memory plane 3 perform both TLC read operations and SLC read operations. Moreover, the SCO operations of each plane start at the same time, i.e., are synchronous. For example, the TLC / SLC read operations of plane 0, plane 1, and plane 3 start at time t2C1, the TLC / SLC read operations of plane 0 and plane 2 start at time t2C2, and the SLC read operation of plane 0 starts at time t2C3.

[0119] Asynchronous independent plane operations (AIPO) or overlapping independent plane operations

[0120] Figure 3A1 and Figure 3A2 An example asynchronous independent plane operation (AIPO) is shown for accessing data from memory array 104b, memory array 104d of two example memory planes 102b, 102d, respectively. Similar to Figure 2A1 and Figure 2A2 , in Figure 3A1 and Figure 3A2In the example of FIG. 1, assume that four memory planes 102a,..., 102d exist in the memory 101, where the memory array 104b of the memory plane 102b stores data A, and the memory array 104d of the memory plane 102d stores data B. Data A and data B can be any suitable type of data.

[0121] From time to, a data A is being accessed from the memory plane 102b. At time ti, a request is issued to access data B from the memory array 104d of the memory plane 102d. Figure 3A1 and Figure 3A2 Asynchronous independent plane operations (AIPOs) (also referred to in the present disclosure as "overlapping independent plane operations" operations) are shown that can be performed in one memory plane independent of or without affecting the state of other memory planes. In AIPOs, each plane can start any operation at any time, as long as the selected plane is ready for the embedded operation command. Thus, AIPOs can be performed in a plane regardless of the state of other planes. That is, the host 130 can issue an embedded operation command to a particular memory plane that can be executed by the memory, as long as the particular plane is ready (and regardless of the ready state of other planes). For AIPOs, the host 130 can treat each plane as an independent memory unit, and the host 130 checks the plane busy status PRDY and the plane busy status PARDY for progress of operations in each plane. For example, if an AIPO operation is being performed in one memory plane, another AIPO operation on another memory plane can be performed in an overlapping manner. Thus, AIPO memory operations allow operations to be performed in more than one memory plane in an overlapping or at least partially simultaneous manner.

[0122] Thus, when data B is requested at time ti, the request is immediately performed, e.g., because an AIPO (e.g., accessing data A) is currently being performed in the memory plane 102b. Thus, as shown in FIG. 1, data B is accessed from the memory plane 102d starting at time ti. Thus, the host 130 can access a non-busy plane (e.g., plane 102d) for new data while another memory operation is still being performed in another busy plane (e.g., plane 102b). Figure 3A1 and Figure 3A2 Thus, as shown in FIG. 1, data B is accessed from the memory plane 102d starting at time ti. Thus, the host 130 can access a non-busy plane (e.g., plane 102d) for new data while another memory operation is still being performed in another busy plane (e.g., plane 102b).

[0123] Figure 3B Example AIPO operations are shown. In the example, AIPO operations of different planes can start at different times. For example, TLC read and SLC read operations of different planes start at different times, i.e., the AIPO operations are asynchronous in nature.

[0124] Memory-embedded protocol supporting both SCO and AIPO operations

[0125] As will be discussed in further detail herein, in embodiments, the memory system 100 supports both SCO operations and AIPO operations.

[0126] Background and foreground memory operations

[0127] Figure 4 Example background memory operations and foreground memory operations performed by the memory system 100 of Figure 1 are shown.

[0128] Background memory operations are those memory operations performed on the memory system by a controller (e.g., within the control circuitry 120), such as a state machine, which can provide address and control signals for access to the memory array. In background memory operations, the I / O interface 118 is available to the host 130 for other concurrent operations. For example, background memory operations are performed internally within the memory 101.

[0129] Figure 4 Some example background memory operations (also referred to simply as background operations) are shown. For example, a data transfer between a memory array (e.g., the memory array 104N in the example of Figure 4 ) and a corresponding page buffer (e.g., the page buffer 108N in the example of Figure 4 ) can be performed on the memory system by the controller and does not involve the host 130, and is an example of a background array operation 404a. In the background array operation 404a, data can be transferred from the memory array 104N to the page buffer 108N and / or from the page buffer 108N to the memory array 104N. It should be noted that in some embodiments, a “background operation” can be indicated by the case when PxARDY = 0, and PxRDY can be 1 or 0, and a “background array operation” can indicate PxRDY = 1 and PxARDY = 0.

[0130] Another example of a background operation 404b is a data transfer between a page buffer (e.g., the page buffer 108N) and a corresponding cache (e.g., the cache 112N), such that the data transfer does not involve the host 130. In the background operation 404b, data can be transferred from the cache 112N to the page buffer 108N and / or from the page buffer 108N to the cache 112N.

[0131] As will be discussed later herein (e.g., with respect to Figure 6A , Figure 6B , Figure 7and Figure 8), when a background operation is in progress in a plane, the memory array ready signal (PxARDY) for the particular plane is in a busy state, indicating that the corresponding memory array for the plane is busy.

[0132] In contrast to background memory operations, foreground memory operations can directly involve the host 130 utilizing the I / O interface 118 for one or more of command, address, and data communication. For example, the host 130 including the I / O interface 118 communicates with the cache 112a,..., cache 112N of the memory 101 during a foreground memory operation. Figure 4 An example foreground memory operation 408 is shown, in which data is transferred between the host 130 (e.g., I / O interface 118) and a cache (e.g., cache 112N). For example, during the foreground memory operation 408, data can be transferred from the cache 112N to the host 130 and / or from the host 130 to the cache 112N.

[0133] Memory commands including both foreground operations and background operations

[0134] A memory command can be executed by performing a number of memory operations, such as one or more foreground memory operations and / or one or more background memory operations. Thus, to execute a memory command, a number of corresponding foreground memory operations and / or background memory operations must be performed.

[0135] For example, a read command involves the following memory operations: (i) reading data from a memory array and writing the data to a corresponding page buffer, (ii) reading the data from the corresponding page buffer to a corresponding cache, and (iii) reading the data from the corresponding cache to the host 130. Note that transferring data from the memory array to the page buffer and from the page buffer to the cache are examples of background memory operations; while transferring data from the cache to the host 130 is an example of a foreground memory operation. Thus, the example read command discussed above includes both background memory operations and foreground memory operations.

[0136] Background memory operations are performed while a memory command is being executed

[0137] In embodiments, when a memory command is being executed for a particular memory plane, one or more other memory operations can be performed for one or more other memory planes in an overlapped manner. For example, when a cache read operation is in progress for one memory plane (e.g., memory plane 102N), background memory operations (e.g., transferring data between the memory array 104a and the page buffer 108a) can also be performed in an overlapped manner.

[0138] However, not every memory command can allow overlapping execution of background memory operations when a memory command is being executed. For example, a "block erase" memory command erases data from one or more blocks of one or more memory arrays of one or more memory planes. In an example, due to the design of the circuitry within the memory 101, no other background memory operations can be executed while a block erase memory command is being executed, as discussed later in the disclosure.

[0139] Conventional memory operations

[0140] Table 1 below in the disclosure shows various example SCO commands that can be executed using a conventional command protocol. Commands labeled "not supported" can be supported using the techniques described in the disclosure.

[0141] Table 1

[0142]

[0143] Based on the discussion regarding Table 2, the various entries of Table 1 will be apparent to one of ordinary skill in the art.

[0144] Classes of memory commands and memory operations

[0145] Table 2 below in the disclosure shows various example memory commands that can be implemented by the memory system 100 discussed throughout the disclosure, as well as their corresponding types and classes. Commands labeled "not supported" can not be needed in a memory that utilizes the techniques described in the disclosure. In some embodiments, such commands labeled "not supported" in Table 2 can also be supported.

[0146] Table 2

[0147]

[0148] The first row of Table 2 lists the sequence number corresponding to various memory commands. The second row of Table 2 lists the memory command. The third row of Table 2 indicates whether the memory command is an AIPO or an SCO. For example, a "set feature" memory command (e.g., which can be used to set a feature of one or more configurable elements of the memory 101) is an SCO memory command, such as a set feature write to a register file that is common to multiple planes. In another example, a "cache read random" memory command (e.g., which can be used to read data from a cache) is an AIPO memory command.

[0149] The fourth row of Table 2 indicates whether the memory command allows execution of overlapping or at least partially concurrent cache operations. For example, a Set Features command is an SCO memory command, e.g., when a Set Features command is being executed, the SCO memory command does not allow any cache operations to be executed in an overlapping manner. In other words, when a cache operation is being executed, a Set Features command cannot be executed in an overlapping manner with a cache operation in any plane.

[0150] In another example, a Cache Read Random is an AIPO memory command, e.g., when a Cache Read Random command is being executed, the AIPO memory command allows cache operations (in another memory plane) to be executed in an overlapping manner.

[0151] The fifth row of Table 2 classifies each memory command as a corresponding one of five possible categories. The last column of Table 2 identifies the possible categories. For example, Category 1 refers to an SCO memory command that does not allow any overlapping cache operations, Category 2 refers to an SCO memory command that allows overlapping cache operations, Category 3 refers to a system management command, Category 4 refers to an AIPO memory command that does not allow overlapping cache operations, and Category 5 refers to an AIPO memory command that allows overlapping cache operations.

[0152] It should be noted that Table 1 above in the disclosure is for a system that supports only SCO commands, while Table 2 above in the disclosure is for a memory system discussed in the disclosure that supports both SCO commands and AIPO commands.

[0153] It should be noted that the operations associated with SCO commands in the memory system 100 discussed in the disclosure are the same as the SCO commands of the conventional system discussed with respect to Table 1.

[0154] In an example, some AIPO commands come from existing SCO commands. The host 130 expects the same or similar operational scheme for AIPO commands, and in this way, the host 130 can make only minor adjustments with respect to SCO to take AIPO. AIPO commands are single-plane operation commands.

[0155] It can be noted that, as discussed in the disclosure, AIPO does not need to support multi-plane operations, e.g., because the host 130 treats each plane as an independent unit of operation when executing an AIPO command. For example, an AIPO command is issued to one selected plane, and the other planes are referred to as unselected from the perspective of the AIPO command. In contrast, an SCO command engages all planes of the memory 101.

[0156] The operation of the selected plane (i.e., the plane to which the AIPO command is issued) for an AIPO command can be the same as a conventional SCO operation.

[0157] For unselected planes (i.e., planes to which an AIPO command is not issued, and to which a different AIPO command is issued), the AIPO command can be implemented in a greater than one type of way. For example, during a first type of AIPO command, the unselected plane is in a ready state after the AIPO command is issued (e.g., see Figure 6B ). During a second type of AIPO command, the unselected plane is busy only for a short period of time after the AIPO command is issued, which can be used for command processing (e.g., see Figure 6A ). These two types of AIPO command behavior for unselected planes are discussed in further detail with respect to Figure 6A , Figure 6B and elsewhere in this disclosure.

[0158] Some SCO commands (e.g., cache read sequence commands, cache read end commands, etc.) do not include a column address, and thus, cannot be used as AIPO commands. These commands are indicated by "not supported" in Table 2.

[0159] It can be noted that whether a memory command is an AIPO memory command or a SCO memory command is based on the command type and the selection of the circuit design for the memory 101. For example, program commands (e.g., page program and / or cache program) and / or erase commands (e.g., block erase and / or multi-plane block erase) are classified as SCO in Table 2 for a particular circuit design implementation of the memory 101. However, for another circuit design implementation of the memory 101, one or more of the commands can be AIPO memory commands. Thus, the characteristics and classification of the various commands shown in Table 2 are examples only, and are specific to an implementation. For example, the characteristics and classification of the various commands shown in Table 2 can change for a different implementation or design selection of the circuit of the memory 101.

[0160] Figure 3C1 A timing diagram associated with a "cache read end" command supported by a conventional memory system is shown, and Figure 3C2A timing diagram associated with the "cache read end random" command supported by the memory system 100 discussed in this disclosure is shown. For example, as seen in Table 1, the "cache read end" command is supported by a conventional memory system, but the "cache read end random" command is not supported by a conventional memory system. However, as seen in Table 2, the memory system 100 disclosed in this disclosure supports the "cache read end random" command, but does not support the "cache read end" command. For example, the "cache read end random" command in the memory system 100 can replace the "cache read end" command of a conventional memory system. For example, as discussed above, if the original SCO command does not support column address selection, then the new AIPO command, such as cache read end random, can replace the original SCO command, such as cache read end.

[0161] Figure 3D1 A timing diagram associated with the reset command supported by a conventional memory system in which the operation of all planes is terminated is shown; and Figure 3D2 A timing diagram associated with the reset command supported by the memory system 100 in which only the ongoing operation of the selected plane is terminated is shown. For example, Figure 3D2 The reset command has the address of the plane to be reset, and thus, only the selected plane is reset (e.g., instead of resetting all planes as done in Figure 3D2 The reset command of the conventional memory system).

[0162] Memory plane ready status signals (PxRDY) and memory array ready status signals (PxARDY)

[0163] In an embodiment, various planes of the memory 101 (or the control circuit 120) issue various status signals, for example, to indicate whether the corresponding memory plane 102 or the corresponding memory array 104 is ready to perform a new memory operation or is busy performing a current memory operation and cannot accept a new memory operation.

[0164] For example, one such ready signal is a memory plane ready status signal (PxRDY) issued for various memory planes Px, where "x" in Px is the index of the corresponding memory plane. For example, for the memory plane 102a, the memory plane ready status signal is PaRDY; for the memory plane 102b, the memory plane ready status signal is PbRDY; for the memory plane 102N, the memory plane ready status signal is PNRDY, and so on. In general, the signal PxRDY indicates whether the memory plane 102x is in a busy state or a ready state, as will be discussed in further detail later in this disclosure.

[0165] Another such ready signal is a memory array ready status signal (PxARDY) issued for each memory array, where "x" in PxARDY is an index of the corresponding memory array for the corresponding memory plane. For example, for memory plane 102a, the memory array ready status signal is PaARDY; for memory plane 102b, the memory array ready status signal is PbARDY; for memory plane 102N, the memory array ready status signal is PNARDY, and so on. In general, signal PxARDY indicates whether the memory array 104x of memory plane 102x is in a busy state or a ready state.

[0166] Whether a particular memory plane can receive and execute a new memory command at any given time is based on the PxRDY and / or PxARDY of the particular memory plane as well as the PxRDY and / or PxARDY of various other memory planes.

[0167] Figure 5 The memory plane ready status signals (PxRDY) and the memory array ready status signals (PxARDY) of the various memory planes 102 and the various memory arrays 104 of memory 101 of system 100 are symbolically shown. As shown, each memory plane / memory array has a corresponding PxRDY signal and a PxARDY signal. It is noted that in an example, control circuit 120 or another suitable component of memory plane 102 or memory 101 issues the PxRDY signal and the PxARDY signal for the memory plane 102.

[0168] The memory plane ready status signals (PxRDY) are also referred to simply as plane ready signals, and the memory array ready status signals (PxARDY) are also referred to simply as array ready signals.

[0169] In an example, the PxRDY bits and the RxARDY bits are stored in the status register 140 of Figure 1 .

[0170] In general, if a background operation in memory plane 102x is currently being executed (where the background operation has been previously discussed in this disclosure, for example, with respect to Figure 4 the PxARDY (i.e., the array ready status signal) is in a busy state, which is indicated by PxARDY being, for example, 0. This is because the background operation in memory plane 102x implies that the corresponding memory array 104x is engaged in the background operation. Otherwise, if the memory plane 102x that includes memory array 104x is not conducting any operation (e.g., any background operation), the corresponding PxARDY (i.e., the array busy status signal) is in a ready state, which is indicated by PxARDY being, for example, 1.

[0171] Thus, for memory plane 102x:

[0172] PxARDY = 0 indicates that the memory array 104x of the memory plane 102x is busy; and

[0173] PxARDY = 1 indicates that the memory array 104x of the memory plane 102x is ready.

[0174] For memory plane 102x:

[0175] PxRDY = 0 indicates that the memory plane 102x is busy and cannot accept new commands; and

[0176] PxRDY = 1 indicates that the memory plane 102x is ready and can accept new commands.

[0177] PxARDY is 1 if no background operation is in progress in the memory array 104x of the memory plane 102x. In an example, when PxARDY is 1, the plane ready signal PxRDY can also be 1, i.e., PxRDY = PxARDY.

[0178] When no background operation is in progress (i.e., PxRDY = PxARDY = ready for the particular plane), an AIPO command can be issued to the particular plane.

[0179] When no background operation is in progress in the particular plane (i.e., PxRDY = PxARDY = 1 or ready for the particular plane), the host 130 can issue an AIPO command to a non-busy particular plane that can execute. That is, when PxRDY = PxARDY = 1, the host 130 can issue an AIPO command to the memory plane 102x, and the AIPO command can be accepted by the memory plane 102x.

[0180] After an AIPO command is issued to a particular plane (e.g., plane 102a), there are one or more possible options for the AIPO command to be executed, such as Figure 6A Option A shown in FIG. 4A, and Figure 6B Option B shown in FIG. 4B. The selection of Figure 6A Option A for Figure 6B Option B for

[0181] Figure 6AOption A shown: The plane ready state of all planes transitions to a busy state to process commands within a “short time period” (PxRDY=0, x=a, ..., N). This “short time period” is also referred to in this invention as the “command preprocessing period,” which is the first phase of executing AIPO commands. After this first phase, the plane ready states of non-operating or unselected planes (e.g., planes to which AIPO commands were not issued) return to the ready state. Therefore, after time t602a at the end of the command preprocessing period, for the selected or busy plane Pa to which the AIPO command was issued, PaRDY=0, and for all other unselected and non-busy memory planes, PbRDY, PcRDY, and PdRDY=1. The length of the command preprocessing period is implementation-specific, for example, based on the design of memory-based circuitry and other implementation details.

[0182] Figure 6A A timing diagram illustrating an example of the plane ready signal and array ready signal in response to the receipt of AIPO command 604a is shown, wherein execution of AIPO command 604a includes a command preprocessing period during which all planes are busy. It should be noted that in Figure 6A In timing diagrams and various other diagrams, dotted rectangles correspond to associated signals that are busy, while unshaded rectangles correspond to associated signals that are ready (i.e., not busy), such as... Figure 6A As shown in the "Legend" section. Figure 6A Although any number of memory planes can exist, it is assumed that there are four memory planes: 102a, 102b, 102c, and 102d. Therefore, four plane ready signals PaRDY, PbRDY, PcRDY, and PdRDY are shown, and four array ready signals PaARDY, PbARDY, PcARDY, and PdARDY are also shown. Figure 6A Before time t601a, all signals PaRDY, PbRDY, PcRDY, PdRDY, PaARDY, PbARDY, PcARDY, and PdARDY are either ready or not busy.

[0183] In t601a, AIPO command 604a is received from plane 102a. Figure 6A In the example, immediately after receiving the AIPO command 604a from plane 102a, all plane ready signals and array ready signals become busy from time t601a to time t602a. The time from time t601a to time t602a is called the command preprocessing period or the first stage of the execution cycle of AIPO command 604a.

[0184] Subsequently, the plane ready signals and array ready signals of plane 102b, plane 102c, and plane 102d become ready or non-busy at time t602a (e.g., upon issuance of AIPO command 604a for memory plane 102a). PaRDY and PaARDY continue to be busy after time t602a. Thus, memory plane 102a, which contains corresponding memory array 104a, is executing AIPO command 604a. At time t603a, memory plane 102a becomes ready to accept a new command, and PaRDY becomes ready. The time period between time t602a and time t603a is also referred to as the second phase of the execution period of AIPO command 604a. Note that the background array operations of AIPO command 604a can still be in progress in memory plane 102a, and thus, PaARDY is still busy. Eventually, the background array operations of AIPO command 604a end at time t604a, and array ready signal PaARDY now transitions from busy to ready. The time period between time t603a and time t604a, during which only the background array operations of AIPO command 604a are executing, is also referred to as the AIPO background array operation phase or the third phase of the execution period of AIPO command 604a.

[0185] Figure 6B Option B shown in FIG. 6B: In this option, the plane ready state and array ready of the selected plane (e.g., for which the AIPO command is issued) become busy (PxRDY changes from 1 to 0), and the plane ready states of other unselected planes are not affected. Thus, unlike Option A discussed above with respect to Figure 6A Option B lacks a command pre-processing period. Figure 6B Another example timing diagram showing the plane ready signals and array ready signals in response to receiving AIPO command 604b, in which the execution of AIPO command 604a lacks any command pre-processing period, during which all planes are in a busy state. In contrast to the example of Figure 6A In the example of Figure 6B only the selected plane (for which AIPO command 604b is issued) transitions its plane ready signal and array ready signal (i.e., PaRDY and PaARDY) to busy, and the signals of all other planes remain ready. Thus, PaRDY is busy from t601b to t603b, which is the first phase of the execution period of AIPO command 604b. PaARDY is busy from t601b to t604b (e.g., as also discussed with respect to Figure 6A the AIPO background array operation phase or the second phase of the execution period of AIPO command 604b.

[0186] Thus, the comparison Figure 6A Figure 6B In FIG. 6A, all plane ready and array ready signals are busy for a short period of time after the AIPO command is issued (i.e., during the command pre-processing period); whereas in Figure 6B Figure 6B achieves higher operational efficiency since the unselected planes are always available in Figure 6A However, the timing diagram of the implementation Figure 6B requires more complex circuitry in the memory 101 than, for example, the case of Figure 6A Figure 6B Thus, whether the timing diagram of Figure 6A Figure 6B is implemented depends on the design of the memory 101.

[0187] When no background array operation is in progress (i.e., PxARDY for all planes) and a SCO command is issued for a particular plane

[0188] In an example, when all memory arrays of a plane are ready (e.g., PxARDY = 1 for all planes), the host 130 can issue a SCO command to the memory 101. After the SCO command is issued, all planes and corresponding arrays become busy (PxRDY = PxARDY = busy for all planes) and no other command can be issued until all planes become ready (PxRDY = ready for all planes).

[0189] Figure 7 An example timing diagram of the plane ready and array ready signals in response to receiving a SCO command is shown. In this example, similar to Figure 6A , it is assumed that in response to the AIPO command of the plane 102a at time t601a, PaRDY is busy from t601a to t603a, PaARDY is busy from t601a to t604a, and the plane and array ready signals of the other planes are busy from t601a to t602a, for example, for the reasons discussed with respect to Figure 6A .

[0190] ​​​​Suppose that a SCO command 704a for plane 102c is issued between t602a and t603a. Because at least one plane is not ready at this time (e.g., PaRDY is busy), the SCO command 704a for plane 102c is declared invalid, since the host 130 can issue a SCO command to the memory 101 only when all planes are ready for a new command and there is no AIPO background array operation.

[0191] Suppose that a SCO command 704b for plane 102d is issued at time t604a, e.g., at time t702. Because all planes are now ready and there is no ongoing background array operation, the SCO command 704b for plane 102d is executed. All plane and array ready signals transition to busy state from time t702. The plane ready state remains busy from time t702 to t706, where the time period between time t702 and time t706 is also referred to as a "plane engagement period" or a first phase of the execution cycle of a SCO memory command.

[0192] In an example, during the plane engagement period, the SCO engages the resources of all memory planes (or engages the common resources of the memory planes) such that no other operation can be executed - thus, the PxRDY of all planes is busy during this period. In an example, during the plane engagement period, the PxRDY of all planes is busy and all planes are shown as engaged to prevent any command input until the memory 101 is ready for the next command. It should be noted that any AIPO (or SCO) command issued during the plane engagement period is declared invalid (as also later in this disclosure with respect to the Figure 19A discussed).

[0193] At time t706, the cache operation associated with the SCO command 704b for plane 102d can complete, and thus, the plane ready signal can be ready for all planes from time t706 (e.g., PxRDY = ready, x = a,..., d). However, all array ready signals of all planes are still busy (e.g., PxARDY = busy, x = a,..., d) while a background array operation can be in progress in the selected plane 102d. At time t708, the SCO command 704b for plane 102d can complete, and thus, all array ready signals of all planes become ready (e.g., PxARDY = ready, x = a,..., d).

[0194] Thus, during the time period between time t706 and time t708, the array ready signal is busy for all planes while the plane ready signal is ready for all planes. This time period is referred to in this disclosure as a SCO background array operation phase or a second phase of the execution cycle of a SCO command.

[0195] When a background operation is in progress for at least one plane (i.e., PxARDY = busy), issue an AIPO command for a particular plane that does not have a background operation in progress

[0196] Assume that a background operation is in progress for at least one plane, such as plane 102a, i.e., for that plane, PaARDY = 0 (e.g., busy). One or more other planes, such as at least plane 102b, do not have a background operation in progress (e.g., PbRDY = PbARDY = 1 or ready). That is, one or more other planes, such as at least plane 102b, are non-operational or non-busy planes. In this scenario, host 130 can issue an AIPO command to a non-operational plane.

[0197] Figure 8A An example timing diagram is shown depicting the issuance of an AIPO memory command to a non-operational plane while another operational plane has a background operation in progress, where Figure 8A The AIPO memory command of Figure 8A In

[0198] Figure 8B Another example timing diagram is shown depicting the issuance of an AIPO memory command to a non-operational plane while another plane has a background operation in progress, where Figure 8B The AIPO memory command of Figure 8B is similar to Figure 8A The difference between these two figures is that in Figure 8B After the AIPO command 804 for plane 102b is issued at time t802b, only the signals for plane 102b become busy. Thus, Figure 8BThere is no command pre-processing period. Thus, the signals corresponding to the unselected planes do not become busy, as also discussed with respect to Figure 6B .

[0199] When the AIPO background array operation is in progress in a particular plane (i.e., PxRDY = ready and PxARDY = busy), the AIPO command is issued for the particular plane with the in-progress background array operation

[0200] Assume that a background array operation is in progress for at least one plane, such as plane 102a, i.e., for the plane, PaRDY = 1 (e.g., ready) and PaARDY = 0 (e.g., busy). In this scenario, the host 130 can issue a selected (rather than all) AIPO command to the plane with the background array operation.

[0201] Figure 9A An example timing diagram depicting the issuance of an AIPO memory command to a plane with an in-progress background array operation is shown. For example, in Figure 9A , prior to time 902a only, a background array operation is in progress in plane 102a (i.e., PaRDY = ready, PaARDY = busy), and the other planes are ready (e.g., PyRDY = PyARDY = ready, for y = b, c, d). At time 902a, an AIPO command 904 for plane 102a is issued by the host 130. Thus, from t902a to t903a, PxRDY and PxARDY (for x = a,..., d) become busy within a short period of time (i.e., a command pre-processing period). After the short period of time (discussed with respect to Figure 6A ), PbRDY, PcRDY, PdRDY, PbARDY, PcARDY, and PdARDY transition to ready. PbRDY and PaARDY remain busy due to the execution of the AIPO command 904 for plane 102a.

[0202] Figure 9B An example timing diagram depicting the issuance of an AIPO memory command to a plane with an in-progress background array operation is shown. Figure 9B Similar to Figure 9A , the difference between these two figures is that in Figure 9B , after the AIPO command 904 for plane 102a is issued at time t902b, only the signals for plane 102a become busy (e.g., Figure 9B There is no command pre-processing period). The signals corresponding to the unselected planes do not become busy within a short period of time, as also discussed with respect to Figure 6B .

[0203] It is noted that in the example timing diagram of FIG. 9B, the AIPO command 904 for plane 102a is issued at time t902b.Figure 9A and Figure 9B In this case, only some selected types of AIPO memory commands can be allowed, such as those that can be performed in coordination with a prior background array operation that kept plane 102a busy before time t902a. Examples of some such selected AIPO memory commands include a cache read command. For example, as seen in Table 2, a cache read command is an AIPO memory command that can be performed in coordination with a background array operation. Thus, Figure 9A and Figure 9B Operation command 904 can be, for example, a cache read command.

[0204] However, there are some other example AIPO memory commands that cannot be issued to a plane with an ongoing background array operation. For example, as seen in Table 2, a page read command is an AIPO memory command that cannot be performed in coordination with a background array operation. Thus, Figure 9A and Figure 9B Operation command 904 can not be, for example, a page read command.

[0205] There are some commands that can be issued at any time (e.g., system management commands, see Table 2). One example of such a command is a reset command, which can be issued at any time to terminate an ongoing operation in one or more planes.

[0206] SCO and AIPO vs. SCO background array operation

[0207] Figure 10 A timing diagram is shown depicting the issuance of a SCO memory command and the resulting SCO background array operation. For example, at time t1001, a SCO command 1004 for plane 102a is issued by host 130. The PxRDY signal for all planes becomes busy between time period t1001 and time period t1002, which are also referred to in this disclosure as the plane engagement period or the first phase of the execution cycle of a SCO memory command (see Figure 7 ). Phase 1 can include command processing and data transfer between the page buffer and the cache. In phase 1, PRDY and PARDY = 0 (busy) because the cache is busy and the host cannot read / write data in / from the cache. After phase 1, the cache is free and the host can read / write data in / from the cache, so PRDY returns to 1 and PARDY remains 0. Thus, after time t1002, the PxRDY signal for all planes transitions to the ready state. However, for example, as with the AIPO memory command, the PxRDY signal for plane 102a remains busy until time t1003, at which time the PxRDY signal for plane 102a transitions to the ready state. Figure 7As discussed, all-plane array ready signal PxARDY remains busy until the SCO is completed at t1003. As also discussed with respect to Figure 7 the time period between time t1002 and time t1003 is referred to as the background array operation phase or phase 2, which can be a read or write.

[0208] It is noted that during the SCO background array operation phase of the SCO memory command, all- plane PxARDY is busy, as shown in Figure 10 contrast, for the AIPO, the corresponding AIPO background array operation phase (see Figure 6A ) keeps PxARDY busy only for the selected plane (i.e., for which the AIPO has been issued), as shown in Figure 6A and Figure 6B

[0209] Thus, a SCO background array operation is associated with a SCO memory command, and any such operation will engage all planes (i.e., for all planes, PxARDY = busy), as shown in Figure 10 contrast, an AIPO background array operation is associated with an AIPO memory command, and any such operation will engage a specific plane (i.e., for the specific plane, PxARDY = busy), as shown in Figure 6A and Figure 6B

[0210] When a SCO background array operation is in progress (i.e., for all planes, PxRDY = ready and PxARDY = busy), and (i) an AIPO command is issued (which becomes invalid) and (ii) an SCO command is issued

[0211] Figure 11 An example timing diagram is shown depicting a SCO background array operation in progress (see Figure 10 i.e., for all planes, PxRDY = ready and PxARDY = busy) as well as the issuance of an AIPO command 1104a and the issuance of an SCO command 1104b.

[0212] It is noted that when a SCO background array operation is in progress (see Figure 10 for further discussion of a SCO background array operation), the host 130 can issue only selected operation commands. For example, when a SCO background array operation is in progress, the host 130 can not issue an AIPO command 1104a, and thus, will Figure 11 ​​The AIPO command 1104a is declared invalid. This illustrates an example of a method in which a second type of memory command (e.g., an AIPO command) is received by the memory while the memory is executing a first type of memory command (e.g., an SCO command) for simultaneously engaging multiple planes; and in response to receiving the second type of memory command during the execution of the first type of memory command, the execution of the second type of memory command is rejected. However, when SCO background array operation is in progress, the host 130 can effectively issue the SCO command 1104b at t1004, as... Figure 11 As shown in the image. Figure 11 As shown, the states of various signals after time t1104 are already related to Figure 10 This will be discussed further.

[0213] Cache operation

[0214] In this embodiment, cache 112 serves as a data unit that can be directly accessed by host 130. In this example, memory 101 provides cache read and cache program functions that perform data transfers between the page buffer and the cache. After a data transfer operation between the page buffer and the cache is completed, host 130 can access cache 112 while a memory read / write operation is still in progress.

[0215] Cache Read

[0216] Figure 11A1 and Figure 11A2 The various steps associated with a cache read operation are shown. It should be noted that a cache read is an AIPO operation. Therefore, in step 0 ( Figure 11A1 and Figure 11A2 In the case of (not shown), after issuing a cache read command, memory 101 waits until the last cache operation in the selected plane completes before starting a new operation in the selected plane. After issuing a cache read command (e.g., PxRDY changes from 1 to 0), the selected plane becomes busy.

[0217] exist Figure 11A1 In step 1 shown, data is transferred from the page buffer to the cache, where data is read from the memory array into the page buffer during the previous command. During this period, the plane remains busy (e.g., PxRDY=0).

[0218] exist Figure 11A2In Step 2 shown in FIG. 6, after the data transfer from the page buffer to the cache is complete, the plane is ready and can accept a new command (PxRD goes from 0 to 1), and the host 130 can access the cache to get the current data. Also during this time, new data is being read from the memory array to the page buffer in the background (PxARDY = 0). Thus, during Step 2, new data is being transferred from the memory array to the page buffer in parallel with the transfer of the current data from the cache to the host 130. The host 130 can issue another cache read command to the plane after the current data readout in the cache, even though the current background array operation is not complete.

[0219] Cache program

[0220] Figure 11B and Figure 11C1 , Figure 11C2 A timing diagram and various steps associated with a cache program operation are shown. In an embodiment, the cache program operation can program one page of data. In Step 0 (tO), the host 130 issues a cache program command (15h in the example of FIG. 6) to the memory 101. The memory 101 waits until the page buffer is free for data transfer (SCO in the current example) before starting the new operation after the cache program command is issued. Figure 11C1 , Figure 11C2 In Step 2 shown in FIG. 6, after the data transfer from the cache to the page buffer is complete, the plane is ready and can accept a new command (PxRD goes from 0 to 1), and the host 130 can write new data to the cache. While the host 130 is writing data to the cache, the data written to the page buffer in Step 1 is being programmed from the page buffer to the memory array in the background (i.e., PxARDY = 0). The host 130 can issue another cache program command (command code 15h in FIG. 6) or page program command (command code 10h in FIG. 6) to the chip after the data into the cache is complete, even though the current background array operation is not complete. Figure 11B

[0221] In Step 1 shown in FIG. 6, data is transferred from the cache to the page buffer. During this period, the memory remains busy, and all PxRDY = 0, x = a,..., d. Figure 11C1 In Step 2 shown in FIG. 6, after the data transfer from the cache to the page buffer is complete, the plane is ready and can accept a new command (PxRD goes from 0 to 1), and the host 130 can write new data to the cache. While the host 130 is writing data to the cache, the data written to the page buffer in Step 1 is being programmed from the page buffer to the memory array in the background (i.e., PxARDY = 0). The host 130 can issue another cache program command (command code 15h in FIG. 6) or page program command (command code 10h in FIG. 6) to the chip after the data into the cache is complete, even though the current background array operation is not complete.

[0222] Figure 11C2 In Step 2 shown in FIG. 6, after the data transfer from the cache to the page buffer is complete, the plane is ready and can accept a new command (PxRD goes from 0 to 1), and the host 130 can write new data to the cache. While the host 130 is writing data to the cache, the data written to the page buffer in Step 1 is being programmed from the page buffer to the memory array in the background (i.e., PxARDY = 0). The host 130 can issue another cache program command (command code 15h in FIG. 6) or page program command (command code 10h in FIG. 6) to the chip after the data into the cache is complete, even though the current background array operation is not complete. Figure 11B Figure 11B

[0223] Overview of memory plane ready status signal (PxRDY) and memory array ready status signal (PxARDY)

[0224] ​​​​In an embodiment, the host 130 can check the plane busy status (PRDY and PARDY) for operations. To simplify the host operation scheme, the host 130 can only check the plane busy status for operations.

[0225] If there are no ongoing operations in any plane of the memory 101 (all PxRDY and PxARDY = 1), the host can issue any command to the chip.

[0226] If there is an ongoing AIPO operation in the memory 101, the host 130 must check the PxRDY and PxARDY of the selected plane. If the selected plane is free (PxRDY and PxARDY = 1, where 102x is the selected plane), the host can issue any AIPO command to the selected plane. If the selected plane is busy (PxRDY and PxARDY = 0, where 102x is the selected plane), the host 130 cannot issue any command to the selected plane 102x. If the selected plane is ready but there is a background array operation (i.e., PxRDY = 1 and PxARDY = 0, where 102x is the selected plane), the host 130 can issue the selected AIPO command to the selected plane.

[0227] If there is an ongoing SCO operation in the chip, the host 130 must check the PxRDY and PxARDY of the selected plane. If the selected plane is busy (i.e., PxRDY and PxARDY = 0, where 102x is the selected plane), the host cannot issue any command that will be accepted by the selected plane. If the selected plane is ready but there is a background array operation (PxRDY = 1 and PxARDY = 0, where 102x is the selected plane), the host can only issue the selected SCO or AIPO command (not all SCO or AIPO commands) to the selected plane.

[0228] In an embodiment, system management commands can be issued to the chip at any time.

[0229] Figure 11D A table 1190 showing the use of PxRDY and PxARDY for various memory operations is shown, some of which are discussed above.

[0230] As discussed previously in this disclosure, each plane has its own ready status - PxRDY and PxARDY. Thus, the ready status of an individual memory plane includes two status bits, one each for PxRDY and PxARDY.

[0231] PxRDY specifies whether a plane is ready to execute the next command input. For a given memory plane, if PxRDY is busy (PxRDY = 0), then this plane can not accept other commands. On the other hand, if PxRDY is ready (PxRDY = 1), then this plane can selectively accept new commands (or can not accept new commands) based on the command type and other state signals of other planes.

[0232] In an example, when all planes are ready (all PxRDY = 1 and PxARDY = 1), the memory 101 can accept SCO operation commands, as previously discussed in the present disclosure.

[0233] In an example, when a selected particular plane is ready (PxRDY = 1) and the plane is not under an SCO background array operation (see, e.g., Figure 11 where the AIPO operation command 1104a is invalid), the memory 101 can accept an AIPO operation command for the particular plane.

[0234] When a plane is under an SCO background array operation (see, e.g., for all planes, PxRDY = 1 and PxARDY = 0, see Figure 11 ), only limited or selected types of new commands can be accepted. An AIPO operation command can not be included in such limited or selected types of commands (see, e.g., Figure 11 where the AIPO operation command 1104a is invalid).

[0235] As discussed, PxARDY provides a plane ready status for a corresponding memory array operation. If PxARDY is busy (PxARDY = 0) for a particular plane, then a memory array operation for this plane is still in progress, such as accessing an array in the plane by engaging bitlines and wordlines in the array. If PxARDY is ready (PxARDY = 1) for a particular plane, then the plane is not performing any memory array operation.

[0236] Read Plane Busy Status (RPBS) command

[0237] In an example, the host 130 can read out plane status signals (e.g., PxRDY and / or PxARDY) via one or both of a Read Plane Busy Status (RPBS) command and a Read Status Enhancement (RSE) command (the RSE command is discussed in a next section in the present disclosure).

[0238] In an embodiment, the RPBS command reports plane status signals, such as PxRDY and PxARDY, for all planes in the memory 101. For example, for a four-plane memory including memory plane 102a, memory plane 102b, memory plane 102c, memory plane 102d, the RPBS command reports plane status signals PxRDY and PxARDY, where x = a,..., d.

[0239] Figure 12A Bits of a read plane busy status (RPBS) register for a four-plane memory including memory plane 102a, memory plane 102b, memory plane 102c, memory plane 102d are shown. For example, the RPBS register is one of the status registers 140 of Figure 1 Thus, Figure 12A Bits of a read plane busy status (RPBS) register for a four-plane memory including memory plane 102a, memory plane 102b, memory plane 102c, memory plane 102d are shown. For example, the RPBS register is one of the status registers 140 of Figure 12B Issuance of a RPBS command by the host 130 and output of the RPBS including contents of the corresponding status register SR to the host 130 are shown.

[0240] As seen in Figure 12A RPBS signals of 8 bits are used to convey PxRDY and PxARDY, x = a,..., d. The host 130 receives the RPBS signals and knows the various busy / ready status associated with the various planes. For example, bit 7 of the RPBS indicates PdRDY - if bit 7 is 0, then PdRDY is 0 or busy; and if bit 7 is 1, then PdRDY is 1 or ready.

[0241] In some embodiments of the memory device, control signals are provided including a memory chip enable (CE#) signal as a low-active signal; a write enable (WE#) signal as a low-active signal; and a read enable (RE#) signal as a low-active signal. In addition, data input / output (I / O) port signals can be transmitted between the host 130 and the memory 101. The host 130 transmits a command (CMD) requesting RPBS (e.g., during which WE# is low, which enables the host 130 to write or transmit data to the memory 101). In response, the memory 101 outputs data from a status register (SR) including 7 bits of RPBS (e.g., during which RE# is low, which enables the host 130 to read the SR including PxRDY and PxARDY status signals from the memory 101 for coordinating memory operations).

[0242] Read status enhanced (RSE) command

[0243] In contrast to the RPBS command which reports the status of all planes in the report memory, the RSE command reports the status of a particular plane.

[0244] Figure 13A Bits of the Read Status Enhancement (RSE) command register for a particular memory plane (e.g., plane 102x, where x can be any of a,..., N) are shown. Figure 13B The issuance of the RSE signal and the RSE command waveform are shown. The RSE command register is one of the status registers 140 of Figure 1

[0245] The host 130 receives the RSE signal (i.e., the contents of the RSE command register) and knows the various busy / ready status associated with the corresponding plane.

[0246] Referring to Figure 13A , bits 0 and 1 of the RSE signal indicate PxFAIL and PxFAILC, respectively, where PxFAIL is the plane x PASS / FAIL status of the last command issued to plane 102x, and PxFAILC is the plane x PASS / FAIL status of the command issued to plane 102x prior to the last command. Bits 2, 3, and 4 are reserved for future use. Bits 5 and 6 are PxARDY and PxRDY, respectively, for plane 102x. Bit 7 is WP#, providing a chip protection status bit (e.g., which is not directly memory plane related).

[0247] Referring to Figure 13B , the DQ bus provides column addresses (R1 through R3) to indicate the particular plane 102x for which the RSE command is being issued. The RSE status register is output to the host 130 after a time period tWHR has elapsed since the issuance of column address R1 through column address R3.

[0248] Figure 1 The system 100 of Figure 12A and Figure 13A may support either or both of the RPBS command and the RSE command to read the plane busy status. As discussed with respect to

[0249] The plane ready notification (PRN or PRN#) pin

[0250] ​The previously discussed RPBS or RSE registers are used to indicate the PxRDY and PxARDY status of the various planes, and the contents of these registers can be received by the host 130 upon request to the memory 101. In some embodiments, the memory 101 includes hardware pins to indicate changes in the PxRDY and / or PxARDY status of the various memory planes.

[0251] Figure 14A Circuitry 1400 is shown for generating plane ready notification (PRN or PRN#) pins for the memory 101 of Figure 1 Circuitry 1400 assumes there are four memory planes 102a, 102b, 102c, 102d, and accordingly, four plane PRN signals PaPRN, PbPRN, PcPRN, and PdPRN are generated corresponding to the four memory planes 102a, 102b, 102c, 102d. However, as will be readily understood by one of ordinary skill in the art, the memory 101 can have any different number of memory planes, and the circuitry 1400 can be readily modified to accommodate a different number of memory planes.

[0252] In embodiments, each plane has a corresponding plane-specific PRN pin (e.g., also referred to in the present disclosure as a plane PRN, such as PxPRN), as shown in FIG. 14. The PxPRN pins corresponding to multiple memory planes are then used in combination to generate a PRN 1427, which is then inverted to generate a PRN# 1429. Although the example implementation of FIG. 14 shows circuitry 1400 outputting a PRN# 1429, in examples, the circuitry 1400 can instead output a PRN 1427.

[0253] In embodiments, the PRN 1427 and / or PRN# 1429 will indicate to the host 130 to take action, for example, after at least one plane has returned to ready, and the host 130 can clear the PRN# notification information through an RSE or RPBS command. For example, whenever the PxRDY of at least one plane transitions from busy to ready, the host 130 is notified via the PRN and / or PRN# pins (e.g., PRN# 1429 transitions to "notification state"). The host 130 can then receive additional information about the PxRDY that has transitioned to ready through the previously discussed RSE and / or RPBS commands. Upon issuance of the RSE and / or RPBS command, the PRN# signal is cleared, and the PRN# 1429 transitions to "idle state."

[0254] As shown in FIG. 14, there are PRN circuit modules 1401 corresponding to each plane of memory 101 (e.g., PRN circuit module 1401a corresponding to plane 102a, PRN circuit module 1401b corresponding to plane 102b, and so on). The example PRN circuit module 1401a corresponding to plane 102a is discussed in further detail below, and the same discussion applies to the other PRN circuit modules 1401b, 1401c, and 1401d.

[0255] PRN circuit module 1401a receives the PaRDY signal. PRN circuit module 1401a further includes a PRN register 1402 that receives the PaPRN_Set signal, which is the PRN set signal for plane 102a. PRN register 1402 also receives the PaPRN_ReSet signal, which is the PRN reset signal for plane 102a. The output of PRN register 1402a and the PaRDY signal are input to an AND gate 1406a.

[0256] In an embodiment, if PaRDY = 1 (ready) and the PRN register (1402a) is set to 1 (PRNI = 1), then the plane PRN signal PaPRN for plane 102a is set to "1" (i.e., the notify state). Thus, the PRN register is set (PRNI = 1) during the busy period (PaRDY = 0), and PaPRN changes from "0" (i.e., the idle state) to "1" (i.e., the notify state) after PaRDY changes from 0 (busy) to 1 (ready), for example, to notify the host 130 of the PaRDY transition to the ready state.

[0257] If for a plane, PxRDY = 1 (ready), then the plane PRN state (i.e., PxPRN) is cleared to "0" (idle state) by the RSE or RPBS command. If PxRDY = 0 (busy), then the plane PRN state is also cleared to "0" (idle state) to avoid the case where PRN = 1 if the host does not clear the PRN register, all PxRDY = 0. The PaPRN_SET and PaPRN_ReSET signals selectively set or reset the PRN register 1402a of PaPRN for plane 102a. For example, in response to the host issuing an RSE or RPBS command, the PRN register 1402a of PaPRN is cleared to "0" by the PaPRN_ReSET signal to know the current state of PaRDY.

[0258] All state PRN pins (e.g., PaPRN, PbPRN, PcPRN, and PdPRN) undergo an OR operation via OR gate 1426 to generate PRN 1427. The PRN 1427 signal is amplified and inverted by transistor 1428 to be displayed on PRN# plate 1430 (e.g., which may be coupled to...). Figure 1 The PRN# signal is generated at hardware pin 142. For example, PRN 1427 = (P0PRN or P1PRN or P2PRN or P3PRN). Furthermore, the PRN# pin is the inverted version of the PRN signal. In this example, the PRN# pin is an open-drain pin.

[0259] Therefore, if any plane's PRN state (such as PaPRN, PbPRN, PcPRN, and / or PdPRN) is 1 (i.e., in the notification state), then the PRN# pin = 0 (i.e., in the notification state). It should be noted that when the corresponding PxRDY state transitions from busy to ready, PxPRN (where x = a, b, c, or d) is in the notification state.

[0260] If the plane PRN states of all planes (i.e., PaPRN, PbPRN, PcPRN, and PdPRN) are 0 or in an idle state, then the PRN# pin is 1 (i.e., in an idle state). As discussed, the plane PRN state of a plane is idle when the corresponding notification of the state has been cleared by the host (e.g., by issuing an RSE or RPBS command).

[0261] Figure 14B Show Figure 14A The circuit 1400 has various alternating configurations. Specifically, Figure 14B Four different configurations, 1480, 1481, 1482, and 1483, are shown to generate PRN# 1429 according to PRN 1427. Configurations 1480 and 1481 do not have chip enable signal (CE) control, while configurations 1482 and 1483 do. Configurations 1480 and 1482 are open-drain type, while configurations 1481 and 1483 are complementary metal-oxide-semiconductor (CMOS) type. In instances where CE is used, this can be used to identify active dies in multi-die applications, such as where PRN# plates can be combined into a single channel.

[0262] Figure 15 Show depiction Figure 14Athe timing diagram 1500 of the generation of the PRN# 1429 signal. At time tO, PaRDY goes low or busy, e.g., due to the plane 102a receiving a memory command 1502 (see, e.g., the depiction of PaRDY going busy in Figure 6A ), thus causing PaRDY to transition to a low or busy state. The memory command that caused PaRDY to transition to busy can be the command 1502.

[0263] At time tl, the PaPRN SET signal outputs a pulse to indicate that the plane 102a is ready, which at time t2, resets PaRDY from busy to ready. Upon receiving the pulse of the PaPRN SET signal, the signal PRNI(Pa) transitions to high or a notify state.

[0264] It should be noted that between time tO and time t2, PaPRN (see FIG. 14) and PRN# do not provide any notification (i.e., are in an idle state) since PaRDY has not yet transitioned from busy to ready.

[0265] At time t2, upon the PaRDY signal transitioning to ready or 1, the plane PRN PaPRN (see FIG. 14) transitions to 1 or a notify state. Thus, for example, upon the OR gate 1426 causing PRN 1427 to become high due to PaPRN transitioning to high, PRN 1427 (see FIG. 14, Figure 15 not depicted in FIG. 14) also becomes high at time t2. Since PRN# 1429 is the inverse of PRN 1427, at time t2, PRN# 1429 becomes low or a notify state. Thus, from time t2, PRN 1427 and PRN# 1429 issue a notification that at least one PxPRY signal has transitioned to a ready state.

[0266] At time t3, the host 130 issues an RPBS (or RSE) command. The status register SR of the RPBS command is output to the host 130 at time t4. Thus, at time t4, PaPRN ReSET (see FIG. 14) issues a pulse, indicating that the host has issued an RPBS or RSE command.

[0267] Thus, at time t4, the PaPRN signal is reset (e.g., transitions from notify to idle). Thus, PRN 1427 and PRN# 1429 also transition from a notify state to an idle state.

[0268] In an embodiment, to ensure clearing PaPRN based on the read status bit PaRDY, the PaRDY status bit is latched to the PaPRN OUT signal after a RPBS or RSE command. The RPBS or RSE command will output the latch status bit P0PRN OUT and clear the PRN register through P0PRN OUT and RE (read enable). This can ensure notifying the user (i.e., host 130) and clearing the register.

[0269] Reset plane command

[0270] As previously discussed with respect to Figure 3D1 and Figure 3D2 , a "reset plane" command can be supported by the memory 101, where the reset plane command will abort any AIPOs being performed in a selected plane, the reset plane command being issued for the selected plane. Figure 16 A configuration (e.g., cycle type) of the reset plane command is shown. As shown in Figure 16 , the reset plane command includes one command cycle followed by one or more (e.g., three) address cycles, where the addresses included in the address cycles indicate one or more addresses (e.g., column addresses) of the memory plane to be reset (see also Figure 3D2 ). In an example, after the memory 101 receives this command, the memory 101 aborts any AIPOs being performed in the memory plane identified by the addresses in the address cycles.

[0271] AIPO memory command issued to a memory plane that does not have a background operation in progress (other planes can have AIPO background operations)

[0272] Figure 17A and Figure 17B Timing diagrams 1700a and 1700b depicting scenarios where an AIPO memory command is issued to a memory plane that does not have a background operation in progress, while one or more other memory planes can have an AIPO background operation in progress, are shown, respectively.

[0273] In the example of Figure 17A , an AIPO command 1704a for plane 102b is issued at time t1702a. Prior to time t1702a, PaRDY and PaARDY are busy, indicating that an AIPO is being performed in plane 102a. The AIPO command 1704a is issued to a non-busy plane, such as plane 102b, where PbRDY = "ready" at the time the AIPO command 1704a is issued. In an example, the AIPO command 1704a can be any suitable AIPO command listed in Table 2 discussed previously, such as a page read operation.

[0274] As previously discussed with respect toFigure 6A The discussion is in Figure 17A In this example, after the AIPO command 1704a is issued, all planes become busy for a short period of time (e.g., between time t1702a and time t1703a), which is the command preprocessing period. After the command preprocessing period, PxRDY and PxADRY of planes 102c and 102d become "ready". Memory plane 102b begins processing AIPO command 1704a from time t1703a. Plane 102a remains busy due to ongoing operations that began before time 1702a.

[0275] In this embodiment, new commands are not permitted to be issued via host 130 during the command preprocessing period. As discussed, after the command preprocessing period, the plane ready state signals of the non-operational planes (e.g., planes 102c and 102d) are again switched to the ready state.

[0276] Figure 17B Alternative embodiments are shown (e.g., they may be...) Figure 17A Alternatives to the embodiments shown). For example, in Figure 17A In this context, there exists a command preprocessing period during which all planes become busy immediately after the issuance of AIPO command 1704a (e.g., PxRDY and PxARDY, x=a, ..., d). In contrast, Figure 17B This command's preprocessing phase is missing. For example, in Figure 17B In this embodiment, only the selected plane to which the AIPO command 1704b is issued at time t1702b becomes busy from time t1702b. Other unselected planes (e.g., plane 102c, plane 102d) remain ready—that is, the PcRDY, PdRDY, PcARDY, and PdARDY status signals are unaffected by the AIPO command 1704b, and these status signals remain available.

[0277] In the example, Figure 17A The embodiment is more Figure 17B The embodiments are relatively easier to use for circuit implementation (e.g., this is because...). Figure 17A The embodiments have a relatively simple command interface. However, in Figure 17A In this embodiment, there may be a slight loss in performance because the host 130 needs to wait during the command preprocessing period, during which the host 130 cannot issue any new commands.

[0278] Other examples of AIPO memory commands

[0279] If an AIPO background array operation is in progress in a particular plane, such as the first plane where PxRDY = ready and PxARDY = busy for the first plane, then an AIPO command such as a page read or a cache read command can be issued to another plane, such as the second plane, that does not have any background operation (PxRDY = PxARDY = ready for the second plane).

[0280] If an AIPO background array operation is in progress in a particular plane, such as the first plane where PxRDY = ready and PxARDY = busy for the first plane, then only a selected AIPO command such as a cache read command can be issued to the first plane that has a background array operation. For example, referring to Table 2 previously discussed in the disclosure, a cache read random command is an AIPO command that is allowed during a background array operation (i.e., Category 5 of Table 2). Thus, any Category 5 AIPO command of Table 2 can be issued to a plane that has a background array operation.

[0281] There can be other AIPO memory commands such as a page read command or some Category 4 AIPO commands (see Table 2) that cannot be issued to a plane that has an AIPO background array operation in progress. The type of command that can be issued during an AIPO background array operation can depend on the particular implementation of the memory device.

[0282] If an AIPO background array operation is in progress, then a SCO command (e.g., a block erase command) is not allowed.

[0283] Figure 18A and Figure 18B Timing diagrams 1800a and 1800b are shown, respectively, depicting various example scenarios for issuing AIPO commands. It should be noted that Figure 18A Timing diagrams 1800a and 1800b are shown, respectively, depicting various example scenarios for issuing AIPO commands. It should be noted that Figure 18B Timing diagrams 1800a and 1800b are shown, respectively, depicting various example scenarios for issuing AIPO commands. It should be noted that Figure 18A Timing diagrams 1800a and 1800b are shown, respectively, depicting various example scenarios for issuing AIPO commands. It should be noted that Figure 15 the PRN# signal 1429 of FIG. 14 to illustrate the operation of the PRN# signal 1429.

[0284] Referring to Figure 18A Prior to time t1801a, none of the planes are busy (i.e., PxRDY = PxARDY = ready for all planes). At time t1801a, an AIPO command 1804a for plane 102a is issued. Thus, there is a command pre-processing period between time t1801a and time t1802a during which all planes are busy (i.e., PxRDY = PxARDY = busy for all planes).

[0285] For example, at time 1802a, planes 102b, 102c, and 102d transition to ready, which the host 130 knows by issuing the RPBS command. For example, at time t1802a, the host 130 receives an indication of one or more planes that transitioned to ready via PRN 1427 or PRN# 1429 (see FIG. 14). Thus, after time 1802a, the host 130 issues the RPBS (or RSE) command to detect the status of the various planes. As shown, as discussed with respect to FIG. 14 and Figure 15 As discussed, the PRN# 1429 is reset to the idle state based on the issuance of the RPBS command.

[0286] At time t1803a, plane 102a transitions to ready (e.g., as discussed with respect to t603a of FIG. 18). At time t1803a, the host 130 receives an indication of one or more planes that are available via PRN 1427 or PRN# 1429 (see FIG. 14). Thus, after time 1803a, the host 130 issues the RPBS (or RSE) command to detect the status of the various planes and knows that plane 102a is ready (i.e., PaRDY = ready). The PRN# 1429 is reset to the idle state based on the issuance of the RPBS. Figure 6A

[0287] At t1804a, the host 130 issues another AIPO command 1804b for plane 102b. Similar to the previous discussion, there is a command pre-processing period between time t1804a and time t1805a, during which all planes are busy (i.e., PxRDY = PxARDY = busy for all planes). At time 1805a, planes 102a, 102c, and 102d are ready (i.e., PaRDY = PcRDY = PdRDY = ready), but the background array operation is still in progress in plane 102a for executing AIPO command 1804a. As discussed, the host 130 issues the RPBS signal to detect the status of the various planes.

[0288] At t1806a, the host 130 issues another AIPO command 1804c for plane 102a. Similar to the previous discussion, there is a command pre-processing period between time t1806a and time t1807a, during which all planes are busy (i.e., PxRDY = PxARDY = busy for all planes). At time 1807a, planes 102c and 102d are ready (i.e., PcRDY = PdRDY = ready), but operations are still in progress in planes 102a and 102b for executing AIPO command 1804c and AIPO command 1804b, respectively.

[0289] ​Therefore, as previously discussed, if an AIPO background array operation is in progress in a specific plane (such as the first plane, where PxRDY = Ready and PxARDY = Busy for the first plane), an AIPO command (such as a page read or cache read command) can be issued to another plane (such as the second plane) that does not have any background array operation (PxRDY = PxARDY = Ready for the second plane). The AIPO command 1804b issued in plane 102b at time t1804a is an example of this AIPO command.

[0290] As previously discussed, if an AIPO background array operation is in progress in a specific plane (such as the first plane, where PxRDY = Ready and PxARDY = Busy for the first plane), then only selected AIPO commands (such as cache read random commands or commands from another category 5 of Table 2 previously discussed in this invention) can be issued to the first plane having a background array operation. For example, at time t1806a, AIPO command 1804c is issued for plane 102a, while plane 102a is still performing an AIPO background array operation (i.e., PaRDY = Ready, PaARDY = Busy). Therefore, AIPO command 1804c can be a cache read random command or a command from another category 5 of Table 2, but cannot be a page read or a command from another category 4 of Table 2.

[0291] Figure 18B Timing diagram 1800b and Figure 18A The timing diagram 1800a is partially similar. The difference between these two timing diagrams is that... Figure 18A The timing diagram 1800a includes the command preprocessing period. Figure 18B The timing diagram 1800b lacks the command preprocessing period. For example, compared with... Figure 6B similar, Figure 18B The timing diagram 1800b lacks a command preprocessing period. Therefore, the preprocessing periods at the end of various command preprocessing periods are missing. Figure 18B The RPBS in timing diagram 1800a is not present Figure 18B In the timing diagram 1800b. Based on about Figure 18A and Figure 6B The argument, Figure 18B The timing diagram 1800b will be obvious to those skilled in the art.

[0292] Other examples of SCO memory commands

[0293] If no background array operation is in progress, then a SCO command (e.g., a page program command or a block erase command) can be issued only when all planes are ready (i.e., PxRDY = PxARDY = ready for all planes). After a SCO command is issued, all planes will become busy (i.e., PxRDY = PxARDY = busy for all planes).

[0294] Figure 19A A timing diagram 1900a depicting an example of a SCO command is shown. At t1901a, an AIPO command 1904a for plane 102a is issued. This is followed by a command pre-processing period between time t1901a and time t1902a (although in another example, this command pre-processing period can not exist, as discussed with respect to Figure 6B ). This is followed by an RPBS command issued by the host 130, as discussed with respect to Figure 18A . Thus, after time t1902a, PaRDY = PaARDY = busy, and all other status signals are ready. At time t1904a, the execution of the AIPO command 1904a for plane 102a is complete, and both PaRDY and PaARDY become ready at time t1904a. Note that although in this example of Figure 19A , both PaRDY and PaARDY become ready at the same time, PaRDY can become ready after PaARDY becomes ready, as seen in Figure 6A .

[0295] As also shown in Figure 19A , at time t1903a (e.g., which is between time t1902a and time t1904a), a SCO command 1904b for plane 102b is issued. Since not all planes are ready at time 1903a (e.g., at time t1903a, PaRDY = busy), the SCO command 1904b for plane 102b is invalid and not executed by the memory 101.

[0296] After all planes are ready from time t1904a, another SCO command 1904c for plane 102b is issued at time t1905a. Note that at this time, all planes are ready. Thus, the SCO command 1904c is valid, and the SCO command 1904c is executed from time t1905a.

[0297] As discussed with respect to Figure 7 , at Figure 19AOnce SCO command 1904c is issued, all planes will become busy, for example, during the plane joining period between time t1905a and time t1906a (i.e., PxRDY = PxARDY = busy, x = a, ..., d). At t1906a (i.e., after the plane joining period ends), all planes become ready (i.e., PxRDY = ready, x = a, ..., d), but the SCO background array operation is in progress in all planes (i.e., PxARDY = busy, x = a, ..., d). Finally, at time t1907a, the SCO background array operation completes, and PxARDY = ready, x = a, ..., d.

[0298] It should be noted that during the plane engagement period between time t1905a and time t1906a, all planes are drawn as busy (i.e., PxRDY = busy, x = a, ..., d), but SCO command 1904c is used for a specific plane 102b. That is, although planes 102a, 102c, and 102d may not actively participate in SCO command 1904c, they are still drawn as busy or in operation to avoid any command input until memory 101 is ready for the next command. Therefore, when a plane is drawn as engaged, the time period between time t1905a and time t1906a is also referred to as the plane engagement period in this invention to avoid any command input until memory 101 is ready for the next command.

[0299] It should be noted that any AIPO (or SCO) operations published during the planar junction period will be declared invalid. For example, in Figure 19A In the event that AIPO command 1904d was issued at time t1905a1, which falls within the plane junction period, this command is therefore declared invalid.

[0300] Figure 19B Another timing diagram 1900b depicting an example of the SCO command is shown.

[0301] Figure 19B Timing diagram 1900b and Figure 19A The timing diagram 1900a is partially similar. The difference between these two timing diagrams is that... Figure 19A The timing diagram 1900a includes the command preprocessing period. Figure 19B The timing diagram 1900b lacks the command preprocessing period. For example, compared with... Figure 6B similar, Figure 19B The timing diagram 1900b lacks a command preprocessing period. Therefore, the preprocessing periods at the end of various command preprocessing periods are missing. Figure 19BThe RPBS in timing diagram 1900a is also not present. Figure 19B In the timing diagram 1900b. Based on about Figure 19A and Figure 6B The argument, Figure 19B The timing diagram 1900b will be obvious to those skilled in the art.

[0302] Figure 20 Timing diagram 2000 illustrates other instances of SCO commands and also shows that some AIPO memory commands may not be issued when performing SCO background array operations on a plane. In timing diagram 2000, SCO command 2004a for plane 102a is issued at time t2001, thereby making all planes busy during the previously discussed plane engagement period, which occurs between time t2001 and time t2002. At time t2002, PxRDY becomes ready, x=a, ..., d, that is, all planes become ready, and PRN# 1429 is issued. Therefore, RPBS is issued and PRN# 1429 is reset. It should be noted that the SCO background array operation is still in progress after time t2002, and therefore, PxRDY = busy, x=a, ..., d.

[0303] At time t2003 (e.g., while the SCO background array operation is still in progress), AIPO command 2004b is issued for plane 102b. Note that if the SCO background array operation is in progress, memory 101 may not be able to execute AIPO memory commands, such as page read commands. Therefore, AIPO command 2004b for plane 102b is invalid.

[0304] However, if the SCO background array operation is in progress, memory 101 may be able to execute selected SCO memory commands, such as cache commands or another category 2 SCO commands as previously discussed in Table 2 of this invention. It should be noted that if the SCO background array operation is in progress, category 1 SCO commands may not be effectively received and executed.

[0305] For example, at time t2004 (e.g., while SCO background array operation is still in progress), SCO command 2004c (such as a cache command or another category 2 SCO command from Table 2) is issued to plane 102b. This command is valid and executed via memory 101. For example, all planes become busy during the corresponding plane engagement period starting from time t2004. The timing diagram portion after time t2004 is related to... Figure 19B The parts discussed are similar, and therefore, no further details were provided.

[0306] Figure 21A and Figure 21B Timing diagram 2100a and timing diagram 2100b show other examples of SCO commands being described, and also describe some AIPO memory commands that can be issued and executed concurrently with a plane executing a SCO background array operation.

[0307] It should be noted that, Figure 21A and FIG. 21B show scenarios opposite to FIG. 20 . For example, in FIG. 20 , AIPO command 2004b is not allowed while a plane is executing a SCO background array operation. In contrast, in FIG. 21A and FIG. 21B , AIPO command 2104b is allowed while a plane is executing a SCO background array operation.

[0308] For example, the circuitry within memory 101 implementing the scenarios of FIG. 20 may be different from the circuitry within memory 101 implementing the scenarios of FIG. 21A and FIG. 21B . Thus, whether an AIPO memory command is allowed or not while a plane is executing a SCO background array operation is implementation specific - based on the design of memory 101. When a plane is executing a SCO background array operation, memory 101 can support selectively allowing (or disallowing) AIPO memory commands.

[0309] In another example, FIG. 20 AIPO command 2004b is different from FIG. 21A AIPO command 2104. Thus, AIPO command 2104b of FIG. 21A (e.g., category 4 command of Table 2) is allowed, while AIPO command 2004b of FIG. 20 (e.g., category 5 command of Table 2) is disallowed.

[0310] In timing diagram 2100a, SCO command 2104a of plane 102a is issued at time t210la, whereby all planes become busy during the previously discussed plane engagement period, which occurs between time t210la and time t2102a. At time t2102a, PxRDY transitions to ready, x = a,..., d, i.e., all planes become ready, and PRN#1429 issues a notification. Thus, RPBS is issued and PRN#1429 is reset. It should be noted that the SCO background array operation is still in progress after time t2102a, and thus, PxARDY = busy, x = a,..., d.

[0311] At time t2103a (e.g., while the SCO background array operation is still in progress), AIPO command 2104b is issued to plane 102b. FIG. 21A In the examples (and with respect to...) FIG. 20 (Conversely to the previous discussion), if SCO background array operation is in progress, memory 101 may be able to execute AIPO memory commands, such as page read commands. Therefore, AIPO command 2104b is enabled for plane 102b.

[0312] Therefore, from time 2103a, all planes become busy during the command preprocessing period until time t2104a, after which planes 102a, 102c, and 102d become available. It should be noted that SCO background array operations are in progress in all planes, for example, executing SCO command 2104a for plane 102a. At time t2106a, plane 102b becomes ready (e.g., PbRDY), for example, as per [reference to...]. FIG. 6A This is discussed at time t603a. It should be noted that SCO background array operations may still be in progress in all planes after time t2106a.

[0313] FIG. 21B Timing diagram 2100b and FIG. 21A The timing diagram 2100a is partially similar. The difference between these two timing diagrams is that... FIG. 21A The timing diagram 2100a includes the command preprocessing period. FIG. 21B The timing diagram 2100b lacks the command preprocessing period. For example, compared with... FIG. 6B similar, FIG. 21B The timing diagram 2100b lacks a command preprocessing period. Therefore, the command preprocessing period at the end of the preprocessing period is missing. FIG. 21B The RPBS in timing diagram 2100a is not present FIG. 21B In the timing diagram 2100b. Based on about FIG. 21A and FIG. 6B The argument, FIG. 21B The timing diagram 2100b will be obvious to those skilled in the art.

[0314] FIG. 22A to FIG. 22H The diagram illustrates example timing diagrams of the plane-ready signal PxRDY for planes P0 to P3 and the array-ready signal PxARDY for planes P0 to P3 in response to receiving commands of various classes that can be implemented in various embodiments. It should be noted that in FIG. 22A to FIG. 22H In the timing diagram, as in the previous diagram, the dotted rectangles correspond to associated signals that are busy, and the unshaded rectangles correspond to associated signals that are ready (i.e., not busy), as shown below. FIG. 6A As shown in the "Legend" section.

[0315] FIG. 22A The timing of the status signals for a SCO command without cache operations, such as Category 1 in Table 2, is illustrated. Upon receiving the SCO command for plane P0, all status signals are in the ready state. During execution of the command, all status signals are in the busy state until the command is complete. Both the plane ready signals for all planes and the array ready signal are in the busy state during the operation period.

[0316] FIG. 22B The timing of the status signals for a SCO command with cache operations, such as Category 2 in Table 2, is illustrated, the cache operations having two operation periods. Upon receiving the SCO command for plane P0, all status signals are in the ready state. After receiving the command, the plane ready signals for all planes transition to the busy state during the cache busy period and transition to the ready state at the end of the cache busy period. The array ready signal remains in the busy state during the background array operation period, which is a longer interval beyond the end of the cache busy period.

[0317] FIG. 22C The timing of the status signals for an AIPO command without cache operations, such as Category 4 in Table 2, is illustrated, the cache operations having two operation periods. Upon receiving the AIPO command for plane P0, all status signals are in the ready state. After receiving the command, the plane ready signals for all planes transition to the busy state. In addition, after receiving the command, the array ready signals for all planes transition to the busy state. At the end of the command processing interval, the plane ready and array ready signals for the unselected planes transition to the ready state. The plane ready and array ready signals for the selected plane P0 remain busy during the operation interval.

[0318] FIG. 22DThe timing of status signals for an AIPO command with a cache operation, such as Category 5 of Table 2, is illustrated with three operation phases, including: a command processing phase, where all plane ready and array ready signals are busy; a data transfer phase, where for unselected planes, the plane ready and array ready signals are ready and the plane ready and array ready signals of the selected plane remain busy; and an array read / write phase, where the plane ready signal of the selected plane transitions to ready and the array ready signal of the selected plane remains busy until completion. Upon receiving an AIPO command for plane PO, all status signals are in the ready state. After receiving the command, the plane ready signals of all planes transition to the busy state. Also, after receiving the command, the array ready signals of all planes transition to the busy state. At the end of the cache operation interval, the plane ready signal of the selected plane PO transitions to the ready state. However, the array ready signal of the selected plane remains busy for a longer operation interval. The plane ready signals of unselected planes and the array ready signals of unselected planes transition to the ready state at the end of the command processing interval.

[0319] The operation sequence for different commands can be different. For example, for an example page read command: phase 1 : command processing; phase 2: array read operation; and phase 3: data transfer from page buffer to cache. For an example cache read command: phase 1 : command processing; phase 2: data transfer from page buffer to cache; and phase 3: array read operation. However, the operation sequence for example page program command and cache program command can be the same: phase 1 : command processing; phase 2: data transfer from cache to page buffer; and phase 3: array write operation.

[0320] FIG. 22E The timing of status signals for an AIPO command sequence that supports multiple overlapping plane operations is illustrated. For example, as shown, for a memory device with multiple planes that supports multi-plane read with cache operation, a command sequence is received that includes a first command for plane PO and a second command for plane PI. In some embodiments, there can be a received multi-plane command sequence that addresses all planes or any subset of planes in the memory. For example, the multi-plane command can have a form as specified by the Open NAND Flash Interface (ONFI) Standard (Revision 5.0, May 25, 2021, which is incorporated by reference as fully set forth in the present invention) such as the following:

[0321] MP command set 1 : 00h - ADDR - 32h

[0322] MP command set 2: 00h - ADDR - 30h / 31 h

[0323] In the illustrated embodiment, upon receiving the first command, all plane ready and array ready signals are in the ready state. Upon receiving the command, the command processing interval during which all plane ready and array ready signals transition to the busy state begins. At the end of the command processing interval, the array ready and plane ready signals of the unselected planes transition to the ready state, while the selected plane array ready and plane ready signals remain in the busy state. Upon receiving the second command addressed to plane PI, the array ready and plane ready signals of planes PI to P3 are in the ready state, and the array ready and plane ready signals of plane PO are in the busy state. Upon receiving the second command, the plane ready and array ready signals of planes PI to P3 transition to the busy state for the command processing interval. At the end of the command processing interval, the array ready and plane ready signals of planes P2 and P3 transition to the ready state, while the array ready and plane ready signals of plane PI remain in the busy state for the duration of the operation. At the end of the operation in plane PO, the plane ready and array ready signals of plane PO transition to the ready state. At the end of the operation of plane PI, the plane ready and array ready signals of plane PI transition to the ready state.

[0324] FIG. 22F The case of an AIPO command sequence of multiple planes that can be issued during the background array operation phase of other planes is shown. Thus, in addition to the array ready signal of plane P2 being in the busy state upon receiving the first command of plane PO and upon receiving the second command of plane PI, FIG. 22F as FIG. 22E like.

[0325] FIG. 22G The case of an AIPO command sequence of multiple planes that can be issued during the background array operation phase of other planes is shown. Thus, in addition to the array ready signal of plane P2 being in the busy state upon receiving the first command of plane PO and upon receiving the second command of plane PI,

[0326] FIG. 22HA case of parallel operation showing the AIPO command sequences of multiple planes that can be issued during other planes' background array operation phases. Thus, in addition to the array ready signal of plane P2 being busy at the time the first command of plane P0 is received and at the time the second command of plane P1 is received, FIG. 22H Like FIG. 22G

[0327] FIG. 23 An example of issuing a second SCO command during the operation of a first SCO command is shown. After issuing a cache SCO command 1, the chip becomes busy only in phase 1 (all PxRDY = 0), then the chip returns to ready (all PxRDY = 1) after phase 1 is completed. A new SCO command 2 can be issued even though phase 2 of the previous command is still in progress. However, the 2ndSCO operation does not start until the 1stcommand operation is finished, so it still satisfies the SCO criteria.

[0328] FIG. 24 Another example of an AIPO command that can issue temporarily suspending the operation of a previous SCO command is shown. After issuing a cache SCO command 1, the chip becomes busy only in phase 1 (all PxRDY = 0), then the chip returns to ready (all PxRDY = 1) after phase 1 is completed. A new AIPO command 2 can be issued even though phase 2 of the previous command is still in progress. In this case, the previous operation is temporarily suspended to perform the new command and automatically resumes the old operation after the new operation is completed. This can be a special case when one command has higher priority than the other.

[0329] Various example configurations that can be supported by the embodiments of the plane ready / array ready signals described in this invention are presented. One example can be characterized as follows:

[0330] 1. Whether there is no background operation (PxRDY = PxARDY = 1).

[0331] i. If the selected plane is ready (PxRDY = PxARDY = 1), an AIPO command (including cache and non-cache AIPO commands) can be issued for the selected plane.

[0332] ii. If all planes are ready (PxRDY = PxARDY = 1), an SCO command (including cache and non-cache SCO commands) can be issued.

[0333] 2. Whether there is a background array operation (PxRDY = 1 and PxARDY = 0).

[0334] i. If the background array operation is a cache AIPO operation for the selected plane, a selected AIPO command can be issued for the selected plane.​

[0335] ii. If the background array operation is a non-selected plane cacheable AIPO operation, then AIPO commands (both cacheable and non-cacheable AIPO commands) can be issued for the selected plane.

[0336] iii. If the background array operation is a cacheable SCO operation, then selected SCO and AIPO commands can be issued.

[0337] iv. Note that the selected commands referred to herein are not only cacheable (SCO / AIPO) commands, they can also include non-cacheable (SCO / AIPO) commands.

[0338] 3. If the selected plane is busy (PxRDY = PxARDY = 0), then no AIPO or SCO commands can be issued to the selected plane.

[0339] Thus, in some configurations, cacheable and non-cacheable commands can be issued when no background operation is in progress (PxRDY = PxARDY = 1).

[0340] Furthermore, selected commands, including commands that are not cacheable commands, can be issued during a background array operation (PxRDY = 1 and PxARDY = 0).

[0341] While the application has been disclosed with reference to the preferred embodiments and examples detailed above, it should be understood that the examples are intended in an illustrative sense and not a limiting sense. It is contemplated that modifications and combinations will readily occur to those skilled in the art, which modifications and combinations will be within the spirit and scope of the application and the following claims.

Claims

1. A memory having multiple memory planes, characterized in that, include: Multiple memory planes, each memory plane including (i) at least one corresponding memory array and (ii) one or more peripheral circuits, the peripheral circuits being dedicated to read and write operations associated with the at least one corresponding memory array and the corresponding memory plane; Input / output (I / O) interface for receiving memory commands and data from the host and outputting data to the host; as well as One or more memory cells are configured to store (i) a corresponding plane ready (PRDY) signal indicating the busy or ready state of the corresponding memory plane and (ii) a corresponding plane array ready (PARDY) signal indicating the busy or ready state of the corresponding memory array of the corresponding memory plane for each of the multiple memory planes, thereby storing multiple PRDY signals and multiple PARDY signals corresponding to the multiple memory planes; The memory is configured to perform (i) a first type of operation and (ii) a second type of operation, wherein the first type of operation occupies multiple memory planes of the memory during at least a portion of the execution of the operation, and the second type of operation occupies one memory plane instead of the multiple memory planes during at least a portion of the execution of the operation. The first type of operation occupies a memory array across multiple memory planes during at least a partial execution, causing multiple PARDY signals across the multiple memory planes to be busy simultaneously; and The second type of operation occupies the memory array of one memory plane during at least a portion of the execution, rather than the entire memory array of multiple memory planes, such that the PARDY signal of one memory plane is busy, while the PARDY signal of one or more other memory planes is busy or ready.

2. The memory according to claim 1, characterized in that, Also includes: Ready notification pin; as well as A circuit for transitioning the ready notification pin from an idle state to a notification state, to provide an indication that at least one of the plurality of PRDY signals has changed from the busy state to the ready state.

3. The memory according to claim 2, characterized in that, The circuitry will further respond to the memory by providing at least some of the contents of the one or more memory cells to the host, changing the ready notification pin from the notification state to the idle state, and the at least some of the contents of the one or more memory cells recognizing the at least one PRDY signal that changes from the busy state to the ready state.

4. The memory according to claim 3, characterized in that, The memory can receive a status read command from the host after the transition of the ready notification pin from the idle state to the notification state; The memory is configured to, in response to receiving the status read command, provide at least some of the contents of the one or more memory cells to the host; and In response to providing at least some of the contents of the one or more storage units to the host, the circuitry is configured to transition the ready notification pin from the notification state to the idle state.

5. The memory according to claim 1, characterized in that, The memory is configured to perform operations that engage multiple memory planes of the memory during at least a portion of the execution of the operation, and During the first phase of the operation, multiple PRDY signals and multiple PARDY signals corresponding to the multiple memory planes are set to indicate a busy state.

6. The memory according to claim 5, characterized in that, During the second background array operation phase of performing the operation, the plurality of PRDY signals are set to indicate the busy state and the plurality of PRDY signals are set to indicate the ready state.

7. The memory according to claim 1, characterized in that, The memory is configured to perform operations targeting a first memory plane, engaging the first memory plane but not all of the plurality of memory planes during at least a portion of the execution of the operations, and During the first phase of the operation, the plurality of PRDY signals and the plurality of PARDY signals corresponding to the plurality of memory planes are set to indicate the busy state.

8. The memory according to claim 7, characterized in that, During the second phase of the operation, the first PRDY signal and the first PARDY signal corresponding to the first memory plane are set to indicate the busy state, and one or more other PRDY signals and one or more other PARDY signals among the plurality of PRDY signals are set to indicate the ready state or the busy state.

9. A method for operating a memory comprising multiple memory planes, each memory plane comprising (i) at least one corresponding memory array and (ii) one or more peripheral circuits, the peripheral circuits being configured to support operation of the corresponding memory array and the corresponding memory plane, characterized in that, The method includes: For each of the plurality of memory planes, generate (i) a corresponding plane ready (PRDY) signal indicating the busy or ready state of the corresponding memory plane and (ii) a corresponding plane array ready (PARDY) signal indicating the busy or ready state of the corresponding memory array of the corresponding memory plane, thereby generating a plurality of PRDY signals and a plurality of PARDY signals corresponding to the plurality of memory planes. The memory is configured to perform (i) a first type of operation and (ii) a second type of operation, wherein the first type of operation occupies multiple memory planes of the memory during at least a portion of the execution of the operation, and the second type of operation occupies one memory plane instead of the multiple memory planes during at least a portion of the execution of the operation. The first type of operation occupies a memory array across multiple memory planes during at least a partial execution, causing multiple PARDY signals across the multiple memory planes to be busy simultaneously; and The second type of operation occupies the memory array of one memory plane during at least a portion of the execution, rather than the entire memory array of multiple memory planes, such that the PARDY signal of one memory plane is busy, while the PARDY signal of one or more other memory planes is busy or ready.

10. The method of operating a memory comprising a plurality of memory planes according to claim 9, characterized in that, Also includes: Based on the state of one or more of the plurality of PRDY signals and the plurality of PARDY signals, memory commands of memory planes in the plurality of memory planes are selectively allowed or denied.

11. The method of operating a memory comprising a plurality of memory planes according to claim 9, characterized in that, Also includes: The first type of operation performed in the memory, involving a memory array of the plurality of memory planes engaging the memory during at least a portion of the execution, includes... During the plane engagement phase of the operation, a plurality of PRDY signals and a plurality of PARDY signals corresponding to the plurality of memory planes are generated to indicate the busy state.

12. The method of operating a memory comprising a plurality of memory planes according to claim 11, characterized in that, Also includes: During the background array operation phase of performing the operation, the plurality of PARDY signals indicating the busy state and the plurality of PRDY signals indicating the ready state are generated.

13. The method of operating a memory comprising a plurality of memory planes according to claim 9, characterized in that, The first PRDY signal and the first PARDY signal are associated with a first memory plane among the plurality of memory planes, and performing a second type of operation that engages a memory array of one memory plane rather than all of the plurality of memory planes during at least a portion of the execution includes: During the first phase of performing the second type of operation, the plurality of PRDY signals and the plurality of PARDY signals corresponding to the plurality of memory planes are generated to indicate the busy state.

14. The method of operating a memory comprising a plurality of memory planes according to claim 13, characterized in that, Also includes: During the second phase of performing the second type of operation, (i) a first PRDY signal and a first PARDY signal indicating the busy state, and (ii) one or more other PRDY signals and one or more other PARDY signals indicating the ready state or the busy state.

15. The method of operating a memory comprising a plurality of memory planes according to claim 9, characterized in that, The first PRDY signal and the first PARDY signal are associated with a first memory plane among the plurality of memory planes, and wherein performing the second type of operation for the first memory plane includes: During the execution of the second type of operation, simultaneously (i) a first PRDY signal and a first PARDY signal indicating the busy state, (ii) at least one second PRDY signal and at least one third PRDY signal respectively corresponding to the second memory plane and the third memory plane indicating the ready state, and (iii) at least one second PARDY signal and at least one third PARDY signal respectively corresponding to the second memory plane and the third memory plane indicating the ready state or the busy state.

16. The method of operating a memory comprising a plurality of memory planes according to claim 9, characterized in that, Also includes: While the memory is executing a first type of memory command to simultaneously engage multiple planes, the memory receives a second type of memory command. as well as In response to receiving a second type of memory command during the execution of a first type of memory command, the execution of the second type of memory command is refused.

17. The method of operating a memory comprising a plurality of memory planes according to claim 9, characterized in that, Also includes: Generate a plane-ready notification signal; as well as In response to the transition of one or more of the plurality of PRDY signals from the busy state to the ready state, the plane ready notification signal is changed to a notification state.

18. The method of operating a memory comprising a plurality of memory planes according to claim 17, characterized in that, Also includes: In response to the notification from the memory to the host of the transition of one or more PRDY signals from the busy state to the ready state, the plane ready notification signal is reset to the idle state; and The plane ready notification signal is supplied to a dedicated hardware pin accessible to the host.

19. A method for operating a memory comprising a plurality of memory planes, each memory plane comprising at least one corresponding memory array, characterized in that, The method includes: For each of the plurality of memory planes, generate (i) a corresponding Plane Ready (PRDY) signal and (ii) a corresponding Plane Array Ready (PARDY) signal; and In the memory, (i) a Synchronous Chip Operation (SCO) memory command and (ii) an Asynchronous Independent Plane Operation (AIPO) memory command are executed, wherein the SCO memory command sets multiple PARDY signals associated with the plurality of memory planes to indicate a busy state during the SCO background array operation phase of executing the SCO memory command, and the AIPO memory command sets at most one PARDY signal associated with a corresponding memory plane among the plurality of memory planes to a busy state during the AIPO background array operation phase of executing the AIPO memory command.

20. The method of operating a memory comprising a plurality of memory planes according to claim 19, characterized in that, Also includes: When the corresponding PRDY signal of the first memory plane is busy, new memory commands for the first memory plane among the plurality of memory planes are refused.

21. The method of operating a memory comprising a plurality of memory planes according to claim 19, characterized in that, Also includes: Generate a read plane status signal, the read plane status signal including (i) a ready or busy state corresponding to each of the plurality of PRDY signals of the plurality of memory planes and (ii) a ready or busy state corresponding to each of the plurality of PRDY signals of the plurality of memory planes; as well as Generate a plane-ready notification signal such that: In response to the transition of one or more of the plurality of PRDY signals from the busy state to the ready state, the plane ready notification signal transitions to the notification state. as well as In response to the generation of the read plane state signal, the plane ready notification signal transitions to the idle state.

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