Detection result recording and output device

Abstract

A detecting result recording and outputting device is located in an integrated circuit and is capable of recording and outputting detecting results generated at high speed at different speeds respectively. The device comprises a sensing circuit, a judging circuit, a storage circuit and a control circuit. The sensing circuit detects changes in characteristics of a target circuit and generates a plurality of detecting results at a first speed. The judging circuit receives the plurality of detecting results and generates a trigger signal or changes a level thereof when a first detecting result satisfies a preset condition. The control circuit writes the first detecting result and subsequent (N-1) detecting results into the storage circuit at a second speed according to the trigger signal. After the detecting results are written into the storage circuit, the control circuit reads the detecting results from the storage circuit at a third speed and outputs the detecting results at a fourth speed. The second speed is equal to or lower than the first speed but higher than the fourth speed.

Description

TECHNICAL FIELD

[0001] The present invention relates to a detection result recording and outputting device, and more particularly to a detection result recording and outputting device located in an integrated circuit. BACKGROUND

[0002] Integrated circuits (ICs) can experience voltage variations (IR drop) due to changes in the operating environment or workload. Users can want to know the voltage variation trends and voltage profiles of the circuits within the ICs to determine how to optimize the performance of the ICs.

[0003] However, the voltage variations within the ICs are very fast (e.g., nanoseconds), but the input / output interfaces (IO interfaces) of the ICs are usually slower (e.g., microseconds), so it is difficult for users to observe the voltage variations within the ICs through the IO interfaces of the ICs. SUMMARY

[0004] One of the objectives of the present invention is to provide a detection result recording and outputting device located in an integrated circuit, which can separately record and output detection results generated at different speeds.

[0005] One embodiment of the detection result recording and outputting device of the present invention comprises a sensing circuit, a judging circuit, a storage circuit, and a control circuit. The sensing circuit is used to detect changes in a characteristic of a target circuit and sequentially generates a plurality of detection results at a first speed according to the changes in the characteristic. The judging circuit is used to sequentially receive the plurality of detection results and generate a trigger signal or change the level of the trigger signal when a first detection result of the plurality of detection results satisfies a predetermined condition, wherein the first detection result is the first one to satisfy the predetermined condition among the plurality of detection results. The control circuit is used to write the first detection result and (N-1) detection results of the plurality of detection results into the storage circuit at a second speed according to the trigger signal when the first detection result satisfies the predetermined condition, wherein the first detection result and the (N-1) detection results total N detection results, and the (N-1) detection results continue the first detection result. The control circuit is also used to read the N detection results from the storage circuit at a third speed after M detection results of the N detection results are written into the storage circuit, and output the N detection results to an output interface of the integrated circuit at a fourth speed. The second speed is equal to or lower than the first speed; the fourth speed is lower than the second speed; N is an integer greater than 1; and M is a positive integer and equal to or less than N.

[0006] The features, implementations, and technical effects of the present invention are described in detail below with reference to preferred embodiments and the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0007] Figure 1 An embodiment of a detection result recording and output apparatus of the present disclosure is shown.

[0008] Figure 2a An embodiment of a detection result recording and output apparatus of the present disclosure is shown. Figure 1 An embodiment of a detection result recording and output apparatus of the present disclosure is shown.

[0009] Figure 2b An embodiment of a detection result recording and output apparatus of the present disclosure is shown. Figure 1 An embodiment of a detection result recording and output apparatus of the present disclosure is shown.

[0010] Figure 3 An embodiment of a detection result recording and output apparatus of the present disclosure is shown. Figure 1 An embodiment of a detection result recording and output apparatus of the present disclosure is shown.

[0011] LIST OF SYMBOLS

[0012] 10: target circuit

[0013] 100: detection result recording and output apparatus

[0014] 110: sensing circuit

[0015] 120: judging circuit

[0016] 130: storage circuit

[0017] 140: control circuit

[0018] 142: asynchronous FIFO buffer

[0019] S DET : multiple detection results

[0020] S TRIG : trigger signal

[0021] S DET_N : N detection results

[0022] Clk_A, Clk_B: clock

[0023] Clk_1, Clk_2, Clk_3: clock DETAILED DESCRIPTION

[0024] The present specification discloses a detection result recording and output apparatus, which is located in an integrated circuit (IC) and is capable of recording and outputting high-speed generated detection results at different speeds respectively.

[0025] Figure 1An embodiment of a detection result recording and output device of the present disclosure is shown. Figure 1 The detection result recording and output device 100 comprises a sensing circuit 110, a judging circuit 120, a storage circuit 130, and a control circuit 140, wherein the sensing circuit 110 and the judging circuit 120 can be selectively integrated as a sensor, such as Figure 1 as shown in the dashed box.

[0026] Please refer to Figure 1 . The sensing circuit 110 is used to detect a change in a characteristic of a target circuit 10, and sequentially generates a plurality of detection results S DET at a first speed according to the change in the characteristic. Both the target circuit 10 and the detection result recording and output device 100 are included in the aforementioned IC (not shown in the figure), so that the detection result recording and output device 100 can record the change in the characteristic of the target circuit 10 in real time. In an implementation example, the sensing circuit 110 comprises a running speed detection circuit (not shown in the figure), which is used to detect a running speed of the target circuit 10 to generate the plurality of detection results S DET , and the change in the characteristic is the change in the running speed; for example, the running speed detection circuit can be found in the U.S. patent application No. 16586157 or the U.S. patent application No. 17368436 applied by the applicant. In another implementation example, the sensing circuit 110 comprises an analog-to-digital conversion circuit (not shown in the figure), which is used to detect a power or a voltage of the target circuit 10 to generate the plurality of detection results S DET , and the change in the characteristic is the change in the power or the voltage. Both the running speed detection circuit and the analog-to-digital conversion circuit can be realized by known / self-developed technology, and the details are not within the discussion scope of the present disclosure.

[0027] Please refer to Figure 1 . The judging circuit 120 is used to sequentially receive the plurality of detection results S DET , and generate a trigger signal S TRIG or change the level of the trigger signal S TRIG when a first detection result of the plurality of detection results S DET satisfies a preset condition, wherein the first detection result is the first one that satisfies the preset condition among the plurality of detection results S DET . In an implementation example, each of the plurality of detection results S DET is a digital value, and the preset condition is a threshold value, and the judging circuit 120 is used to judge whether the digital value reaches the threshold value to judge the plurality of detection results S DETwhether each of the detection results S meets the preset condition. For example, the digital value can be the "number of enabled delay cells" as described in the aforementioned U.S. Patent Application No. 16586157 or the "margin of circuit operating speed" as described in the aforementioned U.S. Patent Application No. 17368436; the digital value can also be the output value of the aforementioned analog-to-digital conversion circuit; the determination circuit 120 uses the digital value to determine whether the digital value is equal to and / or less than the threshold value, to determine whether each of the detection results S DET meets the preset condition.

[0028] Please refer to Figure 1 . One embodiment of the storage circuit 130 is a memory (e.g., a static random access memory). In one implementation example, the storage circuit 130 can store at most N detection results, where N is an integer greater than one. In one implementation example, when the storage circuit 130 stores M detection results, the control circuit 140 actively starts to read the detection results from the storage circuit 130, where M is a positive integer and is not greater than N; for example, the control circuit 140 includes a counter (not shown in the figure) that counts a total number of detection results written into the storage circuit 130, and when the total number reaches M, the control circuit 140 is caused to actively read the detection results from the storage circuit 130; the counter can also be used to cause the control circuit 140 to stop writing any detection result into the storage circuit 130 when the total number reaches N. In one implementation example, when the storage circuit 130 stores M detection results, the storage circuit 130 actively notifies the control circuit 140, so that the control circuit 140 starts to read the detection results from the storage circuit 130.

[0029] As mentioned above. In one implementation example, M is less than N, after the control circuit 140 starts to read the detection results, the storage circuit 130 continues to receive and store subsequent detection results until the storage circuit 130 stores a total of N detection results, and the control circuit 140 reads the N detection results from the storage circuit 130. In another implementation example, M is equal to N, after the storage circuit 130 stores a total of N detection results, the storage circuit 130 stops storing subsequent detection results, and the control circuit 140 reads the N detection results from the storage circuit 130.

[0030] Please refer to Figure 1 . The control circuit 140 sequentially receives the detection results S DET at the first speed. The control circuit 140 is further used to, when the first detection result meets the preset condition, output the first detection result and the detection results S TRIG at the second speed according to the trigger signal S DETThe (N-1) detection results are written into the storage circuit 130, wherein the first detection result and the (N-1) detection results total N detection results S. DET_N The (N-1) detection results continue with the first detection result. The control circuit 140 is further used to process the N detection results S DET_N After the M detection results are written into the storage circuit 130, the N detection results S are read from the storage circuit 130 at a third speed. DET_N And output the N detection results S at a fourth speed. DET_N To an output interface of the aforementioned IC (e.g., the IC's input / output interface (IO interface) or register interface (not shown in the figure).

[0031] As stated above, the first speed reflects the rate of change of the characteristic of the target circuit 10, and therefore, the first speed is quite fast. Each of the second and third speeds is the speed of the access memory circuit 130, which may be equal to or lower than the first speed; for example, the second / third speed may be one-K times the first speed, where K is an integer greater than one. The third speed may be equal to or not equal to the second speed, depending on implementation requirements. The fourth speed is limited by the speed of the output interface, and therefore, the fourth speed will be lower than the second speed; if the third speed is lower than the second speed, the fourth speed may be equal to or not equal to the third speed.

[0032] Figure 2a An embodiment of the device 100 for displaying, recording, and outputting test results operates according to a clock. For example... Figure 2a As shown, the sensing circuit 110 outputs the multiple detection results S according to a clock Clk_A. DET The control circuit 140 and the storage circuit 130 receive the N detection results S from the control circuit 140 according to the clock Clk_A. DET_N The control circuit 140 transmits the N detection results S according to a clock Clk_A. DET_N The storage circuit 130 receives and outputs the N detection results S according to a clock Clk_B. DET_N The speed of clock Clk_B is slower than the speed of clock Clk_A. Figure 2b In another embodiment of the display and output device 100, which operates according to a clock, the control circuit 140 includes an asynchronous first-in-first-out buffer 142. For example... Figure 2b As shown, the asynchronous first-in-first-out buffer 142 receives the multiple detection results S from the sensing circuit 110 according to a clock Clk_1. DET, another clock Clk_2 is used to read the N detection results S DET_N to the storage circuit 130, and the control circuit 140 receives and outputs the N detection results S DET_N , wherein the speed of the clock Clk_2 can be equal to or slower than the speed of the clock Clk_1, and the speed of the clock Clk_3 is slower than the speed of the clock Clk_2. Since the technology of implementing different operating speeds according to different clocks and the asynchronous first-in-first-out buffer are common in the art, the details are omitted here.

[0033] Figure 3 display Figure 1 the change of the supply voltage of the target circuit 10, the N detection results S DET (sequence: 8, 8, 8, 7, 4, 3, 2, 4, 6, 9, 11, 10, 10, 8, 7, 6, 7), the trigger signal S TRIG the change of the supply voltage of the target circuit 10, the N detection results S DET_N (sequence: 7, 4, 3, 2, 4, 6, 9, 11, 10, 10, 8, 7, 6, 7, wherein N=14). As shown in Figure 3 the N detection results S DET become smaller when the supply voltage decreases (for example, when multiple circuits in the system containing the target circuit 10 are started at the same time); when a detection result (i.e., the aforementioned first detection result) is less than the value 8 (i.e., the aforementioned threshold value), the level of the trigger signal S TRIG is pulled high; when the level of the trigger signal S TRIG is pulled high, the N detection results S DET_N start to be read out and output. It is worth noting that according to different detection circuit designs, there can be a time delay between the occurrence time of the change of the supply voltage and the generation time of the N detection results S DET , as shown by the dashed arrow in Figure 3 .

[0034] Please note that, under the premise of implementation, the person skilled in the art can selectively implement part or all of the technical features in any of the foregoing embodiments, or selectively implement part or all of the technical features of the foregoing embodiments in combination, to flexibly implement the present application.

[0035] In summary, the present application can record and output high-speed generated detection results at different speeds, respectively.

[0036] Although the present application has been described in connection with the embodiments thereof, it will occur to those skilled in the art that modifications can be made of the present application, that depart from the specific designs chosen, yet those modifications will fall within the scope of the present application as defined in the claims appended hereto.

Claims

1. A detection result recording and output device, the detection result recording and output device being located within an integrated circuit, comprising: A sensing circuit is used to detect a change in a characteristic of a target circuit and generate multiple detection results sequentially at a first speed based on the change in the characteristic. A judgment circuit is used to receive the plurality of detection results in sequence, and when a first detection result of the plurality of detection results meets a preset condition, generate a trigger signal or change the level of the trigger signal, wherein the first detection result is the first one to meet the preset condition among the plurality of detection results. A storage circuit; as well as A control circuit is configured to, when the first detection result meets the preset condition, write the first detection result and (N-1) other detection results into the storage circuit at a second speed according to the trigger signal, whereby the first detection result and the (N-1) other detection results total N detection results, and the (N-1) other detection results continue from the first detection result. The control circuit is further configured to, after M of the N detection results have been written into the storage circuit, read the N detection results from the storage circuit at a third speed, and output the N detection results to an output interface of the integrated circuit at a fourth speed. Wherein the second speed is equal to or lower than the first speed, the fourth speed is lower than the second speed, N is an integer greater than one, and M is a positive integer equal to or less than N.

2. The detection result recording and output device as claimed in claim 1, wherein the sensing circuit includes a running speed detection circuit, the running speed detection circuit being used to detect a running speed of the target circuit, and the change in the characteristic being a change in the running speed.

3. The detection result recording and output device as claimed in claim 1, wherein the sensing circuit includes an analog-to-digital conversion circuit, the analog-to-digital conversion circuit being used to detect a power or a voltage of the target circuit, the change in the characteristic being a change in the power or a change in the voltage.

4. The detection result recording and output device as described in claim 1, wherein each of the plurality of detection results is a digital value, the preset condition is a threshold value, and the judgment circuit is used to determine whether the digital value reaches the threshold value, so as to determine whether each of the plurality of detection results satisfies the preset condition.

5. The detection result recording and output device as described in claim 1, wherein the storage circuit can store up to N detection results.

6. The detection result recording and output device as claimed in claim 1, wherein the control circuit includes a counter for counting a total number of detection results written to the storage circuit, and when the total number reaches M, the control circuit reads and outputs the N detection results.

7. The detection result recording and output device as claimed in claim 1, wherein the second speed is one-K times the first speed, and K is an integer greater than one.

8. The detection result recording and output device as claimed in claim 1, wherein the second speed is equal to the first speed.

9. The detection result recording and output device as claimed in claim 1, wherein the third speed is equal to or not equal to the second speed.

10. The detection result recording and output device as claimed in claim 9, wherein the third speed is lower than the second speed, and the fourth speed is equal to or not equal to the third speed.

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