Method, control system and apparatus for processing semiconductor wafers, and semiconductor wafer

Abstract

The invention relates to a method of processing a semiconductor wafer (600), wherein the semiconductor wafer (600) is placed on a susceptor (310) in a coating device (300), and then processed in a processing operation, wherein an etching gas is passed through the coating device (300) in an etching step of the processing operation. The invention further relates to a control system (400) for controlling a coating device (300) for processing a semiconductor wafer (600), to an apparatus (500) for processing a semiconductor wafer (600) having a coating device (300), comprising the control system, and to a semiconductor wafer (600). The method is characterized in that a first side (FS) of the semiconductor wafer (600), which has been subjected to a polishing operation by CMP, or a second side (BS) of the semiconductor wafer (600) opposite to the first side, is coated with a protective layer (601) prior to the processing operation.

Description

[0001] This application is a divisional application of the application with the application number 201880041643.7, the title "Method, control system and apparatus for processing semiconductor wafers, and semiconductor wafer" filed on 4 June 2018. TECHNICAL FIELD

[0002] The present invention relates to a method for processing semiconductor wafers, a control system for controlling a coating apparatus for processing semiconductor wafers, an apparatus for processing semiconductor wafers having such a processing apparatus and control system, and a semiconductor wafer. BACKGROUND

[0003] Semiconductor wafers, in particular silicon wafers, are suitable for use, for example, in the semiconductor industry, in particular for the production of highly integrated electronic components, such as microprocessors or memory chips. For modern microelectronics, the raw material, referred to as a substrate, has high requirements in terms of overall and local flatness, edge geometry, thickness distribution, local flatness based on a single side (referred to as nanotopology) and freedom from defects.

[0004] In order to obtain semiconductor wafers having these properties, various processing operations can be carried out on these semiconductor wafers. These include, in particular, double-sided polishing (referred to as DSP), in which both sides of a semiconductor wafer are simultaneously subjected to a material-removing treatment by means of two working surfaces in one processing step, preferably in such a way that the treatment forces acting on the front and back sides of the semiconductor wafer are essentially in equilibrium during the material-removing process and the guiding apparatus does not exert a constraining force on the semiconductor wafer, i.e. the semiconductor wafer is processed in a "free-floating" manner. In this case, it is in particular possible to insert a plurality of semiconductor wafers into one or more "carrier plates" having recesses for the semiconductor wafers and then to polish them by means of forces acting on both sides of the semiconductor wafers. A DSP process for silicon wafers is described, for example, in US 2003 / 054650 A1, and an apparatus suitable therefor is described in DE 100 07 390 A1.

[0005] A further processing operation that is useful is chemical mechanical polishing ("CMP"), known, for example, from DE 10 2008 045 534 B4. In this case, the semiconductor wafer is pressed against a polishing pad (which can be on a polishing plate) by means of a carrier and then moved in rotation, usually under pressure. By using a suitable polishing medium or polishing medium suspension, one side of the semiconductor wafer is then polished.

[0006] A further processing operation which is useful is a coating operation, for example known from DE 10 2005 045 339 A1. In epitaxial coating of a semiconductor wafer, deposition gas is passed through an epitaxial reactor, as a result of which material can be deposited epitaxially on the surface of the semiconductor wafer. However, in addition to on the semiconductor wafer, material is always deposited in the epitaxial reactor as well. Therefore, it is often necessary to remove such residues which are deposited uncontrolled on the surfaces in the epitaxial reactor during the deposition process from time to time.

[0007] In all the processing steps described above, inhomogeneities can occur both in the radial and in the circumferential direction. One prominent example to be mentioned here is the fourfold symmetry of an epitaxially deposited layer, one reason for which is the different growth rates along the different crystal axes.

[0008] Against this background, the problem to be solved is to specify a method of obtaining a better semiconductor wafer, in particular a better semiconductor wafer in terms of the flatness of its surface. SUMMARY

[0009] What is proposed according to the invention is a method for processing a semiconductor wafer, a control system and a device for processing a semiconductor wafer and a semiconductor wafer having the features of the independent claims. Advantageous embodiments are the dependent claims and the subject matter described below.

[0010] The invention starts from a method of processing a semiconductor wafer, wherein the semiconductor wafer is arranged on a susceptor in a coating device. A useful coating device here is in particular an epitaxial reactor. The method comprises one or more processing operations, wherein one such processing operation comprises an etching step and optionally a deposition step. During the etching step, an etching gas is passed through the coating device. The etching gas preferably consists of a mixture of hydrogen chloride and hydrogen, although the etching gas can also consist of hydrogen chloride alone or of hydrogen alone.

[0011] During any deposition step, a deposition gas is passed through the coating device to deposit a layer epitaxially on the semiconductor wafer. A useful deposition gas here is in particular trichlorosilane. It is particularly preferred when the processing operation comprises an etching step followed by a deposition step.

[0012] The etching step can serve to at least partially remove any deposits or depositions in the coating device or epitaxial reactor which originate from a previous deposition step. Such deposits affect the flow of gas in the coating device and the temperature gradient and thus also the layer which can be deposited epitaxially on the semiconductor wafer by the deposition gas. The etching step can also serve to achieve a higher material removal in the middle of the semiconductor wafer than at the edge.

[0013] It has now been found that under conditions selected in the context of the present application, material is removed in the etching step on the side of the semiconductor wafer that is remote from the susceptor, but material is deposited on the side facing the susceptor, in particular in the edge region or in the region of the semiconductor wafer adjoining the susceptor. The way in which this occurs is, inter alia, that the etching gas (in the equilibrium reaction) dissolves the material present in the coating apparatus, for example the material deposited in a previous deposition operation, and then deposits it again on the semiconductor wafer, or material present on the susceptor from a previous process step is bound to the wafer material to be processed and is entrained when the coating apparatus is unloaded.

[0014] It is envisaged according to the present application that one of the two sides of the semiconductor wafer is coated with a protective layer before the process operation. The first side (FS) of the semiconductor wafer, which has been polished by a CMP (chemical mechanical polishing) polishing operation, or the second side (BS) of the semiconductor wafer, which is opposite the first side and which can have been polished by a CMP, is coated. Preferably, the semiconductor wafer that is coated with a protective layer is a semiconductor wafer having a first side and a second side that have been simultaneously polished by a double side polishing (DSP), the first side (FS) having been polished by a polishing operation of a CMP after the double side polishing. The semiconductor wafer is preferably a semiconductor wafer composed of monocrystalline silicon and preferably has a diameter of not less than 200 mm, more preferably of not less than 300 mm. The protective layer that is useful preferably comprises an oxide layer, in particular a low temperature oxide (LTO) layer. The term "low temperature oxide layer" or "LTO" means herein an oxide layer applied by a specific method. An example that can be envisaged is silicon dioxide. In order to obtain particularly good results, the thickness of the layer can be in particular at most 200 nm, preferably at most 150 nm, more preferably at most 100 nm. It can be additionally appropriate to form the protective layer with an edge exclusion of not more than 0.5 mm, preferably of not more than 0.2 mm, more preferably of not more than 0.1 mm, which means that the respective area at the edge of the semiconductor wafer is not coated or covered by the protective layer. In this case, the etching step can be appropriately carried out in the coating apparatus at a temperature of 1000 °C to 1250 °C, preferably of 1100 °C to 1150 °C. Alternatively, the protective layer can be a silicon dioxide protective layer that is produced by an RTA (rapid thermal annealing) heat treatment.

[0015] The presence of the protective layer on the first side (FS) or on the second side (BS) prevents the removal of material from the side of the semiconductor wafer having the protective layer in the etching step. This makes use of the fact that, for example, the etching gas attacks the oxide of the semiconductor material and thus etches it much less than the corresponding pure semiconductor material. In addition, the protective layer also prevents the material transport and the deposition of material when in contact with the susceptor, as described at the outset.

[0016] If the protective layer is on the side facing away from the susceptor during the etching step, no operation of depositing material, particularly in the edge region of this side, takes place. In a first preferred embodiment of the application, the first side (FS) is the side on which the protective layer is arranged, and the second side (BS) is the side facing the susceptor during the etching step. In this case, the etching step is employed in order to deposit material, particularly in the edge region of the second side (BS). After the etching step and the removal of the protective layer, an epitaxial layer can be deposited on the first side (FS).

[0017] If the protective layer is on the side facing the susceptor during the etching step, no operation of depositing material, particularly in the edge region of this side, takes place. In a second preferred embodiment of the application, the second side (BS) is the side on which the protective layer has been arranged and which faces the susceptor during the etching step. In this case, the etching step is employed in order to remove material from the first side (FS). Preferably, the etching step is followed by a deposition step, during which an epitaxial layer is deposited on the first side (FS). The protective layer is removed before or after the deposition of the epitaxial layer.

[0018] In a third preferred embodiment of the application, the processing operations are divided into a first etching step and a second etching step, and the second etching step is followed by a deposition step, during which an epitaxial layer is deposited on the first side (FS). During the first etching step, the first side (FS) is the side on which the protective layer has been arranged, and the second side (BS) is the side facing the susceptor during the etching step. After the first etching step, the protective layer is removed from the first side (FS), and the second side (BS) is arranged with a protective layer. During the second etching step, the second side (BS) is the side on which the protective layer has been arranged and which faces the susceptor. After the second etching step or after the deposition of the epitaxial layer on the first side (FS) of the semiconductor wafer, the protective layer is removed from the second side (BS).

[0019] If the method is performed in one of the described embodiments, both sides of the semiconductor wafer can be processed independently of one another and in a controlled manner.

[0020] The second preferred embodiment of the present invention is particularly suitable to counteract the symmetrical variation of the thickness that occurs in the edge region of the semiconductor wafer after coating the semiconductor wafer with an epitaxial layer. The variation of the thickness is due to the fact that in the deposition of the epitaxial layer, the material is deposited at different rates in the edge region depending on the polar angle. For example, an epitaxial layer of monocrystalline silicon, without further measures, grows faster at the polar angle positions of 0°, 90°, 180° and 270° than at the polar angle positions that are shifted by 45° relative to the positions mentioned on a {100} oriented monocrystalline silicon semiconductor wafer having an orientation notch indicating the <110> direction and defining the 0° polar angle position. Thus, in the four regions of a circumference that are equal in distance to each other, the thickness of the epitaxially coated semiconductor wafer is greater than in the regions between both (called fourfold symmetry).

[0021] It has been found that when the process according to the second preferred embodiment of the present invention is carried out before the deposition of the epitaxial layer, the thickness of the epitaxially coated semiconductor wafer in the edge region can be made uniform. In the edge region, at those points where the material is deposited at a higher rate during the deposition of the epitaxial layer, the rate of material removal that occurs on the first face (FS) during the etching step is greater. This effect that occurs during the etching step is referred to in the following as anti-fourfold symmetry etching (4FSE). In particular, the removal of material to be achieved locally is guided by the duration of the etching step. For example, the procedure in the second preferred embodiment of the present invention can be used in combination with the deposition of the epitaxial layer to obtain an epitaxially coated semiconductor wafer that has a more uniform thickness profile in the circumferential direction.

[0022] Therefore, for the manufacture of a semiconductor wafer of silicon, the second preferred embodiment of the present invention is preferably employed, wherein the first face (FS) has been coated with an epitaxial layer of silicon, and wherein the first face (FS) has a {100} orientation or a {110} orientation.

[0023] The first preferred embodiment of the present invention is particularly suitable to counteract any edge roll-off caused by the DSP and possibly by the CMP on the first face (FS) and / or the second face (BS). The material deposited in the edge region of the second face (BS) locally increases the thickness of the semiconductor wafer and ensures that the thickness is radially homogenized, respectively. The amount and the position of the deposited material can be influenced by configuring the susceptor and the duration of the etching step. At least within an etching time of 60 s, a linear growth of the deposited material will be observed. The susceptor preferably has a downwardly inclined ledge on which the edge region of the semiconductor wafer is located. The radial width of the ledge and the angle of inclination of the ledge are influencing parameters that should be considered in particular in the configuration of the susceptor. The third preferred embodiment of the present invention essentially comprises a combination of the first preferred embodiment and the second preferred embodiment.

[0024] During the etching step or during the first and second etching steps, the volume flow rate of hydrogen chloride is preferably not less than 2 slm and not more than 5 slm; the volume flow rate of hydrogen is preferably not less than 30 slm and not more than 110 slm, more preferably not less than 40 slm and not more than 70 slm (standard liters per minute). Particularly smooth surfaces are produced at a volume flow rate of hydrogen chloride of 4 slm and a volume flow rate of hydrogen of 50 slm. These gas flow rates make it possible to achieve, for example, a higher material removal in the middle of the semiconductor wafer than at the edge.

[0025] The proposed process with respect to etching against tetramorphy (4FSE) can reduce the tetramorphy after the coating, wherein a longer duration of the etching step (with a flow of etching gas) leads to less remaining tetramorphy. In general, the maximum possible duration in this process is due to the fact that, in the case of a too long duration of the etching step, the deposition on the second side (BS) leads to a degradation of the local geometry (planarity) of the semiconductor wafer. Here, this problem is solved by the protective layer, since an unnecessary material deposition is suppressed. In addition, by a skilled combination of the inhomogeneities occurring in the treatment with the coating device and other previous polishing operations, a significantly better planarity can be achieved than hitherto.

[0026] It should be noted that the treatment operations after the etching step can also - as a matter of course - comprise a deposition step in which the protective layer is also present. However, it is also possible to use only the etching step in order to selectively remove material without depositing it again. In the case of a plurality of treatment operations, it is also conceivable to carry out the deposition step only in some of the treatment operations, i.e. for example only in the first of two treatment operations.

[0027] With the proposed method, it is possible to obtain a semiconductor wafer, in particular a silicon wafer, having better values on the requirements mentioned at the beginning. Such a semiconductor wafer can be a single-crystal silicon semiconductor wafer whose at least one side has been polished by CMP, or a single-crystal silicon semiconductor wafer which has been coated with a single-crystal silicon layer epitaxially. The semiconductor wafer has an ESFQR max with an edge exclusion of not more than 2 mm and 72 sectors, each of which has a length of 30 mm. Preferably, the semiconductor wafer has an ESFQR max with an edge exclusion of not more than 1 mm and 72 sectors, each of which has a length of 30 mm. More preferably, the semiconductor wafer has an ESFQR max with an edge exclusion of not more than 0.5 mm and 72 sectors, each of which has a length of 30 mm. Such a semiconductor wafer also forms part of the subject matter of the present application.

[0028] SFQR stands for "surface front reference least square / range" and its value represents the flatness of the semiconductor wafer. More particularly, this relates the positive and negative deviations of the surface from a flat reference surface. Typically, the deviations are used separately for the calculation of areas of a certain size on the surface of the semiconductor wafer. ESFQR stands for "edge surface front reference least square / range" and its value is defined as the SFQR value, but only for the edge areas of the semiconductor wafer. ESFQD av stands for "edge surface front reference least square / deviation" and the subscript av indicates the average of the ESFQD values of the edge sites in the circumferential area of the semiconductor wafer. Typically, the circumferential area comprises 72 such sites (sectors).

[0029] The definitions and test methods of the mentioned wafer parameters are included in the standards SEMI M67 (ESFQR and ESFQD) and SEMI M1 5 SEMI MF1530 and SEMI M49 (SFQR).

[0030] Another advantage of the protective layer is that the semiconductor wafer cannot be fixed to the susceptor by growth when the protective layer is adjacent to the susceptor in the deposition step. The reason for this is that the protective layer is made of a different material. For example, silicon dioxide hardly bonds with silicon. In this way it can be achieved that, when the semiconductor wafer is removed from the susceptor, also no material is removed from the susceptor, so, more particularly, only a significantly smaller stress occurs in the semiconductor wafer, particularly in the edge areas, if at all. This effect already occurs when the coating device is heated, i.e. regardless of whether an etching step or a deposition step is carried out.

[0031] Preferably, the protective layer is removed again from the semiconductor wafer after the processing operation, particularly depending on what should happen to the semiconductor wafer subsequently. For example, a further processing operation can then be carried out, before the other side is provided with a protective layer again. At the end of all processing operations carried out using the coating device, the protective layer can be removed to obtain the final semiconductor wafer. For example, hydrofluoric acid (HF) can be used to remove the protective layer, particularly in the case of an oxide layer on a silicon wafer, since it dissolves the oxide but not the silicon.

[0032] It is also particularly preferred when the semiconductor wafer is polished on at least one of the two sides in one or more polishing operations using a polishing device before one or more processing operations. A suitable device here is the polishing device mentioned at the outset for chemical mechanical polishing (CMP), which allows a controllable treatment of only one side. More particularly, the polishing can be carried out here in such a way that the individual areas of the semiconductor wafer are affected to a different extent in the treatment, particularly by specifying different pressures on the individual areas of the semiconductor wafer in each case.

[0033] This different pressure can be generated, for example, by a suitably designed carrier of the respective polishing device, by which the pressure is exerted on the semiconductor wafer. Thus, the pressure can be defined specifically for individual regions or zones of the semiconductor wafer. Thus, a recipe (for the respective operating parameters of the polishing device) can be defined separately for each semiconductor wafer. It is thus in particular possible to counteract the undesired components of the material build-up at the edge of the semiconductor wafer that occur in the coating device in subsequent processing operations.

[0034] It is particularly advantageous here for at least one operating parameter in the polishing operation to be defined as a function of at least one operating parameter in the processing operation and / or as a function of a wafer parameter that can be expected by means of the polishing operation or the processing operation. Useful wafer parameters include, for example, ESFQD av values or other parameters by means of which the flatness or planarity can be reported. In this way, it is thus possible in a controlled manner to exploit the interaction between the polishing operations on the one hand and the processing operations in the coating device on the other hand in order to achieve a semiconductor wafer that is overall more planar. More particularly, it is possible in a controlled manner to compensate for any disadvantageous removal of material in the polishing operation in the coating, and vice versa. In particular, it is also possible in this way to take into account operating parameters of individual devices, which would not be taken into account in a conventional process in which each device is optimized separately, since they would lead to poorer results for the respective device itself. However, this is no longer the case when a plurality of devices are taken into account in combination.

[0035] For the sake of completeness, it should also be noted that, before the polishing operation of the chemical-mechanical polishing, a polishing operation of the double-side polishing (as described at the outset) can also be provided. The operating parameters relating to this polishing operation can then also be taken into account for the other polishing and / or processing operations and their operating parameters.

[0036] The application also provides a control system for controlling a coating device for processing semiconductor wafers, in which etching gas can be passed in a processing operation and / or a layer can be deposited epitaxially on a semiconductor wafer, and also in particular for controlling a polishing device in which a semiconductor wafer can be polished in a polishing operation. In use with a coating device, in particular with a polishing device, the control system is set up to implement the method of the application.

[0037] The application also provides a device for processing semiconductor wafers, which has a coating device in which etching gas can be passed in a processing operation and / or a layer can be deposited epitaxially on a semiconductor wafer, and also in particular has a polishing device in which a semiconductor wafer can be polished in a polishing operation, and also has a control system of the application.

[0038] As to further constructions and advantages, as well as control systems and devices, reference is made to the description of the method proposed, which is accordingly applicable herewith.

[0039] Further advantages and embodiments of the application will become apparent from the description and drawings.

[0040] It is understood that the features specified above and still to be elucidated hereinafter can be used not only in the particular combinations indicated, but also in other combinations or alone, without departing from the scope of the present application.

[0041] The application is described hereinafter with reference to the drawings. BRIEF DESCRIPTION OF DRAWINGS

[0042] Figure 1 A schematic representation of the device of the application is shown in a preferred embodiment, with which the method of the application can be performed.

[0043] Figure 2 A schematic representation of a first polishing apparatus usable in the context of the method of the application is shown.

[0044] Figure 3 A schematic representation of a second polishing apparatus usable in the context of the method of the application is shown.

[0045] Figure 4 A schematic representation of a coating apparatus usable in the context of the method of the application is shown.

[0046] Figure 5 A schematic representation of a semiconductor wafer with a protective layer is shown in various views.

[0047] Figure 6 A schematic representation of the distribution of the thickness difference over the diameter of two semiconductor wafers after the etching step in the coating apparatus in the context of the method of the application is shown.

[0048] Figure 7 A schematic representation of the distribution of the thickness difference over the entire circumference of a semiconductor wafer after the etching step in the coating apparatus in the context of the method of the application is shown.

[0049] Figure 8 A schematic representation of the process of three preferred embodiments of the method of the application is shown.

[0050] Figure 9 and Figure 10 Measurement results of two epitaxially coated semiconductor wafers are shown, which relate to the thickness difference in the edge region.

[0051] Figure 11 A flowchart of the control of the operating parameters is shown. DETAILED DESCRIPTION

[0052] Figure 1 A schematic diagram of an apparatus 500 of the present application is shown, with which the method of the present application can be performed. The apparatus 500 is used for processing a semiconductor wafer 600 and comprises, as processing devices, a first polishing device 100, a second polishing device 200 and a coating device 300. These three processing devices are used for processing the semiconductor wafer 600, which can pass through the individual processing devices in succession. For the sake of completeness, it should be mentioned here again that further processing devices can also be provided before, between and / or after these processing devices, but if at all, these have at least virtually no relevance for the present application. Of particular relevance for the present application is the coating device 300 and, according to this embodiment, also the second polishing device 200, which is incidentally also referred to as polishing device only. However, the first polishing device 100 shown here can also be used for the processing of the semiconductor wafer, more precisely this is indeed conventional. For a more detailed description of the individual processing devices, reference is made here to Figures 2 to 4 .

[0053] In addition, the apparatus 500 comprises a control system 400, which can be used with the three processing devices shown to activate or operate them. In the embodiment shown, the control system 400 comprises three separate control units 410, 420 and 430, each of which is provided for activating or operating one of the three processing devices. By means of the respective control unit, at least one operating parameter can in particular be defined or set for the respective processing device in each case.

[0054] For each of the control units 410, 420 and 430, a measurement device 411, 421 and 431 is provided in each case, respectively. By means of these measurement devices, at least one wafer parameter of the semiconductor wafer can be measured after processing the semiconductor wafer in the respective processing device. It is apparent that these measurement devices can also be integrated into the respective control unit, depending on the application.

[0055] In addition, a central control unit 440 is shown here, which is connected to each of the control units 410, 420 and 430 and to each of the measurement devices 411, 421 and 431. This connection comprises at least one connection for data transmission, for example in wired or wireless form. The values determined by the individual measurement devices 411, 421 and 431 can be transmitted in this way to the central control unit 440, so that suitable operating parameters for the individual processing devices can be determined by means of the central control unit 440, which can then be transmitted to the individual control units 410, 420 or 430. It is apparent that the determination of the individual processing parameters can also be implemented in other ways, for example directly in one of the individual control units.

[0056] Figure 2 In the form of a diagram and compared Figure 1 The first polishing apparatus 100 (for DSP) is shown in more detail, in cross-section. In this case, four semiconductor wafers 600 (of which only the two in the left half are given reference numerals) in corresponding recesses of a carrier plate 130 are inserted between an upper polishing plate 110 and a lower polishing plate 111, the carrier plate 130 being moved by means of an inner gear ring 131 and an outer gear ring 132 referred to as a rolling device.

[0057] A polishing pad 121 is provided on the lower polishing plate 111. A polishing pad 120 is provided on the upper polishing plate 210. The polishing plate 110 and the polishing pad 120 are pressed together in the direction of polishing or contact pressure p1 onto the carrier plate 130, the semiconductor wafer 600 and the lower polishing plate 111 with the polishing pad 121.

[0058] The upper polishing plate 110 and the lower polishing plate 111 can rotate or rotate at rotational speeds ω1 and ω2. Two rotational speeds in opposite directions are shown here, but they can also have the same direction of rotation but different magnitudes, for example, according to this application. Changing the rotational speed during operation is also possible—and similarly, changing the contact pressure or polishing pressure. For polishing, a suitable polishing medium can be applied to the polishing pad.

[0059] Figure 3 In the form of a diagram and compared Figure 1 A second polishing apparatus 200 (for CMP), which can be used in the method of the present invention in a preferred embodiment, is shown in more detail, in cross-section. Here, a semiconductor wafer 600 has been applied onto a polishing pad 220, which is in turn arranged on a polishing plate 210. The semiconductor wafer 600 is pressed onto the polishing pad 220 by means of a carrier 230. During polishing, the carrier 230 rotates about a first axis at a rotational speed ω3, and the polishing plate 210 rotates about a second axis at a rotational speed ω4. Additionally, the carrier can move at a radial speed v1 (inward or outward). For polishing, a suitable polishing medium can be applied to the polishing pad.

[0060] More specifically, in another case, the pressure that can be applied to the semiconductor wafer 600 can be set differently for different regions by means of the carrier 230. In the simplified embodiment shown, pressure p2 can be applied in the radially outer region 231, while pressure p3 can be applied in the radially inner region 232. These pressures p2 and p3 are particularly useful operating parameters for the second polishing apparatus. It is also conceivable that rotational speeds ω3 and ω4 and radial velocity v1 can be used additionally or alternatively as operating parameters.

[0061] The pressure can be selected such that, for example, pressure p2 is greater than pressure p3. More specifically, the magnitude of the pressure can also be specifically set. Obviously, even more different zones can be provided in the radial direction, in which the pressure is individually adjustable.

[0062] Figure 4 In the form of a diagram and compared Figure 1 The coating apparatus 300 in the preferred embodiment is shown in more detail. This coating apparatus 300 is in the form of a vapor-phase epitaxial reactor available in the context of the method of the present invention, shown in cross-section. In the center of the coating apparatus 300 is a base 310 on which the semiconductor wafer 600 to be coated is disposed. The base 310 has a recess in the center such that the semiconductor wafer 600, for example, only a few millimeters of its edge, lies on the base 310.

[0063] Gas can pass through the epitaxial reactor 300, in this embodiment from the left opening of the epitaxial reactor 300 to the right opening of the epitaxial reactor 300, as indicated by the two arrows. Gas passes through the epitaxial reactor 300 by means of heaters, such as heating lamps 330 on the upper and lower sides of the epitaxial reactor 300, one of which is exemplarily provided with reference numerals, and the semiconductor wafer can be heated to the desired temperature as needed.

[0064] In the case of a coating operation, an etching gas, such as a mixture of hydrogen chloride and hydrogen, is then passed through the epitaxial reactor 300 in an etching step, thereby pretreating the semiconductor wafer in a controlled manner before any subsequent deposition step. Without such a subsequent deposition step, controlled material removal may also be performed, for example. Preferably, the volumetric flow rate of hydrogen chloride can be set to 4 slm, and the volumetric flow rate of hydrogen can be set to 50 slm.

[0065] To coat the semiconductor wafer 600 or deposit an epitaxial layer, a deposition gas, such as trichlorosilane, optionally mixed with hydrogen, is passed through the epitaxial reactor 300. The volumetric flow rate f1 and / or the duration of passage and / or temperature can be adjusted as operating parameters, for example, according to the desired thickness of the layer to be epitaxially deposited on the semiconductor wafer 600. Additionally, the substrate 310 on which the semiconductor wafer 600 is disposed can rotate about an axis at a defined rotational speed ω5, which is also an additional or alternative operating parameter, as shown. In this way, uniform deposition of the epitaxial layer can be achieved.

[0066] In the case of a coating operation, the etching gas, for example a mixture of hydrogen chloride and hydrogen, can be passed through the epitaxy reactor 300 in an etching step before the deposition gas is passed, thus pre-treating the semiconductor wafer in a controlled manner before the actual coating operation. Preferably, the volume flow rate of the hydrogen chloride here can be set to 4 slm and the volume flow rate of the hydrogen can be set to 50 slm.

[0067] Figure 5 A semiconductor wafer 600 is shown in various views, which can be used in the method of the application in various preferred embodiments.

[0068] In the upper view, a protective layer 601, for example silicon dioxide, has been applied to the first side (FS) of the semiconductor wafer 600. The silicon dioxide can be applied, for example, by a conventional method in which the layer then exists in the form of an LTO (low temperature oxide) layer. The second side (BS) of the two sides is uncoated. The protective layer 601 is provided here up to the edge excluding dl, for example, which can be 0.1 mm.

[0069] In the middle view, a protective layer 601, for example also silicon dioxide, has been applied on the second side (BS) of the semiconductor wafer 600. The first side (FS) is uncoated.

[0070] In the lower view, the semiconductor wafer 600 has now been applied to the susceptor 310 of the coating device or the epitaxy reactor 300, as shown in Figure 4 In this case, the protective layer 601 has been applied to the second side (BS), and the semiconductor wafer 600 is then also located in the application area 311 on the susceptor 310. The semiconductor wafer overlaps the application area 311 or the susceptor 310 in the radial direction by a size d2. This size d2 can be, for example, 1 mm. It should be noted in this regard that the figures are not drawn to scale; rather, the individual dimensions are disproportionate.

[0071] Figure 6 In each case, a radial profile of the thickness difference th (nm) over the entire diameter d (mm) of two semiconductor wafers after passage through the coating device in the context of the method of the application is shown, here in each case after an etching step of a duration of 60 s in the coating device, in which one side is covered by a semiconductor wafer with a protective layer. The thickness difference is found by comparing the thicknesses of the respective semiconductor wafers measured before and after the etching step. For reasons of legibility of the graphs, a global offset has been subtracted in order to bring the minimum value of the wafer thickness close to zero.

[0072] The top diagram shows the typical profile of the thickness difference which occurs in the etching step when the second side (BS) is covered by the protective layer and this side is the one facing the susceptor. Here it can be clearly seen that a difference in material removal in the radial direction occurs. Due to the protective layer, this is essentially material removal from the first side (FS).

[0073] The bottom diagram shows the typical profile of the thickness difference in the etching step when the first side (FS) is covered by the protective layer and the second side (BS) faces the susceptor. Here it can be clearly seen that during the etching step, there is a selective material growth very close to the edge, i.e. in particular in the region lying on the susceptor, as Figure 5 is shown in the bottom. Due to the protective layer on the first side (FS), this is essentially material deposited on the second side (BS).

[0074] Thus, by the proposed method, in particular the two sides of the semiconductor wafer can be treated separately from one another and with the action of material removal and material growth separately from one another and in a controlled manner. More particularly, for each treatment operation, a set of operating parameters tailored to the treatment of one side can be established. Without the protective layer, this would not be possible, because with whatever operating parameters are chosen, the treatment operation would simultaneously change the properties of both sides.

[0075] Figure 7 In the form of a diagram, the typical profile of the thickness difference th in the circumferential direction of the semiconductor wafer mentioned already with the {100} orientation after the etching step in the coating device when in the etching step the second side (BS) has been covered by the protective layer and the second side (BS) is the one facing the susceptor is shown (polar angle with respect to the radius of approximately 148 mm in degrees).

[0076] It is apparent that there are four regions per deviation of 90° in which the material removal is greater. Due to the crystal structure, it is found that when using etching gases, the material removal here is greater than in the regions in between. The thickness difference is approximately 10 nm. The position of the regions with greater material removal on the circumference of the semiconductor wafer corresponds to the position of the four regions in which the epitaxial layer grows more quickly. This result can be utilized preferably by combining the etching step and the deposition step, with the aim that the greater removal of material during the etching step and the greater increase of material during the deposition step lead to a thickness of the epitaxially coated semiconductor wafer which is essentially uniform in the circumferential direction and has the desired value.

[0077] Figure 8A schematic diagram showing the process of the three preferred embodiments of the inventive method. Regardless, the present invention also comprises embodiments which relate to the combination of coating a specific face of the semiconductor wafer with a protective layer and placing the specific face on a susceptor of a coating device such that the face faces the susceptor. The preferred embodiments (a), (b) and (c) shown first comprise a polishing operation by a polishing device 200. Obviously, the polishing operation (here: CMP) can also be performed after other processing operations, including other polishing operations, for example more particularly, a DSP polishing operation, wherein both faces are polished at the same time. The polished semiconductor wafer has a radial thickness profile characteristic.

[0078] In the process of the first preferred embodiment (a), an etching step is performed in a coating device, wherein the first face (FS) of the semiconductor wafer is provided with a protective layer and placed on a susceptor such that the second face (BS) faces the susceptor. In this way, by the etching step, material can be deposited in a controlled manner on the edge of the second face (BS), for example, to counteract the edge roll-off resulting from the previous polishing operation. After removal of the protective layer, the resulting semiconductor wafer has at least one face polished by CMP and especially a particularly uniform thickness in the edge region. More particularly, a relatively low ESFQR max value is achieved even in the case of low edge exclusion.

[0079] In the second preferred embodiment (b), an etching step is performed in a coating device, wherein the second face (BS) of the semiconductor wafer is provided with a protective layer and the semiconductor wafer is placed on a susceptor such that the second face faces the susceptor. In this way, material can be removed from the first face (FS) in a controlled manner, for example, with the aim of creating prerequisites for minimizing thickness differences due to four-fold symmetry when subsequently depositing an epitaxial layer on the first face (FS). At the same time, unwanted material growth on the second face (BS) is counteracted, which has a detrimental effect on the local flatness of the semiconductor wafer.

[0080] In the third preferred embodiment (c), the first and second preferred embodiments (a) and (b) are essentially combined. The etching step is divided into a first etching step and a second etching step. After the polishing operation, a first protective layer is formed on the first face (FS) and the semiconductor wafer is placed on a susceptor such that the second face faces the susceptor. Then, the first etching step is performed in a coating device 300, during which material is deposited in the edge region of the second face (BS). Subsequently, the first protective layer is removed from the first face (FS) and a second protective layer is formed on the second face (BS). Thereafter, the second etching step is performed in the coating device 300, during which material is removed from the first face (FS). After the second etching step, a deposition step is performed in the coating device, during which an epitaxial layer is deposited on the first face (FS).

[0081] Figure 9 and Figure 10 The measurement of the thickness difference th in the edge region is shown on two epitaxially coated semiconductor wafers. In each case, the distribution of the respective thickness difference found after an etching step with a duration of 60 s is shown, depending on the manner of execution of the method. The thickness difference is produced by comparing the thickness of the respective semiconductor wafer in the state before and after the etching step. In the smaller diagram, the critical feature at a distance R from the edge of the semiconductor wafer is emphasized by magnification.

[0082] If the steps of the first preferred embodiment are followed, i.e. the semiconductor wafer is located on the susceptor during the etching with hydrogen chloride such that the second side (BS) faces the susceptor and the first side (FS) carries the protective layer, a typical sharp rise in the thickness profile in the edge region is evident, which is emphasized by an arrow ( Figure 9 ). It is this sharp rise in the thickness profile, in particular in the case of epitaxially coated semiconductor wafers according to the prior art, which critically limits the achievable flatness with a low edge exclusion (< 2 mm).

[0083] If the steps of the second preferred embodiment are followed, i.e. the semiconductor wafer is located on the susceptor during the etching step such that the second side (BS) faces the susceptor and the second side carries the protective layer (BS), the semiconductor wafer remains almost uniformly flat during the heating and etching operation, which is likewise emphasized by an arrow ( Figure 10 ). This advantage allows the production of semiconductor wafers with excellent flatness / planarity, which have an edge exclusion of 2 mm, even a very small edge exclusion of < 0.5 mm.

[0084] In addition, for the performance of each embodiment, it is possible to define for each respective processing operation (e.g. DSP polishing, CMP polishing, etching step and deposition of an epitaxial layer (EPI)) at least one operating parameter of the respective processing operation, in particular

[0085] based on at least one wafer parameter determined on the semiconductor wafer to be processed;

[0086] based on the actual state of the processing device carrying out the respective processing operation; and

[0087] based on an optimization of wafer parameters characterizing the flatness in the state after the three processing operations, rather than an optimization of these wafer parameters in the state after each individual processing operation of the three processing operations.

[0088] Figure 11The processing steps of the DSP, CMP and EPI are shown in a representative manner. For each of the three processing operations information is provided in order to be able to define at least one operating parameter specific to each processing device:

[0089] At least one wafer parameter is determined on the semiconductor wafer to be processed in order to define at least one operating parameter for the subsequent processing operation (cross-process feed forward, ff).

[0090] The actual state of the respective processing device (DSP, CMP, EPI) is evaluated with respect to the semiconductor wafer being processed and on the basis thereof at least one operating parameter of the processing device being evaluated is defined for processing a subsequent semiconductor wafer with the processing device (in-process feedback, wp).

[0091] After the three processing operations, a parameter characterizing the flatness of the processed semiconductor wafer, for example the ESFQR max and the SFQR max are considered and compared with the respective target value in order to define at least one operating parameter for one or more of the three processing operations for processing a subsequent semiconductor wafer (cross-process feedback, fb).

Claims

1. A semiconductor wafer comprised of single crystal silicon having an ESFQR of no more than 5 nm max and having an edge exclusion of no more than 2 mm and 72 sectors each of 30 mm in length.

2. A semiconductor wafer comprised of single crystal silicon having an ESFQR of no more than 10 nm max and having an edge exclusion of no more than 1 mm and 72 sectors each of 30 mm in length.

3. A semiconductor wafer comprised of single crystal silicon having an ESFQR of no more than 15 nm max and having an edge exclusion of no more than 0.5 mm and 72 sectors each of 30 mm in length.

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