Multilayer capacitors, their manufacturing methods, and storage devices

Abstract

This invention relates to multilayer capacitors, their fabrication methods, and storage devices. The fabrication method creates a multilayer capacitor with capacitor connection nodes. The multilayer capacitor includes a multi-layer fin structure, comprising horizontal and vertical fins. A first conductive layer covers the surface of the multi-layer fin structure, resulting in a large surface area. A capacitor dielectric layer covers the surface of the first conductive layer, and a second conductive layer covers the capacitor dielectric layer, thus the multilayer capacitor has a large capacitance, easily meeting requirements. Furthermore, after forming the multilayer film, the fabrication method uses self-aligned anisotropic etching and isotropic etching to process the multilayer film to obtain the multi-layer fin structure, eliminating the need for a photomask and additional deposition processes, resulting in lower manufacturing costs. The storage device includes the aforementioned multilayer capacitor.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a multilayer capacitor, its manufacturing method, and a storage device. Background Technology

[0002] Dynamic random access memory (DRAM) uses capacitors to store charge and maintains the charge in the capacitors at a level that can be read through periodic update operations. The trend toward high operating speeds requires DRAM capacitors to have high capacitance.

[0003] To meet capacitance requirements, multilayer capacitors or trench capacitors are used because they provide a large capacitor area internally and reduce interference between DRAM cells. However, as DRAM integration density increases, the size and area of ​​DRAM cells become smaller, making it increasingly difficult to form trenches with higher aspect ratios, thus significantly increasing the manufacturing difficulty of trench capacitors. Compared to trench capacitors, multilayer capacitors have lower aspect ratio requirements.

[0004] However, the capacitance of multilayer capacitors still needs to be improved. Summary of the Invention

[0005] To improve the capacitance of multilayer capacitors, the present invention provides a method for manufacturing multilayer capacitors, and also provides a multilayer capacitor and a storage device.

[0006] On one hand, the present invention provides a method for manufacturing a multilayer capacitor, comprising:

[0007] A capacitor connection node is provided, the capacitor connection node being formed on the surface of a first interlayer insulating layer;

[0008] A second interlayer insulating layer is formed on the capacitor connection node and the first interlayer insulating layer;

[0009] A through-hole is formed in the second interlayer insulating layer, the through-hole exposing the capacitor connection node;

[0010] A first material layer and a second material layer are sequentially stacked on the surface of the second interlayer insulating layer and the inner surface of the through hole, and this process is repeated at least once to form a laminated film.

[0011] Perform self-aligned anisotropic etching to remove a portion of each of the second material layers and a portion of each of the first material layers, leaving the remaining stacked film covering the sidewalls of the through-hole and exposing the second interlayer insulating layer and the capacitor connection node;

[0012] Isotropic etching is performed to etch back each of the first material layers in the stacked film to expose a portion of the surface of each of the second material layers, forming a multilayer fin structure connected to the sidewall of the through-hole. The multilayer fin structure includes horizontal and longitudinal fins formed from a portion of each of the second material layers; and

[0013] A first conductive layer, a capacitor dielectric layer, and a second conductive layer are formed sequentially. The first conductive layer covers the surface of the multilayer fin structure and the surface of the capacitor connection node exposed in the through hole. The capacitor dielectric layer covers the surface of the first conductive layer, and the second conductive layer covers the capacitor dielectric layer.

[0014] On one hand, the present invention provides a multilayer capacitor, the multilayer capacitor comprising:

[0015] Capacitor connection nodes are formed on the surface of a first interlayer insulating layer;

[0016] A second interlayer insulating layer is formed on the first insulating layer, and the second interlayer insulating layer has through holes that expose the capacitor connection nodes.

[0017] A multi-layer fin structure, connected to the capacitor connection node on the sidewall of the through hole and exposing the bottom surface of the through hole, the multi-layer fin structure includes horizontal fins and longitudinal fins;

[0018] A first conductive layer covers the surface of the multilayer fin structure and the exposed surface of the capacitor connection node;

[0019] A capacitor dielectric layer, covering the surface of the first conductive layer; and

[0020] A second conductive layer covers the capacitor dielectric layer.

[0021] On one hand, the present invention provides a storage device, the storage device including the above-described multilayer capacitor.

[0022] The method for fabricating a multilayer capacitor provided by this invention forms a multilayer capacitor with connected capacitor connection nodes. In the multilayer capacitor, the multilayer fin structure includes horizontal fins and vertical fins. A first conductive layer covers the surface of the multilayer fin structure, thereby increasing the surface area of ​​the first conductive layer and resulting in a larger capacitance of the multilayer capacitor, which is convenient for meeting requirements. Furthermore, the fabrication method first forms a multilayer film by repeatedly depositing a first material layer and a second material layer, and then processes the multilayer film using self-aligned anisotropic etching and isotropic etching to obtain the multilayer fin structure. This method does not require a photomask or additional deposition processes, resulting in lower manufacturing costs.

[0023] In the multilayer capacitor and storage device provided by the present invention, the multilayer fin structure includes horizontal fins and vertical fins, and there can be multiple horizontal fins and vertical fins. A first conductive layer covers the surface of the multilayer fin structure, thereby the surface area of ​​the first conductive layer is large, which helps to increase the capacitance of the multilayer capacitor to meet the requirements, and the manufacturing cost of the multilayer capacitor is low. Attached Figure Description

[0024] Figure 1 This is a schematic cross-sectional view of the multilayer capacitor manufacturing method according to an embodiment of the present invention, obtained after forming the second interlayer insulating layer.

[0025] Figure 2 This is a schematic cross-sectional view of the fabrication method of a multilayer capacitor according to an embodiment of the present invention, after forming a through hole in the second interlayer insulating layer.

[0026] Figure 3 This is a schematic cross-sectional view of the fabrication method of a multilayer capacitor according to an embodiment of the present invention after the multilayer film is formed.

[0027] Figure 4 This is a cross-sectional structural diagram of a method for manufacturing a multilayer capacitor according to an embodiment of the present invention after etching the top layer of the multilayer film.

[0028] Figure 5 This is a cross-sectional structural diagram of the fabrication method of a multilayer capacitor according to an embodiment of the present invention after etching the second-to-last layer of the multilayer film.

[0029] Figure 6 This is a cross-sectional structural diagram of a method for manufacturing a multilayer capacitor according to an embodiment of the present invention after etching the third layer of the multilayer film.

[0030] Figure 7 This is a cross-sectional structural diagram of the fabrication method of a multilayer capacitor according to an embodiment of the present invention after etching the bottom layer of the multilayer film.

[0031] Figure 8 This is a cross-sectional structural diagram of a method for manufacturing a multilayer capacitor according to an embodiment of the present invention after etching back the first material layer.

[0032] Figure 9 This is a cross-sectional structural diagram of a method for manufacturing a multilayer capacitor according to an embodiment of the present invention after the formation of the first conductive layer.

[0033] Figure 10 This is a cross-sectional structural diagram of a method for manufacturing a multilayer capacitor according to an embodiment of the present invention after forming the capacitor dielectric layer and the second conductive layer. Detailed Implementation

[0034] The multilayer capacitor, its manufacturing method, and storage device of the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the drawings in this specification are all in a very simplified form and use non-precise scales, and are only used to facilitate clarity in illustrating the embodiments of the present invention. Furthermore, spatial relative terms are intended to include different orientations in use or operation besides the orientation of the device as depicted in the figures. For example, if the structure in the figures is inverted or positioned in other different ways (e.g., rotated), the exemplary term "on" may also include "below" and other orientational relationships.

[0035] One embodiment of the present invention relates to a method for manufacturing a multilayer capacitor. The following refers to... Figures 1 to 10 The manufacturing method is described below.

[0036] Reference Figure 1 A capacitor connection node is provided, the capacitor connection node is formed on the surface of a first interlayer insulating layer 110, and a second interlayer insulating layer 120 is formed on the capacitor connection node and the first interlayer insulating layer 110.

[0037] The capacitor connection node and the first interlayer insulating layer 110 are formed, for example, on a semiconductor substrate 100. The capacitor connection node is connected to a circuit, for example, to an electronic component within or on the semiconductor substrate 100. The semiconductor substrate 100 is, for example, a silicon substrate, a germanium (Ge) substrate, a germanium-silicon substrate, an SOI (Silicon-on-Insulator) substrate, or a GOI (Germanium-on-Insulator) substrate. The semiconductor substrate 100 may be implanted with certain dopant ions according to design requirements, for example, having P-type doping or N-type doping. The semiconductor substrate 100 includes, for example, an isolation region and an active region defined by the isolation region, the active region forming an active / drain region, at least one of the source / drain regions being connectable to the capacitor connection node.

[0038] Reference Figure 1For example, the multilayer capacitor to be fabricated is used in dynamic random access memory (DRAM), and the semiconductor substrate 100 is, for example, a p-type doped silicon substrate (P-Si). The semiconductor substrate 100 may be fabricated by the following process: first, forming isolation regions (such as shallow trench isolation, STI) and active regions in the semiconductor substrate 100; then, forming multiple word lines WL on the semiconductor substrate 100, some of the word lines WL being located on the active regions and serving as gates of MOS transistors, and some of the word lines WL being located on the isolation regions and serving as passing gates PG; a dielectric layer (such as silicon nitride) is formed on the upper surface of the word lines WL; the word lines WL are connected to the semiconductor substrate 100. A gate dielectric layer 101 is formed between the gate and the sidewall 102, which covers the word line WL and the sidewall of the gate dielectric layer 101. Next, a source region 103 and a drain region 104 of a MOS transistor are formed in the active regions on both sides of the gate. The source region 103 and drain region 104 are, for example, heavily N-type doped (N+). Optionally, the source region 103 and drain region 104 are exposed through self-aligned contact holes formed by the sidewall 102. Then, the contact holes of the exposed drain region 104 are filled, and a bit line BL connecting the drain region 104 is formed. Next, a second bit line is deposited. An interlayer insulating layer 110 is deposited on the semiconductor substrate 100. The first interlayer insulating layer 110 may include one or a combination of dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, and nitrogen-doped silicon carbide (NDC). Next, the first interlayer insulating layer 110 is etched to form contact holes exposing the source region 103, and the top of the contact holes is enlarged to form a capacitor connection node range. Then, conductive material is filled into the contact holes and the capacitor connection node range on top of them, and a planarization process is performed. A contact plug 105 and a conductive plate 106 located on the contact plug 105 are simultaneously formed in the first interlayer insulating layer 110. One end of the contact plug 105 is connected to the source region 103, and the other end is connected to the conductive plate 106. In some embodiments, the contact plug 105 and the conductive plate 106 may be formed asynchronously. After that, a second interlayer insulating layer 120 is deposited, which covers the conductive plate 106 and the first interlayer insulating layer 110. The second interlayer insulating layer 120 may include one or a combination of dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, and nitrogen-doped silicon carbide.

[0039] In this embodiment, the conductive plate 106 connected to the source region 103 of the MOS transistor is used as the capacitor connection node.

[0040] Reference Figure 2 A through hole 120a is formed in the second interlayer insulating layer 120, the through hole 120a exposing the capacitor connection node (here, the conductive plate 106).

[0041] Specifically, a patterned photoresist layer PR1 can be first formed on the surface of the second interlayer insulating layer 120 to define the formation location of the multilayer capacitor. Then, using the photoresist layer PR1 as a mask, a first anisotropic etching process 10 is performed to form a through-hole 120a in the second interlayer insulating layer 120. After that, the photoresist layer PR1 is removed. In this embodiment, a plurality of conductive plates 106 serving as capacitor connection nodes are formed on the semiconductor substrate 100, and a through-hole 120a is formed in the second interlayer insulating layer for each conductive plate 106. Optionally, the through-hole 120a exposes at least a portion of the conductive plate 106, while the first interlayer insulating layer 110 is still covered by the second interlayer insulating layer 120.

[0042] Reference Figure 3 A first material layer 131 and a second material layer 132 are sequentially and conformally stacked on the surface of the second interlayer insulating layer 120 and the inner surface of the through hole 120a, and this process is repeated at least once to form a laminated film 130. The total number of the first material layer 131 and the second material layer 132 in the laminated film 130 is not particularly limited here; for example, it can be dozens or even hundreds of layers. Figure 3 The diagram shows four layers, including two first material layers 131 and two second material layers 132.

[0043] The thicknesses of both the first material layer 131 and the second material layer 132 are smaller than the width of the through-hole 120a (the distance between the two opposing inner surfaces of the through-hole 120a) to conformally stack the surface of the second interlayer insulating layer 120 and the inner surface of the through-hole 120a. The thickness of each of the first material layer 131 and the second material layer 132 is, for example, in the range of 2 nm to 20 nm. In this embodiment, the thickness of the laminated film 130 is smaller than the width of the through-hole 120a. The laminated film 130 is, for example, formed into a barrel shape along the sidewall of the through-hole 120a.

[0044] The first material layer 131 and the second material layer 132 can be selected from suitable insulating or conductive materials; in this embodiment, both are insulating materials. The first material layer 131 and the second material layer 132 preferably have a high etching selectivity to improve the effect of subsequent self-aligned directional etching. Exemplarily, the first material layer 131 includes silicon oxide, for example, a silicon oxide layer, and the second material layer 132 includes silicon nitride, for example, a silicon nitride layer. In other embodiments, one of the first material layer 131 and the second material layer 132 can also be a material with a high dielectric constant (highk, k > 3.9), such as Al2O3, Ta2O5, ZrO2, LaO, BaZrO, AlO, HfZrO, HfZrON, HfLaO, HfSiON, HfSiO, LaSiO, AlSiO, HfTaO, HfTiO, (Ba,Sr)TiO3 (BST), and TiO2, etc.

[0045] Next, refer to Figures 4 to 7 A self-aligned anisotropic etching process is performed to remove a portion of each second material layer 132 and a portion of each first material layer 131 in the stacked film 130, layer by layer. The remaining stacked film 130 covers the sidewalls of the through-hole 120a and exposes the second interlayer insulating layer 120 and the conductive plate 106. In this embodiment, the self-aligned anisotropic etching is performed, for example, along the normal direction of the semiconductor substrate 100, that is, the etching direction is substantially perpendicular to the surface of the semiconductor substrate 100.

[0046] Specifically, refer to Figure 4 First, a second anisotropic etching process 20 is performed, etching the exposed second material layer 132 located on the top layer of the stacked film 130, removing the lateral extensions of the second material layer 132 outside the through-hole 120a and the lateral extensions within the through-hole 120a. This process utilizes the selectivity of the second anisotropic etching process 20 for the second material layer 132 and the first material layer 131, allowing etching to stop when the lateral extensions of the top second material layer 132 are removed, exposing the underlying first material layer 131. The remaining portion of the top second material layer 132 extends longitudinally and covers the side of the lower first material layer 131 in a sidewall manner (the remaining portion of the top second material layer 132 forms a tubular shape along the side of the lower first material layer 131), achieving self-alignment without the need for a mask.

[0047] Reference Figure 5 Next, a third anisotropic etching process 30 is performed to etch the first material layer 131 exposed after the second anisotropic etching process 20. This first material layer 131 is the second-layer layer of the stacked film 130. This process utilizes the selectivity of the third anisotropic etching process 30 for the first material layer 131 and the second material layer 132. Etching can be stopped when the exposed lateral extension of the second-layer first material layer 131 is removed to expose the underlying second material layer 132. This allows the remaining portion of the second-layer first material layer 131 to form a structure similar to the structure obtained in the previous etching step, which covers the side of the underlying second material layer 132.

[0048] Reference Figure 6 Then, a fourth anisotropic etching process 40 is performed to etch the second material layer 132 exposed after the third anisotropic etching process 30. This step is repeated as follows. Figure 4 The etching process is shown. Thus, the two etched second material layers 132 and one first material layer 131 extend longitudinally and cover the side of the bottom first material layer 131.

[0049] Following the above method, each second material layer 132 and each first material layer 131 in the stacked film 130 can be etched alternately in a self-aligned manner without the need for a mask. (Refer to...) Figure 7 For example, a fifth anisotropic etching process 50 is performed to etch the bottom first material layer 131 and other exposed first material layers 131 in the stacked film 130. Furthermore, using an etching stop mode, the fifth anisotropic etching process 50 can stop etching when the conductive plate 106 in the second interlayer insulating layer 120 and the through hole 120a is exposed.

[0050] Using the method described above, a portion of the laminated film 130 located on the second interlayer insulating layer 120 and within the through-hole 120a can be removed. After the self-aligned anisotropic etching described above, the remaining laminated film 130 covers the sidewall of the through-hole 120a. In this embodiment, at least a portion of the longitudinally extending film layer of the remaining laminated film 130 protrudes from the top surface of the second interlayer insulating layer 120.

[0051] Reference Figure 8 An isotropic etching process is performed to etch back each of the first material layers 131 in the laminated film 130 to expose a portion of the surface of each of the second material layers 132, forming a multilayer fin structure FS connected to the sidewall of the through hole 120a. The multilayer fin structure FS includes horizontal fins 132a and longitudinal fins 132b formed from a portion of each of the second material layers 132 in the laminated film 130. The isotropic etching is, for example, wet etching or chemical dry etching (CDE).

[0052] As an example, the first material layer 131 is a silicon oxide layer, and the back etching can be performed using a hydrofluoric acid solution. By selecting suitable etching conditions, a portion of each first material layer 131 can be removed, thereby exposing the surface covered by the removed portion. After this isotropic etching, the contact area between the first material layer 131 and the second material layer 132 is reduced, and the portions of the second material layer 132 that are not in contact with the first material layer 131 on both sides form fins; and, a portion of the fins extend parallel to the surface of the semiconductor substrate 100, forming horizontal fins 132a, while another portion of the fins extend along the normal direction of the semiconductor substrate 100, forming vertical fins 132b. Each second material layer 132 is connected by the remaining first material layer 131 after back etching and stacked on the sidewall of the through-hole 120a, forming a multilayer fin structure FS. The multilayer fin structure FS can protrude from the top surface of the second interlayer insulating layer 120.

[0053] Furthermore, through the isotropic etching, the bottom surface of the through hole 120a is enlarged, thereby increasing the exposed area of ​​the conductive plate 106, such as... Figure 8 As shown, by way of example, the laminated film 130 covering the surface of the conductive plate 106 can be completely removed.

[0054] Reference Figure 9 and Figure 10 A first conductive layer 141, a capacitor dielectric layer 142, and a second conductive layer 143 are formed sequentially. The first conductive layer 141 conformally covers the surface of the multilayer fin structure and the surface of the conductive plate 106 exposed in the through hole 120a (i.e., the first conductive layer 141 connects to the capacitor connection node). The capacitor dielectric layer 142 covers the surface of the first conductive layer 141, and the second conductive layer 143 covers the capacitor dielectric layer 142.

[0055] Specifically, refer to Figure 9 First, a first conductive material layer is deposited along the surface of the multilayer fin structure FS, the surface of the conductive plate 106 exposed within the through-hole 120a, and the surface of the second interlayer insulating layer 120. The first conductive material layer may include one or more of tungsten (W), tungsten silicide (SiW), titanium (Ti), titanium nitride (TiN), doped polycrystalline silicon, surface-roughened polycrystalline silicon, and hemispherical grained polycrystalline silicon. The thickness of the first conductive material layer is approximately 1 nm to 15 nm. In this embodiment, the first conductive material layer is, for example, N-type doped polycrystalline silicon or surface-roughened polycrystalline silicon. Alternatively, a hemispherical grain polycrystalline silicon is used; then, a patterned photoresist layer PR2 is formed on the first conductive material layer to define the extent of the first conductive layer 141; next, using the photoresist layer PR2 as a mask, the first conductive material layer is etched to expose the second interlayer insulating layer 120 disposed circumferentially along the through hole 120a. The first conductive material layer surrounded by the exposed second interlayer insulating layer 120 forms the first conductive layer 141, and the first conductive layers 141 formed corresponding to two adjacent through holes 120a are separated. After that, the photoresist layer PR2 is removed.

[0056] Then, a capacitor dielectric layer 142 is deposited along the surface of the first conductive layer 141 and the exposed surface of the second interlayer insulating layer 120. The capacitor dielectric layer 142 may include one or more of silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide (HfO), and arsenic oxide (As2O5), and the thickness of the capacitor dielectric layer 142 is about 1 nm to 10 nm.

[0057] Next, a second conductive material layer is formed on the surface of the capacitor dielectric layer 142. The second conductive material layer covers the surface of the capacitor dielectric layer 142 and fills the through-hole 120a. The top surface of the second conductive material layer may be higher than the multilayer fin structure FS. Subsequently, optionally, the top surface of the second conductive material layer is planarized (e.g., CMP) to form the second conductive layer 143. The second conductive layer 143 may include one or more of tungsten, tungsten silicide, titanium, titanium nitride, and doped polycrystalline silicon. In this embodiment, for example, it is N-type doped polycrystalline silicon.

[0058] The aforementioned multilayer fin structure FS, the first conductive layer 141, the capacitor dielectric layer 142, and the second conductive layer 143 constitute a multilayer capacitor. The second conductive layer 143 can be shared by multiple multilayer capacitors located in the region of the through-hole 120a. In the multilayer capacitor, the multilayer fin structure FS includes horizontal fins 132a and vertical fins 132b, and there can be multiple horizontal fins 132a and vertical fins 132b. This results in a larger surface area for the first conductive layer 141, leading to a larger contact area between the first conductive layer 141 and the capacitor dielectric layer 142, and between the capacitor dielectric layer 142 and the second conductive layer 143. This results in a larger capacitance for the multilayer capacitor, easily meeting requirements. Furthermore, the fabrication method of the multilayer capacitor employs self-aligned anisotropic etching and isotropic etching to process the multilayer film 130, eliminating the need for a photomask and additional deposition, thus reducing manufacturing costs.

[0059] One embodiment of the present invention relates to a multilayer capacitor, see reference to Figure 10 The multilayer capacitor includes:

[0060] Capacitor connection nodes (such as) Figure 10 The conductive plate 106 shown is formed on the surface of a first interlayer insulating layer 110;

[0061] A second interlayer insulating layer 120 is formed on the first insulating layer 110. The second interlayer insulating layer 120 has a through hole 120a, the bottom of which exposes the capacitor connection node.

[0062] A multi-layer fin structure FS is formed on the sidewall of the through hole 120a, and the multi-layer fin structure FS includes horizontal fins 132a and longitudinal fins 132b.

[0063] The first conductive layer 141 covers the surface of the multilayer fin structure FS and the exposed surface of the capacitor connection node;

[0064] The capacitor dielectric layer 142 covers the surface of the first conductive layer 141; and

[0065] The second conductive layer 143 covers the capacitor dielectric layer 142.

[0066] The multilayer capacitor is formed on the semiconductor substrate 100. The multilayer fin structure FS may include alternately stacked first material layers 131 and second material layers 132, such as silicon oxide and silicon nitride. Specifically, the first material layer 131 and the second material layer 132 have good adhesion due to lattice matching, forming a stable multilayer fin structure FS. This multilayer fin structure FS utilizes the first material layer 131 to connect the sidewalls of the through-hole 120a. The contact surface between the first material layer 131 and the second material layer 132 is small. The portions of the second material layer 132 that do not contact the first material layer 131 on both sides form fins. A portion of these fins extend parallel to the surface of the semiconductor substrate 100, forming horizontal fins 132a, while another portion extends along the normal direction of the semiconductor substrate 100, forming vertical fins 132b. The top of the multilayer fin structure FS may protrude from the top surface of the second interlayer insulating layer 120.

[0067] One embodiment of the present invention relates to a storage device comprising the multilayer capacitors described in the above embodiments. The storage device is, for example, a dynamic random access memory (DRAM).

[0068] Reference Figure 10 The storage device may include a semiconductor substrate 100 and a first interlayer insulating layer 110 formed on the semiconductor substrate 100. The semiconductor substrate 100 includes an isolation region (e.g., an STI) and an active region defined by the isolation region. Further, the storage device may also include a MOS transistor formed on the surface of the active region. The MOS transistor includes a gate and a source region 103 and a drain region 104 located on either side of the gate within the active region. The storage device may also include a contact plug 105 and a conductive plate 106. The contact plug 105 is formed in the first interlayer insulating layer 110 and one end is connected to the source region 103. The conductive plate 106 is formed on the surface of the first interlayer insulating layer 110 and is connected to the other end of the contact plug 105. In this embodiment, the conductive plate 106 serves as the capacitor connection node for a multilayer capacitor.

[0069] In the multilayer capacitor and storage device of the present invention, the multilayer fin structure FS includes horizontal fins 132a and vertical fins 132b, and there can be multiple horizontal fins 132a and vertical fins 132b, which makes the surface area of ​​the first conductive layer 141 larger, and the first conductive layer 141 and the capacitor dielectric layer 142 and the capacitor dielectric layer 142 and the second conductive layer 143 have a larger contact area, which helps to increase the capacitance of the multilayer capacitor to meet the requirements, and the manufacturing cost of the multilayer capacitor is low.

[0070] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same and similar parts between the various embodiments can be referred to each other.

[0071] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention. Any person skilled in the art can make possible changes and modifications to the technical solutions of the present invention by utilizing the methods and techniques disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solutions of the present invention shall fall within the protection scope of the technical solutions of the present invention.

Claims

1. A method for manufacturing a multilayer capacitor, characterized in that, include: A capacitor connection node is provided, the capacitor connection node being formed on the surface of a first interlayer insulating layer; A second interlayer insulating layer is formed on the capacitor connection node and the first interlayer insulating layer; A through-hole is formed in the second interlayer insulating layer, the through-hole exposing the capacitor connection node; A first material layer and a second material layer are sequentially stacked on the surface of the second interlayer insulating layer and the inner surface of the through hole, and this process is repeated at least once to form a laminated film. Utilizing the etching selectivity of the first material layer and the second material layer, self-aligned anisotropic etching is performed alternately for etching the second material layer and for etching the first material layer to remove a portion of each second material layer and a portion of each first material layer. The remaining stacked film covers the sidewall of the through hole and exposes the second interlayer insulating layer and the capacitor connection node. Each first material layer has an upward exposed surface and an exposed surface facing into the through hole. Isotropic etching is performed to etch back each of the first material layers in the stacked film to expose a portion of the surface of each of the second material layers, forming a multi-layer fin structure connected to the sidewall of the through hole. The multi-layer fin structure includes horizontal fins and longitudinal fins formed from a portion of each of the second material layers. as well as A first conductive layer, a capacitor dielectric layer, and a second conductive layer are formed sequentially. The first conductive layer covers the surface of the multilayer fin structure and the surface of the capacitor connection node exposed in the through hole. The capacitor dielectric layer covers the surface of the first conductive layer, and the second conductive layer covers the capacitor dielectric layer.

2. The manufacturing method as described in claim 1, characterized in that, The isotropic etching is either wet etching or chemical dry etching.

3. The manufacturing method as described in claim 1, characterized in that, Both the first material layer and the second material layer are insulating materials.

4. The manufacturing method as described in claim 1, characterized in that, The first material layer comprises silicon oxide, and the second material layer comprises silicon nitride.

5. The manufacturing method as described in claim 1, characterized in that, The thickness of each of the first and second material layers is in the range of 2nm to 20nm.

6. The manufacturing method as described in claim 1, characterized in that, The thickness of the laminated film is less than the width of the through hole.

7. The manufacturing method as described in claim 1, characterized in that, The first interlayer insulating layer is formed on a semiconductor substrate, the semiconductor substrate including an isolation region and an active region defined by the isolation region, the active region forming an active / drain region, and at least one of the active / drain regions connecting to the capacitor connection node.

8. The manufacturing method as described in claim 7, characterized in that, A MOS transistor is formed on the surface of the active region of the semiconductor substrate. The MOS transistor includes a gate and a source region and a drain region located on both sides of the gate. A contact plug connected to the source region at one end and a conductive plate connected to the other end of the contact plug are formed in the first interlayer insulating layer, with the conductive plate serving as the capacitor connection node.

9. The manufacturing method as described in claim 1, characterized in that, The thickness of the first conductive layer is 1 nm to 15 nm; the thickness of the capacitor dielectric layer is 1 nm to 10 nm.

10. The manufacturing method as described in claim 1, characterized in that, The first conductive layer includes one or more of the following: tungsten, tungsten silicide, titanium, titanium nitride, doped polycrystalline silicon, surface-roughened polycrystalline silicon, and hemispherical grain polycrystalline silicon.

11. The manufacturing method as described in claim 1, characterized in that, The capacitor dielectric layer includes one or more of silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, and arsenic oxide.

12. The manufacturing method as described in claim 1, characterized in that, The second conductive layer comprises one or more of tungsten, tungsten silicide, titanium, titanium nitride, and doped polycrystalline silicon.

13. The manufacturing method as described in claim 1, characterized in that, The top of the multi-layer fin structure protrudes from the top surface of the second interlayer insulating layer.

14. The manufacturing method as described in claim 1, characterized in that, The formation of the first conductive layer, the capacitor dielectric layer, and the second conductive layer in sequence includes: A first conductive material layer is formed along the surface of the multilayer fin structure, the surface of the capacitor connection node exposed in the through hole, and the surface of the second interlayer insulating layer; The first conductive layer is formed by etching the first conductive material layer and exposing the second interlayer insulating layer disposed along the circumferential direction of the through hole; The capacitor dielectric layer is formed along the surface of the first conductive layer and the exposed surface of the second interlayer insulating layer; A second conductive material layer is formed on the surface of the capacitor dielectric layer, the second conductive material layer filling the through-hole and having its top surface higher than the multilayer fin structure; and The top surface of the second conductive material layer is planarized to form the second conductive layer.

15. A multilayer capacitor, characterized in that, include: Capacitor connection nodes are formed on the surface of a first interlayer insulating layer; A second interlayer insulating layer is formed on the first interlayer insulating layer, and the second interlayer insulating layer has through holes that expose the capacitor connection nodes. A multi-layer fin structure is connected to the capacitor connection node on the sidewall of the through hole and exposes the bottom surface of the through hole. The multi-layer fin structure includes horizontal fins and vertical fins. The multi-layer fin structure is formed by first selectively and alternately etching the first material layer and the second material layer in a stacked film formed by a first material layer and a second material layer in the through hole using self-aligned anisotropic etching to etch the second material layer and the first material layer, so that each first material layer has an upward exposed surface and an exposed surface facing the through hole. Then, each first material layer is isotropically etched. The horizontal fins and the vertical fins are formed by a portion of the second material layer. A first conductive layer covers the surface of the multilayer fin structure and the exposed surface of the capacitor connection node; A capacitor dielectric layer, covering the surface of the first conductive layer; and A second conductive layer covers the capacitor dielectric layer.

16. The multilayer capacitor as claimed in claim 15, characterized in that, The first material layer comprises silicon oxide, and the second material layer comprises silicon nitride.

17. A storage device, characterized in that, Including the multilayer capacitor as described in claim 15.

18. The storage device as claimed in claim 17, characterized in that, include: A semiconductor substrate, wherein the first interlayer insulating layer is formed on the semiconductor substrate, the semiconductor substrate including an isolation region and an active region defined by the isolation region; A MOS transistor is formed in the active region, the MOS transistor including a gate and a source region and a drain region formed on both sides of the gate in the active region; A contact plug is formed in the first interlayer insulating layer, and one end of the contact plug is connected to the source region; as well as A conductive plate is formed on the surface of the first interlayer insulating layer, and the conductive plate is connected to the other end of the contact plug, with the conductive plate serving as the capacitor connection node.

Images