Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a method of forming the same, the method comprising: providing a substrate, the substrate comprising an active region and an isolation region adjacent to the active region, a device gate structure being formed on the substrate in both the active region and the isolation region, a first interlayer dielectric layer being formed on top of the substrate; forming a first trench on top of the device gate structure in the isolation region; forming a sacrificial layer in the first trench; forming a second interlayer dielectric layer on top of the first interlayer dielectric layer; forming a second trench in the second interlayer dielectric layer, a projection of the second trench on the substrate being orthogonal to a projection of the sacrificial layer on the substrate; removing the sacrificial layer exposed by the second trench to form a first contact hole in the first interlayer dielectric layer; forming a first gate plug in the first contact hole, the first gate plug being configured to carry a first electrical potential; forming a second gate plug on top of the device gate structure in the active region, the second gate plug being configured to carry a second electrical potential, the second electrical potential being opposite to the first electrical potential. The probability of shorting the first gate plug to an adjacent source / drain doped region is reduced.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a forming method thereof. BACKGROUND

[0002] With the rapid growth of the semiconductor integrated circuit (IC) industry, semiconductor technology continues to advance toward smaller process nodes under the driving force of Moore's Law, so that integrated circuits are developing toward smaller size, higher circuit precision, and higher circuit complexity.

[0003] In the development of integrated circuits, generally, as the functional density (i.e., the number of interconnected elements per chip) increases, the geometry size (i.e., the smallest component that can be produced using a process step) is gradually reduced, and the design of three-dimensional structures such as fin field effect transistors (FinFET) becomes a hot spot in the field. Moreover, in order to make smaller and more densely distributed fins, the prior art introduces a single diffusion break (SDB) structure, which is generally distributed along the extension direction of the fin, removes some regions of the fin by etching process, forms one or more break trenches in the fin, and then fills the break trenches with insulating material, thereby dividing the fin along the extension direction of the fin, thereby preventing source-drain bridges between adjacent source-drain doped regions.

[0004] At present, with the continuous reduction of the technology node, the difficulty of the preparation process of the break structure also increases accordingly. SUMMARY

[0005] The problem solved by embodiments of the present application is to provide a semiconductor structure and a forming method thereof, which is beneficial to improve the performance of the semiconductor structure.

[0006] To solve the above problems, the embodiment of the present application provides a semiconductor structure, comprising: a substrate, the substrate comprising a substrate and a fin standing on the substrate, the substrate comprising an adjacent working area and an isolation area; an isolation layer, located on the exposed substrate of the fin, the isolation layer covering part of the sidewall of the fin; a device gate structure, respectively located on the substrate of the device area and the isolation area, the device gate structure of the isolation area used as a partition structure; a bottom dielectric layer, located on the exposed substrate of the device gate structure and covering the sidewall of the device gate structure, and the top of the bottom dielectric layer is flush with the top of the device gate structure; a first dielectric layer, located on the top of the device gate structure and the bottom dielectric layer of the isolation area, the extension direction of the first dielectric layer is the same as that of the device gate structure, and the first dielectric layer exposes part of the top surface of the device gate structure; a second dielectric layer, located on the top of the substrate, covering the top of the device gate structure and the sidewall of the first dielectric layer, and the top of the second dielectric layer is flush with the top of the first dielectric layer; a first gate plug, located in the isolation area, penetrating the second dielectric layer on the top of the device gate structure, and electrically connected with the top of the device gate structure exposed by the first dielectric layer; a second gate plug, located in the working area, penetrating the second dielectric layer on the top of the device gate structure, and electrically connected with the device gate structure of the working area.

[0007] Correspondingly, the embodiment of the present application also provides a forming method of a semiconductor structure, comprising: providing a substrate, the substrate comprising an adjacent working area and an isolation area, the substrate of the device area and the isolation area are both formed with a device gate structure extending along a first direction, the device gate structure of the isolation area used as a partition structure, and the top of the substrate is formed with a first interlayer dielectric layer covering the top of the device gate structure; in the isolation area, a first trench extending along the first direction and penetrating the first interlayer dielectric layer is formed on the top of the device gate structure; a sacrificial layer is formed in the first trench; a second interlayer dielectric layer is formed on the top of the first interlayer dielectric layer and the sacrificial layer; a second trench extending along a second direction and penetrating the second interlayer dielectric layer is formed in the second interlayer dielectric layer, the projection of the second trench on the substrate is orthogonal to the projection of the sacrificial layer on the substrate, and the second trench exposes part of the top surface of the sacrificial layer, and the second direction is perpendicular to the first direction; the sacrificial layer exposed by the second trench is removed, and a first contact hole exposing the top of the device gate structure is formed in the first interlayer dielectric layer; a first gate plug is formed in the first contact hole, the first gate plug is electrically connected with the device gate structure of the isolation area, and the first gate plug is used to load a first potential; a second gate plug is formed on the top of the device gate structure of the working area, the second gate plug is electrically connected with the device gate structure of the working area, and the second gate plug is used to load a second potential, and the second potential and the first potential are opposite potentials.

[0008] Compared with the prior art, the technical scheme of the embodiment of the present application has the following advantages:

[0009] The embodiment of the present application provides a forming method of a semiconductor structure. In an isolation region, a first trench extending along a first direction and penetrating a first interlayer dielectric layer is formed on top of a device gate structure, a second trench extending along a second direction and penetrating a second interlayer dielectric layer is formed in the second interlayer dielectric layer, a projection of the second trench on a substrate is orthogonal to a projection of a sacrificial layer on the substrate, and the second trench exposes a part of a top surface of the sacrificial layer, the second direction is perpendicular to the first direction, the sacrificial layer exposed by the second trench is removed, a first contact hole exposing the top of the first device gate structure is formed in the first interlayer dielectric layer, and a first gate plug is formed in the first contact hole. Compared with the scheme of directly forming the first contact hole on the top of the device gate structure of the isolation region by a one-time etching process, the embodiment of the present application forms the long-strip-shaped first trench extending along the first direction first, and then forms the long-strip-shaped second trench extending along the second direction, which is easy to obtain the first trench and the second trench with smaller widths respectively, so that the first contact hole capable of meeting the process size requirement is obtained by using the first trench and the second trench orthogonal to each other, and the device gate structure of the working region is usually formed with source-drain doped regions on both sides, so that the device gate structure of the isolation region can be used as a partition structure while the probability of short circuit between the first gate plug and the adjacent source-drain doped regions is reduced, thereby improving the performance of the semiconductor structure. BRIEF DESCRIPTION OF DRAWINGS

[0010] Figures 1 to 3 is a structural schematic diagram of an embodiment of the semiconductor structure of the present application;

[0011] Figures 4 to 31 is a structural schematic diagram corresponding to each step in an embodiment of the forming method of the semiconductor structure of the present application. DETAILED DESCRIPTION

[0012] At present, due to the restriction of the photolithography equipment, the size of the gate plug formed in the semiconductor device is too large, which cannot meet the process requirement of smaller and smaller gate plug size, thereby increasing the probability of short circuit between the gate plug and the adjacent source-drain doped regions.

[0013] To solve the technical problem, the embodiment of the present application provides a forming method of a semiconductor structure, comprising: a substrate, the substrate comprising an adjacent working area and an isolation area; a device gate structure, respectively located on the substrate of the device area and the isolation area, the device gate structure of the isolation area being used as a partition structure; a sacrifice layer, located on top of the device gate structure of the isolation area, the extension direction of the sacrifice layer being the same as the extension direction of the device gate structure, and the sacrifice layer exposing part of the top surface of the device gate structure; an interlayer dielectric layer, located on top of the substrate and covering the top of the device gate structure and the sidewall of the sacrifice layer, the top of the interlayer dielectric layer being flush with the top of the sacrifice layer; a first gate plug, located in the isolation area, penetrating the interlayer dielectric layer on top of the device gate structure, and electrically connected with the top of the device gate structure exposed by the sacrifice layer, the first gate plug being used to load a first potential; and a second gate plug, located in the working area, penetrating the interlayer dielectric layer on top of the device gate structure, the second gate plug being electrically connected with the device gate structure of the working area, the second gate plug being used to load a second potential, the second potential and the first potential being opposite potentials.

[0014] In the forming method provided by the embodiment of the present application, the long-strip-shaped first groove extending along the first direction is formed first, and then the long-strip-shaped second groove extending along the second direction is formed, so that the first groove and the second groove with smaller width are respectively obtained, and the first contact hole meeting the process size requirement is obtained by using the first groove and the second groove being perpendicular to each other, and the device gate structure of the working area is usually formed with source-drain doped areas on both sides, so that the device gate structure of the isolation area can be used as the partition structure, and the probability of short circuit between the first gate plug and the adjacent source-drain doped areas is reduced, thereby improving the performance of the semiconductor structure.

[0015] In order to make the above-mentioned objects, features and advantages of the embodiments of the present application more obvious and easy to understand, the specific embodiments of the present application will be described in detail below with reference to the drawings.

[0016] Figures 1 to 3 is a structural schematic diagram of an embodiment of the semiconductor structure of the present application. Among them, Figure 1 is a top view, Figure 2 is Figure 1 is a sectional view along the ab direction, Figure 3 is Figure 1 is a sectional view along the cd direction.

[0017] Among them, in order to facilitate the illustration, Figure 1 the interlayer dielectric layer 205 is not shown in the figure.

[0018] The semiconductor structure includes: a substrate (not shown), the substrate including a base (not shown) and fins 200 protruding from the base, the substrate including adjacent working regions 200A and isolation regions 200B; an isolation layer (not shown) located on the substrate exposed by the fins 200, the isolation layer covering part of the sidewalls of the fins; a device gate structure 202 located on the substrates of the working regions 200A and the isolation regions 200B respectively, the device gate structure 202 of the isolation region 200B serving as a barrier structure; a bottom dielectric layer 203 located on the substrate exposed by the device gate structure 202 and covering the sidewalls of the device gate structure 202, and the top of the bottom dielectric layer 203 being flush with the top of the device gate structure 202; a first dielectric layer 209 located on top of the device gate structure 202 and the bottom dielectric layer 203 of the isolation region 200B, the second... A dielectric layer 209 extends in the same direction as the device gate structure 202, and the first dielectric layer 209 exposes part of the top surface of the device gate structure 202; a second dielectric layer 205 is located on top of the substrate and covers the top of the device gate structure 202 and the sidewall of the first dielectric layer 209, and the top of the second dielectric layer 205 is flush with the top of the first dielectric layer 209; a first gate plug 219 is located in the isolation region 200B and penetrates the second dielectric layer 205 on top of the device gate structure 202, and is electrically connected to the exposed top of the device gate structure 202 of the first dielectric layer 209; a second gate plug 220 is located in the working region 200A and penetrates the second dielectric layer 205 on top of the device gate structure 202, and is electrically connected to the device gate structure 202 in the working region 200A.

[0019] In this embodiment, the working area 200A and the isolation area 200B are along the second direction (e.g., Figure 1 The device gate structure 202 is arranged in the first direction (as shown in the X direction), and extends along the first direction (e.g., as shown in the X direction). Figure 1 (as shown in the Y direction) and along the second direction (as shown in the Y direction) Figure 1 The arrangement is shown in the X direction, meaning that the arrangement direction of the device gate structure 202 is the same as the arrangement direction of the working region 200A and the isolation region 200B.

[0020] In the method for forming the semiconductor structure, the first long strip-shaped trench is formed first, and then the second long strip-shaped trench is formed after the first trench is filled with the sacrificial layer 209. This is easy to obtain the first trench and the second trench with small width, and the first contact hole is obtained by removing the exposed sacrificial layer 209 in the second trench with the first trench and the second trench being perpendicular to each other, so as to meet the process size requirement. The first contact hole is used to form the first gate plug 219, and the active source / drain doped regions are usually formed on both sides of the device gate structure 202 in the working area 200A. Accordingly, the device gate structure 202 in the isolation area 200B can be used as a partition structure, and the probability of short circuit between the first gate plug 219 formed in the first contact hole and the adjacent source / drain doped regions is reduced, thereby improving the performance of the semiconductor structure.

[0021] Moreover, the first contact hole with small size is obtained by using the first trench and the second trench being perpendicular to each other, so as to increase the process window of the photolithography process for forming the first contact hole and reduce the requirement for the photolithography process.

[0022] Therefore, in the isolation area 200B, the sacrificial layer 209 is located on the top of the device gate structure 202 on the side of the first gate plug 219, and the sacrificial layer 209 is reserved after the first contact hole is formed.

[0023] It should be noted that, in order to reduce the probability of short circuit between the second gate plug 220 in the device area 200A and the source / drain doped regions on both sides of the device gate structure 202, a sufficient distance is left between the device gate structure 202 in the device area 200A and the source / drain doped regions on both sides thereof.

[0024] The substrate includes a substrate (not shown in the figure) and a fin 200 on the substrate. In the embodiment, the material of the substrate is silicon. In other embodiments, the material of the substrate can also be germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and other materials. The substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, and other types of substrates.

[0025] In the embodiment, the fin 200 is separated on the substrate, and the material of the fin 200 is the same as that of the substrate, both of which are silicon.

[0026] In the embodiment, the substrate includes a working area 200A and an isolation area 200B. The working area 200A is used to form a transistor, and the isolation area 200B is used to form a partition structure.

[0027] Specifically, the isolation zone 200B is located on both sides of the work area 200A.

[0028] In this embodiment, the semiconductor structure further includes an isolation layer (not shown) located on the substrate exposed by the fin 200, the isolation layer covering a portion of the sidewall of the fin 200.

[0029] The isolation layer is used to isolate adjacent devices. The material of the isolation layer can be silicon oxide, silicon nitride, or silicon oxynitride. In this embodiment, the material of the isolation layer is silicon oxide.

[0030] When the transistor device is in operation, the device gate structure 202 in the device region 200A is used to control the opening or closing of the conductive channel.

[0031] The device gate structure 202 of the isolation region 200B is used as a barrier structure to electrically isolate the transistors in the adjacent working region 200A.

[0032] It should be noted that the device gate structure 202 formed in the isolation region 200B is used as an isolation structure. Compared with the existing scheme of forming an isolation structure in the fin of the isolation region by cutting the fin, this embodiment eliminates the process step of cutting the fin 200 in the isolation region 200B, reduces the impact of the cutting process on the conductive channel in the fin 200, and also reduces the probability of other process defects generated during the cutting process.

[0033] In this embodiment, the device gate structure 202 is a metal gate structure, and the device gate structure 202 includes a gate dielectric layer and a gate electrode layer covering the gate dielectric layer.

[0034] In this embodiment, the material of the gate dielectric layer includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2, and La2O3.

[0035] The gate electrode layer is used for subsequent electrical connection with external interconnect structures. The material of the gate electrode layer includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN, and TiAlC. Specifically, the gate electrode layer may include a work function layer and an electrode layer covering the work function layer, or the gate electrode layer may only include a work function layer.

[0036] In this embodiment, the semiconductor structure further includes a source / drain doped layer (not shown), which is located in the substrate on both sides of the device gate structure 202. The source / drain doped layer serves as the source or drain region of the transistor.

[0037] In this embodiment, the semiconductor structure further comprises: a bottom source-drain plug 230 located on the top of the source-drain doped layer and on both sides of the device gate structure 202.

[0038] The bottom source-drain plug 230 is electrically connected with the source-drain doped layer (not shown in the figure) to realize electrical connection between the source-drain doped layer and external circuit or other interconnection structure.

[0039] In this embodiment, the semiconductor structure further comprises: a bottom dielectric layer 203 located on the substrate exposed by the device gate structure 202 and covering the sidewall of the device gate structure 202.

[0040] Specifically, the bottom source-drain plug 230 is located in the first interlayer dielectric layer 205 on the top of the source-drain doped layer, that is, the bottom dielectric layer 203 is located on the substrate exposed by the device gate structure 202 and the bottom source-drain plug 230.

[0041] The device gate structure 202 is a metal gate structure, the bottom dielectric layer 203 is used to provide a process basis for the formation of the device gate structure 202, and is also used to provide a process basis for the formation of the bottom source-drain plug 230.

[0042] In this embodiment, the device gate structure 202 located in the isolation region 200B is used as a partition structure.

[0043] Specifically, the device gate structure 202 is used as the partition structure of the isolation region 200B, which can be formed in the same step as the device gate structure 202 in the device region 200A. Compared with the scheme of forming a partition structure in the fin of the isolation region by cutting the fin, this embodiment simplifies the process steps, reduces the process cost, and also reduces the probability of other process defects in the cutting process.

[0044] The material of the bottom dielectric layer 203 is an insulating material, which includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride. In this embodiment, the material of the bottom dielectric layer 203 is silicon oxide.

[0045] The interlayer dielectric layer 205 is used to isolate the first gate plug 219 and the second gate plug 220.

[0046] The material of the interlayer dielectric layer 205 is an insulating material, which includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride. In this embodiment, the material of the interlayer dielectric layer 205 is silicon oxide.

[0047] As can be seen from the foregoing, in the method for forming the semiconductor structure, the long-strip-shaped first trenches extending along the first direction are formed first, then the long-strip-shaped second trenches extending along the second direction are formed after the first trenches are filled with the sacrificial layer 209, and then the exposed sacrificial layer 209 is removed by using the first trenches and the second trenches orthogonal to each other (i.e., the sacrificial layer 209 and the second trenches are orthogonal to each other), so as to form the first contact hole meeting the process size requirement, and the sacrificial layer is used to define the size of the first contact hole and also to electrically isolate the adjacent first gate plug 219.

[0048] In this embodiment, the material of the sacrificial layer includes one or more of silicon nitride, silicon carbide and silicon carbonitride.

[0049] The material hardness of silicon nitride, silicon carbide and silicon carbonitride is large, and the etching selectivity between the sacrificial layer 209 and the interlayer dielectric layer 205 is large, so that the damage to the interlayer dielectric layer 205 can be reduced during the process of removing the exposed sacrificial layer 209, thereby facilitating to ensure that the size and morphology of the first contact hole meet the process requirements. In addition, silicon nitride, silicon carbide and silicon carbonitride are also insulating materials, which can achieve good isolation effect.

[0050] The first gate plug 219 is used to realize the electrical connection between the device gate structure 202 in the isolation region 200B and the external circuit or other interconnection structure.

[0051] In this embodiment, the material of the first gate plug 219 is tungsten. The resistivity of tungsten is low, which is beneficial to improve the signal delay of the back-end RC and improve the processing speed of the chip, and also beneficial to reduce the resistance of the first gate plug 219 and reduce the power consumption. In other embodiments, the material of the first gate plug can also be a conductive material such as cobalt or ruthenium.

[0052] It also needs to be explained that, taking the extending direction of the device gate structure 202 as the first direction, the size of the first gate plug 219 along the first direction should not be too large or too small. If the size of the first gate plug 219 along the first direction is too large, it is easy to cause the first gate plug 219 to be short-circuited with the source-drain doped layer on both sides of the device gate structure 202 in the working area 200A, thereby reducing the performance of the semiconductor structure. If the size of the first gate plug 219 along the first direction is too small, it is easy to cause the size of the first gate plug 219 to not meet the process requirements, so that the electrical property of the first gate plug is reduced, and accordingly, the electrical isolation effect of the device gate structure 202 in the isolation area 200B is reduced, thereby affecting the performance of the semiconductor structure. Therefore, in the embodiment, taking the extending direction of the device gate structure 202 as the first direction, the size of the first gate plug 219 along the first direction is 10-15 nm. For example, the size of the first gate plug 219 along the first direction is 11 nm, 12 nm or 14 nm.

[0053] It also needs to be explained that, taking the direction perpendicular to the extending direction of the device gate structure 202 as the second direction, the size of the first gate plug 219 along the second direction should not be too large or too small. If the size of the first gate plug 219 along the second direction is too large, it increases the probability of short-circuiting between the first gate plug 219 and the source-drain doped layer on both sides of the device gate structure 202 in the working area 200A, thereby reducing the performance of the semiconductor structure. If the size of the first gate plug 219 along the second direction is too small, it is easy to cause the size of the first gate plug 219 along the second direction to not meet the process requirements, and accordingly, the electrical property of the first gate plug 219 in the isolation area 200B is reduced, and accordingly, the electrical isolation effect of the device gate structure in the isolation area 200B is reduced, thereby affecting the performance of the semiconductor structure. Therefore, in the embodiment, taking the direction perpendicular to the extending direction of the device gate structure 202 as the second direction, the size of the first gate plug 219 along the second direction is 10-15 nm. For example, the size of the first gate plug 219 along the second direction is 11 nm, 12 nm or 14 nm.

[0054] The second gate plug 220 is used to realize the electrical connection between the device gate structure 202 in the working area 200A and an external circuit or other interconnection structure.

[0055] In this embodiment, the material of the second gate plug 220 is tungsten. The resistivity of tungsten is low, which is beneficial to improve the signal delay of the back-end RC, increase the processing speed of the chip, and reduce the resistance of the first gate plug 219 and the power consumption correspondingly. In other embodiments, the material of the second gate plug can also be a conductive material such as cobalt or ruthenium.

[0056] It should be noted that the device gate structure 202 in the isolation region 200B is used to electrically isolate the device gate structure in the adjacent working region 200A. For this purpose, the first gate plug 219 is used to load a first potential, and the second gate plug 220 is used to load a second potential, and the second potential and the first potential are opposite potentials.

[0057] When the device region 200A is used as an NMOS transistor, the device gate structure 202 in the isolation region 200B needs to load a negative voltage in order to achieve the effect of electrically isolating the adjacent NMOS transistor. Since the NMOS transistor in the device region 200A needs to load a positive second potential to be turned on, the device gate structure 202 in the isolation region 200B needs to load a negative voltage, so that there is no current conduction between the device regions 200A on both sides of the isolation region 200B, and the device gate structure 202 in the isolation region 200B can achieve the effect of electrical isolation.

[0058] When the device region 200A is used as a PMOS transistor, the device gate structure 202 in the isolation region 200B needs to load a positive voltage in order to achieve the effect of electrically isolating the adjacent PMOS transistor. Since the PMOS transistor in the device region 200A needs to load a negative second potential to be turned on, the device gate structure 202 in the isolation region 200B needs to load a positive voltage, so that there is no current conduction between the device regions 200A on both sides of the isolation region 200B, and the device gate structure 202 in the isolation region 200B can achieve the effect of electrical isolation.

[0059] In this embodiment, the semiconductor structure further comprises: a top source-drain plug 221 located in the interlayer dielectric layer 205 on top of the bottom source-drain plug 230 and electrically connected to the bottom source-drain plug 230.

[0060] The top source-drain plug 221 is electrically connected to the source-drain doped layer through the bottom source-drain plug 230, so as to lead out the electrical property of the source-drain doped layer.

[0061] The material of the top source-drain plug 221 can refer to the aforementioned corresponding description of the first gate plug 219, and will not be repeated here.

[0062] Figures 4 to 31 is the structure diagram corresponding to each step in an embodiment of the forming method of the semiconductor structure.

[0063] Reference Figures 4 to 7 , wherein, Figure 4 is a top view, Figure 5 is a top view, Figure 4 is a sectional view along the AB direction, Figure 6 is a top view, Figure 7 is a top view, Figure 6 is a sectional view along the AB direction, provides a substrate, the substrate includes adjacent working areas 100A and isolation areas 100B, and the device gate structure 102 extending along the first direction (as shown in the Y direction in the figure) is formed on the substrate of the device area 100A and the isolation area 100B, the device gate structure 102 of the isolation area 100B is used as a partition structure, and the top of the substrate is formed with a first interlayer dielectric layer 105 covering the top of the device gate structure 102. Figure 4

[0064] The substrate is used to provide a process platform for subsequent process.

[0065] The substrate includes a substrate (not shown in the figure) and a fin 100 on the substrate. In this embodiment, the material of the substrate is silicon. In other embodiments, the material of the substrate can also be germanium, silicon germanium, silicon carbide, gallium arsenide, or other materials such as indium gallium. The substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or other types of substrates.

[0066] In this embodiment, the fin 100 is separated on the substrate, and the material of the fin 100 is the same as that of the substrate, both of which are silicon.

[0067] In this embodiment, the substrate includes working areas 100A and isolation areas 100B, the working areas 100A are used to form transistors, and the isolation areas 100B are used to form partition structures.

[0068] In this embodiment, the working areas 100A and the isolation areas 100B are arranged along the second direction (as shown in the X direction in the figure). Figure 1

[0069] In this embodiment, the forming method of the semiconductor structure further includes: after forming the fin 100, forming an isolation layer (not shown in the figure) on the exposed substrate of the fin 100, and the isolation layer covers part of the sidewall of the fin 100. ​​

[0070] The isolation layer is used to isolate adjacent devices. The material of the isolation layer can be silicon oxide, silicon nitride or silicon oxynitride. In this embodiment, the material of the isolation layer is silicon oxide.

[0071] In this embodiment, the device gate structure 102 extends along a first direction (as indicated by the Y direction in the middle) and is arranged along a second direction (as indicated by the X direction in the middle), that is, the arrangement direction of the device gate structure 102 is the same as the arrangement direction of the working area 100A and the isolation area 100B. Figure 4 Figure 4 In this embodiment, the device gate structure 102 extends along a first direction (as indicated by the Y direction in the middle) and is arranged along a second direction (as indicated by the X direction in the middle), that is, the arrangement direction of the device gate structure 102 is the same as the arrangement direction of the working area 100A and the isolation area 100B.

[0072] When the transistor is in operation, the device gate structure 102 in the device area 100A is used to control the opening or closing of the conductive channel.

[0073] The device gate structure 102 in the isolation area 100B is used as a partition structure, thereby electrically isolating the transistors in the adjacent working area 100A.

[0074] It should be noted that the device gate structure 102 formed in the isolation area 100B is used as a partition structure. Compared with the prior art of cutting the fin portion, the scheme of forming a partition structure in the fin portion of the isolation area eliminates the process step of cutting the fin portion 100 in the isolation area 100B, reduces the impact of the cutting process on the conductive channel in the fin portion 100, and also reduces other process defects generated in the cutting process.

[0075] In this embodiment, the device gate structure 102 is located on the substrate, the device gate structure 102 spans the fin portion 100 and covers part of the top and part of the sidewall of the fin portion 100.

[0076] In this embodiment, the device gate structure 102 is a metal gate structure, and the device gate structure 102 includes a gate dielectric layer and a gate electrode layer covering the gate dielectric layer.

[0077] In this embodiment, the material of the gate dielectric layer includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2 and La2O3.

[0078] The gate electrode layer is used for subsequent electrical connection with an external interconnection structure. The material of the gate electrode layer includes one or more of TiN, TaN, Ta, Ti, TiAl, W, AL, TiSiN and TiAlC. Specifically, the gate electrode layer can include a work function layer and an electrode layer covering the work function layer, or the gate electrode layer can only include a work function layer.

[0079] ​In this embodiment, active source / drain doped layers (not shown) are formed in the substrate on both sides of the device gate structure 102. The source / drain doped layers are used as source regions or drain regions of transistors.

[0080] In this embodiment, bottom source / drain plugs 130 are formed on top of the source / drain doped layers on both sides of the device gate structure 102. The bottom source / drain plugs 130 are electrically connected to the source / drain doped layers and are used to electrically connect the source / drain doped layers to external circuits or other interconnect structures.

[0081] In this embodiment, top source / drain plugs are formed on top of the bottom source / drain plugs 130 and are in contact with the bottom source / drain plugs 115. The top source / drain plugs are electrically connected to the source / drain doped layers through the bottom source / drain plugs 130.

[0082] Reference is made to Figure 5 In this embodiment, a bottom dielectric layer 103 is formed on the substrate exposed by the device gate structure 102 and the bottom source / drain plugs 130. The bottom dielectric layer 103 covers the sidewalls of the device gate structure 102.

[0083] The material of the bottom dielectric layer 103 is an insulating material, which includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride. In this embodiment, the material of the bottom dielectric layer 103 is silicon oxide.

[0084] Specifically, the bottom source / drain plugs 130 are located in the bottom dielectric layer 103 on top of the source / drain doped layers.

[0085] Reference is made to Figure 6 and Figure 7 In this embodiment, after the device gate structure 102 is formed, a first interlayer dielectric layer 105 is formed to cover the device gate structure 102.

[0086] Specifically, the first interlayer dielectric layer 105 is formed after the bottom source / drain plugs 130 are formed, and thus the first interlayer dielectric layer 105 covers the bottom source / drain plugs 130.

[0087] The first interlayer dielectric layer 105 is used to provide a process basis for the subsequent formation of a sacrificial layer, and is also used to isolate a first gate plug and a second gate plug formed subsequently.

[0088] The material of the first interlayer dielectric layer 105 is an insulating material, which includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride. In this embodiment, the material of the first interlayer dielectric layer 105 is silicon oxide.

[0089] In this embodiment, the process of forming the first interlayer dielectric layer 105 includes a chemical vapor deposition process.

[0090] Reference is made to Figures 8 to 11 wherein, Figure 8 is a top view, Figure 9 is a top view, Figure 8 is a sectional view along the AB direction;

[0091] Figure 10 is a top view, Figure 11 is a top view, Figure 10 is a sectional view along the AB direction; in the isolation region 100B, a first trench 108 extending along the first direction (as indicated by the Y direction in the figure) and penetrating the first interlayer dielectric layer 105 is formed on top of the device gate structure 102. Figure 10

[0092] The first trench 108 provides a spatial position for the subsequent formation of a sacrificial layer.

[0093] In this embodiment, along the first direction, the first trench 108 simultaneously exposes each of the device gate structures 102 in the isolation region 100B, which is conducive to increasing the process window of the process of forming the first trench 108.

[0094] In other embodiments, the first trench can also correspond one-to-one to the device gate structures in the isolation region.

[0095] Reference is made to Figures 8 to 11 for a detailed description of the step of forming the first trench 108 in the isolation region 100B.

[0096] Reference is made to Figures 8 to 9 on top of the first interlayer dielectric layer 105, the first mask layer 107 has a first mask opening 106 in the isolation region, the top dimension W1 of the first mask opening 106 is greater than the bottom dimension of the first mask opening 106, the first mask opening 106 extends along the first direction (as indicated by the Y direction in the figure) and is located on top of the device gate structure 102. Figure 8

[0097] In this embodiment, the first mask layer 107 serves as an etching mask for forming the first trench 108.

[0098] ​​It should be noted that the top dimension W1 of the first mask opening 106 is larger than the bottom dimension of the first mask opening 106. This ensures that the first trench 108 formed in the isolation region 100B can have a smaller size during the process of transferring the first mask opening pattern to the first interlayer dielectric layer 105, so as to meet the process requirements. At the same time, compared with the scheme where the top and bottom dimensions of the first mask opening are equal, this embodiment can increase the process window for forming the first mask opening 106, thereby increasing the process window of the photolithography process required to form the first mask opening 106 and reducing the requirements for the photolithography process.

[0099] It should also be noted that the first mask opening 106 is along the second direction (e.g., Figure 8 The top dimension W1 (shown in the X direction) should not be too large or too small. If the first mask opening 106 is too large along the second direction, it is easy for the first mask opening 106 to also be located on top of the bottom source / drain plug 130 adjacent to the device gate structure 102 of the isolation region 100B. In the subsequent process of forming the first trench 108 using the first mask layer 107 as an etching mask, the probability of the related etching process damaging the top of the bottom source / drain plug 130 of the adjacent working region 100A increases, and it is also easy for the first trench 108 to expose the bottom source / drain plug 130 of the adjacent working region 100A, thereby causing the subsequently formed first gate plug to be short-circuited with the bottom source / drain plug 130 of the adjacent working region 100A, thus affecting the performance of the semiconductor structure. If the first mask opening 106 is too small along the second direction, it is easy for the size of the subsequently formed first trench along the second direction to fail to meet the process requirements, thereby affecting the formation quality and conductivity of the first gate plug, and thus affecting the performance of the semiconductor structure. Therefore, in this embodiment, the top dimension W1 of the first mask opening 106 along the second direction is 37 nanometers to 39 nanometers. For example, the top dimension W1 of the first mask opening 106 along the second direction is 38 nanometers.

[0100] In this embodiment, the first mask layer 107 includes a first organic material layer, a first anti-reflective coating on the first organic material layer, and a first photoresist layer on the first anti-reflective coating.

[0101] The material of the first organic material layer includes an organic material. In this embodiment, the material of the first organic material layer is spin-on carbon (SOC). In other embodiments, the material of the first organic material layer can also be other organic materials, such as one or more of an ODL (organic dielectric layer) material, a DUO (Deep UV Light Absorbing Oxide) material, and an APF (Advanced Patterning Film) material.

[0102] The material of the first anti-reflective coating layer includes a BARC (bottom anti-reflective coating) material. As an example, the BARC material is a Si-ARC (silicon-containing anti-reflective coating) material.

[0103] In this embodiment, in the process of forming the first mask layer 107, the first anti-reflective coating layer and the first organic material layer are etched in sequence with the first photoresist layer as a mask.

[0104] It should be noted that in other embodiments, in the process of etching the first anti-reflective coating layer and the first organic material layer, the first photoresist layer is consumed, and the first mask layer can correspondingly include only the first organic material layer and the first anti-reflective coating layer located on the first organic material layer.

[0105] Reference Figures 10 to 11 The first interlayer dielectric layer 105 is etched with the first mask layer 107 as a mask to form a first trench 108 extending along a first direction and penetrating through the first interlayer dielectric layer 105 on top of the device gate structure 102.

[0106] In this embodiment, the process of etching the first interlayer dielectric layer 105 with the first mask layer 107 as a mask includes an anisotropic dry etching process.

[0107] The anisotropic dry etching process has the characteristics of anisotropic etching, with a longitudinal etching rate much greater than a lateral etching rate, which can achieve quite accurate pattern transfer, improve the morphology quality of the sidewall of the first trench 108, and facilitate accurate control of the size D1 of the first trench 108 along the second direction. At the same time, the dry etching process has high process controllability, which reduces the probability of damage to the source-drain doped layer in the working area 100A in the process of forming the first trench 108.

[0108] It should be noted that the direction perpendicular to the extending direction of the device gate structure 102 is defined as the second direction (e.g., Figure 10 (As shown in the X direction), the dimension D1 of the first trench 108 along the second direction should not be too large or too small. If the dimension D1 of the first trench 108 along the second direction is too large, it will easily increase the probability that the first trench 108 exposes the bottom source / drain plug 130 of the adjacent working region 100A, thereby increasing the probability that the first gate plug subsequently formed in the first trench 108 will short-circuit with the source / drain doped regions on both sides of the device gate structure 102 in the working region 100A, thus reducing the performance of the semiconductor structure. If the dimension D1 of the first trench 108 along the second direction is too small, it will easily lead to the first gate plug subsequently formed in the first trench 108 having a dimension that is also too small along the second direction, making the conductivity of the first gate plug unable to meet the process requirements. Correspondingly, the electrical isolation effect of the device gate structure 102 in the isolation region 100A will decrease, thereby affecting the performance of the semiconductor structure. Therefore, in this embodiment, the direction perpendicular to the extension direction of the device gate structure 102 is taken as the second direction, and the dimension D1 of the first trench 108 along the second direction is 10 nanometers to 15 nanometers. For example, the dimension D1 of the first trench 108 along the second direction is 11 nanometers, 12 nanometers, or 14 nanometers.

[0109] It should be noted that, in this embodiment, after forming the first trench 108, the method for forming the semiconductor structure further includes: removing the first mask layer 107.

[0110] refer to Figures 12 to 13 ,in, Figure 12 It is a top view. Figure 13 for Figure 12 A cross-sectional view along the AB direction; a sacrificial layer 109 is formed in the first trench 108.

[0111] By forming a sacrificial layer 109 in the first trench 108, and subsequently forming the second trench, the position of the first contact hole is defined by the sacrificial layer 109 exposed by the mutual orthogonality between the first trench 108 and the second trench, thereby obtaining a first contact hole that can meet the process size requirements.

[0112] In this embodiment, the step of forming a sacrificial layer 190 in the first trench 108 includes: forming a sacrificial material layer (not shown) on the top of the first interlayer dielectric layer 105 and in the first trench 108; taking the top of the first interlayer dielectric layer 105 as the stop position, performing planarization processing on the sacrificial material layer above the top of the first interlayer dielectric layer 105, and using the remaining sacrificial material layer in the first trench 108 as the sacrificial layer 190.

[0113] In this embodiment, the material of the sacrificial layer includes one or more of silicon nitride, silicon carbide, and silicon carbide nitride.

[0114] Silicon nitride, silicon carbide, and silicon carbide nitride have high material hardness and a large etching selectivity with the first interlayer dielectric layer 105 and with the subsequently formed second interlayer dielectric layer. This makes it easier to remove the sacrificial layer 109 exposed by the second trench in the subsequent removal process, thereby reducing damage to the first interlayer dielectric layer 105 and the second interlayer dielectric layer. This, in turn, helps to accurately control the morphology, size, and position of the subsequently formed first contact hole.

[0115] In this embodiment, the process of forming a sacrificial material layer on top of the first interlayer dielectric layer 105 and in the first trench 108 includes a chemical vapor deposition process.

[0116] In this embodiment, the process for planarizing the sacrificial material layer above the top of the first interlayer dielectric layer 105 includes a chemical mechanical polishing process.

[0117] refer to Figures 14 to 15 ,in, Figure 14 It is a top view. Figure 15 for Figure 14 A cross-sectional view along the AB direction; a second interlayer dielectric layer 110 is formed on top of the sacrificial layer 109 and the first interlayer dielectric layer 105.

[0118] The second interlayer dielectric layer 110 provides the technological basis for the subsequent formation of the second trench.

[0119] The material of the second interlayer dielectric layer 110 is an insulating material, which includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, and silicon carbonitride. In this embodiment, the material of the second interlayer dielectric layer 110 is silicon oxide.

[0120] In this embodiment, the process for forming the second interlayer dielectric layer 110 includes chemical vapor deposition.

[0121] refer to Figures 16 to 21 ,in, Figure 16 It is a top view. Figure 17 for Figure 16 A sectional view along the AB direction. Figure 18 for Figure 16 A sectional view along the CD direction. Figure 19 It is a top view. Figure 20 for Figure 19 A sectional view along the AB direction. Figure 21 for Figure 19A cross-sectional view along the CD direction; a second direction (e.g., formed in the second interlayer dielectric layer 110) is described. Figure 19 A second trench 113 (as shown in the X direction) extends and penetrates the second interlayer dielectric layer 110. The projection of the second trench 113 onto the substrate is orthogonal to the projection of the sacrificial layer 109 onto the substrate, and the second trench 113 exposes a portion of the top surface of the sacrificial layer 109. The second direction is perpendicular to the first direction (e.g., as shown in the X direction). Figure 19 shown in the Y direction).

[0122] The projection of the second trench 113 onto the substrate is orthogonal to the projection of the sacrificial layer 109 onto the substrate, which means that the projection of the second trench 113 onto the substrate is orthogonal to the projection of the first trench 108 onto the substrate. Therefore, in this embodiment, by first forming a long strip-shaped first trench 108 extending along the first direction and then forming a long strip-shaped second trench 113 extending along the second direction, it is easy to obtain a first trench 108 and a second trench 113 with smaller widths respectively. By utilizing the mutual orthogonality of the first trench 108 and the second trench 113, a first contact hole that can meet the process size requirements can be subsequently obtained. Since active and drain doped regions are usually formed on both sides of the device gate structure 102 of the working region 100A, the device gate structure 102 of the isolation region 100B can be used as an isolation structure, while reducing the probability of short circuit between the subsequently formed first gate plug and the adjacent source and drain doped regions, thereby improving the performance of the semiconductor structure.

[0123] In this embodiment, along the second direction, the second trench 113 simultaneously exposes a portion of the top surface of each of the sacrificial layers 109 in the second direction, thereby increasing the process window for forming the second trench 113.

[0124] Furthermore, the sacrificial layer 109 exposed by the second trench 113 needs to be removed subsequently, and a first contact hole is formed in the first interlayer dielectric layer 105 to expose the top of the device gate structure 102. Therefore, by exposing a portion of the top surface of each of the sacrificial layers 109 in the second direction simultaneously by the second trench 113, it is beneficial to remove the exposed sacrificial layer 109 subsequently. For example, it can improve the efficiency of removing the exposed sacrificial layer 109 or increase the process window for removing the exposed sacrificial layer 109.

[0125] It should be noted that a first gate plug will be formed in the first contact hole. Since the interconnect structure connected to the first gate plug is usually located at the end of the device gate structure 102 in the first direction in the isolation region, in order to reduce the impact on conventional circuit design, the sacrificial layer 109 exposed by the second trench 113 is located at the end of the sacrificial layer 109.

[0126] With reference to Figures 16 to 21 The step of forming the second trench 113 in the second interlayer dielectric layer 110 is described in detail.

[0127] With reference to Figures 16 to 18 A second mask layer 112 with a second mask opening 111 is formed on top of the second interlayer dielectric layer 110, the top size W2 of the second mask opening 111 is larger than the bottom size of the second mask opening 111, the second mask opening 111 extends along the second direction and is located on top of the device gate structure 102.

[0128] In this embodiment, the second mask layer 112 serves as an etching mask for forming the second trench 113.

[0129] It is to be noted that the top size W1 of the second mask opening 111 is larger than the bottom size of the second mask opening 111, so that in the process of transferring the second mask opening pattern to the second interlayer dielectric layer 110, the size of the second trench 113 formed in the second interlayer dielectric layer 110 along the first direction can be ensured to be small enough to meet the process requirements. Meanwhile, compared with the scheme in which the top size and the bottom size of the second mask opening are equal, this embodiment can increase the process window for forming the second mask opening 111, and reduce the process window of the photolithography process required for forming the second mask opening 111, and reduce the requirements for the photolithography process.

[0130] It is to be further noted that the second mask opening 111 extends along the first direction (for example, the horizontal direction) and the second direction (for example, the vertical direction) of the device gate structure 102. Figure 16The top size W2 of the second mask opening 111 in the first direction should not be too large or too small. If the top size W2 of the second mask opening 111 in the first direction is too large, the size of the second groove 113 formed by taking the second mask layer 112 as a mask in the first direction will also be too large, and accordingly, the size of the first contact hole formed subsequently in the first direction will also be too large, so that the first gate plug formed subsequently in the first contact hole cannot meet the process size requirement, affecting the performance of the semiconductor structure. If the top size W2 of the second mask opening 111 in the first direction is too small, the size of the second groove 113 formed in the first direction will also be too small, and accordingly, the size of the first contact hole formed subsequently in the first direction will also be too small, which will increase the difficulty of filling the material of the subsequent first gate plug in the first contact hole, and cause the first gate plug formed subsequently in the first contact hole to be unable to meet the process size requirement, so that the electrical isolation effect of the device gate structure 102 formed subsequently in the isolation region 100A is reduced, and the performance of the semiconductor structure is affected. Therefore, in the embodiment, the top size W2 of the second mask opening 111 in the first direction is 37-39 nm. For example, the top size W2 of the second mask opening 111 in the first direction is 38 nm.

[0131] In the embodiment, the second mask layer 112 is described as described above for the first mask layer 107, and will not be described here.

[0132] Reference is made to Figures 19 to 21 The second interlayer dielectric layer 110 is etched by taking the second mask layer 112 as a mask to form a second groove 113 extending in the second direction (as shown in the X direction) and penetrating through the second interlayer dielectric layer 110 on the top of the device gate structure 102. Figure 19 The second groove 113 extends in the second direction (as shown in the X direction) and penetrates through the second interlayer dielectric layer 110.

[0133] In the embodiment, the process of etching the second interlayer dielectric layer 110 by taking the second mask layer 112 as a mask includes an anisotropic dry etching process.

[0134] The anisotropic dry etching process has the characteristics of anisotropic etching, and the longitudinal etching rate is much larger than the lateral etching rate, which can obtain quite accurate pattern transfer, improve the morphology quality of the sidewall of the second groove 113, and is beneficial to accurately control the size D2 of the second groove 113 in the first direction.

[0135] It should be noted that the size D2 of the second trench 113 in the first direction should not be too large or too small. If the size D2 of the second trench 113 in the first direction is too large, it will easily lead to the size of the first gate plug subsequently formed in the second trench 113 in the first direction being too large, increasing the probability of shorting the first gate plug and the bottom source-drain plug 130 on both sides of the device gate structure 102 in the device region 100A, thereby affecting the performance of the semiconductor structure. If the size D2 of the second trench 113 in the first direction is too small, it will easily lead to the size of the first gate plug subsequently formed in the second trench 113 in the first direction being too small, i.e., the size of the first gate plug in the first direction cannot meet the process requirements, so that the conductive performance of the first gate plug cannot meet the process requirements, and accordingly, the electrical isolation effect of the device gate structure 102 in the isolation region 100A is reduced, thereby affecting the performance of the semiconductor structure. Therefore, in the embodiment, the size D2 of the second trench 113 in the first direction is 10-15 nm. For example, the size D2 of the second trench 113 in the first direction is 11 nm, 12 nm or 14 nm.

[0136] It should also be noted that after the second trench 113 is formed, the method for forming the semiconductor structure further includes removing the second mask layer 112.

[0137] Reference Figures 22 to 24 , wherein, Figure 22 is a top view, Figure 23 is Figure 22 is a sectional view in the AB direction, Figure 24 is Figure 22 is a sectional view in the CD direction; removing the sacrificial layer 109 exposed by the second trench 113 to form a first contact hole 115 in the first interlayer dielectric layer 105, which exposes the top of the device gate structure 102.

[0138] The first contact hole 115 provides a spatial position for the subsequent formation of a first gate plug.

[0139] In the embodiment, the process of removing the sacrificial layer 109 exposed by the second trench 113 includes a dry etching process.

[0140] The dry etching process is an anisotropic dry etching process. The anisotropic dry etching process has the characteristics of anisotropic etching, with a longitudinal etching rate much greater than a lateral etching rate, which can achieve quite accurate pattern transfer and improve the morphology quality and size accuracy of the side wall of the first contact hole 115.

[0141] It should be noted that in the step of removing the exposed sacrificial layer 109 from the second trench 113, the etching selectivity ratio of the sacrificial layer 109 to the first interlayer dielectric layer 105 should not be too small. If the etching selectivity ratio of the sacrificial layer 109 to the first interlayer dielectric layer 105 is too small, the etching process used in the process of removing the exposed sacrificial layer 109 from the second trench 113 is also likely to remove the first interlayer dielectric layer 105, thereby increasing the probability of shorting the first gate plug formed in the isolation region 100B to the bottom source / drain plug 130 in the subsequent process, thereby affecting the performance of the semiconductor structure. Therefore, in the embodiment, the etching selectivity ratio of the sacrificial layer 109 to the first interlayer dielectric layer 105 is greater than 5:1 in the step of removing the exposed sacrificial layer 109 from the second trench 113.

[0142] It should also be noted that in the step of removing the exposed sacrificial layer 109 from the second trench 113, the etching selectivity ratio of the sacrificial layer 109 to the second interlayer dielectric layer 110 should not be too small. If the etching selectivity ratio of the sacrificial layer 109 to the second interlayer dielectric layer 110 is too small, the etching process used in the process of removing the exposed sacrificial layer 109 from the second trench 113 is also likely to cause damage to the second interlayer dielectric layer 110 exposed by the sidewall of the second trench 113, and accordingly, the size of the second trench 113 in the first direction is increased, so that the size of the first contact hole 115 formed in the first direction cannot meet the process requirements, thereby affecting the performance of the semiconductor structure. Therefore, in the embodiment, the etching selectivity ratio of the sacrificial layer 109 to the second interlayer dielectric layer 110 is greater than 5:1 in the step of removing the exposed sacrificial layer 109 from the second trench 113.

[0143] Reference Figure 25 In the working area 100A, a second contact hole 117 is formed in the second interlayer dielectric layer 110 and the first interlayer dielectric layer 105 on top of the device gate structure 102.

[0144] The second contact hole 117 provides a spatial position for the subsequent formation of a second gate plug in the working area 100A.

[0145] In the embodiment, the process of forming the second contact hole 117 includes a dry etching process.

[0146] It should be noted that in the step of forming the second contact hole 117 in the first interlayer dielectric layer 105, it also includes forming a source / drain contact hole 116 through the second interlayer dielectric layer 110 and the first interlayer dielectric layer 105 on top of the bottom source / drain plug 130 located between adjacent device gate structures 102, and the source / drain contact hole 116 exposes the bottom source / drain plug 130.

[0147] The source-drain contact hole 116 provides a spatial position for a subsequently formed top source-drain plug.

[0148] Reference is made to Figures 26 to 31 wherein, Figure 26 is a top view, Figure 27 is Figure 26 is a sectional view along the AB direction, Figure 28 is Figure 26 is a sectional view along the CD direction, Figure 29 is a top view, Figure 30 is Figure 29 is a sectional view along the AB direction, Figure 31 is Figure 29 is a sectional view along the CD direction; a first gate plug 119 is formed in the first contact hole 115, the first gate plug 119 is electrically connected with the device gate structure 102 of the isolation region 100B, the first gate plug 119 is used to load a first electric potential, a second gate plug 120 is formed on the top of the device gate structure 102 of the working region 100A, the second gate plug 120 is electrically connected with the device gate structure 102 of the working region 100A, the second gate plug 120 is used to load a second electric potential, the second electric potential and the first electric potential are opposite electric potentials.

[0149] The first gate plug 119 is used to realize electrical connection between the device gate structure 102 in the isolation region 100B and an external circuit or other interconnection structure, and the second gate plug 120 is used to realize electrical connection between the device gate structure 102 in the working region 100A and an external circuit or other interconnection structure.

[0150] In the embodiment, the first gate plug 119 is formed in the first contact hole 115 and the second gate plug 120 is formed in the second contact hole 117 in the same step.

[0151] Specifically, the first gate plug 119 and the second gate plug 120 are formed in the same step, which reduces the process steps and lowers the process cost. In other embodiments, the first gate plug can be formed first and then the second gate plug is formed, or the second gate plug can be formed first and then the first gate plug is formed.

[0152] In the embodiment, the steps of forming the first gate plug 119 and the second gate plug 120 include: forming a conductive material layer 118 in the first contact hole 115, the second contact hole 117, and the second trench 113, as shown in FIG. 6A; and removing the conductive material layer 118 in the first contact hole 115 and the second contact hole 117, as shown in FIG. 6B. Figures 26 to 28 Figures 29 to 31 ​As shown, the conductive material layer 118 above the top of the first interlayer dielectric layer 105 and the sacrificial layer 109 and the second interlayer dielectric layer 110 are planarized with the top of the first interlayer dielectric layer 105 as a stop position, the conductive material layer 118 remaining in the first contact hole 115 as the first gate plug 119, and the conductive material layer 118 remaining in the second contact hole 117 as the second gate plug 120.

[0153] Subsequently, interconnection structures electrically connected to the first gate plug 119 and the second gate plug 120 are formed, and therefore, the second interlayer dielectric layer 110 is removed during the planarization process to obtain the discrete first gate plug 119, so as to reduce the influence on the subsequent formation process of the interconnection structures and improve the process compatibility of the second gate plug 120.

[0154] In the embodiment, the materials of the first gate plug 119 and the second gate plug 120 are tungsten. The tungsten has a low resistivity, which is beneficial to improve the signal delay of the back-end RC and improve the processing speed of the chip, and is also beneficial to reduce the resistance of the first gate plug 119 and the second gate plug 120 and accordingly reduce the power consumption. In other embodiments, the materials of the first gate plug and the second gate plug can also be cobalt or ruthenium or other conductive materials.

[0155] It should be noted that the top source / drain plug 121 is formed in the source / drain contact hole 116 during the process of forming the first gate plug 119 in the first contact hole 115 and forming the second gate plug 120 in the second contact hole 117.

[0156] The top source / drain plug 121 is electrically connected to the source / drain doped layer through the bottom source / drain plug 130, so as to lead out the electrical property of the source / drain doped layer.

[0157] In the embodiment, the device gate structure 102 in the isolation region 100B plays a role of electrical isolation for the adjacent working region 100A.

[0158] Specifically, the first gate plug 119 is used to load a first potential, and the second gate plug 120 is used to load a second potential, and the second potential and the first potential are opposite potentials.

[0159] When the device region 100A is used as an NMOS transistor, the device gate structure 102 in the isolation region 100B needs to load a first potential as a cutoff gate voltage in order to achieve the electrical isolation effect on the adjacent NMOS transistor. Since the NMOS transistor in the device region 100A needs to load a positive second potential to be turned on, the device gate structure 102 in the isolation region 100B needs to load a negative voltage, so that there is no current conduction between the device regions 100A on both sides of the isolation region 100B, and the device gate structure 102 in the isolation region 100B can achieve the electrical isolation effect.

[0160] When the device region 100A is used as a PMOS transistor, the device gate structure 102 in the isolation region 100B needs to load a first potential as a cutoff gate voltage in order to achieve the electrical isolation effect on the adjacent PMOS transistor. Since the PMOS transistor in the device region 100A needs to load a negative second potential to be turned on, the device gate structure 102 in the isolation region 100B needs to load a positive voltage, so that there is no current conduction between the device regions 100A on both sides of the isolation region 100B, and the device gate structure 102 in the isolation region 100B can achieve the electrical isolation effect.

[0161] Although the present application has been disclosed as above, the present application is not limited to this. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present application, and the protection scope of the present application should be limited by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized by, The application relates to a semiconductor device and a manufacturing method thereof. The semiconductor device comprises: a substrate comprising a substrate and a fin standing on the substrate, the substrate comprising adjacent working areas and isolation areas; an isolation layer on the substrate exposed by the fin, the isolation layer covering part of the sidewall of the fin; a device gate structure on the substrate of the working areas and the isolation areas respectively, the device gate structure of the isolation area serving as a partition structure; a bottom dielectric layer on the substrate exposed by the device gate structure and covering the sidewall of the device gate structure, the top of the bottom dielectric layer being flush with the top of the device gate structure; a first dielectric layer on the top of the device gate structure and the bottom dielectric layer of the isolation area, the first dielectric layer extending in the same direction as the device gate structure, the first dielectric layer exposing part of the top surface of the device gate structure; a second dielectric layer on the top of the substrate, covering the top of the device gate structure and the sidewall of the first dielectric layer, the top of the second dielectric layer being flush with the top of the first dielectric layer; a first gate plug in the isolation area, penetrating the second dielectric layer on the top of the device gate structure and electrically connected with the top of the device gate structure exposed by the first dielectric layer, the first gate plug being used for loading a first electric potential; 2. The semiconductor structure of claim 1, wherein, a second gate plug in the working area, penetrating the second dielectric layer on the top of the device gate structure, the second gate plug being electrically connected with the device gate structure of the working area, the second gate plug being used for loading a second electric potential, the second electric potential and the first electric potential being opposite electric potentials.

3. The semiconductor structure of claim 1, wherein, The device gate structure extends in a first direction, and the size of the first gate plug along the first direction is 10-15 nm.

4. The semiconductor structure of claim 1, wherein, The device gate structure extends in a second direction perpendicular to the extending direction of the device gate structure, and the size of the first gate plug along the second direction is 10-15 nm.

5. The semiconductor structure of claim 1, wherein, The material of the first dielectric layer comprises one or more of silicon nitride, silicon carbide and silicon carbon nitride. The device gate structure comprises a gate dielectric layer and a gate electrode layer covering the gate dielectric layer; The material of the gate dielectric layer comprises one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2 and La2O3; 6. The semiconductor structure of claim 1, wherein, The material of the gate electrode layer comprises one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN and TiAlC.

7. A method of forming a semiconductor structure, comprising: The material of the first gate plug comprises one or more of tungsten, cobalt and ruthenium; and the material of the second gate plug comprises one or more of tungsten, cobalt and ruthenium. The application relates to a semiconductor device and a manufacturing method thereof. The semiconductor device comprises: a substrate comprising adjacent working areas and isolation areas, the substrate of the working areas and the isolation areas being provided with device gate structures extending in a first direction, the device gate structure of the isolation area serving as a partition structure, and the top of the substrate being provided with a first interlayer dielectric layer covering the top of the device gate structure. forming a first trench extending along the first direction and penetrating through the first interlayer dielectric layer on top of the device gate structure in the isolation region; forming a sacrificial layer in the first trench; forming a second interlayer dielectric layer on top of the sacrificial layer and the first interlayer dielectric layer; forming a second trench extending along a second direction and penetrating through the second interlayer dielectric layer in the second interlayer dielectric layer, a projection of the second trench on the substrate being orthogonal to a projection of the sacrificial layer on the substrate, and the second trench exposing a part of a top surface of the sacrificial layer, the second direction being perpendicular to the first direction; removing the sacrificial layer exposed by the second trench to form a first contact hole exposing the top of the device gate structure in the first interlayer dielectric layer; forming a first gate plug in the first contact hole, the first gate plug being electrically connected to the device gate structure of the isolation region, and the first gate plug being used to load a first electric potential; forming a second gate plug on top of the device gate structure of the working region, the second gate plug being electrically connected to the device gate structure of the working region, and the second gate plug being used to load a second electric potential, the second electric potential and the first electric potential being opposite electric potentials.

8. The method of forming a semiconductor structure of claim 7, wherein, The step of forming the first trench in the isolation region comprises: forming a first mask layer on top of the first interlayer dielectric layer, the first mask layer having a first mask opening in the isolation region, a top dimension of the first mask opening being greater than a bottom dimension of the first mask opening, the first mask opening extending along the first direction and being located on top of the device gate structure; and etching the first interlayer dielectric layer with the first mask layer as a mask to form the first trench extending along the first direction and penetrating through the first interlayer dielectric layer on top of the device gate structure.

9. The method of forming a semiconductor structure of claim 8, wherein, The top dimension of the first mask opening along the second direction is 37 nm to 39 nm.

10. The method of forming a semiconductor structure of claim 7, wherein, The second direction is perpendicular to the extending direction of the device gate structure, and the size of the first trench along the second direction is 10 nm to 15 nm.

11. The method of forming a semiconductor structure of claim 7, wherein, The step of forming the second trench extending along the second direction and penetrating through the second interlayer dielectric layer in the second interlayer dielectric layer comprises: forming a second mask layer having a second mask opening on top of the second interlayer dielectric layer, a top dimension of the second mask opening being greater than a bottom dimension of the second mask opening, the second mask opening extending along the second direction and being located on top of the device gate structure; and etching the second interlayer dielectric layer with the second mask layer as a mask to form the second trench extending along the second direction and penetrating through the second interlayer dielectric layer on top of the device gate structure.

12. The method of forming a semiconductor structure of claim 11, wherein, The top dimension of the second mask opening along the first direction is 37 nm to 39 nm.

13. The method of forming a semiconductor structure of claim 7, wherein, The size of the second trench along the first direction is 10 nm to 15 nm.

14. The method of forming a semiconductor structure of claim 7, wherein, The step of forming the sacrificial layer in the first trench comprises: forming a sacrificial material layer on top of the first ILD layer and in the first trench; planarizing the sacrificial material layer above the top of the first ILD layer with the top of the first ILD layer as a stop layer, the remaining sacrificial material layer in the first trench as the sacrificial layer.

15. The method of forming a semiconductor structure of claim 7, wherein, After forming the first contact hole, before forming the first gate plug in the first contact hole, the method further comprises: forming a second contact hole in the second ILD layer and the first ILD layer on top of the device gate structure in the working area, the second contact hole exposing the top of the device gate structure The first gate plug is formed in the first contact hole and the second gate plug is formed in the second contact hole in the same step.

16. The method of forming a semiconductor structure of claim 15, wherein, The step of forming the first gate plug and the second gate plug comprises: forming a conductive material layer in the first contact hole, the second contact hole, and the second trench; planarizing the conductive material layer above the top of the first ILD layer and the sacrificial layer and the second ILD layer with the top of the first ILD layer as a stop layer, the remaining conductive material layer in the first contact hole as the first gate plug, and the remaining conductive material layer in the second contact hole as the second gate plug.

17. The method of forming a semiconductor structure of claim 7, wherein, Along the first direction, the first trench exposes the device gate structure in the isolation region in the first direction simultaneously.

18. The method of forming a semiconductor structure of claim 7, wherein, Along the second direction, the second trench exposes the top surface of the sacrificial layer in the second direction simultaneously.

19. The method of forming a semiconductor structure of claim 7, wherein, In the step of removing the sacrificial layer exposed by the second trench, the etching selectivity ratio of the sacrificial layer to the first ILD layer is greater than 5:1.

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