Shared-gate vertical two-dimensional complementary field-effect transistor device and its fabrication method

Abstract

This invention provides a vertically aligned two-dimensional complementary field-effect transistor (FET) device with a shared gate and its manufacturing method. The device includes: a substrate with protrusions; and FET units disposed on the protrusions in a vertical direction perpendicular to the substrate, each FET unit corresponding to a protrusion. The FET units include P-type FET sub-units and N-type FET sub-units, with the N-type and P-type FET sub-units sharing a common gate. The method includes: fabricating the protrusions and multiple FET unit prototypes perpendicular to the substrate on the substrate, with a framework connection at both ends of the FET unit prototypes; performing N-type and P-type doping treatments on the upper and lower sections of the FET unit prototypes, respectively; etching to expose the upper section of the FET unit prototypes, with a silicon oxynitride layer disposed on the upper section; growing an inter-FET connection of the same material as the substrate at the connection between the upper and lower sections; and then performing post-processing.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device and fabrication technology, and particularly to a vertical two-dimensional complementary field-effect transistor device with a shared gate and its manufacturing method. Background Technology

[0002] Complementary field-effect transistor devices (i.e., CMOS field-effect transistor devices) include two types of transistors: NMOS and PMOS. CMOS integrated circuits use field-effect transistors, and they are all complementary structures. When working, the two field-effect transistors connected in series are always in a state where one transistor is on and the other is off. Theoretically, the static power consumption of the circuit is zero. In reality, due to leakage current, CMOS circuits still have a small amount of static power consumption.

[0003] Traditional complementary field-effect devices are horizontally mounted on a substrate, meaning that the source, gate, and drain of the field-effect device are all horizontally laid on the silicon substrate. They have mature manufacturing processes to produce. During the manufacturing process, due to the large area of ​​support provided by the silicon substrate, the device height is small, resulting in good structural stability during the process and preventing instability and deformation that could affect quality and yield.

[0004] However, the laying process occupies a large area of ​​the silicon substrate, thus reducing the number and density of devices per unit area. In addition, multiple field-effect devices on the same substrate often require additional wiring connections, which occupy space and thus affect the integration of semiconductors, hindering miniaturization. Summary of the Invention

[0005] To address the aforementioned technical problems, this invention provides a vertical two-dimensional complementary field-effect transistor device with a shared gate, comprising:

[0006] The substrate includes the protrusions;

[0007] A field-effect transistor (FET) unit is disposed on the protrusion in a vertical direction perpendicular to the substrate. Each FET unit corresponds to one of the protrusions. The FET unit includes a P-type FET sub-unit and an N-type FET sub-unit. The N-type FET sub-unit and the P-type FET sub-unit each include a source, a gate, and a drain. The N-type FET sub-unit and the P-type FET sub-unit share a gate.

[0008] Optionally, the P-type field-effect transistor unit is n-shaped, and the N-type field-effect transistor unit is u-shaped; the two sides of the lower opening of the n-shaped P-type field-effect transistor unit are the source or drain respectively and are connected to the protrusion of the substrate, and the upper connection terminal of the n-shaped P-type field-effect transistor unit is the gate; the two sides of the upper opening of the u-shaped N-type field-effect transistor unit are the source or drain respectively, and the lower connection terminal of the u-shaped N-type field-effect transistor unit is the gate; the N-type field-effect transistor unit is located above the P-type field-effect transistor unit, and the gates of the two are an integral structure.

[0009] Optionally, the field-effect transistor units are arranged in multiple groups on the same substrate in a parallel, vertically spaced manner.

[0010] Optionally, the field-effect transistor units are multiple and arranged in parallel and spaced apart on the substrate, and fracture grooves are provided between adjacent field-effect transistor units.

[0011] Optionally, the gate and the top of the protrusion are connected to the opening at the bottom of the P-type field-effect transistor unit with titanium nitride sheets extending horizontally to the fracture groove.

[0012] Optionally, a cobalt silicide block is provided on both sides of the opening end of the lower part of the protrusion and the lower part of the n-shaped P-type field effect tube unit.

[0013] The present invention also provides a method for manufacturing a vertical two-dimensional complementary field-effect transistor device with a shared gate, comprising the following steps:

[0014] S100 processes protrusions on a substrate and sets field-effect transistor (FET) unit prototypes perpendicular to the substrate on the protrusions. Each FET unit prototype corresponds to a protrusion. Each FET unit prototype includes two FET sub-unit prototypes. The two ends of the FET unit prototypes are connected by a skeleton. The upper and lower sections of the FET unit prototypes are N-type and P-type doped, respectively, and filled with a first insulating material.

[0015] The S200 has a first etching mask on its skeleton to perform the first etching to remove the first insulating material between the upper sections of the prototype field-effect transistor unit.

[0016] The S300 has a silicon oxynitride layer on the upper section of the prototype field-effect transistor unit, exposing the connection between the upper and lower sections of the prototype field-effect transistor unit.

[0017] S400 grows a single crystal material with the same lattice arrangement as the substrate at the connection between the upper and lower sections of the exposed field-effect transistor unit prototype, so that the two field-effect transistor units of the same field-effect transistor unit prototype are connected, and then a post-processing process is performed to obtain a vertical two-dimensional complementary field-effect transistor device with a shared gate.

[0018] Optionally, the processing technology for the protrusions and the prototype of the field-effect transistor unit in step S100 is as follows:

[0019] S10 Based on the wafer spacing of the opening ends of the P-type field-effect transistor unit and / or the inter-group distance of the field-effect transistor group, a first forming line film layer is set on the substrate surface with the thickness dimension of the field-effect transistor unit as the width, and a first etching mask intersecting with the first forming line film layer is set on the substrate surface at intervals according to a set distance.

[0020] S20 performs the first pre-etching on the substrate, forming a first groove of a first depth between two field-effect transistor sub-unit prototypes in the same field-effect group, and forming a second groove of a second depth on the outside of the field-effect group, thus forming a field-effect transistor unit prototype; the first depth is less than the second depth and the height difference between the two forms a protrusion on the substrate;

[0021] S30 removes the first forming line film layer and the first etching mask, performs doping treatment, fills the first groove and the second groove with the second insulating material and performs flattening treatment, restores the first forming line film layer and the first etching mask, and performs a second pre-etching. Except for the root of the field effect tube unit prototype, the second insulating material layer is retained at the first groove and the second groove.

[0022] S40 undergoes cobalt infiltration treatment to form a cobalt silicide block at the root of the field-effect transistor unit prototype; titanium nitride connection is set between the roots of two field-effect transistor unit prototypes in adjacent effect modules.

[0023] Optionally, in step S300, the post-processing includes:

[0024] S410 fills the upper section of the field-effect transistor unit prototype with a first insulating material and performs a flattening process. In addition to the skeleton, a second etching mask is set to perform a second etching to form a third groove with a third depth, the third depth reaching the lower edge of the gate.

[0025] After filling the third groove with the second insulating material and smoothing it out, S430 performs a third etching to form a fourth groove with a fourth depth, and the upper edge of the gate at the fourth depth; a first insulating material film layer is formed on the sidewall of the fourth groove;

[0026] S450 forms a gate slot by etching the middle gate segment through the fourth groove, forms a second insulating material layer on the sidewall of the gate slot, and fills the gate slot with metal to form a metal layer;

[0027] S470 uses a first insulating material to fill the fourth groove and performs intelligent diffusion fracture cutting at the middle position of adjacent field effect groups.

[0028] Optionally, in step S10, the first forming line film layer is configured as follows:

[0029] S11 involves setting a polymer layer on the surface of a silicon substrate, and performing dry photolithography with spaced strip-shaped protective layers to form multiple spaced strip-shaped polymer layers.

[0030] S12 After filling the groove of dry photolithography with the first insulating material and flattening it, the first sidewall etching is performed to form the first insulating material layer on both sides of the strip-shaped polymer layer.

[0031] S13 fills the grooves etched on the sidewalls with carbon-containing material and polishes them smooth.

[0032] S14 Remove the strip-shaped polymer layer, fill with the second insulating material, and perform a second sidewall etching to form the second insulating layer on the side of the first insulating material layer away from the carbon-containing material filling layer;

[0033] S15 removes the first insulating material layer and the carbon-containing material, and the remaining second insulating material layer is the first molded wire film layer.

[0034] Optionally, in step S30, the doping process is as follows:

[0035] The upper and lower ends of the two field-effect transistor sub-unit prototypes in the same field-effect group are respectively doped with N-type source / drain and P-type source / drain.

[0036] The upper and lower connecting pieces of the two field-effect transistor unit prototypes in the same field-effect group are subjected to gate doping treatment.

[0037] The present invention discloses a shared-gate vertical two-dimensional complementary field-effect transistor (FET) device and its manufacturing method. This involves fabricating protrusions and FET sub-unit prototypes perpendicular to the substrate on a substrate. Two FET sub-unit prototypes are correspondingly positioned at the top of each protrusion. A frame is provided at both ends of each FET sub-unit prototype. Two FET sub-unit prototypes at the same top of the same protrusion form a group. The upper and lower sections of the FET sub-unit prototypes are subjected to N-type and P-type doping treatments, respectively, and filled with a first insulating material. A first etching mask is provided on the frame as a protective layer. A first etching is performed to remove the first insulating material between the upper sections of the FET sub-unit prototypes. Because the FET sub-unit prototypes are protected by the frame at both ends, the vertical field-effect transistor device… Tensioned framework structures are formed at both ends of the prototype to prevent the prototype field-effect transistor unit from falling over. A silicon oxynitride layer is set on the upper section of the prototype field-effect transistor unit, exposing a single crystal material with the same lattice arrangement as the substrate at the connection between the upper and lower sections of the prototype field-effect transistor unit. This allows two field-effect transistor units in the same group to be connected. After post-processing, a vertical two-dimensional complementary field-effect transistor device with a shared gate is obtained. Since the formed N-type field-effect transistor unit and P-type field-effect transistor unit share a gate and a metal connection is set at the shared gate, it is not necessary to add wiring connections to each field-effect transistor unit, avoiding the space occupied by connection lines, thereby further improving the integration density of the vertical two-dimensional field-effect device.

[0038] Other features and advantages of the invention will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of the invention may be realized and obtained by means of the structures particularly pointed out in the written description, claims, and drawings.

[0039] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0040] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used in conjunction with embodiments of the invention to explain the invention and do not constitute a limitation thereof. In the drawings:

[0041] Figure 1 This is a schematic cross-sectional view of a vertical two-dimensional complementary field-effect transistor device with a shared gate according to an embodiment of the present invention;

[0042] Figure 2 This is a flowchart illustrating a manufacturing method for a vertical two-dimensional complementary field-effect transistor device with a shared gate, according to an embodiment of the present invention.

[0043] Figure 3 This is a process flow diagram of the prototype manufacturing process of the field-effect transistor sub-unit in an embodiment of the manufacturing method of the shared-gate vertical two-dimensional complementary field-effect transistor device of the present invention.

[0044] Figure 4 This is a post-processing flow chart of an embodiment of the manufacturing method of the shared-gate vertical two-dimensional complementary field-effect transistor device of the present invention.

[0045] Figure 5 This is a flowchart illustrating the setting of the first molding line film layer in the manufacturing process of the prototype field-effect transistor sub-unit in an embodiment of the manufacturing method of the shared-gate vertical two-dimensional complementary field-effect transistor device of the present invention.

[0046] Figure 6 This is a schematic planar view of a prototype field-effect transistor sub-unit in an embodiment of the manufacturing method of the shared-gate vertical two-dimensional complementary field-effect transistor device of the present invention.

[0047] Figure 7 This is a schematic cross-sectional view of the prototype field-effect transistor sub-unit a-a' formed by doping treatment in an embodiment of the manufacturing method of the vertical two-dimensional complementary field-effect transistor device with shared gate of the present invention.

[0048] Figure 8 This is a schematic diagram of the a-a' cross-section of the prototype field-effect transistor sub-unit after the formation of the cobalt silicide block in an embodiment of the manufacturing method of the shared-gate vertical two-dimensional complementary field-effect transistor device of the present invention.

[0049] Figure 9 A schematic diagram of cross section a-a' after titanium nitride connection is provided between the roots of the prototype field-effect transistor sub-units in an embodiment of the manufacturing method of a vertical two-dimensional complementary field-effect transistor device with a shared gate.

[0050] Figure 10 A schematic diagram of cross section a-a' after titanium nitride connection is provided between the roots of the prototype field-effect transistor sub-units and the first insulator is filled in an embodiment of the manufacturing method of a vertical two-dimensional complementary field-effect transistor device with a shared gate.

[0051] Figure 11 A schematic diagram of the a-a' cross-section of the prototype field-effect transistor sub-unit after the first etching in an embodiment of the manufacturing method of a vertical two-dimensional complementary field-effect transistor device with a shared gate.

[0052] Figure 12 This is a schematic diagram of the a-a' section of a prototype field-effect transistor sub-unit after the first etching and with a silicon nitride layer disposed on the upper section, in an embodiment of a method for manufacturing a vertical two-dimensional complementary field-effect transistor device with a shared gate.

[0053] Figure 13 This is a schematic diagram of cross section a-a' of the field-effect transistor sub-unit prototype exposed at the connection between the upper and lower sections after the first etching and the application of a silicon nitride layer on the upper section in an embodiment of the manufacturing method for a vertical two-dimensional complementary field-effect transistor device with a shared gate.

[0054] Figure 14 A schematic diagram of cross section a-a' of a prototype field-effect transistor sub-unit in an embodiment of a manufacturing method for a vertical two-dimensional complementary field-effect transistor device with a shared gate, in which the first insulating layer is removed at the connection between the exposed upper and lower sections.

[0055] Figure 15 In an embodiment of the manufacturing method for a vertical two-dimensional complementary field-effect transistor device with a shared gate, a single crystal material with the same lattice arrangement as the substrate is grown at the connection between the exposed upper and lower sections, so that the prototype of the field-effect transistor unit after the connection of two field-effect transistor sub-units in the same group is shown in cross section a-a'.

[0056] Figure 16 A schematic diagram of cross section a-a' after filling the upper segment of the prototype field-effect transistor sub-unit with a first insulator in the post-processing stage of the manufacturing method embodiment of a vertical two-dimensional complementary field-effect transistor device with a shared gate.

[0057] Figure 17 A planar schematic diagram of the post-processing stage after setting the second etch mask in an embodiment of the manufacturing method for a vertical two-dimensional complementary field-effect transistor device with a shared gate.

[0058] Figure 18 A schematic diagram of the b-b' cross-section after a second etching and filling of a second insulator in the post-processing stage of a manufacturing method embodiment for a vertical two-dimensional complementary field-effect transistor device with a shared gate.

[0059] Figure 19 A schematic diagram of the c-c' cross-section after a second etching and filling of a second insulator in the post-processing stage of a manufacturing method embodiment for a vertical two-dimensional complementary field-effect transistor device with a shared gate.

[0060] Figure 20 A schematic diagram of the a-a' cross-section after the third etching in the post-processing stage of a manufacturing method embodiment for a vertical two-dimensional complementary field-effect transistor device with a shared gate.

[0061] Figure 21 A schematic diagram of the b-b' cross-section after the third etching in the post-processing stage of a manufacturing method embodiment for a vertical two-dimensional complementary field-effect transistor device with a shared gate.

[0062] Figure 22 A schematic diagram of the c-c' cross-section after the third etching in the post-processing stage of a manufacturing method embodiment for a vertical two-dimensional complementary field-effect transistor device with a shared gate.

[0063] Figure 23 This is a schematic diagram of cross-section a-a' after forming the gate slot and filling the metal layer in the post-processing stage of a manufacturing method embodiment for a vertical two-dimensional complementary field-effect transistor device with a shared gate.

[0064] Figure 24 This is a schematic diagram of the b-b' cross-section after the gate slot is formed and the metal layer is filled in the post-processing stage of a manufacturing method embodiment for a vertical two-dimensional complementary field-effect transistor device with a shared gate.

[0065] Figure 25 A schematic diagram of the c-c' cross-section after forming the gate slot and filling the metal layer in the post-processing stage of a manufacturing method embodiment for a vertical two-dimensional complementary field-effect transistor device with a shared gate.

[0066] Figure 26 A schematic diagram of a planar image after intelligent diffusion fracture cutting is performed in the post-processing stage of a manufacturing method embodiment for a vertical two-dimensional complementary field-effect transistor device with a shared gate.

[0067] Figure 27 A schematic diagram of the b-b' cross-section after intelligent diffusion fracture cutting in the post-processing stage of an embodiment of a manufacturing method for a vertical two-dimensional complementary field-effect transistor device with a shared gate.

[0068] Figure 28 A schematic diagram of the d-d' cross-section after intelligent diffusion fracture cutting in the post-processing stage of an embodiment of a manufacturing method for a vertical two-dimensional complementary field-effect transistor device with a shared gate.

[0069] Figure 29 This is a cross-sectional schematic diagram of a strip-shaped polymer layer and a first insulating material layer formed on the surface of a silicon substrate in an embodiment of the manufacturing method of the vertical two-dimensional complementary field-effect device of the present invention.

[0070] Figure 30 This is a schematic cross-sectional view of the first molding line film layer setting in an embodiment of the manufacturing method of the vertical two-dimensional complementary field-effect device of the present invention, in which a strip-shaped polymer layer and a first insulating material layer are formed on the surface of a silicon substrate, and carbon is filled into the groove etched in the sidewall and polished flat.

[0071] Figure 31 This is a cross-sectional view of the first molding line film layer setting in an embodiment of the manufacturing method of the vertical two-dimensional complementary field-effect device of the present invention, after filling the groove etched in the sidewall with carbon, polishing and smoothing it, and removing the strip-shaped polymer layer.

[0072] Figure 32 This is a cross-sectional view of the first molding wire film layer setting in an embodiment of the manufacturing method of the vertical two-dimensional complementary field-effect device of the present invention, after removing the strip-shaped polymer layer, filling the second insulating material, and performing a second sidewall etching. The second insulating material layer is formed after the first insulating material layer is separated from the carbon-filled side.

[0073] Figure 33This is a cross-sectional schematic diagram of the first molding wire film layer setting in an embodiment of the manufacturing method of the vertical two-dimensional complementary field-effect device of the present invention, in which the first insulating material and carbon are removed and the second insulating material layer is retained as the first molding wire film layer. Detailed Implementation

[0074] The preferred embodiments of the present invention will be described below with reference to the accompanying drawings. It should be understood that the preferred embodiments described herein are for illustration and explanation only and are not intended to limit the present invention.

[0075] like Figure 1 As shown, an embodiment of the present invention provides a vertical two-dimensional complementary field-effect transistor device with a shared gate, comprising:

[0076] Substrate 3 includes protrusion 1;

[0077] A field-effect transistor (FET) unit is disposed on the protrusion 1 in a vertical direction perpendicular to the substrate. Each FET unit is disposed in a one-to-one correspondence with the protrusion 1. The FET unit includes a P-type FET sub-unit and an N-type FET sub-unit. The N-type FET sub-unit and the P-type FET sub-unit each include a source, a gate, and a drain. The N-type FET sub-unit and the P-type FET sub-unit share a gate 2.

[0078] The working principle and beneficial effects of the above technical solution are as follows: This solution provides a vertical two-dimensional complementary field-effect transistor device with a shared gate; since the formed N-type field-effect transistor sub-unit and P-type field-effect transistor sub-unit share a gate and a metal connection is set at the shared gate, it is not necessary to add a line connection between the gates of each field-effect transistor sub-unit, thus avoiding the space occupied by the connection line, thereby further improving the integration of the vertical two-dimensional field-effect transistor device.

[0079] In one embodiment, such as Figure 1 As shown, the P-type field-effect transistor unit is n-shaped, and the N-type field-effect transistor unit is u-shaped; the two sides of the lower opening of the n-shaped P-type field-effect transistor unit are the source or drain 11 respectively and are connected to the top of the protrusion 1 of the substrate 3, and the upper connection end of the n-shaped P-type field-effect transistor unit is the gate; the two sides of the upper opening of the u-shaped N-type field-effect transistor unit are the source or drain 12 respectively, and the lower connection end of the u-shaped N-type field-effect transistor unit is the gate; the N-type field-effect transistor unit is located above the P-type field-effect transistor unit, and the gates of the two are an integral structure 6.

[0080] The working principle and beneficial effects of the above technical solution are as follows: The field-effect transistor group of this solution includes an n-shaped P-type field-effect transistor unit and a u-shaped N-type field-effect transistor unit; the two sides of the opening at the bottom of the n-shaped P-type field-effect transistor unit are the source or drain respectively and are connected to the protrusion of the substrate, and the connection end at the top of the n-shaped P-type field-effect transistor unit is the gate; the two sides of the opening at the top of the u-shaped N-type field-effect transistor unit are the source or drain respectively, and the connection end at the bottom of the u-shaped N-type field-effect transistor unit is the gate; the N-type field-effect transistor unit is located above the P-type field-effect transistor unit and the gates of the two are an integral structure, forming an X-shape by sharing the gate; the gaps between the N-type field-effect transistor unit and the P-type field-effect transistor unit are filled with a first insulating material, thereby ensuring the function of the corresponding vertical two-dimensional field-effect device.

[0081] In one embodiment, such as Figure 1 As shown, the field-effect transistor units are multiple units disposed on the same substrate and arranged vertically in a parallel and spaced manner; a fracture groove 4 is provided between adjacent field-effect transistor units, and a titanium nitride sheet 5 extending horizontally to the fracture groove is connected to the connection between the gate and the top of the protrusion 1 and the opening end of the lower part of the P-type field-effect transistor unit; a cobalt silicide block 7 is provided on both sides of the top of the protrusion 1 and the opening end of the lower part of the n-type P-type field-effect transistor unit.

[0082] The working principle and beneficial effects of the above technical solution are as follows: In this solution, multiple field-effect transistor units are connected to the source and drain of the P-type field-effect transistor subunit by forming a titanium nitride sheet. Therefore, it is not necessary to add a line connection between the source and drain of each P-type field-effect transistor unit, thus avoiding the space occupied by the connection line and further improving the integration of vertical two-dimensional field-effect devices. Cobalt silicide blocks are connected to the top of the protrusion and the two sides of the opening at the bottom of the n-shaped P-type field-effect transistor unit. The titanium nitride sheet realizes the connection between the source and drain of each P-type field-effect transistor unit through the cobalt silicide blocks.

[0083] like Figure 2 , 6 7 and Figure 10-28 As shown, this embodiment of the invention provides a method for manufacturing a vertical two-dimensional complementary field-effect transistor device with a shared gate, comprising the following steps:

[0084] S100 Figure 6 As shown, a protrusion 1 is fabricated on the substrate 3, and a field-effect transistor (FET) unit prototype is disposed on the protrusion 1 perpendicular to the substrate. Each FET unit prototype corresponds one-to-one with the protrusion 1. The FET unit prototype includes two FET sub-unit prototypes, and the two ends of the FET unit prototype are connected by a skeleton 211, as shown. Figure 7 As shown, the upper and lower sections of the prototype field-effect transistor unit are subjected to N-type and P-type doping treatments, respectively, and filled with the first insulating material 6;

[0085] S200 Figure 11 As shown, a first etching mask is provided on the skeleton to perform the first etching to remove the first insulating material between the upper sections of the prototype field-effect transistor unit;

[0086] S300 Figure 12 As shown, a silicon oxynitride layer 223 is provided on the upper section of the prototype field-effect transistor unit, exposing the connection between the upper and lower sections of the prototype field-effect transistor unit;

[0087] S400 Figure 13-15 As shown, a single-crystal material with the same lattice arrangement as the substrate is grown at the connection between the upper and lower sections of the exposed field-effect transistor prototype, connecting two field-effect transistor units within the same prototype. This grown single-crystal material connection serves as the basis for shared gate fabrication. (Further details follow.) Figure 16-28 The post-processing shown in the figure yields a vertical two-dimensional complementary field-effect transistor device with a shared gate.

[0088] The working principle and beneficial effects of the above technical solution are as follows: This solution processes protrusions and field-effect transistor (FET) prototypes perpendicular to the substrate on a substrate. Two FET prototypes are correspondingly set at the top of each protrusion. The two ends of each FET prototype are connected by a skeleton. Two FET prototypes at the top of the same protrusion form a group. The upper and lower sections of the FET prototypes are subjected to N-type and P-type doping treatments, respectively, and filled with a first insulating material. A first etching mask is provided on the skeleton as a protective layer. The first etching removes the first insulating material between the upper sections of the FET prototypes. Because the FET prototypes are protected by the skeleton at both ends, the material perpendicular to the FET prototypes is effectively removed. A tensioned framework structure is formed to prevent the prototype field-effect transistor (FET) unit from collapsing. A silicon oxynitride layer is placed on the upper section of the prototype FET unit, exposing the connection between the upper and lower sections. A single-crystal material with the same lattice arrangement as the substrate is grown there, allowing two FET units in the same group to connect. Post-processing is then performed to obtain a vertical two-dimensional complementary field-effect transistor (FET) device with a shared gate. Since the formed N-type and P-type FET units share a gate and a metal connection is set at the shared gate, it is not necessary to add wiring connections to each FET unit, avoiding the space occupied by wiring and thus further improving the integration density of the vertical two-dimensional FET device.

[0089] In one embodiment, such as Figure 3 and Figure 6-9 As shown, the fabrication process for the protrusion and the prototype of the field-effect transistor unit in step S100 is as follows:

[0090] S10 Figure 6As shown, based on the wafer pitch of the opening ends of the P-type field-effect transistor unit and / or the inter-group distance of the field-effect transistor group, a first forming line film layer is set on the substrate surface with the thickness dimension of the field-effect transistor unit as the width, and a first etching mask intersecting the first forming line film layer is set on the substrate surface at intervals according to a set distance.

[0091] S20 Figure 6 and 7 As shown, the substrate is pre-etched for the first time to form a first groove of a first depth between two field-effect transistor sub-unit prototypes in the same field-effect group, and a second groove of a second depth is formed on the outside of the field-effect group to form a field-effect transistor unit prototype; the first depth is less than the second depth and the height difference between the two forms the protrusion 1 of the substrate;

[0092] S30 Figure 7 As shown, after removing the first forming line film layer and the first etching mask, and performing doping treatment, the second insulating material is filled into the first groove and the second groove and the surface is leveled. The first forming line film layer and the first etching mask are restored, and a second pre-etching is performed. Except for the root of the field effect tube unit prototype, the second insulating material layer is retained in the first groove and the second groove.

[0093] S40 Figure 8 As shown, a cobalt silicide block 7 is formed at the root of the prototype field-effect tube unit by cobalt infiltration treatment; Figure 9 As shown, titanium nitride 222 is connected between the roots of two field-effect transistor prototypes in adjacent effect modules.

[0094] The working principle and beneficial effects of the above technical solution are as follows: In the prototype of the field-effect transistor unit in this solution, based on the wafer spacing of the opening ends of the P-type field-effect transistor unit and / or the N-type field-effect transistor unit and the inter-group distance of the field-effect group, a first forming line film layer with a width equal to the thickness of the field-effect transistor unit is set on the substrate surface. A first etching mask intersecting the first forming line film layer is set at intervals on the substrate surface according to a set distance. The substrate is pre-etched for the first time, forming a first groove of a first depth between two prototype field-effect transistor units in the same field-effect group, and a second groove of a second depth is formed on the outside of the field-effect group, thus forming the prototype field-effect transistor unit. Due to the retention of the position of the first etching mask, a tensioned skeleton structure is formed at both ends of the vertical two-dimensional complementary field-effect device prototype, ensuring that even if the height and thickness of the P-type and N-type field-effect transistor unit prototypes are relatively large, they can maintain an upright planar shape and will not tilt or fall over before filling. Furthermore, because... The inter-group distance of the field-effect transistor array is greater than the wafer spacing. Therefore, the first depth formed at the wafer spacing is less than the second depth formed at the inter-group distance of the field-effect transistor array, and the height difference between the first depth and the second depth forms a protrusion on the substrate. After removing the first molding line film layer and the first etching mask, and performing doping treatment to optimize the material of the P-type field-effect transistor unit prototype and the N-type field-effect transistor unit prototype, the second insulating material is filled into the first groove and the second groove and leveled. The first molding line film layer and the first etching mask are restored, and a second pre-etching is performed. Except for the root of the field-effect transistor unit prototype, the second insulating material layer is retained in the first groove and the second groove. Cobalt infiltration treatment is performed to form a cobalt silicide block at the root of the field-effect transistor unit prototype. A titanium nitride connection is set between the cobalt silicide blocks at the roots of the two field-effect transistor unit prototypes of adjacent effect modules. This titanium nitride connection will be cut off during the smart diffusion fracture cutting in step S470 of the post-processing process to form two titanium nitride sheets.

[0095] In one embodiment, such as Figure 4 and Figure 16-28 As shown, in step S300, the post-processing technology includes:

[0096] S410 Figure 16 As shown, the upper section of the prototype field-effect transistor unit is filled with a first insulating material and then leveled. Figure 17 As shown, a second etching mask 310 is provided in addition to the skeleton 211, and a second etching is performed to form a third groove 311 with a third depth, the third depth reaching the lower edge of the gate;

[0097] S430 Figure 18-19 As shown, after the third groove 311 is filled with the second insulating material and leveled, a third etching is performed to form the fourth groove 314 with a fourth depth, and the upper edge of the gate at the fourth depth; a first insulating material film layer 312 is provided on the sidewall of the fourth groove 314.

[0098] S450 Figure 20-22 As shown, a gate slot is formed by etching the middle gate segment through the fourth groove 314, and a second insulating material layer is formed on the sidewall of the gate slot, as follows. Figure 23-25 As shown, a metal layer 224 is formed by filling the door groove with metal;

[0099] S470 Figure 26-28 As shown, the fourth groove 314 is filled with the first insulating material, and intelligent diffusion fracture cutting is performed at the middle position of the adjacent field effect group.

[0100] The working principle and beneficial effects of the above technical solution are as follows: The post-processing of this solution shapes the gate structure at the connection between the upper and lower sections of the device through multiple etching processes, allowing the gate to include a base layer and a second insulating material layer and a metal layer symmetrically arranged on both sides of the base layer. Multiple field-effect transistors are connected through the metal layer to achieve conductivity, and the source, gate, and drain of the N-type field-effect transistor unit and the PN-type field-effect transistor unit are shaped, ultimately forming an X-shaped shared gate vertical complementary field-effect device. This structure ensures that the gate has sufficient area, thereby guaranteeing the performance of the device. The second insulating material can generally be silicon oxide.

[0101] In one embodiment, such as Figure 5 and Figures 29-33 As shown, in step S10, the first forming line film layer is configured as follows:

[0102] S11 as Figure 29 As shown, a polymer layer is formed on the surface of a silicon substrate 3, and strip-shaped protective layers are formed at intervals by dry photolithography to form multiple spaced strip-shaped polymer layers 101.

[0103] S12 as Figure 29 As shown, after filling the groove of the dry photolithography with the first insulating material and smoothing it, the first sidewall etching is performed to form the first insulating material layer 102 on both sides of the strip polymer layer.

[0104] S13 as Figure 29 and 30 As shown, carbon 104 is filled into the groove 103 of the first sidewall etching and then polished flat.

[0105] S14 as Figure 31 As shown, the strip-shaped polymer layer 101 is removed, as... Figure 32 As shown, a second insulating material is filled, and a second sidewall etching is performed to form a second insulating material layer 105 on the side of the first insulating material layer away from the filled carbon.

[0106] S15 Figure 33As shown, after removing the first insulating material layer 102 and carbon 104, the remaining second insulating material layer 105 is the first molded wire film layer 110.

[0107] The working principle and beneficial effects of the above technical solution are as follows: This solution sets a polymer layer on the surface of the substrate, forms a strip-shaped polymer layer by dry photolithography, fills the groove of the dry photolithography with a first insulating material, performs the first sidewall etching, and forms a first insulating material layer by retaining the first insulating material on both sides of the strip-shaped polymer layer. Carbon is filled into the groove of the first sidewall etching, the strip-shaped polymer layer is removed, and the original position of the strip-shaped polymer layer is filled with a second insulating material. The second sidewall etching is performed, and the second insulating material retained on the side of the first insulating material layer away from the carbon-filled side forms a second insulating layer. The second insulating material can generally be silicon oxide. The first insulating material layer and the filled carbon are removed, and the remaining second insulating layer is the first forming line film layer. This process can ensure the accuracy of the setting distance of the first forming line film layer.

[0108] In one embodiment, such as Figure 17 As shown, the doping process in step S30 is as follows:

[0109] The upper and lower ends of the two field-effect transistor sub-unit prototypes in the same field-effect group are respectively doped with N-type source / drain and P-type source / drain.

[0110] The upper and lower connecting pieces of the two field-effect transistor unit prototypes in the same field-effect group are subjected to gate doping treatment.

[0111] The working principle and beneficial effects of the above technical solution are as follows: This solution arranges the doping process before filling the first and second grooves. At this time, the prototype of the field-effect device is fully exposed, and it can be carried out simultaneously on both sides of the prototype of the vertical field-effect device, which increases the doping area and improves the doping efficiency. During doping, the prototype of the field-effect device is divided into upper and lower ends for N-type source-drain and P-type source-drain doping treatments, respectively. The connecting pieces at the upper and lower ends of the prototypes of the two field-effect transistor sub-units in the same field-effect group are subjected to gate doping treatment. The doping density of the upper and lower sections is higher than that at their connection points, which ensures the quality and performance requirements of each part of the device, so as to form a gate prototype at the connection point of the upper and lower sections, and form N-type source-drain prototypes and P-type source-drain prototypes at the upper and lower sections, respectively.

[0112] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A vertical two-dimensional complementary field-effect transistor device with a shared gate, characterized in that, include: The substrate includes the protrusions; A field-effect transistor (FET) unit is disposed on the protrusion in a vertical direction perpendicular to the substrate. Each FET unit corresponds to one of the protrusions. The FET unit includes a P-type FET sub-unit and an N-type FET sub-unit. The N-type FET sub-unit and the P-type FET sub-unit each include a source, a gate, and a drain. The N-type FET sub-unit and the P-type FET sub-unit share a common gate. The P-type field-effect transistor unit is n-shaped, and the N-type field-effect transistor unit is u-shaped. The two sides of the lower opening of the n-shaped P-type field-effect transistor unit are the source or drain, respectively, and are connected to the protrusion of the substrate. The upper connection terminal of the n-shaped P-type field-effect transistor unit is the gate. The two sides of the upper opening of the u-shaped N-type field-effect transistor unit are the source or drain, respectively, and the lower connection terminal of the u-shaped N-type field-effect transistor unit is the gate. The N-type field-effect transistor unit is located above the P-type field-effect transistor unit, and the gates of both are integrally structured.

2. The vertical two-dimensional complementary field-effect transistor device with a shared gate according to claim 1, characterized in that, The field-effect transistor units are arranged in parallel and spaced apart on the substrate, and fracture grooves are provided between adjacent field-effect transistor units.

3. The vertical two-dimensional complementary field-effect transistor device with a shared gate according to claim 2, characterized in that, The gate and the top of the protrusion are connected to the opening at the bottom of the P-type field-effect transistor unit, and a titanium nitride sheet extending horizontally to the fracture groove is connected.

4. The vertical two-dimensional complementary field-effect transistor device with a shared gate according to claim 1, characterized in that, The top of the protrusion is connected to the two sides of the opening at the bottom of the n-shaped P-type field effect tube unit, and a cobalt silicide block is provided.

5. A method for manufacturing a vertical two-dimensional complementary field-effect transistor device with a shared gate, characterized in that, Includes the following steps: S100 processes protrusions on a substrate and sets field-effect transistor (FET) unit prototypes perpendicular to the substrate on the protrusions. Each FET unit prototype corresponds to a protrusion. Each FET unit prototype includes two FET sub-unit prototypes. The two ends of the FET unit prototypes are connected by a skeleton. The upper and lower sections of the FET unit prototypes are N-type and P-type doped, respectively, and filled with a first insulating material. The S200 has a first etching mask on its skeleton to perform the first etching to remove the first insulating material between the upper sections of the prototype field-effect transistor unit. The S300 has a silicon oxynitride layer on the upper section of the prototype field-effect transistor unit, exposing the connection between the upper and lower sections of the prototype field-effect transistor unit. S400 grows a single crystal material with the same lattice arrangement as the substrate at the connection between the upper and lower sections of the exposed field-effect transistor unit prototype, so that the two field-effect transistor units of the same field-effect transistor unit prototype are connected, and then a post-processing process is performed to obtain a vertical two-dimensional complementary field-effect transistor device with a shared gate.

6. The method for manufacturing a vertical two-dimensional complementary field-effect transistor device with a shared gate according to claim 5, characterized in that, The fabrication process for the protrusions and the prototype of the field-effect transistor unit in step S100 is as follows: S10 Based on the wafer spacing of the opening ends of the P-type field-effect transistor unit and / or the inter-group distance of the field-effect transistor group, a first forming line film layer is set on the substrate surface with the thickness dimension of the field-effect transistor unit as the width, and a first etching mask intersecting with the first forming line film layer is set on the substrate surface at intervals according to a set distance. S20 performs the first pre-etching on the substrate, forming a first groove of a first depth between two field-effect transistor sub-unit prototypes in the same field-effect group, and forming a second groove of a second depth on the outside of the field-effect group to form a field-effect transistor unit prototype. The first depth is less than the second depth, and the height difference between the two forms a protrusion on the substrate; S30 removes the first forming line film layer and the first etching mask, performs doping treatment, fills the first groove and the second groove with the second insulating material and performs flattening treatment, restores the first forming line film layer and the first etching mask, and performs a second pre-etching. Except for the root of the field effect tube unit prototype, the second insulating material layer is retained at the first groove and the second groove. S40 undergoes cobalt infiltration treatment to form a cobalt silicide block at the root of the field-effect transistor unit prototype; titanium nitride connection is set between the roots of two field-effect transistor unit prototypes in adjacent effect modules.

7. The method for manufacturing a vertical two-dimensional complementary field-effect transistor device with a shared gate according to claim 5, characterized in that, In step S300, the post-processing includes: S410 fills the upper section of the field-effect transistor unit prototype with a first insulating material and performs a flattening process. In addition to the skeleton, a second etching mask is set to perform a second etching to form a third groove with a third depth, the third depth reaching the lower edge of the gate. After filling the third groove with the second insulating material and smoothing it out, S430 performs a third etching to form a fourth groove with a fourth depth, and the upper edge of the gate at the fourth depth; a first insulating material film layer is formed on the sidewall of the fourth groove; S450 forms a gate slot by etching the middle gate segment through the fourth groove, forms a second insulating material layer on the sidewall of the gate slot, and fills the gate slot with metal to form a metal layer; S470 uses a first insulating material to fill the fourth groove and performs intelligent diffusion fracture cutting at the middle position of adjacent field effect groups.

8. The method for manufacturing a vertical two-dimensional complementary field-effect transistor device with a shared gate according to claim 6, characterized in that, In step S10, the first forming line film layer is configured as follows: S11 involves setting a polymer layer on the surface of a silicon substrate, and performing dry photolithography with spaced strip-shaped protective layers to form multiple spaced strip-shaped polymer layers. S12 After filling the groove of dry photolithography with the first insulating material and flattening it, the first sidewall etching is performed to form the first insulating material layer on both sides of the strip-shaped polymer layer. S13 fills the grooves etched on the sidewalls with carbon-containing material and polishes them smooth. S14 Remove the strip-shaped polymer layer, fill with the second insulating material, and perform a second sidewall etching to form the second insulating layer on the side of the first insulating material layer away from the carbon-containing material filling layer; S15 removes the first insulating material layer and the carbon-containing material, and the remaining second insulating material layer is the first molded wire film layer.

9. The method for manufacturing a vertical two-dimensional complementary field-effect transistor device with a shared gate according to claim 6, characterized in that, In step S30, the doping process is as follows: The upper and lower ends of the two field-effect transistor sub-unit prototypes in the same field-effect group are respectively doped with N-type source / drain and P-type source / drain. The upper and lower connecting pieces of the two field-effect transistor unit prototypes in the same field-effect group are subjected to gate doping treatment.

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