A cold backup and slew rate control circuit for MLVDS drivers

Abstract

The present invention provides a cold backup and slew rate control circuit for an MLVDS driver. The circuit comprises a pre-driver circuit, a cold backup circuit, and an MLVDS output driver circuit. The pre-driver circuit output is connected to an output stage circuit, and the cold backup circuit is part of the output stage circuit. The pre-driver circuit generates eight equally delayed switching signals, with the delay difference between two adjacent phase switching signals being TD. The eight switching signals control whether MOS transistors of different sizes in the output stage circuit are turned on or off. The cold backup circuit ensures that the output port is resistant to positive high voltage and negative voltage leakage when the power supply is floating or grounded. The MLVDS output driver circuit provides sufficient drive capability while generating a differential signal across an external load.

Description

Technical Field

[0001] The present invention relates to an MLVDS output stage circuit, in particular to an output stage circuit with cold backup and slew rate control, and belongs to the field of high-speed interface circuit design. Background Art

[0002] LVDS uses low-swing differential signaling technology to enable high-speed signal transmission over differential PCB lines or balanced twisted-pair cables. Its advantages include strong anti-interference capabilities, low power consumption, high reliability, and fast transmission rates, making it widely used in point-to-point data transmission. However, LVDS is not suitable for multi-point bus applications. To meet the needs of communication between multi-point systems, MLVDS technology was derived from LVDS.

[0003] When signals are transmitted on the bus, the existence of bus branches causes discontinuous transmission line impedance, which in turn brings serious signal reflection problems. A slower slew rate can effectively reduce electromagnetic interference problems. Therefore, the MLVDS driver circuit must have an output slew rate control function to ensure correct signal transmission on the bus.

[0004] In bus applications, if the circuit does not have a cold backup function, the power supply cannot be completely powered off when the LVDS port is loaded with a signal, causing system errors. Therefore, the circuit LVDS port needs to add a cold backup function. Summary of the Invention

[0005] The present invention aims to provide a cold backup and slew rate control circuit for an MLVDS driver. This circuit can control the transition time of the driver's output differential voltage to meet protocol requirements. In the event of a power failure or floating condition, it can cut off the path from the port to the power supply, meeting cold backup requirements. This circuit can be used in MLVDS driver designs.

[0006] The technical solution of the present invention is: a cold backup and slew rate control circuit suitable for an MLVDS driver, comprising a pre-driving circuit, a cold backup circuit and an MLVDS output stage circuit;

[0007] Pre-driver circuit: The output end of the pre-driver circuit is connected to the MLVDS output stage circuit to generate 8-phase delayed switching signals. The delay difference between two adjacent phase switching signals is TD. The 8-phase delayed switching signals respectively control whether MOS tubes of different sizes in the MLVDS output stage circuit are turned on;

[0008] Cold backup circuit: When the power supply is powered on normally, it ensures the normal operation of the MLVDS output stage circuit; when the power supply is powered off or floating, it cuts off the parasitic channel between the MLVDS output end and the power supply to achieve cold backup function;

[0009] MLVDS output driver circuit: provides driving capability and generates differential signals at both ends of the external load resistor under the control of the output signal of the pre-driver circuit;

[0010] The pre-driver circuit includes combinational logic units Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, an inverter INV2, and a NAND gate NAND1;

[0011] The input terminal A1 of the logic unit Q0 is connected to the output terminal of NAND1, the input terminal A2 is connected to the input terminal A1 of the logic unit Q2, and the input terminal A3 is connected to the enable signal EN;

[0012] The input terminal A1 of the logic unit Q1 is connected to the output terminal of the logic unit Q0, the input terminal A2 is connected to the output terminal of the logic unit Q2, and the input terminal A3 is connected to the enable signal EN;

[0013] The input terminal A1 of the logic unit Q2 is connected to the output terminal of the logic unit Q1, the input terminal A2 is connected to the output terminal of the logic unit Q3, and the input terminal A3 is connected to the enable signal EN;

[0014] The input terminal A1 of the logic unit Q3 is connected to the output terminal of the logic unit Q2, the input terminal A2 is connected to the output terminal of the logic unit Q4, and the input terminal A3 is connected to the enable signal EN;

[0015] The input terminal A1 of the logic unit Q4 is connected to the output terminal of the logic unit Q3, the input terminal A2 is connected to the output terminal of the logic unit Q5, and the input terminal A3 is connected to the enable signal EN;

[0016] The input terminal A1 of the logic unit Q5 is connected to the output terminal of the logic unit Q4, the input terminal A2 is connected to the output terminal of the logic unit Q6, and the input terminal A3 is connected to the enable signal EN;

[0017] The input terminal A1 of the logic unit Q6 is connected to the output terminal of the logic unit Q5, the input terminal A2 is connected to the output terminal of the logic unit Q7, and the input terminal A3 is connected to the enable signal EN;

[0018] The input terminal A1 of the logic unit Q7 is connected to the output terminal of the logic unit Q6, the input terminal A2 is connected to the output terminal of the logic unit Q8, and the input terminal A3 is connected to the enable signal EN;

[0019] An input terminal A1 of the logic unit Q8 is connected to an output terminal of the logic unit Q7, an input terminal A2 is connected to a switching signal SW, and an input terminal A3 is connected to an enable signal EN; an input terminal of the inverter INV2 is connected to an input terminal of the logic unit Q0, and an output terminal of the INV2 is connected to an input terminal of a NAND gate NAND1; a first input terminal of the NAND gate NAND1 is connected to an output terminal of the INV2, a second input terminal of the NAND gate NAND1 is connected to a switching signal SW, and an output terminal of the NAND gate NAND1 is connected to an input terminal A1 of the logic unit Q0; input terminals A3 of the logic units Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, and Q8 are connected to one another and to the enable signal EN; and a pre-driver circuit generates eight control signals SN1, SN2, SN3, SN4, SN5, SN6, SN7, and SN8 whose phases are sequentially delayed.

[0020] The cold backup circuit includes PMOS transistors P1-P8, NMOS transistors N1-N4, current source I0 and tail resistor Rtail;

[0021] The drain of the PMOS transistor P1 is simultaneously connected to the drain of the PMOS transistor P4, the source of the PMOS transistor P3, the drain of the PMOS transistor P2, and the drain of the NMOS transistor N2. The source of the PMOS transistor P1 is simultaneously connected to the current source I0 and the source of the PMOS transistor P5. The gate of the PMOS transistor P1 is simultaneously connected to the drain of the NMOS transistor N1 and the source of the PMOS transistor P4.

[0022] The drain of the PMOS transistor P2 is connected to the drain of the PMOS transistor P1, the drain of the PMOS transistor P4, the source of the PMOS transistor P3, and the drain of the NMOS transistor N2. The gate of the PMOS transistor P2 is connected to VDD.

[0023] The drain of the PMOS transistor P3 is connected to OUTP, the source of the PMOS transistor P3 is connected to the drain of the PMOS transistor P1, the drain of the PMOS transistor P4, the drain of the PMOS transistor P2, and the drain of the NMOS transistor N2, and the gate of the PMOS transistor P3 is connected to the enable signal ENN;

[0024] The drain of the PMOS transistor P4 is connected to the drain of the PMOS transistor P1, the drain of the PMOS transistor P2, the source of the PMOS transistor P3, and the drain of the NMOS transistor N2. The source of the PMOS transistor P4 is connected to the gate of the PMOS transistor P1 and the drain of the NMOS transistor N1.

[0025] The drain of the NMOS transistor N1 is connected to the gate of the PMOS transistor P1 and the source of the PMOS transistor P4. The source of the NMOS transistor N1 is connected to the switching signal SN, and the gate of the NMOS transistor N1 is connected to VDD.

[0026] The drain of the NMOS transistor N2 is connected to the drain of the PMOS transistor P1, the drain of the PMOS transistor P2, the source of the PMOS transistor P3, and the drain of the PMOS transistor P4. The source of the NMOS transistor N2 is connected to the source of the NMOS transistor N4 and the resistor Rtail.

[0027] PMOS transistors P1, P2, and P4 are built in the same N-well FW1, and the source of PMOS transistor P2 is connected to the N-well FW1;

[0028] The drain of the PMOS transistor P5 is simultaneously connected to the drain of the PMOS transistor P6, the source of the PMOS transistor P7, the drain of the PMOS transistor P8, and the drain of the NMOS transistor N4. The source of the PMOS transistor P5 is simultaneously connected to the current source I0 and the source of the PMOS transistor P1. The gate of the PMOS transistor P5 is simultaneously connected to the drain of the NMOS transistor N3.

[0029] The drain of the PMOS transistor P6 is connected to the drain of the PMOS transistor P5, the drain of the PMOS transistor P8, the source of the PMOS transistor P7, and the drain of the NMOS transistor N4. The gate of the PMOS transistor P6 is connected to VDD.

[0030] The drain of the PMOS transistor P7 is connected to OUTP, the source of the PMOS transistor P7 is connected to the drain of the PMOS transistor P5, the drain of the PMOS transistor P8, the drain of the PMOS transistor P7 and the drain of the NMOS transistor N4, and the gate of the PMOS transistor P7 is connected to the enable signal ENN;

[0031] The drain of the PMOS transistor P8 is connected to the drain of the PMOS transistor P5, the drain of the PMOS transistor P6, the source of the PMOS transistor P7, and the drain of the NMOS transistor N4. The source of the PMOS transistor P8 is connected to the gate of the PMOS transistor P5 and the drain of the NMOS transistor N3.

[0032] The drain of the NMOS transistor N3 is connected to the gate of the PMOS transistor P5 and the source of the PMOS transistor P8. The source of the NMOS transistor N1 is connected to the switching signal SP, and the gate of the PMOS transistor N3 is connected to VDD.

[0033] The drain of the NMOS transistor N4 is connected to the drain of the PMOS transistor P5, the drain of the PMOS transistor P6, the source of the PMOS transistor P7, and the drain of the PMOS transistor P8. The source of the NMOS transistor N4 is connected to the source of the NMOS transistor N2 and the resistor Rtail. The source of the NMOS transistor N4 is connected to the switching signal SP.

[0034] The PMOS transistors P5 , P6 , and P8 are fabricated in the same N-well FW2 , and the source of the PMOS transistor P6 is connected to the N-well FW2 .

[0035] The output drive circuit includes PMOS transistors P11, P12, P13, P14, P15, P16, P17, P18, P51, P52, P53, P54, P55, P56, P57, P58, NMOS transistors N21, N22, N23, N24, N25, N26, N27, N28, N41, N42, N43, N44, N45, N46, N47, N48, current source I0 and tail resistor Rtail;

[0036] The sources of the PMOS transistors P11, P12, P13, P14, P15, P16, P17, P18, P51, P52, P53, P54, P55, P56, P57, and P58 are connected to each other and to the current source I0; the drains of the PMOS transistors P11, P12, P13, P14, P15, P16, P17, and P18 are all connected to the source of the PMOS transistor P3; the drains of the PMOS transistors P51, P52, P53, P54, P55, P56, P57, and P58 are all connected to the source of the PMOS transistor P7; The sources of the MOS transistors N21, N22, N23, N24, N25, N26, N27, N28, N41, N42, N43, N44, N45, N46, N47, and N48 are connected to each other and to the tail resistor Rtail. The drains of the NMOS transistors N21, N22, N23, N24, N25, N26, N27, and N28 are connected to the source of the PMOS transistor P3. The drains of the NMOS transistors N41, N42, N43, N44, N45, N46, N47, and N48 are all connected to the source of the PMOS transistor P7.

[0037] The width-to-length ratios of the PMOS transistors P11, P12, P13, P14, P15, P16, P17, and P18, the PMOS transistors P51, P52, P53, P54, P55, P56, P57, and P58, the NMOS transistors N21, N22, N23, N24, N25, N26, N27, and N28, and the NMOS transistors N41, N42, N43, N44, N45, N46, N47, and N48 increase in sequence and form an arithmetic progression.

[0038] The PMOS transistors P11, P12, P13, P14, P15, P16, P17, P18 and the NMOS transistors N21, N22, N23, N24, N25, N26, N27, N28 are respectively controlled by the 8-phase control signals SN1 to SN8 with equal delays. The PMOS transistors P51, P52, P53, P54, P55, P56, P57, P58 and the NMOS transistors N41, N42, N43, N44, N45, N46, N47, N48 are respectively controlled by the 8-phase control signals SP1 to SP8 with equal intervals. SN and SP are a pair of control signals with opposite phases.

[0039] The width-to-length ratio of the PMOS tube connected to the same control signal is twice that of the NMOS tube.

[0040] Compared with the existing MLVDS driver, the present invention has the following advantages:

[0041] (1) The pre-driver circuit of the present invention is composed of a cascade of digital logic gates. The pre-driver circuit and the driver stage are combined to realize slew rate control, which has the advantages of controllable delay time, strong scalability, strong portability, and simple design.

[0042] (2) While satisfying the output signal slew rate control, the present invention cuts off the path from the port to the power supply through the floating well structure when the power is off or floating, supports circuit cold backup, and has a wider range of applications.

[0043] (3) The output end of the circuit can withstand negative voltage, avoiding damage to the circuit under adverse conditions where the MLVDS driver and receiver share the same ground. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 It is the circuit structure block diagram;

[0045] Figure 2 This is the pre-drive circuit diagram;

[0046] Figure 3 This is the cold backup circuit diagram;

[0047] Figure 4 This is the output drive circuit diagram; DETAILED DESCRIPTION

[0048] The specific embodiments of the present invention are described in detail below with reference to the accompanying drawings, but the protection scope of the present invention is not limited to the following description.

[0049] In the present invention, multi-phase switching signals with equal delay differences are used to control switching tubes with successively increasing width-to-length ratios, thereby achieving slew rate control of the output differential signal, which can be used in the circuit design of an MLVDS driver.

[0050] The circuit of the present invention includes a pre-driver circuit, a cold backup circuit, and an MLVDS output stage circuit. The pre-driver circuit outputs eight equally delayed switching signals, with the delay difference between two adjacent switching signals being TD. This is used to control the delayed turn-on of switches with different aspect ratios in the output driver stage circuit, while the output stage circuit outputs differential signals with opposite phases. The cold backup circuit ensures that the output port is resistant to positive high-voltage and negative voltage leakage when the power supply is floating or grounded.

[0051] like Figure 1As shown, a cold backup and slew rate control circuit for an MLVDS driver includes a pre-driver circuit, a cold backup circuit, and an MLVDS output stage circuit. The output end of the pre-driver circuit is connected to the output stage circuit. The cold backup circuit can be seen as part of the output stage circuit. The positive output end of the output stage circuit is connected to the enable control signal. The output negative terminal of the output stage circuit of the switch tube MP1 is connected to the enable control signal The pre-driver circuit outputs 8 equally delayed switching signals, with the delay difference between adjacent two-phase switching signals being TD. The output stage circuit outputs differential signals with opposite phases. The cold backup circuit ensures that the output port is resistant to positive high voltage / negative voltage leakage when the power supply is floating or grounded.

[0052] like Figure 2 As shown, the pre-driver circuit includes combinational logic units Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, an inverter INV2 and a NAND gate NAND1;

[0053] The input terminal A1 of the logic unit Q0 is connected to the output terminal of NAND1, the input terminal A2 is connected to the input terminal A1 of the logic unit Q2, and the input terminal A3 is connected to the enable signal EN;

[0054] The input terminal A1 of the logic unit Q1 is connected to the output terminal of the logic unit Q0, the input terminal A2 is connected to the output terminal of the logic unit Q2, and the input terminal A3 is connected to the enable signal EN;

[0055] The input terminal A1 of the logic unit Q2 is connected to the output terminal of the logic unit Q1, the input terminal A2 is connected to the output terminal of the logic unit Q3, and the input terminal A3 is connected to the enable signal EN;

[0056] The input terminal A1 of the logic unit Q3 is connected to the output terminal of the logic unit Q2, the input terminal A2 is connected to the output terminal of the logic unit Q4, and the input terminal A3 is connected to the enable signal EN;

[0057] The input terminal A1 of the logic unit Q4 is connected to the output terminal of the logic unit Q3, the input terminal A2 is connected to the output terminal of the logic unit Q5, and the input terminal A3 is connected to the enable signal EN;

[0058] The input terminal A1 of the logic unit Q5 is connected to the output terminal of the logic unit Q4, the input terminal A2 is connected to the output terminal of the logic unit Q6, and the input terminal A3 is connected to the enable signal EN;

[0059] The input terminal A1 of the logic unit Q6 is connected to the output terminal of the logic unit Q5, the input terminal A2 is connected to the output terminal of the logic unit Q7, and the input terminal A3 is connected to the enable signal EN;

[0060] The input terminal A1 of the logic unit Q7 is connected to the output terminal of the logic unit Q6, the input terminal A2 is connected to the output terminal of the logic unit Q8, and the input terminal A3 is connected to the enable signal EN;

[0061] The input terminal A1 of the logic unit Q8 is connected to the output terminal of the logic unit Q7, the input terminal A2 is connected to the switching signal SW, and the input terminal A3 is connected to the enable signal EN; the input terminal of the inverter INV2 is connected to the input terminal of the logic unit Q0, and the output terminal of INV2 is connected to the input terminal of the NAND gate NAND1; the first input terminal of the NAND gate NAND1 is connected to the output terminal of INV2, the second input terminal of the NAND gate NAND1 is connected to the switching signal SW, and the output terminal of the NAND gate NAND1 is connected to the input terminal A1 of the logic unit Q0; the input terminals A3 of the logic units Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, and Q8 are connected to each other and to the enable signal EN.

[0062] exist Figure 2 The logic units Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, and Q8 have the same circuit structure, consisting of an inverter INV1, a NOR gate NOR1, and a NOR gate NOR2. The input of the inverter INV1 is A1, and the output is connected to the 1 input of the NOR gate NOR2; the input of the NOR gate NOR1 is A2 and A3, and the output is connected to the 2 input of the NOR gate NOR2; the 1 input of NOR2 is connected to the output of the inverter INV1, the 2 input of NOR2 is connected to the output of the NOR gate NOR1, and the output of NOR2 is Q.

[0063] The pre-drive circuit utilizes inverter delay and combinational logic to make the phase delay difference between the output signals SN1 and SN2 TD, the phase delay between SN2 and SN3 TD, the phase delay between SN3 and SN4 TD, the phase delay between SN4 and SN5 TD, the phase delay between SN5 and SN6 TD, the phase delay between SN6 and SN7 TD, and the phase delay between SN7 and SN8 TD. The size of the phase delay TD can be adjusted by adjusting the inverter INV1.

[0064] like Figure 3 As shown, the cold backup circuit includes PMOS transistors P1-P8, NMOS transistors N1-N4, current source I0 and tail resistor Rtail;

[0065] The drain of the PMOS transistor P1 is simultaneously connected to the drain of the PMOS transistor P4, the source of the PMOS transistor P3, the drain of the PMOS transistor P2, and the drain of the NMOS transistor N2. The source of the PMOS transistor P1 is simultaneously connected to the current source I0 and the source of the PMOS transistor P5. The gate of the PMOS transistor P1 is simultaneously connected to the drain of the NMOS transistor N1 and the source of the PMOS transistor P4.

[0066] The drain of the PMOS transistor P2 is connected to the drain of the PMOS transistor P1, the drain of the PMOS transistor P4, the source of the PMOS transistor P3, and the drain of the NMOS transistor N2. The gate of the PMOS transistor P2 is connected to VDD.

[0067] The drain of the PMOS transistor P3 is connected to OUTP, the source of the PMOS transistor P3 is connected to the drain of the PMOS transistor P1, the drain of the PMOS transistor P4, the drain of the PMOS transistor P2, and the drain of the NMOS transistor N2, and the gate of the PMOS transistor P3 is connected to the enable signal ENN;

[0068] The drain of the PMOS transistor P4 is connected to the drain of the PMOS transistor P1, the drain of the PMOS transistor P2, the source of the PMOS transistor P3, and the drain of the NMOS transistor N2. The source of the PMOS transistor P4 is connected to the gate of the PMOS transistor P1 and the drain of the NMOS transistor N1.

[0069] The drain of the NMOS transistor N1 is connected to the gate of the PMOS transistor P1 and the source of the PMOS transistor P4. The source of the NMOS transistor N1 is connected to the switching signal SN, and the gate of the NMOS transistor N1 is connected to VDD.

[0070] The drain of the NMOS transistor N2 is connected to the drain of the PMOS transistor P1, the drain of the PMOS transistor P2, the source of the PMOS transistor P3, and the drain of the PMOS transistor P4. The source of the NMOS transistor N2 is connected to the source of the NMOS transistor N4 and the resistor Rtail.

[0071] PMOS transistors P1, P2, and P4 are built in the same N-well FW1, and the source of PMOS transistor P2 is connected to the N-well FW1;

[0072] The drain of the PMOS transistor P5 is simultaneously connected to the drain of the PMOS transistor P6, the source of the PMOS transistor P7, the drain of the PMOS transistor P8, and the drain of the NMOS transistor N4. The source of the PMOS transistor P5 is simultaneously connected to the current source I0 and the source of the PMOS transistor P1. The gate of the PMOS transistor P5 is simultaneously connected to the drain of the NMOS transistor N3.

[0073] The drain of the PMOS transistor P6 is connected to the drain of the PMOS transistor P5, the drain of the PMOS transistor P8, the source of the PMOS transistor P7, and the drain of the NMOS transistor N4. The gate of the PMOS transistor P6 is connected to VDD.

[0074] The drain of the PMOS transistor P7 is connected to OUTP, the source of the PMOS transistor P7 is connected to the drain of the PMOS transistor P5, the drain of the PMOS transistor P8, the drain of the PMOS transistor P7 and the drain of the NMOS transistor N4, and the gate of the PMOS transistor P7 is connected to the enable signal ENN;

[0075] The drain of the PMOS transistor P8 is connected to the drain of the PMOS transistor P5, the drain of the PMOS transistor P6, the source of the PMOS transistor P7, and the drain of the NMOS transistor N4. The source of the PMOS transistor P8 is connected to the gate of the PMOS transistor P5 and the drain of the NMOS transistor N3.

[0076] The drain of the NMOS transistor N3 is connected to the gate of the PMOS transistor P5 and the source of the PMOS transistor P8. The source of the NMOS transistor N1 is connected to the switching signal SP, and the gate of the PMOS transistor N3 is connected to VDD.

[0077] The drain of the NMOS transistor N4 is connected to the drain of the PMOS transistor P5, the drain of the PMOS transistor P6, the source of the PMOS transistor P7, and the drain of the PMOS transistor P8. The source of the NMOS transistor N4 is connected to the source of the NMOS transistor N2 and the resistor Rtail. The source of the NMOS transistor N4 is connected to the switching signal SP.

[0078] The PMOS transistors P5 , P6 , and P8 are fabricated in the same N-well FW2 , and the source of the PMOS transistor P6 is connected to the N-well FW2 .

[0079] The N-well FW1 of the PMOS transistors P5 , P6 , and P8 and the N-well FW2 of P1 , P2 , and P3 are two independent N-wells.

[0080] When the power supply is powered on normally, assuming the switch signal SP is high and SN is low, N1 and P1 are turned on, and the N-well FW1 is charged to a high level through the parasitic PN junction of transistor P2, ensuring the normal operation of transistors P1, P2, and P4. There are two types of MLVDS leakage: the first is when the power supply is powered on, the enable signal is disabled, and the output is resistant to positive and negative voltage leakage. When a positive high voltage is applied to the OUTP or OUTN port, the enable signal is disabled, the ENN signal is at the power supply level, and the threshold voltage of transistor P3 is greater than 0.8V, turning off transistors P3 and P4, thus isolating the leakage. When a negative voltage is applied to the OUTP or OUTN port, the enable signal is disabled, turning off transistors P3 and P4, achieving complete leakage isolation. The second is when the power supply is floating or grounded (VDD = 0V to 1.5V), making the output port resistant to positive and negative voltage leakage. When a positive high voltage is applied to the OUTP or OUTN port, transistors P2 and P3 conduct, charging the well potentials of FW1 and FW2 to the same potential as the port. Since transistors P4 and P8 conduct, the VGS of switches P1 and P5 is now 0V, meaning they are off, thus achieving leakage isolation. When a negative voltage is applied to the output port, the ENN signal is low because the power supply is floating or grounded, turning off transistors P3 and P7, thus achieving leakage isolation.

[0081] like Figure 4As shown, the output drive circuit includes PMOS transistors P11, P12, P13, P14, P15, P16, P17, P18, P51, P52, P53, P54, P55, P56, P57, P58, NMOS transistors N21, N22, N23, N24, N25, N26, N27, N28, N41, N42, N43, N44, N45, N46, N47, N48, a current source I0 and a tail resistor Rtail;

[0082] The sources of the PMOS transistors P11, P12, P13, P14, P15, P16, P17, P18, P51, P52, P53, P54, P55, P56, P57, and P58 are connected to each other and to the current source I0; the drains of the PMOS transistors P11, P12, P13, P14, P15, P16, P17, and P18 are all connected to the source of the PMOS transistor P3; the drains of the PMOS transistors P51, P52, P53, P54, P55, P56, P57, and P58 are all connected to the source of the PMOS transistor P7; The sources of the MOS transistors N21, N22, N23, N24, N25, N26, N27, N28, N41, N42, N43, N44, N45, N46, N47, and N48 are connected to each other and to the tail resistor Rtail. The drains of the NMOS transistors N21, N22, N23, N24, N25, N26, N27, and N28 are connected to the source of the PMOS transistor P3. The drains of the NMOS transistors N41, N42, N43, N44, N45, N46, N47, and N48 are all connected to the source of the PMOS transistor P7.

[0083] The width-to-length ratios of the PMOS transistors P11, P12, P13, P14, P15, P16, P17, and P18, the PMOS transistors P51, P52, P53, P54, P55, P56, P57, and P58, the NMOS transistors N21, N22, N23, N24, N25, N26, N27, and N28, and the NMOS transistors N41, N42, N43, N44, N45, N46, N47, and N48 increase in sequence and form an arithmetic progression.

[0084] PMOS transistors P11, P12, P13, P14, P15, P16, P17, and P18, and NMOS transistors N21, N22, N23, N24, N25, N26, N27, and N28 are controlled by eight equally delayed control signals SN1 through SN8. PMOS transistors P51, P52, P53, P54, P55, P56, P57, and P58, and NMOS transistors N41, N42, N43, N44, N45, N46, N47, and N48 are controlled by eight equally delayed control signals SP1 through SP8. SN and SP are a pair of control signals with opposite phases. All four groups of switching transistors follow the principle of "smaller size turns on first, larger size turns off first." By controlling the switching signal interval TD, the slew rate of the output differential signal can be controlled. The width-to-length ratio of the PMOS transistors is approximately twice that of the NMOS transistors.

[0085] The pre-driver circuit in this invention consists of a cascade of digital logic gates, utilizing gate delays and combinational logic to generate multi-phase switching signals with a delay difference of TD. This delay difference of TD facilitates adjustment and is less susceptible to temperature and internal signal interference, offering advantages such as strong scalability, portability, and simple design. The output driver stage switches have increasing width-to-length ratios in an arithmetic progression. The pre-driver circuit outputs eight switching signals with a delay difference of TD, each controlling the delayed conduction of MOS transistors of different sizes in the output driver stage circuit. This controls the slew rate of the output differential signal, reduces reflections, and ensures signal integrity.

[0086] The N-well of the PMOS used in the circuit of the present invention is not directly connected to the power supply. When the power supply is normally powered on, this structure can charge the N-well to ensure the normal operation of the output stage circuit. When the power supply is powered off or floating, the N-end pull-down tubes are all NMOS, and there is no leakage channel from the N-end to the power supply end. The circuit adopts a floating well structure, and the N-well is not directly connected to the power supply end, thereby isolating the leakage from the P-end to the power supply end. The circuit has a cold backup function.

[0087] The above description is only the best specific implementation method of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or replacements that can be easily thought of by any technician familiar with this technical field within the technical scope disclosed by the present invention should be covered by the scope of protection of the present invention.

Claims

1. A cold backup and slew rate control circuit for an MLVDS driver, characterized in that: Including pre-driver circuit, cold backup circuit and MLVDS output stage circuit; Pre-driver circuit: The output end of the pre-driver circuit is connected to the MLVDS output stage circuit to generate 8-phase delayed switching signals. The delay difference between two adjacent phase switching signals is TD. The 8-phase delayed switching signals respectively control whether MOS tubes of different sizes in the MLVDS output stage circuit are turned on; Cold backup circuit: When the power supply is powered on normally, it ensures the normal operation of the MLVDS output stage circuit; when the power supply is powered off or floating, it cuts off the parasitic channel between the MLVDS output end and the power supply to achieve cold backup function; MLVDS output driver circuit: provides driving capability and generates differential signals at both ends of the external load resistor under the control of the output signal of the pre-driver circuit; The pre-driver circuit includes combinational logic units Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, an inverter INV2, and a NAND gate NAND1; The input terminal A1 of the logic unit Q0 is connected to the output terminal of NAND1, the input terminal A2 is connected to the input terminal A1 of the logic unit Q2, and the input terminal A3 is connected to the enable signal EN; The input terminal A1 of the logic unit Q1 is connected to the output terminal of the logic unit Q0, the input terminal A2 is connected to the output terminal of the logic unit Q2, and the input terminal A3 is connected to the enable signal EN; The input terminal A1 of the logic unit Q2 is connected to the output terminal of the logic unit Q1, the input terminal A2 is connected to the output terminal of the logic unit Q3, and the input terminal A3 is connected to the enable signal EN; The input terminal A1 of the logic unit Q3 is connected to the output terminal of the logic unit Q2, the input terminal A2 is connected to the output terminal of the logic unit Q4, and the input terminal A3 is connected to the enable signal EN; The input terminal A1 of the logic unit Q4 is connected to the output terminal of the logic unit Q3, the input terminal A2 is connected to the output terminal of the logic unit Q5, and the input terminal A3 is connected to the enable signal EN; The input terminal A1 of the logic unit Q5 is connected to the output terminal of the logic unit Q4, the input terminal A2 is connected to the output terminal of the logic unit Q6, and the input terminal A3 is connected to the enable signal EN; The input terminal A1 of the logic unit Q6 is connected to the output terminal of the logic unit Q5, the input terminal A2 is connected to the output terminal of the logic unit Q7, and the input terminal A3 is connected to the enable signal EN; The input terminal A1 of the logic unit Q7 is connected to the output terminal of the logic unit Q6, the input terminal A2 is connected to the output terminal of the logic unit Q8, and the input terminal A3 is connected to the enable signal EN; An input terminal A1 of the logic unit Q8 is connected to an output terminal of the logic unit Q7, an input terminal A2 is connected to a switching signal SW, and an input terminal A3 is connected to an enable signal EN; an input terminal of the inverter INV2 is connected to an input terminal of the logic unit Q0, and an output terminal of the INV2 is connected to an input terminal of a NAND gate NAND1; a first input terminal of the NAND gate NAND1 is connected to an output terminal of the INV2, a second input terminal of the NAND gate NAND1 is connected to a switching signal SW, and an output terminal of the NAND gate NAND1 is connected to an input terminal A1 of the logic unit Q0; input terminals A3 of the logic units Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, and Q8 are connected to one another and to the enable signal EN; and a pre-driver circuit generates eight control signals SN1, SN2, SN3, SN4, SN5, SN6, SN7, and SN8 whose phases are sequentially delayed.

2. The cold backup and slew rate control circuit for an MLVDS driver according to claim 1, wherein: The cold backup circuit includes PMOS transistors P1-P8, NMOS transistors N1-N4, current source I0 and tail resistor Rtail; The drain of the PMOS transistor P1 is simultaneously connected to the drain of the PMOS transistor P4, the source of the PMOS transistor P3, the drain of the PMOS transistor P2, and the drain of the NMOS transistor N2. The source of the PMOS transistor P1 is simultaneously connected to the current source I0 and the source of the PMOS transistor P5. The gate of the PMOS transistor P1 is simultaneously connected to the drain of the NMOS transistor N1 and the source of the PMOS transistor P4. The drain of the PMOS transistor P2 is connected to the drain of the PMOS transistor P1, the drain of the PMOS transistor P4, the source of the PMOS transistor P3, and the drain of the NMOS transistor N2. The gate of the PMOS transistor P2 is connected to VDD. The drain of the PMOS transistor P3 is connected to OUTP, the source of the PMOS transistor P3 is connected to the drain of the PMOS transistor P1, the drain of the PMOS transistor P4, the drain of the PMOS transistor P2, and the drain of the NMOS transistor N2, and the gate of the PMOS transistor P3 is connected to the enable signal ENN; The drain of the PMOS transistor P4 is connected to the drain of the PMOS transistor P1, the drain of the PMOS transistor P2, the source of the PMOS transistor P3, and the drain of the NMOS transistor N2. The source of the PMOS transistor P4 is connected to the gate of the PMOS transistor P1 and the drain of the NMOS transistor N1. The drain of the NMOS transistor N1 is connected to the gate of the PMOS transistor P1 and the source of the PMOS transistor P4. The source of the NMOS transistor N1 is connected to the switching signal SN, and the gate of the NMOS transistor N1 is connected to VDD. The drain of the NMOS transistor N2 is connected to the drain of the PMOS transistor P1, the drain of the PMOS transistor P2, the source of the PMOS transistor P3, and the drain of the PMOS transistor P4. The source of the NMOS transistor N2 is connected to the source of the NMOS transistor N4 and the resistor Rtail. PMOS transistors P1, P2, and P4 are built in the same N-well FW1, and the source of PMOS transistor P2 is connected to the N-well FW1; The drain of the PMOS transistor P5 is simultaneously connected to the drain of the PMOS transistor P6, the source of the PMOS transistor P7, the drain of the PMOS transistor P8, and the drain of the NMOS transistor N4. The source of the PMOS transistor P5 is simultaneously connected to the current source I0 and the source of the PMOS transistor P1. The gate of the PMOS transistor P5 is simultaneously connected to the drain of the NMOS transistor N3. The drain of the PMOS transistor P6 is connected to the drain of the PMOS transistor P5, the drain of the PMOS transistor P8, the source of the PMOS transistor P7, and the drain of the NMOS transistor N4. The gate of the PMOS transistor P6 is connected to VDD. The drain of the PMOS transistor P7 is connected to OUTP, the source of the PMOS transistor P7 is connected to the drain of the PMOS transistor P5, the drain of the PMOS transistor P8, the drain of the PMOS transistor P7 and the drain of the NMOS transistor N4, and the gate of the PMOS transistor P7 is connected to the enable signal ENN; The drain of the PMOS transistor P8 is connected to the drain of the PMOS transistor P5, the drain of the PMOS transistor P6, the source of the PMOS transistor P7, and the drain of the NMOS transistor N4. The source of the PMOS transistor P8 is connected to the gate of the PMOS transistor P5 and the drain of the NMOS transistor N3. The drain of the NMOS transistor N3 is connected to the gate of the PMOS transistor P5 and the source of the PMOS transistor P8. The source of the NMOS transistor N1 is connected to the switching signal SP, and the gate of the PMOS transistor N3 is connected to VDD. The drain of the NMOS transistor N4 is connected to the drain of the PMOS transistor P5, the drain of the PMOS transistor P6, the source of the PMOS transistor P7, and the drain of the PMOS transistor P8. The source of the NMOS transistor N4 is connected to the source of the NMOS transistor N2 and the resistor Rtail. The source of the NMOS transistor N4 is connected to the switching signal SP. The PMOS transistors P5 , P6 , and P8 are fabricated in the same N-well FW2 , and the source of the PMOS transistor P6 is connected to the N-well FW2 .

3. The cold backup and slew rate control circuit for an MLVDS driver according to claim 2, wherein: The output drive circuit includes PMOS transistors P11, P12, P13, P14, P15, P16, P17, P18, P51, P52, P53, P54, P55, P56, P57, P58, NMOS transistors N21, N22, N23, N24, N25, N26, N27, N28, N41, N42, N43, N44, N45, N46, N47, N48, current source I0 and tail resistor Rtail; The sources of the PMOS transistors P11, P12, P13, P14, P15, P16, P17, P18, P51, P52, P53, P54, P55, P56, P57, and P58 are connected to each other and to the current source I0; the drains of the PMOS transistors P11, P12, P13, P14, P15, P16, P17, and P18 are all connected to the source of the PMOS transistor P3; the drains of the PMOS transistors P51, P52, P53, P54, P55, P56, P57, and P58 are all connected to the source of the PMOS transistor P7; The sources of the MOS transistors N21, N22, N23, N24, N25, N26, N27, N28, N41, N42, N43, N44, N45, N46, N47, and N48 are connected to each other and to the tail resistor Rtail. The drains of the NMOS transistors N21, N22, N23, N24, N25, N26, N27, and N28 are connected to the source of the PMOS transistor P3. The drains of the NMOS transistors N41, N42, N43, N44, N45, N46, N47, and N48 are all connected to the source of the PMOS transistor P7.

4. The cold backup and slew rate control circuit for an MLVDS driver according to claim 3, wherein: The width-to-length ratios of the PMOS transistors P11, P12, P13, P14, P15, P16, P17, and P18, the PMOS transistors P51, P52, P53, P54, P55, P56, P57, and P58, the NMOS transistors N21, N22, N23, N24, N25, N26, N27, and N28, and the NMOS transistors N41, N42, N43, N44, N45, N46, N47, and N48 increase in sequence and form an arithmetic progression.

5. The cold backup and slew rate control circuit for an MLVDS driver according to claim 4, characterized in that: The PMOS transistors P11, P12, P13, P14, P15, P16, P17, P18 and the NMOS transistors N21, N22, N23, N24, N25, N26, N27, N28 are respectively controlled by the 8-phase control signals SN1 to SN8 with equal delays. The PMOS transistors P51, P52, P53, P54, P55, P56, P57, P58 and the NMOS transistors N41, N42, N43, N44, N45, N46, N47, N48 are respectively controlled by the 8-phase control signals SP1 to SP8 with equal intervals. SN and SP are a pair of control signals with opposite phases.

6. The cold backup and slew rate control circuit for an MLVDS driver according to claim 5, characterized in that: The width-to-length ratio of the PMOS tube connected to the same control signal is twice that of the NMOS tube.

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