A control circuit for SAR ADC

Abstract

The present invention belongs to the fields of integrated circuits and analog-to-digital converters, and more specifically, to a control circuit for a successive approximation analog-to-digital converter (SAR ADC). The present invention utilizes a flag bit of a comparison result output by a comparator to advance the capacitor array switching and preamplifier setup time based on an original fixed reset time. The present invention extends the capacitor array switching and preamplifier setup time based on the original fixed time, i.e., the comparator reset time, to establish a more accurate comparator input value and save the power consumption required to achieve the same parameters under the original synchronous timing.

Description

Technical Field

[0001] The present invention belongs to the field of integrated circuits and analog-to-digital converters, and in particular relates to a control circuit of a successive approximation analog-to-digital converter (SAR ADC). Background Art

[0002] As the integrated circuit industry continues to shrink its manufacturing process, the processing power of digital circuits within them continues to grow, and their applications are becoming increasingly widespread. However, at a macro level, nature remains continuous and analog, and analog-to-digital converters (ADCs) remain indispensable in modern electronic systems. Due to their widespread application, ADCs are a crucial component of most modern electronic systems. However, ADCs are often the performance bottleneck in the signal chain. Continuous advancements in ADC performance are pushing boundaries we once thought impossible. SAR ADCs excel in the low-power realm.

[0003] The SAR ADC's logic functions are based on a specific logic flow. Proper operation of the logic module ensures accurate establishment of the CDAC voltage and correct comparator output. Under synchronous timing, to ensure the correct establishment of the comparator input voltage, the designed settling time must meet the requirements under the worst-case scenario. This can result in excessively long settling times under other conditions, resulting in a waste of bandwidth and power. Therefore, optimizing the SAR ADC's logic design can reduce overall power consumption and improve the SNR. Summary of the Invention

[0004] The present invention aims to provide a circuit architecture for SAR ADCs that can mitigate the degradation of the signal-to-noise ratio (SNR) caused by incomplete setup of the DAC and latch comparator preamplifier in the SAR ADC, thereby reducing power consumption while achieving a certain SNR.

[0005] The technical solution of the present invention is:

[0006] A SAR ADC control circuit comprises a counter circuit, a comparison module, a latch signal generation module, a digital signal storage module and a DAC control signal control module.

[0007] The counter circuit includes a first trigger 100, a second trigger 101, a third trigger 102, a fourth trigger 103 and a thirteenth trigger 119; the comparison module includes a preamplifier 116, a latch comparator 117 and a NAND gate 118; the latch signal generation module includes a fifth trigger 104, a sixth trigger 105, a seventh trigger 106, and an eighth trigger 107; the digital signal storage module includes a ninth trigger 108, a tenth trigger 109, an eleventh trigger 110, and a twelfth trigger 111; the DAC control signal control module includes a second logic module 112, a third logic module 113, and a fourth logic module 114; and a CDAC module 120.

[0008] Specifically, the external CLK signal is connected to the CLK ports of 100 , 101 , 102 , 103 and 119 .

[0009] The digital power supply VDD is connected to the D port of the first trigger 100 .

[0010] The Q port of the first trigger 100 is connected to the D port of the second trigger 101 and the fifth trigger 104, the Q port of the second trigger 101 is connected to the D port of the third trigger 102 and the sixth trigger 105, the Q port of the third trigger 102 is connected to the D port of the fourth trigger 103 and the seventh trigger 106, and the Q port of the fourth trigger 103 is connected to the D port of the eighth trigger 107 and the thirteenth trigger 119.

[0011] The Q port of the thirteenth flip-flop 119 is connected to the RST ports of all flip-flops including the thirteenth flip-flop 119 .

[0012] The Q port of the fifth flip-flop 104 is connected to the CLK port of the ninth flip-flop 108 , the Q port of the sixth flip-flop 105 is connected to the CLK port of the tenth flip-flop 109 , the Q port of the seventh flip-flop 106 is connected to the CLK port of the eleventh flip-flop 110 , and the Q port of the eighth flip-flop 107 is connected to the CLK port of the twelfth flip-flop 111 .

[0013] An output port of the NAND gate 118 is connected to CLK ports of the fifth flip-flop 104 , the sixth flip-flop 105 , the seventh flip-flop 106 , and the eighth flip-flop 107 .

[0014] An output port of the latch comparator 117 is connected to D ports of the ninth flip-flop 108 , the tenth flip-flop 109 , the eleventh flip-flop 110 , and the twelfth flip-flop 111 .

[0015] The Q port of the ninth trigger 108 is connected to the input port of the first logic module 112, the Q port of the tenth trigger 109 is connected to the input port of the second logic module 113, the Q port of the eleventh trigger 110 is connected to the input port of the third logic module 114, and the Q port of the twelfth trigger 111 is connected to the input port of the fourth logic module 115.

[0016] The first logic module 112, the second logic module 113, the third logic module 114 and the fourth logic module 115 are connected to the CDAC module 120; the first logic module 112, the second logic module 113, the third logic module 114 and the fourth logic module 115 generate switch control signals for the CDAC to perform the successive approximation function at different cycles.

[0017] The differential output port of the preamplifier 116 is connected to the differential input port of the latch comparator 117 .

[0018] The counter circuit, comparison module, latch signal generation module, digital signal storage module and DAC control signal control module described in the present invention include other types of modules with the same functions but not limited to specific circuits or numbers.

[0019] The examples of the present invention are based on a SAR ADC with a four-bit resolution, and the scope of the invention includes SAR ADCs with other resolutions, and the logic is similar.

[0020] The simulation diagram of this invention is Figure 4 This figure shows how the signal-to-noise ratio of a nine-bit resolution SAR ADC changes with different normalized settling times under the present invention. This figure is derived under a specific relationship between output delay and input differential value, but is applicable to other specific relationships between output delay and input differential value.

[0021] The beneficial effect of the present invention is that, by generating and outputting a flag signal of the latch comparator, i.e., the output terminal of the NAND gate, the comparison phase of the comparator is terminated in advance, and the remaining time of the comparison phase is used to establish the capacitor array switching of the SAR ADC and the establishment of the preamplifier. The original capacitor array switching establishment time and the preamplifier establishment time are the reset period of the latch comparator. On this basis, the capacitor array switching establishment time and the preamplifier establishment time are extended, making the establishment time longer and the input value of the latch comparator more accurately established. Under the condition of meeting a certain signal-to-noise ratio, the required preamplifier bandwidth is smaller, allowing the on-resistance of the DAC capacitor array switch to be larger, thereby reducing power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 This is a logical architecture diagram with a resolution of four bits proposed by the present invention.

[0023] Figure 2This is a timing diagram of the present invention.

[0024] Figure 3 This is a graph showing how the signal-to-noise ratio of a nine-bit resolution SAR ADC changes with different normalized settling times under synchronous timing.

[0025] Figure 4 This is a graph showing how the signal-to-noise ratio of a nine-bit resolution SAR ADC changes with different normalized settling times under the present invention. DETAILED DESCRIPTION

[0026] The technical method of the present invention is described in detail below with reference to the accompanying drawings and embodiments.

[0027] Attachment Figure 1 The logic architecture of the SAR ADC with four-bit resolution proposed by the present invention includes 13 triggers, 4 logic modules, a preamplifier, a latch comparator and a NAND gate.

[0028] Attachment Figure 2 This is a partial signal timing diagram of the present invention.

[0029] When the rising edge of the first CLK arrives, the input of the first trigger 100 is high, and the output Q follows the input and is high. The output Q of the second trigger 101, the third trigger 102, and the fourth trigger 103 follow the input and remain low. When the second CLK rising edge arrives, the second trigger 101, because the input was set to 1 at the first CLK, the output Q follows the input. Switch to high. The third trigger 102 and the fourth trigger 103 are similarly switched to high in turn. Until the fifth CLK rising edge arrives. The output Q of the thirteenth trigger switches from low to high, and this high-level signal resets all triggers.

[0030] After the first rising edge of CLK arrives, latch comparator 117 begins comparison. After a certain period of time, the comparator outputs the result, namely, a differential output of one high and one low. Compared to the latch comparator's dual-terminal outputs in the same high or low phase during the reset phase, once one high and one low appear, NAND gate 118 receives the one high and one low output signals of latch comparator 117 and outputs a high level as a flag indicating that the latch comparator's comparison is complete. This flag serves as the CLK input to the fifth flip-flop 104, the sixth flip-flop 105, the seventh flip-flop 106, and the eighth flip-flop 107. Due to the differences in the D-terminal input signals of the fifth flip-flop 104, the sixth flip-flop 105, the seventh flip-flop 106, and the eighth flip-flop 107, the Q-terminal output signals of the fifth flip-flop 104, the sixth flip-flop 105, the seventh flip-flop 106, and the eighth flip-flop 107 have different CDAC values, indicating that the comparison is complete at different positions. These flag signals are used for the ninth trigger 108, the tenth trigger 109, the eleventh trigger 110 and the twelfth trigger 111 to collect the CLK signal of the comparison result of the latch comparator 117, that is, the ninth trigger 108 collects and stores the comparison result of the first bit, the tenth trigger 109 collects and stores the comparison result of the second bit, the eleventh trigger 110 collects and stores the comparison result of the third bit, and the twelfth trigger 111 collects and stores the comparison result of the fourth bit.

[0031] The comparison results stored in the ninth flip-flop 108, the tenth flip-flop 109, the eleventh flip-flop 110, and the twelfth flip-flop 111 are respectively fed back to the first logic module 112, the second logic module 113, the third logic module 114, and the fourth logic module 115. The first logic module 112, the second logic module 113, the third logic module 114, and the fourth logic module 115 generate switch control signals for the CDAC to perform the successive approximation function at different cycles.

[0032] Figure 2 The available setup time varies under this operation logic according to the time when the comparator output flag is generated, but is always extended.

[0033] Figure 3 This is a graph showing how the signal-to-noise ratio of a nine-bit resolution SAR ADC changes with different normalized settling times under synchronous timing.

[0034] Figure 4 This is a graph showing how the signal-to-noise ratio of a nine-bit resolution SAR ADC changes with different normalized settling times under the present invention.

[0035] Figure 3 and Figure 4The horizontal axis represents the normalized comparator CLK low-level time, i.e., the comparator reset time, with the numerical value representing a multiple of the RC time constant τ. The vertical axis represents the signal-to-noise ratio (SNR). It can be seen that under the same normalized CLK low-level time, the SNR of the present invention is higher in the first part.

[0036] The present invention prolongs the capacitor array switching establishment time and the preamplifier establishment time on the basis of the original fixed time, that is, the reset time of the comparator, establishes a more accurate comparator input value, and saves the power consumption required to achieve the same parameters under the original synchronous timing.

Claims

1. A control circuit for a SAR ADC, characterized in that: It includes a counter circuit, a comparison module, a latch signal generation module, a digital signal storage module and a DAC control signal control module; The counter circuit includes a first trigger, a second trigger, a third trigger, a fourth trigger, and a thirteenth trigger; the comparison module includes a preamplifier, a latch comparator, and a NAND gate; the latch signal generation module includes a fifth trigger, a sixth trigger, a seventh trigger, and an eighth trigger; the digital signal storage module includes a ninth trigger, a tenth trigger, an eleventh trigger, and a twelfth trigger; the DAC control signal control module includes a first logic module, a second logic module, a third logic module, a fourth logic module, and a CDAC module; The D port of the first flip-flop is connected to the power supply, the CLK port is connected to the external CLK signal, and the Q port is connected to the D port of the second flip-flop and the D port of the fifth flip-flop; the CLK port of the second flip-flop is connected to the external CLK signal, and the Q port is connected to the D port of the third flip-flop and the D port of the sixth flip-flop; the CLK port of the third flip-flop is connected to the external CLK signal, and the Q port is connected to the D port of the fourth flip-flop and the D port of the seventh flip-flop; the CLK port of the fourth flip-flop is connected to the external CLK signal, and the Q port is connected to the D port of the eighth flip-flop and the D port of the thirteenth flip-flop; The CLK port of the thirteenth flip-flop is connected to the external CLK signal, and the Q port is connected to the RST port of all flip-flops; The Q port of the fifth flip-flop is connected to the CLK port of the ninth flip-flop, the Q port of the sixth flip-flop is connected to the CLK port of the tenth flip-flop, the Q port of the seventh flip-flop is connected to the CLK port of the eleventh flip-flop, and the Q port of the eighth flip-flop is connected to the CLK port of the twelfth flip-flop; An input port of the NAND gate is connected to an output port of the latch comparator, and an output port of the NAND gate is connected to a CLK port of a fifth flip-flop, a CLK port of a sixth flip-flop, a CLK port of a seventh flip-flop, and a CLK port of an eighth flip-flop; The output port of the latch comparator is connected to the D port of the ninth flip-flop, the D port of the tenth flip-flop, the D port of the eleventh flip-flop, and the D port of the twelfth flip-flop; The Q port of the ninth flip-flop is connected to the input port of the first logic module, the Q port of the tenth flip-flop is connected to the input port of the second logic module, the Q port of the eleventh flip-flop is connected to the input port of the third logic module, and the Q port of the twelfth flip-flop is connected to the input port of the fourth logic module; The output port of the first logic module, the output port of the second logic module, the output port of the third logic module, and the output port of the fourth logic module are connected to the input port of the CDAC module; the first logic module, the second logic module, the third logic module, and the fourth logic module are used to generate switch control signals for the CDAC to perform a successive approximation function at different cycles; The differential output port of the preamplifier is connected to the differential input port of the latch comparator, and the two input ports of the preamplifier are connected to the two output ports of the CDAC module.

Images