Sleep and wake circuit, circuit board and automobile controller

Abstract

The embodiment of the application provides a kind of dormancy and wake-up circuit, circuit board and automobile controller, it is related to automobile control technical field, in the dormancy and wake-up circuit, the power supply end of power chip module is connected with the power supply pin of connector, the first power supply pin of core processor is connected with the output end of power chip module;CAN transceiver is connected with core processor through bus, CAN transceiver is also connected with connector through twisted pair, the second power supply pin is connected with the output end of power chip module, the power supply pin is connected with dormancy power supply pin, the external enable end of power chip module is connected with disable control pin, the input end of IGN signal conversion module is connected with IGN signal pin, the first output end of IGN signal conversion module is connected with wake-up pin, the second output end of IGN signal conversion module is connected with the general input pin of core processor.The circuit design of the scheme is simple, and the power consumption generated can be effectively reduced.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of automobile control, and in particular to a sleep and wake-up circuit, a circuit board and an automobile controller. BACKGROUND

[0002] Under the tide of the development of information technology, intelligentization, networking and electrification have become the main direction of the development of the automobile industry. Whether it is the three-electric system (battery, motor and electric control) or various vehicle parts, the demand for chips by automobiles is increasing. According to statistics, the number of chips required for the manufacture of an average vehicle in 2021 reached more than 1000, and the number of processors required reached 70-100. The number of chips required by automobiles is large, and even when the control system of the automobile is in sleep mode, the power consumption caused by the chips is large.

[0003] In the face of so many power-consuming chips, from the perspectives of cost and energy, the low-power design of the automobile control system is particularly important. In related technologies, for control systems that use complex processors, the low-power circuit design used is complex, requires many devices, and the power consumption generated in the low-power mode is still high, with a current of more than a milliampere, which is difficult to meet the low-power requirement. SUMMARY

[0004] Embodiments of the present application provide a sleep and wake-up circuit, a circuit board and an automobile controller, which have simple circuit design and can effectively reduce the power consumption generated.

[0005] In a first aspect, embodiments of the present application provide a sleep and wake-up circuit, which includes a connector, a power supply chip module, a core processor, a CAN transceiver and an IGN signal conversion module.

[0006] The connector includes a power supply pin and an IGN signal pin; a power supply end of the power supply chip module is connected with the power supply pin of the connector, and the power supply chip module is configured to provide working voltage for each device; a first power supply pin of the core processor is connected with an output end of the power supply chip module; the CAN transceiver is connected with the core processor through a bus, and the CAN transceiver is further connected with the connector through a twisted pair; the CAN transceiver further includes a second power supply pin, a sleep power supply pin, a wake-up pin and a disable control pin, the second power supply pin is connected with the output end of the power supply chip module, the sleep power supply pin is connected with the power supply pin, the disable control pin is connected with an external enable end of the power supply chip module, the wake-up pin is configured to control the output of the disable control pin, and the external enable end is configured to control the working state of the power supply chip module; an input end of the IGN signal conversion module is connected with the IGN signal pin, a first output end of the IGN signal conversion module is connected with the wake-up pin, and a second output end of the IGN signal conversion module is connected with a general input pin of the core processor; the IGN signal conversion module is configured to control the input of the wake-up pin and the input of the general input pin according to the output of the IGN signal pin.

[0007] In a second aspect, the embodiments of the present application further provide a circuit board, which comprises the sleep and wake-up circuit as described in the above embodiments.

[0008] In a third aspect, the embodiments of the present application further provide an automobile controller, which comprises the circuit board as described in the above embodiments.

[0009] The sleep and wake-up circuit of the present application can realize the compatibility of the IGN signal and the CAN signal through the IGN signal conversion module and the CAN transceiver, and realize the switching of the sleep and wake-up. The design of the sleep and wake-up circuit can make fewer chips in the working state in the sleep mode, thereby effectively realizing the lowest level of power consumption; meanwhile, the circuit design is simple, and does not need too complex hardware architecture, thereby saving the hardware cost. BRIEF DESCRIPTION OF DRAWINGS

[0010] Figure 1 FIG. 1 is a schematic diagram of a low-power sleep and wake-up circuit supporting CAN signal and IGN signal in the related art;

[0011] Figure 2 FIG. 2 is a schematic diagram of another low-power sleep and wake-up circuit supporting CAN signal and IGN signal in the related art;

[0012] Figure 3 FIG. 3 is a principle block diagram of the sleep and wake-up circuit provided by the embodiments of the present application;

[0013] Figure 4 FIG. 4 is a circuit schematic diagram of the first signal conversion unit provided by an embodiment of the present application;

[0014] Figure 5 a circuit schematic diagram of a second signal conversion unit provided by an embodiment of the present application;

[0015] Figure 6 a circuit schematic diagram of a sleep and wake-up circuit provided by an embodiment of the present application. DETAILED DESCRIPTION

[0016] The present application will be further described below in conjunction with the accompanying drawings and embodiments. It can be understood that the embodiments described herein are used to explain the present application, rather than limit the present application. In addition, it should be noted that, for the convenience of description, only the parts related to the present application are shown in the accompanying drawings, rather than all the structures.

[0017] It should be noted that, due to the limitation of the length, all the optional embodiments are not enumerated in the present application, and those skilled in the art should be able to think of that, as long as the technical features are not contradictory, any combination of the technical features can constitute an optional embodiment.

[0018] It should be noted that, in the present application, the relationship terms such as "first" and "second" are only used to distinguish one entity or operation or object from another entity or operation or object, and do not necessarily require or imply any actual relationship or order between the entities or operations or objects. And the objects distinguished by "first", "second" and the like are not limited to the number, which can be one or more. It can be thought that "multiple" is two or more in the description of the present application.

[0019] In the related art, there are two wake-up modes for the automobile control system. One is that the automobile controller switches from the sleep mode to the working mode by detecting the IGN signal output by the ignition switch, so as to realize the wake-up. The other is that the automobile controller switches from the sleep mode to the working mode by detecting the CAN signal, wherein the CAN signal includes but is not limited to the wake-up instruction (also referred to as message, signal, message, etc.) transmitted through the CAN bus.

[0020] The power consumption of the control system compatible with the above two wake-up modes is large, that is, even in the sleep mode, the processor and other chips are in the low-power mode, and the working current is still in the level of milliamperes or above, and it is still impossible to realize the low-power operation. For example, Figure 1 as shown, Figure 1As shown in FIG. 1, two power chip modules convert the power supply voltage provided by the connector into working voltage suitable for the core processor, and provide working voltage for the core processor. The connector also connects the CAN transceiver through the twisted pair, and the CAN transceiver is connected to the core processor for signal transmission. The connector can also transmit the IGN signal to the core processor. When the circuit is in the low-power sleep mode, the CAN transceiver and the two power chip modules in the circuit are still in working state, so there are more working chips in the circuit, and the power consumption is still high, which has not been effectively reduced, and the current of the circuit is in the order of milliamperes.

[0021] Figure 2 As shown in FIG. 2, two power chip modules convert the power supply voltage provided by the connector into working voltage suitable for the core processor, and provide working voltage for the core processor. The connector also connects the CAN transceiver through the twisted pair, and the CAN transceiver is connected to the core processor for signal transmission. The connector can also transmit the IGN signal to the core processor. When the circuit is in the low-power sleep mode, the CAN transceiver and the two power chip modules in the circuit are still in working state, so there are more working chips in the circuit, and the power consumption is still high, which has not been effectively reduced, and the current of the circuit is in the order of milliamperes. Figure 2 Figure 2 Figure 1 As shown in FIG. 2, two power chip modules convert the power supply voltage provided by the connector into working voltage suitable for the core processor, and provide working voltage for the core processor. The connector also connects the CAN transceiver through the twisted pair, and the CAN transceiver is connected to the core processor for signal transmission. The connector can also transmit the IGN signal to the core processor. When the circuit is in the low-power sleep mode, the CAN transceiver and the two power chip modules in the circuit are still in working state, so there are more working chips in the circuit, and the power consumption is still high, which has not been effectively reduced, and the current of the circuit is in the order of milliamperes.

[0022] Therefore, the embodiment of the present application provides a sleep and wake-up circuit, which has simple circuit structure and can effectively reduce the power consumption in low-power operation. As shown in FIG. 3, Figure 3 Figure 3 As shown in FIG. 3, the sleep and wake-up circuit provided by the embodiment of the present application includes a connector 301, a power chip module 302, a core processor 303, a CAN transceiver 304 and an IGN signal conversion module 305.

[0023] The connector 301 is a connecting device of the circuit and external devices, and has a power supply pin, an IGN signal pin and a CAN signal pin. The power supply pin is used to connect the power supply to the power chip module 302, so the power supply pin is connected to the power supply end of the power chip module 302. The power chip module 302 is used to provide working voltage for each device in the circuit. It can be understood that the first power supply pin of the core processor 303 is connected to the output end of the power chip module 302.

[0024] ​​​The CAN transceiver 304 is connected with the connector 301 through a twisted pair, such as being connected with a CAN signal pin of the connector 301. In addition, the CAN transceiver 304 is also connected with the core processor 303 through a bus, so that the CAN transceiver 304 can receive a control signal sent by the core processor 303 and the like. The CAN transceiver 304 comprises a second power supply pin for accessing a working voltage of the CAN transceiver 304, and a sleep power supply pin connected with a power supply pin of the connector 301. It is worth noting that the CAN transceiver 304 of the present application has a wake-up function, and further comprises a wake-up pin and a disable control pin, the wake-up pin can be used to control the output of the disable control pin, and the disable control pin is connected with an external enable end of the power supply chip module 302, which can be used to control the working state of the power supply chip module 302, such as controlling the power supply chip module 302 to start or stop providing a working voltage, so that the output of the power supply chip module 302 can be controlled by controlling the level change of the wake-up pin.

[0025] The first output end of the IGN signal conversion module 305 is connected with the wake-up pin, and the input end of the IGN signal conversion module 305 is connected with the IGN signal pin, so that the IGN signal conversion module 305 can control the input of the wake-up pin according to the received IGN signal, so that the level change of the wake-up pin is effectively controlled. In addition, the second input end of the IGN signal conversion module 305 is connected with a general input pin of the core processor, so that the IGN signal conversion module 305 can also control the input of the general input pin. The core processor 303 can determine the control signal sent to the CAN transceiver 304 according to the level change of the general input pin.

[0026] As can be seen from the above scheme, the sleep and wake-up circuit can realize the compatibility of the IGN signal and the CAN signal and the switching of sleep and wake-up through the IGN signal conversion module and the CAN transceiver. The design of the sleep and wake-up circuit can make fewer chips in the working state in the sleep mode, thereby effectively realizing the lowest level of power consumption; at the same time, the circuit design is simple and does not need too complex hardware architecture, thereby saving the hardware cost.

[0027] In some embodiments, the power supply chip module comprises a first power supply chip and a second power supply chip, a first input pin of the first power supply chip is connected with the power supply pin, a first enable pin of the first power supply chip is connected with the disable control pin, a first output pin of the first power supply chip is connected with a second input pin and a second enable pin of the second power supply chip, and a second output pin of the second power supply chip is connected with the first power supply pin. The first power supply chip is used to provide a first working voltage, such as 5V, and the second power supply chip is used to provide a second working voltage, such as 3.3V.

[0028] Further, the working state of the first power chip is controlled by the CAN transceiver, and the working state of the second power chip is controlled by the first power chip, so that the CAN transceiver can control the power chip module. For example, the first power chip and the second power chip are both enabled and output corresponding voltages when the corresponding enable pins are at a high level. When the enable control pin of the CAN transceiver outputs a high level, the first power chip is enabled and outputs a first working voltage. At this time, since the first output pin of the first power chip is connected to the second enable pin of the second power chip and the first power chip outputs a high level, the second power chip is enabled and outputs a second working voltage. When the enable control pin of the CAN transceiver outputs a low level, the first power chip and the second power chip are both disabled and cannot provide corresponding working voltages.

[0029] Therefore, the first power chip and the second power chip can be enabled to work at the same time, and the first power chip and the second power chip can be further controlled to not work, so as to reduce power consumption in the sleep mode.

[0030] In some embodiments, the power chip module includes the first power chip and the second power chip, and the second power supply pin of the CAN transceiver includes a main power supply pin and an auxiliary power supply pin. Therefore, the main power supply pin is connected to the first output pin of the first power chip, which can provide a working voltage, such as a 5V working voltage, for the CAN transceiver; and the auxiliary power supply pin is connected to the second output pin of the second power chip, so as to internally adjust the level of digital transceiving of the CAN transceiver.

[0031] Therefore, after the system enters the sleep mode, the CAN transceiver is only connected to the voltage of the sleep power supply pin, so that the power supply current in the system is in the microampere level, and low-power design is effectively realized.

[0032] In some embodiments, the IGN signal conversion module includes a first signal conversion unit and a second signal conversion unit, wherein the first signal conversion unit serves as a detection unit of the IGN signal, the input end of the first signal conversion unit is connected to the IGN signal pin, and the output end of the first signal conversion unit is connected to the wake-up pin of the CAN transceiver. The first signal conversion unit can adjust the level change of the wake-up pin according to the output of the IGN signal pin. For example, when the IGN signal pin outputs a corresponding level to enable the first signal conversion unit, the level of the wake-up pin changes, so that the CAN transceiver can control the power chip module.

[0033] Furthermore, the input terminal of the second signal conversion unit is connected to the output terminal of the first signal conversion unit, and the output terminal of the second signal conversion unit is connected to the general-purpose input pin of the core processor. Therefore, the first signal conversion unit can also be used to control the conduction state of the second signal conversion unit, thereby controlling the level change of the input to the general-purpose input pin. That is, the IGN signal conversion module can control the input to the wake-up pin and the general-purpose input pin according to the conduction state of the first and second signal conversion units.

[0034] Specifically, Figure 4 A circuit diagram of a first signal conversion unit provided in an embodiment of this application is shown below. Figure 4 As shown, in one embodiment, the first signal conversion unit includes a first current-limiting resistor R1, a first pull-down resistor R2, a filter capacitor C1, a first switching transistor Q1, and a first pull-up resistor R3. The two ends of the first current-limiting resistor R1 are connected to the IGN signal pin and the control terminal of the first switching transistor Q1, respectively. The first pull-down resistor R2 and the filter capacitor C1 are connected in parallel, with one end of the first pull-down resistor R2 connected to the control terminal of the first switching transistor Q1 and the other end grounded. The parallel connection of the first pull-down resistor R2 and the filter capacitor C1 effectively prevents the control terminal of the first switching transistor Q1 from being left floating and also helps to prevent malfunctions caused by interference. Furthermore, the input terminal of the first switching transistor Q1 is connected to the first pull-up resistor R3 and is connected to the power supply voltage through the first pull-up resistor R3. The input terminal of the first switching transistor Q1 is also connected to a wake-up pin, while the output terminal of the first switching transistor Q1 is grounded.

[0035] The first switching transistor Q1 can be an NPN transistor. The base terminal of the NPN transistor serves as the control terminal of the first switching transistor Q1, while the collector terminal of the NPN transistor serves as the input terminal of the first switching transistor Q1, and the emitter terminal of the NPN transistor serves as the output terminal of the first switching transistor Q1.

[0036] Therefore, it is understandable that when the first switch Q1 is not turned on, since the wake-up pin is connected to the input terminal of the first switch Q1, that is, even when the first switch Q1 is not turned on, the wake-up pin is still connected to the power supply voltage through the first pull-up resistor R3. Therefore, the wake-up pin is at a high level. The first switch Q1 is affected by the IGN signal pin. When the control terminal of the first switch Q1 receives the IGN signal, the first switch Q1 can meet the turn-on condition, thus turning on the first switch Q1. The wake-up pin changes from a high level to a low level, causing the CAN transceiver's disable control pin to output a high level, thereby enabling the power chip module, waking up the system, and entering the working mode from the sleep mode.

[0037] It should be noted that in some embodiments, the first switch tube can also be an NMOS tube, for example, the gate end of the NMOS tube is used as the control end of the first switch tube, the drain end of the NMOS tube is used as the input end of the first switch tube, and the source end of the NMOS tube is used as the output end of the first switch tube.

[0038] Specifically, Figure 5 The circuit schematic diagram of the second signal conversion unit provided by an embodiment of the present application is shown in the figure. In an embodiment, the second signal conversion unit includes a second current limiting resistor R4, a second switch tube Q2, a second pull-up resistor R5, and a second pull-down resistor R6. The two ends of the second current limiting resistor R4 are respectively connected to the output end of the first signal conversion unit and the control end of the second switch tube Q2, the input end of the second switch tube Q2 is connected to the working voltage through the second pull-up resistor R5, the output end of the second switch tube Q2 is grounded through the second pull-down resistor R6, and the output end of the second switch tube Q2 is also connected to the general input pin of the core processor.

[0039] The second switch tube Q2 can be a PNP transistor, for example, the base end of the PNP transistor is used as the control end of the second switch tube Q2, the emitter end of the PNP transistor is used as the input end of the second switch tube Q2, and the collector end of the PNP transistor is used as the output end of the second switch tube Q2.

[0040] It can be understood that when the first signal conversion unit is not turned on, the second signal conversion unit is also in an off state, that is, the first switch tube is not turned on, the control end of the second switch tube is at a high level, and the second switch tube is not turned on, so the general input pin is at a low level. When the first switch tube is turned on, the control end of the second switch tube is grounded, and the second switch tube meets the turn-on condition, the second switch tube is turned on, and the general input pin is at a high level.

[0041] It should be noted that in some embodiments, the second switch tube can also be a PMOS tube, for example, the gate end of the PMOS tube is used as the control end of the second switch tube, the source end of the PMOS tube is used as the input end of the second switch tube, and the drain end of the PMOS tube is used as the output end of the second switch tube.

[0042] Exemplarily, Figure 6 The circuit schematic diagram of the hibernation and wake-up circuit provided by an embodiment of the present application is shown in the figure. The connector J1 includes a power pin for connecting to a power source, a CAN signal pin, and an IGN signal pin. The power pin is used to provide a power voltage for the first power chip U1. The CAN signal pin includes two pins, CAN_H and CAN_L. The CAN_H pin and the CAN_L pin of the connector J1 are connected to the corresponding pins of the CAN transceiver U4 through a twisted pair.

[0043] The OUT pin of the first power supply chip U1 is connected to the IN pin of the second power supply chip U2 as an output pin, and is also connected to the enable pin of the second power supply chip U2, such as the EN pin in the figure. The OUT pin of the second power supply chip is connected to the first power supply pin of the core processor U3.

[0044] The power supply pins of the CAN transceiver include a VCC pin and a VIO pin. The VCC pin is connected to the output pin of the first power supply chip U1 as a main power supply pin, and the VIO pin is connected to the output pin of the second power supply chip U2 as an auxiliary power supply pin. The VBAT pin of the CAN transceiver is connected to the power supply pin of the connector J1 as a sleep power supply pin.

[0045] In addition, the IGN signal conversion module includes a first current limiting resistor R1, a first pull-down resistor R2, a filter capacitor C1, a first switch tube Q1, a first pull-up resistor R3, a second current limiting resistor R4, a second switch tube Q2, a second pull-up resistor R5, and a second pull-down resistor R6.

[0046] The first switch tube Q1 is an NPN triode, and the second switch tube Q2 is a PNP triode. The first current limiting resistor R1 has its two ends connected to the IGN signal pin and the base end of the first switch tube Q1, respectively. The first pull-down resistor R2 and the filter capacitor C1 are connected in parallel, with one end of the first pull-down resistor R2 connected to the control end of the first switch tube Q1 and the other end grounded. The parallel connection of the first pull-down resistor R2 and the filter capacitor C1 can effectively prevent the base end of the first switch tube Q1 from being left hanging, and also prevent interference from causing misoperation. In addition, the collector end of the first switch tube Q1 is connected to the first pull-up resistor R3 and is connected to the power supply voltage through the first pull-up resistor R3, and the collector end of the first switch tube Q1 is also connected to the wake-up pin of the CAN transceiver U4 (such as the WAKE pin in the figure). The emitter end of the first switch tube Q1 is grounded.

[0047] The second current limiting resistor R4 has its two ends connected to the collector end of the first switch tube Q1 and the base end of the second switch tube Q2, respectively. The emitter end of the second switch tube Q2 is connected to the working voltage through the second pull-up resistor R5, and the collector end of the second switch tube Q2 is grounded through the second pull-down resistor R6. The collector end of the second switch tube Q2 is also connected to the general input pin (i.e., the GPIO1 pin) of the core processor U3.

[0048] Therefore, when the system is in the sleep mode, the IGN signal pin is low, the first switch tube Q1 and the second switch tube Q2 are not turned on, the first power supply chip U1, the second power supply chip U2 and the core processor U3 are in the non-working state, and only the VBAT pin inside the CAN transceiver U4 is powered, so that the sleep mode with low power consumption is realized, and the power supply current is in the microampere level, which can reach 60 microamperes.

[0049] When the IGN signal pin of the connector J1 is high, the first switch tube Q1 is turned on, the WAKE pin of the CAN transceiver U4 changes from high to low, so that the INH pin of the CAN transceiver U4 is triggered to be high, the first power supply chip U1 is enabled, and then the second power supply chip U2, the core processor U3 and the CAN transceiver U4 are also in the working state, and therefore the entire circuit is in the working mode. When the IGN signal pin of the connector J1 is low, the first switch tube Q1 is not turned on, the second switch tube Q2 is turned on, and the level of the GPIO1 pin of the core processor U3 changes from high to low, so that the sleep interrupt is generated. After the core processor U3 processes the related procedures, the core processor U3 can inform the CAN transceiver U4 to enter the low-power mode through the bus signal, so that the level of the INH pin is pulled low, and the first power supply chip U1, the second power supply chip U2 and the core processor U3 are in the non-working state. Only the VBAT pin inside the CAN transceiver U4 is powered, the power supply current is in the microampere level, and the sleep mode with low power consumption is realized.

[0050] When the CAN transceiver U4 receives the CAN signal sent by the host through the connector J1 for triggering the wake-up, the INH pin of the CAN transceiver U4 outputs high, so that the first power supply chip U1 is enabled. Therefore, the first power supply chip U1, the second power supply chip U2 and the core processor U4 are in the working state. When the CAN transceiver U4 receives the CAN signal sent by the host for triggering the sleep, the CAN transceiver U4 informs the core processor U3 to process the related procedures through the bus, and after the core processor U3 processes the related procedures, the core processor U3 can inform the CAN transceiver U4 to enter the low-power mode through the bus signal, so that the INH pin is low, so that the first power supply chip U1, the second power supply chip U2 and the core processor U3 are not working, and only the VBAT pin of the CAN transceiver U4 is powered, and the sleep mode with low power consumption is realized.

[0051] From the above workflow, it is known that only the CAN transceiver U4 is powered by VBAT in the low-power mode, and the VBAT power supply current in the low-power mode is only microamperes, which can truly realize the lowest level of power consumption; at the same time, the peripheral circuit design is simple, and a too complex hardware architecture is not needed, saving the hardware cost; the power supply current of the peripheral power supply and the processor does not need to be considered in the low-power mode, and the current size can be directly determined, realizing the platform design.

[0052] The embodiment of the present application also provides a circuit board, which comprises the sleep and wake-up circuit according to the above embodiment, and has the functions and beneficial effects of the sleep and wake-up circuit.

[0053] The embodiment of the present application also provides an automobile controller, which comprises the circuit board according to the above embodiment, and has the functions and beneficial effects of the sleep and wake-up circuit. The automobile controller can support the IGN signal and the CAN signal triggering at the same time, thereby switching the working mode, and the power consumption of the chip is low in the sleep mode, which can reach the microamperes level, effectively realizing the low-power design.

[0054] It should be further understood that the terms "comprise", "comprising", "include", "including", or any other variant thereof are intended to cover non-exclusive inclusion, such that processes, methods, articles, or apparatuses that comprise a list of elements are not limited to those elements, but can also include other elements not expressly listed, or can also include elements inherent in such processes, methods, articles, or apparatuses. Without further limitation, an element defined by the phrase "comprising a" does not exclude the existence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0055] It should be noted that the above are only the preferred embodiments of the present application and the technical principles applied. Those skilled in the art will understand that the present application is not limited to the specific embodiments described herein, and those skilled in the art can make various obvious changes, readjustments and substitutions without departing from the scope of the present application. Therefore, although the present application has been described in more detail through the above embodiments, the present application is not limited to the above embodiments, and can include more other equivalent embodiments without departing from the concept of the present application, and the scope of the present application is determined by the scope of the appended claims.

Claims

1. A sleep and wake-up circuit, characterized in that, include: The connector includes a power supply pin and an IGN signal pin; A power chip module, wherein the power supply terminal of the power chip module is connected to the power pin of the connector, and the power chip module is used to provide operating voltage for each device; The core processor has its first power supply pin connected to the output terminal of the power chip module; The CAN transceiver is connected to the core processor via a bus and also to the connector via a twisted pair cable. The CAN transceiver further includes a second power supply pin, a sleep power supply pin, a wake-up pin, and a disable control pin. The second power supply pin is connected to the output of the power chip module, the sleep power supply pin is connected to the power supply pin, the disable control pin is connected to an external enable pin of the power chip module, the wake-up pin controls the output of the disable control pin, and the external enable pin controls the operating state of the power chip module. The IGN signal conversion module has its input terminal connected to the IGN signal pin, its first output terminal connected to the wake-up pin, and its second output terminal connected to the general-purpose input pin of the core processor. The IGN signal conversion module is used to control the input of the wake-up pin and the input of the general-purpose input pin according to the output of the IGN signal pin.

2. The sleep and wake-up circuit according to claim 1, characterized in that, The power chip module includes a first power chip and a second power chip. The first input pin of the first power chip is connected to the power pin, the first enable pin of the first power chip is connected to the disable control pin, the first output pin of the first power chip is connected to the second input pin and the second enable pin of the second power chip, and the second output pin of the second power chip is connected to the first power supply pin.

3. The sleep and wake-up circuit according to claim 2, characterized in that, The second power supply pin of the CAN transceiver includes a main power supply pin and an auxiliary power supply pin. The main power supply pin is connected to the first output pin, and the auxiliary power supply pin is connected to the second output pin.

4. The sleep and wake-up circuit according to claim 1, characterized in that, The IGN signal conversion module includes a first signal conversion unit and a second signal conversion unit. The input terminal of the first signal conversion unit is connected to the IGN signal pin, and the output terminal of the first signal conversion unit is connected to the wake-up pin. The input terminal of the second signal conversion unit is connected to the output terminal of the first signal conversion unit, and the output terminal of the second signal conversion unit is connected to the general-purpose input pin. The first signal conversion unit is used to control the conduction state of the second signal conversion unit, and the IGN signal conversion module is used to control the input to the wake-up pin and the input to the general-purpose input pin according to the conduction state of the first signal conversion unit and the conduction state of the second signal conversion unit.

5. The sleep and wake-up circuit according to claim 4, characterized in that, The first signal conversion unit includes a first current-limiting resistor, a first pull-down resistor, a filter capacitor, a first switching transistor, and a first pull-up resistor. One end of the first current-limiting resistor is connected to the IGN signal pin, and the other end of the first current-limiting resistor is connected to the control terminal of the first switching transistor. One end of the first pull-down resistor is connected to the control terminal of the first switching transistor, and the other end of the first pull-down resistor is grounded. The filter capacitor is connected in parallel with the first pull-down resistor. The input terminal of the first switching transistor is connected to the power supply voltage through the first pull-up resistor. The input terminal of the switching transistor is connected to the wake-up pin, and the output terminal of the first switching transistor is grounded.

6. The sleep and wake-up circuit according to claim 5, characterized in that, The first switching transistor is an NPN transistor. The base of the NPN transistor is connected to the first current-limiting resistor as the control terminal. The collector of the NPN transistor is connected to the wake-up pin as the input terminal. The emitter of the NPN transistor is grounded as the output terminal.

7. The sleep and wake-up circuit according to claim 4 or 5, characterized in that, The second signal conversion unit includes a second current-limiting resistor, a second switching transistor, a second pull-up resistor, and a second pull-down resistor. One end of the second current-limiting resistor is connected to the output terminal of the first signal conversion unit, and the other end of the second current-limiting resistor is connected to the control terminal of the second switching transistor. The input terminal of the second switching transistor is connected to the operating voltage through the second pull-up resistor, and the output terminal of the second switching transistor is grounded through the second pull-down resistor. The output terminal of the second switching transistor is also connected to the general-purpose input pin.

8. The sleep and wake-up circuit according to claim 7, characterized in that, The second switching transistor is a PNP transistor. The base of the PNP transistor is connected to the second current-limiting resistor as the control terminal, the emitter of the PNP transistor is connected to the second pull-up resistor as the input terminal, and the collector of the PNP transistor is connected to the second pull-down resistor as the output terminal.

9. A circuit board, characterized in that, Includes the sleep and wake-up circuit as described in any one of claims 1-8.

10. An automotive controller for switching the operating mode of an automotive control system, characterized in that, The vehicle controller includes the circuit board as described in claim 9.

Images