A Distributed System Intelligent Processing Interface Control System

Abstract

The present invention belongs to the technical field of airborne embedded computer design for avionics systems, and specifically relates to an intelligent processing interface control system for a distributed system. The intelligent processing interface control system consists of two multi-core processor circuits (a main multi-core processor circuit and a secondary multi-core processor circuit) and an asymmetric heterogeneous dual-core coprocessor; the main processor circuit and the secondary multi-core processor circuit for intelligent interface processing and computing adopt two sets of power supply systems. The present invention realizes the high reliability of the interface control unit, and even when part of the power supply fails, some functions can still continue to work; enables the precise reconstruction of the system and the real-time execution of the key core tasks of the main and secondary processors; and also realizes the high-precision acquisition of sensor data.

Description

Technical Field

[0001] The present invention belongs to the technical field of the design of airborne embedded computers in avionics systems, and particularly relates to an intelligent processing interface control system for a distributed system. Background Art

[0002] With the development of airborne embedded systems, in a distributed intelligent multi-processor (DIMP), an intelligent processing and interface control unit (GACU) is the core unit of the system, serving as the management, control center, and computing center of the system. In the traditional design architecture, the main and slave processors share a power supply module and there is no power management function, which may lead to power failures caused by power problems. Without a coprocessor for control to complete analog quantity acquisition, discrete quantity input / output control, and the control of the bus used for system reconfiguration, the main processor is often interrupted by low-speed devices, delaying the QoS, real-time performance, and determinacy requirements of critical core tasks. The traditional fault location method for the GACU module is complex and can only be carried out in a laboratory environment by manual testing and verification for fault detection, location, determination, with low efficiency, and cannot meet the requirements of rapid location and repair. Summary of the Invention

[0003] In view of this, the present invention provides an architecture for an intelligent processing and interface control unit of a distributed system. The intelligent processing and interface control unit consists of two multi-core processor circuits (a main multi-core processor circuit and a secondary multi-core processor circuit) and an asymmetric heterogeneous dual-core coprocessor; the main processor circuit and the secondary multi-core processor circuit for intelligent interface processing and computing adopt two sets of power supply systems. The present invention realizes the high reliability of the interface control unit, enabling some functions to continue working even when part of the power supply fails; enables the precise reconfiguration of the system and the real-time execution of critical core tasks of the main and secondary processors; and also realizes the high-precision acquisition of sensor data.

[0004] In order to achieve the above technical objectives, the specific technical solutions adopted by the present invention are as follows:

[0005] An architecture for an intelligent processing and interface control unit of a distributed system,

[0006] The intelligent processing and interface control unit is the data processing center, configuration management center, and health monitoring and management center of the system, and consists of a main multi-core processor circuit, a secondary multi-core processor circuit, and an asymmetric heterogeneous dual-core coprocessor;

[0007] The interface control unit architecture includes high / low-speed interfaces and analog / digital hybrid interfaces. The main multi-core processing circuit, secondary multi-core processor circuit, and heterogeneous dual-core coprocessor of the intelligent processing and interface control unit respectively adopt independent power supply systems;

[0008] The heterogeneous dual-core coprocessor is used to decouple the functional circuits for realizing intelligent processing and interface control units; the intelligent processing and interface control unit is configured with temperature sensors, humidity sensors, and current sensors, and uses the I3C bus to collect data of each sensor;

[0009] The intelligent processing and interface control unit supports N+1 backup usage,

[0010] has health detection and management functions and writes fault information into the internal FLASH of the coprocessor, and at the same time reports the fault information through the TT-FDCAN bus, and performs primary / secondary switching and system reconstruction according to the set strategy;

[0011] The intelligent processing and interface control unit has the function of an electronic resume book.

[0012] Furthermore, the main multi-core processor circuit and the secondary multi-core processor circuit have the same structure, including a processor, a storage circuit, an FPGA circuit, a debugging circuit, and a power supply circuit;

[0013] The NVRAM and FLASH memories of the main multi-core processor circuit and the secondary multi-core processor circuit adopt the QSPI interface, and the coprocessor uses its own QSPI interface to detect faults in the BOOT memory and NVRAM memory of the main multi-core processor circuit and the secondary multi-core processor circuit; the FPGA circuit is used to complete the configuration of the processor and the adaptation and conversion between high-speed buses and low-speed buses; the FPGA has the function of online upgrade and the function of online upgrade according to the debugging Ethernet or RS422.

[0014] Furthermore, the main multi-core processor circuit and the secondary multi-core processor circuit communicate through the PCIe bus. The PCIe controllers of the main multi-core processor circuit and the secondary multi-core processor circuit are configured as RC or EP when powered on according to the RC_EP_ID number. The ID is implemented using two discrete quantities. The RC_EP_ID is connected to the FPGA, and after synchronization and debouncing in the FPGA, it is connected to the main multi-core processor circuit, and after synchronization, debouncing and inversion, it is connected to the secondary multi-core processor circuit.

[0015] Furthermore, the controller for PCIe communication between the main multi-core processor circuit and the secondary multi-core processor circuit adopts a synchronous clock, and the power supply for the clock driver uses the power after the "OR" operation of the main / secondary secondary conversion power supply.

[0016] Furthermore, the power supply system includes:

[0017] The main power conversion module, which supports two-way redundant backup input;

[0018] The secondary power conversion unit, which converts the output power of the main power conversion module into the power required inside the main multi-core processor interface circuit.

[0019] Further, the main power conversion module is a programmable intelligent power conversion module; the coprocessor monitors the output voltage and output current of the power conversion module through PMBus. When the output voltage exceeds the set threshold, the coprocessor turns off the output of the main power conversion module through PMBus. When the output current exceeds the threshold, the coprocessor turns off the output of the main power conversion module through PMBus; when the output of the main power conversion module is under-voltage or over-voltage, the power conversion module enters the under-voltage protection working mode.

[0020] Further, the intelligent processing and interface control unit architecture is built-in with temperature, humidity and current sensors, and the sensor data is collected through the I3C bus; the intelligent processing and interface control unit uses FPGA as the main controller to collect the data of the temperature sensor, humidity sensor and current sensor;

[0021] The collected data is put into the built-in dual-port 1 of the FPGA, and the ping-pong operation method is used for the collection and reading of sensor data: the collected data is first stored in the first half of the storage space of the dual-port, and then an interrupt is sent to the coprocessor. The coprocessor reads the data through the FSMC bus; the collected data is stored in the second half of the storage space of the dual-port for the second time, and the M7 core of the coprocessor is notified to read through the interrupt; the collected sensor data uses the neural network development toolkit provided by STM32Cube.AI to process and analyze the temperature, humidity and vibration sensor data;

[0022] The type of the built-in dual-port memory of the FPGA is E2PROM, and the coprocessor is connected to the E2PROM through I2C; when the intelligent processing and interface control unit works normally, the coprocessor enters the electronic resume writing mode; when in the electronic resume writing mode,

[0023] The built-in dual-port memory of the PGA stores the following data: the ID numbers, factory dates, logic version numbers and software version numbers of the processors in the main multi-core processor circuit and the secondary multi-core processor circuit.

[0024] Further, the intelligent processing and interface control unit architecture supports 11 working modes, and is characterized in that: the intelligent processing and interface control unit enters different working modes according to the external discrete quantity state and the working state of the main power conversion module, and the discrete quantity is collected by means of interruption; the working state of the main power conversion module is detected through the PMBUS bus of the coprocessor.

[0025] Further, the operating modes of the intelligent processing and interface control unit include: main power failure detection mode, clock failure detection mode, FLASH failure detection mode, NVRAM failure detection mode, airborne operation mode, online upgrade mode, ground debugging mode, emergency operation mode, degradation operation mode, electronic ID writing mode, and ground maintenance mode. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present disclosure. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0027] Figure 1 It is a block diagram of an intelligent processing and interface control unit architecture of a distributed system in a specific embodiment of the present invention;

[0028] Figure 2 It is a schematic diagram of a coprocessor controlling the main / auxiliary power conversion unit in a specific embodiment of the present invention.

[0029] Figure 3 It is a schematic diagram of a system reconstruction architecture diagram in a specific embodiment of the present invention.

[0030] Figure 4 It is a schematic diagram of the operation flow of an interrupt service processing program in a specific embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0031] The embodiments of the present disclosure will be described in detail below with reference to the drawings.

[0032] The following specific examples illustrate the implementation manners of the present disclosure. Those skilled in the art can easily understand other advantages and effects of the present disclosure from the content disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all the embodiments. The present disclosure can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present disclosure. It should be noted that, without conflict, the following embodiments and the features in the embodiments can be combined with each other. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present disclosure without creative efforts belong to the scope of protection of the present disclosure.

[0033] It should be noted that the following description relates to various aspects of embodiments within the scope of the appended claims. It will be apparent that the aspects described herein can be embodied in a wide variety of forms, and any specific structure and / or function described herein is illustrative only. Based on this disclosure, those skilled in the art will understand that one aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number of the aspects set forth herein can be used to implement a device and / or practice a method. Additionally, this device can be implemented and this method can be practiced using other structures and / or functionality in addition to one or more of the aspects set forth herein.

[0034] It should also be noted that the diagrams provided in the following embodiments merely illustrate the basic concept of the present disclosure schematically. The diagrams only show the components related to the present disclosure and are not drawn according to the number, shape, and size of the components in actual implementation. The type, quantity, and ratio of each component in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0035] In addition, in the following description, specific details are provided to facilitate a thorough understanding of the examples. However, those skilled in the art will understand that the aspects can be practiced without these specific details.

[0036] In an embodiment of the present invention, a distributed system intelligent processing and interface control unit architecture is proposed, as Figure 1 shown:

[0037] The intelligent processing and interface control unit is the data processing center, configuration management center, and health monitoring and management center of the system, and is composed of a main multi-core processor circuit, a secondary multi-core processor circuit, and an asymmetric heterogeneous dual-core coprocessor;

[0038] The interface control unit architecture includes high / low-speed interfaces and analog / digital hybrid interfaces. The main multi-core processing circuit, secondary multi-core processor circuit, and heterogeneous dual-core coprocessor of the intelligent processing and interface control unit respectively adopt independent power supply systems;

[0039] The heterogeneous dual-core coprocessor is used to decouple the functional circuits of the intelligent processing and interface control unit; the intelligent processing and interface control unit is configured with temperature sensors, humidity sensors, and current sensors, and uses the I3C bus to collect data from each sensor;

[0040] The intelligent processing and interface control unit supports N+1 backup usage,

[0041] It has a health detection and management function, writes fault information into the internal FLASH of the coprocessor, and reports the fault information through the TT-FDCAN bus, and performs master-slave switching and system reconstruction according to the set strategy; the system reconstruction architecture diagram is as Figure 3 shown;

[0042] The intelligent processing and interface control unit has an electronic resume function.

[0043] In this embodiment, the main multi-core processor circuit and the secondary multi-core processor circuit have the same structure, including a processor, a storage circuit, an FPGA circuit, a debugging circuit, and a power supply circuit;

[0044] The NVRAM and FLASH memories of the main multi-core processor circuit and the secondary multi-core processor circuit use a QSPI interface, and the coprocessor uses its own QSPI interface to detect faults in the BOOT memory and NVRAM memory of the main multi-core processor circuit and the secondary multi-core processor circuit structure; the FPGA circuit is used to complete the configuration of the processor and the adaptation and conversion of high-speed buses and low-speed buses; the FPGA has an online upgrade function and an online upgrade function according to the debugging Ethernet or RS422.

[0045] In this embodiment, the main multi-core processor circuit and the secondary multi-core processor circuit communicate through a PCIe bus. The PCIe controllers of the main multi-core processor circuit and the secondary multi-core processor circuit are configured as RC or EP when powered on according to the RC_EP_ID number. The ID is implemented using two discrete quantities. The RC_EP_ID is connected to the FPGA, synchronized and de-bounced in the FPGA, and then connected to the main multi-core processor circuit. After synchronization, de-bouncing and inversion, it is connected to the secondary multi-core processor circuit.

[0046] In this embodiment, the controller of the PCIe communication between the main multi-core processor circuit and the secondary multi-core processor circuit uses a synchronous clock, and the power supply of the clock driver uses the power supply after the "OR" operation of the main / secondary secondary conversion power supply.

[0047] In this embodiment, the power supply system includes:

[0048] A main power conversion module that supports two-way redundant backup input;

[0049] A secondary power conversion unit that converts the output power of the main power conversion module into the power required inside the main multi-core processor interface circuit.

[0050] In this embodiment, the main power conversion module is a programmable intelligent power conversion module; the coprocessor monitors the output voltage and output current of the power conversion module through PMBus. When the output voltage exceeds the set threshold, the coprocessor shuts off the output of the main power conversion module through PMBus. When the output current exceeds the threshold, the coprocessor shuts off the output of the main power conversion module through PMBus; when the output of the main power conversion module is under-voltage or over-voltage, the power conversion module enters the under-voltage protection operating mode.

[0051] In this embodiment, the intelligent processing and interface control unit architecture is built-in with temperature, humidity, and current sensors, and the sensor data is collected through the I3C bus; the intelligent processing and interface control unit uses the FPGA as the main controller to collect the data of the temperature sensor, humidity sensor, and current sensor.

[0052] The collected data is put into the built-in dual-port 1 of the FPGA, and the ping-pong operation method is used for the collection and reading of the sensor data: the collected data is first stored in the first half of the storage space of the dual-port, and then an interrupt is sent to the coprocessor, and the coprocessor reads the data through the FSMC bus; the collected data is stored in the second half of the storage space of the dual-port for the second time, and the M7 core of the coprocessor is notified to read through the interrupt; the collected sensor data uses the neural network development toolkit provided by STM32Cube.AI to process and analyze the temperature, humidity, and vibration sensor data.

[0053] The type of the built-in dual-port memory of the FPGA is E2PROM, and the coprocessor is connected to the E2PROM through I2C; when the intelligent processing and interface control unit works normally, the coprocessor enters the electronic resume writing mode; when in the electronic resume writing mode,

[0054] The built-in dual-port memory of the PGA stores the following data: the ID numbers, factory dates, logic version numbers, and software version numbers of the processors in the main multi-core processor circuit and the secondary multi-core processor circuit.

[0055] In this embodiment, the intelligent processing and interface control unit architecture supports 11 working modes, and is characterized in that: the intelligent processing and interface control unit enters different working modes according to the external discrete quantity state and the working state of the main power conversion module, and the discrete quantity is collected in an interrupt manner; the working state of the main power conversion module is detected through the PMBUS bus of the coprocessor.

[0056] In this embodiment, the working modes of the intelligent processing and interface control unit include: main power failure detection mode S0, clock failure detection mode S1, FLASH failure detection mode S2, NVRAM failure detection mode S3, airborne working mode S4, online upgrade mode S5, ground debugging mode S6, emergency working mode S7, degraded working mode S8, electronic ID card writing mode S9, and ground maintenance mode S10.

[0057] The architecture of the intelligent processing and interface control unit of the distributed system in this embodiment follows the airborne embedded system. In the distributed integrated multi-processor (DIMP), the intelligent processing and interface control unit (GACU) serves as the core unit of the system, being the management, control center, and computing center of the system.

[0058] In the traditional design architecture, the main and slave processors share a power supply module and there is no power management function, which may lead to power failures caused by power problems; there is no coprocessor for control to complete analog quantity acquisition, discrete quantity input / output control, and the control of the bus used for system reconfiguration, resulting in the main processor being frequently interrupted by low-speed devices, delaying the QoS, real-time performance, and determinacy requirements of critical core tasks; the traditional GACU module fault location method is complex and can only be carried out in a laboratory environment by means of manual testing and verification for fault troubleshooting, location, and determination, with low efficiency and unable to meet the requirements of rapid location and repair.

[0059] In the specific implementation of the present invention, the main and secondary processors of the intelligent processing and interface control unit are implemented using a quad-core processor, which integrates 4 high-performance 64-bit cores, is compatible with the ARM v8 architecture, supports 64-bit and 32-bit instructions, and supports single-precision and double-precision floating-point operation instructions. The designed working main frequency is 2.0 GHz, and the processing capacity is 4 GIPS@1 GHz.

[0060] The quad-core processor integrates a DDR4-3200 channel. The DDR controller has a 72-bit data width (64-bit data width and 8-bit ECC check width) and supports 8 banks. In the design, DDR3 chips are used, and 5 SM41J512M16M chips of Guowei Corporation are selected. Among them, 4 chips form a 4GB-capacity DDR3 SDRAM, and 1 chip is used for ECC check.

[0061] The FLASH memory of the quad-core processor uses a domestic NOR FLASH chip with a QSPI interface. Each chip has a capacity of 128 GB. Each core uses 2 FLASH chips, and each processor uses 8 NOR FLASH chips with a QSPI interface to implement functions such as storing the BOOT program, operating system, MSL, and application programs. The NVRAM memory uses a domestic SPI NVRAM chip, and each chip has a capacity of 128 KB. Each core uses 2 NVRAM chips.

[0062] The quad-core processor is connected to the TT-FC daughter card through a PCIe3.0 x 8 bus. The PCIe controller of the processor acts as an RC, and the TT-FC daughter card acts as an EP. The multi-core processor is connected to the FPGA through a PCIe3.0 x 1 bus. The FPGA is implemented using the SMQ7K325TFFG676 of Guowei Corporation, with a built-in digital signal processor DSP, block RAM, programmable logic resources, a built-in PLL and MMCM. This chip supports a maximum PCIe2.0 interface of x8 and is downward compatible with x4, x2, x1, and PCIe1.0. The main and secondary processors are connected to the FPGA through PCIe x1.

[0063] In this embodiment, to ensure the high reliability and high security of the DIMP system when the GACU fails and the GACU is the core processing and control unit of the system, the design supports an N+1 backup architecture, and further supports dynamic reconfiguration, a traditional N+1 backup architecture, or a switching circuit for "master" and "slave" backups. The redundant backup interface circuit is implemented using discrete quantities or RS485. The former (discrete quantities) can only transmit '0' and '1' information, with a simple interaction method and unable to transmit error "information codes", resulting in a simple switching algorithm and being unfavorable for the precise reconfiguration of the system. When using the RS485 bus as the redundant backup circuit, due to its "single-master" architecture, the bus utilization rate is low and it will cause a single-point failure, resulting in the failure of the GACU unit reconfiguration, and then causing the degradation or complete loss of functions of the IMP, thus affecting the execution of flight missions. The GACU in this embodiment uses the TT-FD CAN bus as the redundant backup transmission interface, which can accurately transmit the fault information code of the unit, supports a "multi-master" architecture, has no single-point failure, and only one piece of information is transmitted on the bus within the same time slot.

[0064] In this embodiment, to ensure that all or part of the functions of the intelligent processing and interface control unit can still work properly in the extreme case of power failure, the decoupling of the functional circuits is achieved. The main and secondary multi-core processor circuits of the intelligent processing and interface control unit, as well as the co-dual-core processor, are all powered externally separately. The failure of the main processor circuit will not affect the functions of the secondary processing circuit and the co-dual-core processor circuit. At the same time, the failure of the secondary processor circuit will not affect the functions of the main processor circuit and the co-processor circuit. After the failures of the main and secondary processor circuits, the co-processor circuit can still detect the failures of the unit, enabling the fault location of the unit to change from the manual mode to the automatic mode and shortening the fault location time.

[0065] In the distributed intelligent multi-processor (DIMP), a problem is presented in the integrated intelligent multi-processor, that is, the failures of the main and secondary processor circuits and the co-dual-core processor caused by the power failures of both the main processor and the slave processor due to their shared power supply. The critical core tasks of the main processor are interrupted by the non-real-time critical tasks of handling external low-speed devices, thus affecting the execution of the system's critical core tasks. Then, a unit architecture of the multi-core main processor, slave processor, and heterogeneous dual-core processor is proposed, using the co-processor to improve the reliability and testability of the intelligent interface processor unit. At the same time, the data of the temperature sensor, humidity sensor, and vibration sensor on the machine are collected using ARM Cortex M7 and M4, and the neural network development toolkit provided by STM32Cube.AI is used to process and analyze the data of the temperature, humidity, and vibration sensors, increasing the acquisition accuracy by 3.5 times.

[0066] The intelligent processing and interface control unit consists of two multi-core processor circuits (the main multi-processor circuit and the secondary multi-core processor circuit) and an asymmetric heterogeneous dual-core co-processor. The main processor circuit and the secondary multi-core processor circuit of the intelligent interface processing and computing adopt two sets of power supply systems. The power supply system of the main processing circuit includes:

[0067] The main power conversion module, whose function is to convert 12V to 5V for the main secondary power conversion unit; the secondary power conversion unit, which converts +5V into the power required inside the main multi-processor interface circuit. The power supply system of the secondary processor includes: the secondary power conversion module and the secondary power conversion unit, whose functions are the same as those of the power supply system of the main processing circuit. To ensure that the asymmetric heterogeneous dual-core co-processor can still work properly in the case of failures of both the main and secondary power supply systems, the intelligent processing and interface control unit is monitored and managed for health, and the co-processor is powered by an external separate power supply.

[0068] Among them, the multi-core processor is implemented with 8 cores of ARM V8. The multi-core processors communicate through the PCIe bus. The PCIe controllers of the "main" and "sub" processors can be configured as RC or EP according to the system RC_EP_ID number during power-on. The ID is implemented using two discrete quantities. The RC_EP_ID is connected to the FPGA, and after synchronization and debouncing in the FPGA, it is connected to the main processor, and after synchronization, debouncing and inversion, it is connected to the slave processor, making the system configuration more flexible. The PCIe controllers between processors use a synchronous clock, and the power supply of its clock driver uses the power supply after the "OR" of the main and secondary conversion power supplies of the main and sub processors. The OR circuit is implemented using a positive voltage ideal diode controller, so as to ensure that when only one of the main power supply or the sub power supply works properly, the clock driver can work normally, improving the reliability, and at the same time ensuring the requirement of the same source of the PCIe controller clocks of the main and sub processors.

[0069] The FLASH memories and NVRAM memories of the main and sub processors are implemented using the QSPI serial interface. The coprocessor can use its own QSPI interface to detect faults in the BOOT memories and NVRAM memories of the main and sub processors, thereby improving the maintainability of the intelligent processing and interface control unit, making the testability of the intelligent processing and interface control unit much higher than that of the traditional interface computer, getting rid of the way that the traditional interface computer unit needs to perform artificial measurement in the laboratory environment to locate the faults of the BOOT accessor and NVRAM memory, increasing the fault location accuracy and reducing the location time.

[0070] The coprocessor can be implemented by selecting the heterogeneous dual-core processor of STMicroelectronics, which is composed of an embedded ARM Cortex M4 (hereinafter referred to as M4) and an ARM Cortex M7 (hereinafter referred to as M7). Among them, the M4 core mainly completes:

[0071] 1) It is used for external multi-channel analog quantity acquisition. The acquisition method of multi-channel analog quantity is implemented by the DMA chain method in software, which improves the acquisition efficiency. At the same time, the temperature, humidity, and current sensors inside the unit communicate with the FPGA through the I3C bus. Among them, the FPGA acts as the Host device, and the communication rate is set to 8 MHz. After the sensor data acquisition is completed, the M4 first writes it into the dual-port built in the FPGA through the FSMC bus. The dual-port in the FPGA is set using the ISE CORE Generator. Select the attribute as Memories&storage Elements, and then select Block Memory Generator. When generating the Block MemoryGenerator, select True Dual Port RAM. Then, an interrupt is sent to the M7 by writing the FPGA interrupt register. After receiving the interrupt, the M7 reads the temperature, humidity, and current sensor data from the dual-port, and uses the neural network development toolkit provided by STM32Cube.AI to process and analyze the sensor data, which improves the acquisition accuracy by 3.5 times.

[0072] 2) Complete the acquisition and control of external discrete quantity input and output; use the co-processing AD controller to complete the acquisition of the secondary power supply inside the computer. When the acquired value of the secondary power supply exceeds the pre-set value (usually the deviation is greater than 2.5%), to prevent damage to the intelligent interface processor computer during overvoltage or undervoltage, the co-processor will turn off the secondary power conversion module, and send the overvoltage or undervoltage fault information to the main control unit through TT-FDCAN. At the same time, the fault information is written into the internal FLASH of the co-processor for subsequent rapid fault location. The clock is divided by MMCM and then enters the co-processor for acquisition by TimeCapture from core M4, and then the health monitoring of the clock is carried out. When a clock fault occurs, the fault code is written into the built-in FLASH of the co-processor, and the fault information is sent to the main control unit through TT-FDCAN for system reconstruction.

[0073] 3) Complete the TT_FD_CAN bus control and system reconstruction;

[0074] 4) The heterogeneous dual-core processor is externally equipped with E2PROM and NVRAM memories. The E2PROM is connected to the ARM Cortex M4 core of the coprocessor. Among them, the E2PROM is connected to the I2C interface, which is used as a storage interface to process the computer electronic ID card signal, including: intelligent interface processing computer ID number, factory date, main processor software version number, logic version number, coprocessor software version number. When the intelligent interface module works in the S9 state, the coprocessor enters the electronic ID card writing mode, the coprocessor reads the electronic ID card file through the Ethernet, and then writes it into the E2PROM, so that when the intelligent processing and interface control unit works in the maintenance mode, it can read information such as the ID number and factory date of the interface computer to perform quick "identity" recognition when generating the maintenance information table, without manual participation, which improves the time cost of maintenance and enables the "identity" information of the interface computer to be traced and confirmed. The NVRAM is used to record the running state of the interface processing computer when the power is off, and the communication interface with the M4 is QSPI.

[0075] 5) M4 manages the power conversion module through the PMbus, which includes the following steps:

[0076] One: PMBUS initialization:

[0077] 1: Enable the SMBUS clock port;

[0078] 2: Configure the PMBUS pins;

[0079] 3: Initialize the PMBUS to work in the SMBUS_Mode_SMBusDevice mode with a clock of 100K;

[0080] 4: Initialize the PMBUS receive and send mode to the interrupt mode.

[0081] Two: Interrupt service program initialization;

[0082] Three: The processing method is:

[0083] In the interrupt handling function, after an interrupt occurs, set the flag bit SMBUS_Get_Data_Flag to valid, and according to the read SMBusFlagStatus status bit, obtain the current state of the SMBus, obtain the data, and then in the main function, process the data generated by the SMBus according to this flag bit. After the processing is completed, set the SMBus_Get_Data_Flag flag bit to 0. See the processing function flowchart in Figure 4 .

[0084] 6) M7 performs calculations using AI algorithms, and communication between the two cores is achieved through shared memory and interrupts. The intelligent interface processing computer contains both a main power conversion module and a secondary power conversion module; the main power module can operate in the following three states:

[0085] Both 12VA and 12VB have normal inputs;

[0086] 12VA has a normal input and 12VB has an abnormal input;

[0087] 12VA has an abnormal input and 12VB has a normal input.

[0088] A heterogeneous dual-core processor serves as the processor of the coprocessor circuit. The NVRAM memory conducts fault detection to ensure the normal operation of the coprocessor in case of main power input faults or main power circuit faults. The heterogeneous dual-core processor coprocessor is powered by a separate auxiliary power supply so that in case of main power failure, the coprocessor can first perform fault detection; additionally, fault information can be reported through the TT FDCAN of the coprocessor, thereby helping the distributed system to quickly and timely perform primary / backup switching and system reconstruction.

[0089] The interface processing computer uses a programmable intelligent power conversion module, and the programmable conversion function accuracy can reach 2 mV. As Figure 2 shown, the coprocessor can monitor the output voltage and output current of the main power conversion module through PMBUS. When the output voltage VCC exceeds +5.5V or is less than +4.5V, the coprocessor shuts off the output of the main power conversion module through PMBus, thereby protecting the secondary power conversion module of the intelligent interface processing module and the backend circuit from being damaged due to overvoltage or undervoltage; when the output current exceeds 20A, the coprocessor shuts off the output of the main power conversion module through PMBus, thereby protecting the backend circuit from being burned due to overcurrent; when both 12VA and 12VB inputs are undervoltage (<6.25V), the power conversion module enters the undervoltage protection operating mode.

[0090] Schematic diagram of the coprocessor controlling the main / secondary power conversion unit is as Figure 2 shown.

[0091] The addresses of the PMBus built into the main / secondary power conversion module are set by the external pins PINR0 and PINR1 of the chip. The address of the main power conversion module is 68, and the address of the secondary power conversion module is 69.

[0092] For the intelligent processing computer to be used in a 1+3 hot backup mode in DIMP, it has further improved reliability compared to the 1+1 hot backup mode, ensuring the normal use of the IMP system in extreme cases.

[0093] Four nodes in the system are in hot standby working state. All four nodes can receive the total system data normally, but only the main control unit performs data calculation and output.

[0094] The intelligent processing and interface control unit in slot LRM1 has the highest time priority and is the default main node of the system. The TT-FDCAN time node priorities of slots LRM2, LRM3, and LRM4 decrease in turn.

[0095] After the system is powered on, the intelligent computer in slot LRM1 serves as the main control unit of the system. When the main control unit fails, slave unit 1 receives the failure message of the main control unit or the information reception times out. Slave unit 1 takes over the main control unit to complete the system control and management functions and records the total failure code of the main control unit. When slave unit 2 receives the failure information of the main control unit and slave unit 1 or the information reception times out, slave unit 2 takes over the main control unit to complete the system control and management functions and records the failure codes of the default main control unit and slave unit 1. When slave unit 3 receives the failure information of the main control unit, slave unit 1, and slave unit 2 or the information reception times out, slave unit 3 takes over the main control unit to complete the system control and management functions and records the failure information at the same time.

[0096] After power-on synchronization, the main control computer broadcasts messages to other nodes on the TT-FDCAN network at t0 + (4 n + 1) × 120ms ( n = 0, 1, 2, 3...); slave computer 1 broadcasts messages to other nodes on the TT-FDCAN network at t0 + (4 n + 2) × 120ms ( n = 0, 1, 2, 3...); slave computer 2 broadcasts messages to other nodes on the TT-FDCAN network at t0 + (4 n + 2) × 120ms ( n = 0, 1, 2, 3...); slave computer 3 broadcasts messages to other nodes on the TT-FDCAN network at t0 + (4 n + 3) × 120ms ( n= 0, 1, 2, 3...), broadcast messages to other nodes on the TT-FDCAN network; each broadcast sends four bytes. The first byte indicates the main power supply conversion and clock failure information; the second byte indicates the reset, FLASH, and NVRAM failure information; the third byte represents the power-on BIT status of the multi-core CPU; the first 2 bits of the fourth byte represent the slot where the intelligent processing and interface control unit is located, where 00 represents the main unit, 01 represents slave unit 1, 02 represents slave unit 2, 03 represents slave unit 3; the last 6 bits represent the working status of the coprocessor.

[0097] Furthermore, it greatly improves the main functions that the intelligent interface processing computer mainly completes the following functions:

[0098] The intelligent interface processing computer can enter different working modes according to the external discrete quantity status and the working status of the main power supply conversion module. There are 11 working modes (S0~S10) in total. The acquisition of discrete quantities is carried out in an interrupt manner, and the working status of the main power supply circuit is detected through the coprocessor PMBUS bus. It greatly expands the application field of this computer and is also easy to upgrade and maintain.

[0099] The definitions of S0~S10 modes are as follows: main power supply fault detection mode (S0); clock fault detection mode (S1); FLASH fault detection mode (S2); NVRAM fault detection mode (S3); airborne working mode (S4); online upgrade mode (S5); ground debugging mode (S6); emergency working mode (S7); degradation working mode (S8); electronic ID writing mode (S9); ground maintenance mode (S10). The modes are shown in Table 1.

[0100] Table 1 Definition Table of Working Modes of an Intelligent Interface Control Unit

[0101]

[0102] As described above, it is only the specific implementation manner of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed by the present disclosure should be covered by the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A distributed system intelligent processing interface control system, characterized in that: The intelligent processing interface control system is the data processing center, configuration management center, and health monitoring and management center of the system, and is composed of a main multi-core processor circuit, a secondary multi-core processor circuit, and an asymmetric heterogeneous dual-core coprocessor; The interface control unit includes high / low-speed interfaces and analog / digital hybrid interfaces. The main multi-core processing circuit, secondary multi-core processor circuit, and heterogeneous dual-core coprocessor of the intelligent processing interface control system respectively adopt independent power supply systems; The heterogeneous dual-core coprocessor is used to decouple the functional circuits of the intelligent processing interface control system; The intelligent processing interface control system is configured with temperature sensors, humidity sensors, and current sensors, and uses the I3C bus to collect data from each sensor; The intelligent processing interface control system supports N+1 backup usage, has health detection and management functions, writes fault information into the internal FLASH of the coprocessor, and at the same time reports the fault information through the TT-FDCAN bus, and performs master-slave switching and system reconstruction according to the set strategy; The intelligent processing interface control system has an electronic logbook function; Among them, the main multi-core processor circuit and the secondary multi-core processor circuit have the same structure, including a processor, a storage circuit, an FPGA circuit, a debugging circuit, and a power supply circuit; The NVRAM and FLASH memories of the main multi-core processor circuit and the secondary multi-core processor circuit adopt QSPI interfaces. The coprocessor uses its own QSPI interface to detect faults in the BOOT memory and NVRAM memory of the main multi-core processor circuit and the secondary multi-core processor circuit structure; The FPGA circuit is used to complete the configuration of the processor and the adaptation and conversion of high-speed buses and low-speed buses; The FPGA has an online upgrade function and an online upgrade function according to the debugging Ethernet or RS422; Among them, the main multi-core processor circuit and the secondary multi-core processor circuit communicate through the PCIe bus. The PCIe controllers of the main multi-core processor circuit and the secondary multi-core processor circuit are configured as RC or EP when powered on according to the RC_EP_ID number. The ID is implemented using two discrete quantities. The RC_EP_ID is connected to the FPGA, synchronized and de-jittered in the FPGA and then connected to the main multi-core processor circuit, and synchronized, de-jittered and inverted and then connected to the secondary multi-core processor circuit; Among them, the intelligent processing interface control system is built-in with temperature, humidity, and current sensors, and the sensor data is collected through the I3C bus; The intelligent processing interface control system is based on the FPGA as the main controller to collect data from the temperature sensor, humidity sensor, and current sensor; The collected data is placed in the internal dual-port 1 of the FPGA, and the ping-pong operation method is adopted for the acquisition and reading of sensor data: the collected data is first stored in the first half of the storage space of the dual-port, and then an interrupt is sent to the coprocessor. The coprocessor reads the data through the FSMC bus; the collected data is then stored in the second half of the storage space of the dual-port, and the M7 core of the coprocessor is notified to read through the interrupt; the collected sensor data uses the neural network development toolkit provided by STM32Cube.AI to process and analyze the temperature, humidity and vibration sensor data; The type of the internal dual-port memory of the FPGA is E2PROM, and the coprocessor is connected to the E2PROM through I2C; when the intelligent processing interface control system works normally, the coprocessor enters the electronic resume writing mode; when in the electronic resume writing mode, The internal dual-port memory of the PGA stores the following data: the ID numbers, factory dates, logic version numbers and software version numbers of the processors in the main multi-core processor circuit and the secondary multi-core processor circuit.

2. The intelligent processing interface control system of the distributed system according to claim 1, wherein The controller of the PCIe communication between the main multi-core processor circuit and the secondary multi-core processor circuit uses a synchronous clock, and the power supply of the clock driver uses the power supply after the "OR" operation of the main / secondary secondary conversion power supply.

3. The intelligent processing interface control system of the distributed system according to claim 2, characterized in that, The power supply system includes: A main power conversion module that supports two-way redundant backup input; A secondary power conversion unit that converts the output power of the main power conversion module into the power required inside the main multi-core processor interface circuit.

4. The intelligent processing interface control system of the distributed system according to claim 3, characterized in that The main power conversion module is a programmable intelligent power conversion module; the coprocessor monitors the output voltage and output current of the power conversion module through the PMBus. When the output voltage exceeds the set threshold, the coprocessor turns off the output of the main power conversion module through the PMBus. When the output current exceeds the threshold, the coprocessor turns off the output of the main power conversion module through the PMBus; when the output of the main power conversion module is under-voltage or over-voltage, the power conversion module enters the under-voltage protection working mode.

5. The intelligent processing interface control system of the distributed system according to claim 1, wherein The intelligent processing interface control system supports 11 working modes. The intelligent processing interface control system enters different working modes according to the external discrete quantity state and the working state of the main power conversion module. The acquisition of discrete quantities is carried out by means of interrupt; the working state of the main power conversion module is detected through the PMBUS bus of the coprocessor.

6. The intelligent processing interface control system of the distributed system according to claim 5, wherein The working modes of the intelligent processing interface control system include: main power failure detection mode, clock failure detection mode, FLASH failure detection mode, NVRAM failure detection mode, airborne working mode, online upgrade mode, ground debugging mode, emergency working mode, degradation working mode, electronic ID writing mode and ground maintenance mode.

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