Graphics processor, operating method, and machine-readable storage medium

Abstract

A graphics processor (GPU), an operating method, and a machine-readable storage medium are provided. The GPU includes a command processor circuit and a plurality of geometry pipeline circuits. The command processor circuit sequentially sends a primitive block to the geometry pipeline circuits for geometry processing. Each geometry pipeline circuit includes a geometry pipeline front-end and a geometry pipeline back-end. A first geometry pipeline front-end sends front-end processing results to a corresponding bin in a first bin group based on a first mapping relationship between the first bin group and the primitive block. A second geometry pipeline front-end sends front-end processing results to a corresponding bin in a second bin group based on a second mapping relationship between the second bin group and the primitive block. A first geometry pipeline back-end fetches the front-end processing results from the first bin in all bin groups for back-end processing. A second geometry pipeline back-end fetches the front-end processing results from the second bin in all bin groups for second back-end processing.

Description

Technical Field

[0001] This invention relates to an electronic device, and more particularly to a graphics processor, a method of operation, and a machine-readable storage medium. Background Technology

[0002] A Graphics Processing Unit (GPU), also known as a display core, video processor, display chip, or graphics chip, is a microprocessor specifically designed to perform graphics calculations on personal computers, workstations, game consoles, and some mobile devices (such as tablets and smartphones). Modern GPUs' application programming interfaces (APIs), such as DirectX, Vulkan, and OpenGL, typically send rendering tasks to the GPU hardware at the granular level of draw calls. A draw call usually includes a series of primitives, multiple rendering shaders (such as vertex shaders and pixel shaders), and the hardware descriptors and state settings required by the GPU to execute the draw call. Primitives typically make up rendered objects in a 3D scene. Primitives usually contain material properties, such as color, vertex normals, and transparency. For transparent or semi-transparent objects, different rendering orders can result in different effects in the scene, such as the overlay effect of multiple colors. Typically, rendering a complex 3D scene involves 1,000 to 10,000 drawing calls, each responsible for rendering one object. Because out-of-order rendering of primitives can cause scene errors, APIs always require primitives in drawing calls to be executed in order. A group of rendering tasks usually forms a job chain, which contains a series of drawing calls and other tasks. The API needs to guarantee the order of drawing calls within a job chain.

[0003] In graphics rendering, the GPU repeatedly reads and writes depth information corresponding to primitives from the depth buffer to determine the occlusion relationships of objects. If a rendered primitive falls behind the current depth value, it is discarded. Because the rendering resolution is too large, not all depth information can be stored in the GPU's internal depth buffer. Repeatedly reading and writing depth information to off-chip memory by the GPU results in a significant waste of bandwidth. Modern GPUs typically perform tile-based optimizations. A tile is usually small in size relative to the entire screen, such as 32x32 pixels or 64x64 pixels. Typically, the GPU renders only one or more tiles at a time, depending on the size of the on-chip storage unit. This ensures that all the corresponding depth information is stored on-chip, greatly reducing the waste of external read / write bandwidth and effectively improving energy efficiency.

[0004] To reduce rendering overhead, modern GPUs typically employ multiple passes for rendering. One approach is to divide rendering into two passes: a binning pass and a rendering pass. The binning pass primarily performs vertex shading, trivial rejection, coarse-grained depth testing, and tiling. Following the order of draw calls and primitives, the binning pass sorts primitives onto individual tiles on the screen. Primitives on each tile must be ordered according to the API submission order; out-of-order sorting is not allowed. During the rendering pass, individual tiles are handled by different processing units (streaming processing clusters, SPCs). Each SPC, depending on its internal buffer size, allows one or more tiles to be processed simultaneously. This approach improves the locality of SPCs and reduces memory access. Another implementation method is to use a single pass for rendering. After vertex shading is completed, the post-vertex data is sorted into different tiles for pixel shading.

[0005] As rendering scenes become increasingly complex, the number of streaming processing clusters (SPCs) in GPUs increases accordingly to improve rendering speed. Increasing the number of SPCs significantly enhances the concurrency of tile processing, thereby improving performance. However, the order-preserving requirements of binning passes or geometry processing pose a significant challenge to overall concurrency. Modern games typically have very complex geometry, and the order-preserving requirement makes the geometry processing stage a bottleneck, limiting the potential of the number of SPCs. One existing technique involves the GPU activating only one binning pass or geometry processing pass when a rendering scene task (job chain) is issued to the GPU, allowing the primitives of the entire job chain to be sorted onto tiles sequentially according to API order. Another existing technique allows different job chains to execute concurrently on different binning and geometry processing passes only when multiple job chains can execute concurrently. Another existing technique uses a high-throughput binning pass or geometry processing unit across the entire GPU to accelerate sequential processing. However, this technique suffers from several problems. Firstly, the entire GPU utilizes only one geometry pass to sequentially process chained tasks, making geometry job processing completely serialized. This leads to insufficient utilization of the streaming processing cluster (SPC) and fails to leverage the GPU's high concurrency. Secondly, concurrency based on task chains is impractical in real-world scenarios. The main issue is the excessively large granularity, resulting in excessive memory consumption for geometry and poor concurrency. Furthermore, the workload varies significantly between task chains, easily leading to a long-tail effect and GPU imbalance. Thirdly, high-throughput binning passes or geometry processing units result in poor GPU scalability. It is typically difficult to achieve very high throughput in geometry processing. Summary of the Invention

[0006] The present invention provides a graphics processing unit (GPU) and its operation method, as well as a machine-readable storage medium, to allow multiple primitives in a job chain to be concurrently dispatched to different geometry pipeline (GP) circuits for geometry processing at a certain granularity.

[0007] In an embodiment of the present invention, the graphics processor includes a command processor (CP) circuit and a plurality of geometry pipeline circuits. The command processor circuit is used to divide a task chain into rendering tasks for a plurality of primitive blocks (PB), wherein each primitive block includes a plurality of primitives. The geometry pipeline circuits are coupled to the command processor circuit. The command processor circuit sends the plurality of primitive blocks to the plurality of geometry pipeline circuits for geometry processing according to the order of the plurality of primitive blocks in the task chain. Each of the plurality of geometry pipeline circuits includes a geometry pipeline front end and a geometry pipeline back end. The plurality of geometry pipeline circuits includes a first geometry pipeline circuit and a second geometry pipeline circuit. The first geometry pipeline front end of the first geometry pipeline circuit establishes a first mapping relationship between a first bucket group of the first geometry pipeline circuit and a plurality of tiles on the screen. The first geometry pipeline front end performs first front-end processing on the first primitive block sent to the first geometry pipeline circuit from the plurality of primitive blocks. The first geometric pipeline front-end, based on a first mapping relationship, sends the front-end processing result of the first front-end processing to the corresponding bucket in the first bucket group. The second geometric pipeline front-end of the second geometric pipeline circuit constructs a second mapping relationship between the second bucket group of the second geometric pipeline circuit and the plurality of primitive blocks. The second geometric pipeline front-end performs second front-end processing on the second primitive blocks sent to the second geometric pipeline circuit by the command processor circuit in the plurality of primitive blocks. The second geometric pipeline front-end, based on the second mapping relationship, sends the front-end processing result of the second front-end processing to the corresponding bucket in the second bucket group. The first geometric pipeline back-end of the first geometric pipeline circuit retrieves the front-end processing result from the first bucket in the first bucket group and the first bucket in the second bucket group for back-end processing. The second geometric pipeline back-end of the second geometric pipeline circuit retrieves the front-end processing result from the second bucket in the first bucket group and the second bucket in the second bucket group for second back-end processing.

[0008] In an embodiment of the present invention, the operation method includes: dividing a task chain into rendering tasks for multiple primitive blocks, wherein each primitive block includes multiple primitives; and sending the multiple primitive blocks to multiple geometry pipeline circuits for geometric processing according to the order of the multiple primitive blocks in the task chain. Each of the multiple geometry pipeline circuits includes a geometry pipeline front-end and a geometry pipeline back-end, and the multiple geometry pipeline circuits include a first geometry pipeline circuit and a second geometry pipeline circuit. The geometric processing includes: constructing a first mapping relationship between a first group of buckets of the first geometry pipeline circuit and multiple primitive blocks on the screen by the first geometry pipeline front-end; performing first front-end processing on the first primitive blocks sent to the first geometry pipeline circuit by the command processor circuit in the multiple primitive blocks; sending the front-end processing result of the first front-end processing to the corresponding bucket in the first bucket group based on the first mapping relationship; constructing a second mapping relationship between a second group of buckets of the second geometry pipeline circuit and the multiple primitive blocks by the second geometry pipeline front-end; and performing first front-end processing on the first primitive blocks sent to the first geometry pipeline circuit by the command processor circuit in the multiple primitive blocks; and performing second front-end processing on the first primitive blocks sent to the first geometry pipeline circuit by the second geometry pipeline front-end. The pipeline front end performs second front-end processing on the second primitive block sent by the command processor circuit to the second geometric pipeline circuit in the plurality of primitive blocks; the second geometric pipeline front end sends the front-end processing result of the second front-end processing to the corresponding bucket in the second bucket group based on the second mapping relationship; the first geometric pipeline back end of the first geometric pipeline circuit retrieves the front-end processing result from the first bucket in the first bucket group and the first bucket in the second bucket group for back-end processing; and the second geometric pipeline back end of the second geometric pipeline circuit retrieves the front-end processing result from the second bucket in the first bucket group and the second bucket in the second bucket group for second back-end processing.

[0009] In an embodiment of the invention, the machine-readable storage medium is used to store non-transitory machine-readable instructions. When the non-transitory machine-readable instructions are executed by a computer, the operation method of the graphics processor can be implemented.

[0010] Based on the above, each geometry pipeline circuit in the GPU has its own bucket group. Based on the current primitive's position on the screen, each geometry pipeline front-end sends its front-end processing result for the current primitive to the corresponding bucket in its own bucket group. Each geometry pipeline front-end sends the request corresponding to the primitive block's identifier (ID) to the corresponding geometry pipeline back-end in all geometry pipeline back-ends. Each geometry pipeline back-end specifically processes one corresponding bucket from all bucket groups. For example, the first geometry pipeline back-end retrieves the front-end processing result from the first bucket in all bucket groups for back-end processing, and the second geometry pipeline back-end retrieves the front-end processing result from the second bucket in all bucket groups for second back-end processing. Therefore, the GPU can concurrently distribute primitive blocks (multiple primitives) to different geometry pipeline circuits for geometry processing at a certain granularity, while ensuring that primitives on the same block are kept in order. Attached Figure Description

[0011] Figure 1 This is a schematic diagram of a circuit block of a graphics processing unit (GPU) according to an embodiment of the present invention.

[0012] Figure 2 This is a schematic diagram illustrating, according to an embodiment of the present invention, that a rendered screen is divided into multiple tiles.

[0013] Figure 3 This is a circuit block diagram of a geometric pipeline circuit drawn according to an embodiment of the present invention.

[0014] Figure 4 This is a flowchart illustrating an operation method of a graphics processor according to an embodiment of the present invention.

[0015] Figure 5 This is a schematic diagram illustrating the mapping relationship between bucket groups and blocks according to an embodiment of the present invention.

[0016] Figure 6 This is a schematic diagram illustrating a scenario in which the front-end processing result is sent to the corresponding bucket in memory, according to an embodiment of the present invention.

[0017] Explanation of reference numerals in the attached figures

[0018] 100: Graphics Processing Unit (GPU)

[0019] B0, B1, B2, B3: Buckets

[0020] BB0, BB1, BB2, BB3: Bucket Group

[0021] BG0: Bucket Generation Module

[0022] CP1: Command Processor Circuit

[0023] CZ0: Coarse-grained depth testing module

[0024] GP1_0, GP1_1, GP1_2, GP1_3, GP1_N: Geometric pipeline circuit

[0025] GPBE0, GPBE1, GPBE2, GPBE3: Rear end of geometric pipeline

[0026] GPFE0, GPFE1, GPFE2, GPFE3: Geometric pipeline front end

[0027] MEM1: Memory

[0028] S410, S420: Steps

[0029] SPC1_0, SPC1_4, SPC1_N*4: Stream processor cluster circuit

[0030] T0, T1, T2, T3: Primitives

[0031] TIL0: Tiling Module

[0032] TILE0, TILE1, TILE2, TILE3, TILE4, TILE5, TILE6, TILE7, TILE8, TILE9, TILE10, TILE11, TILE12, TILE13, TILE14, TILE15: Tiles

[0033] VPT0: Viewport Transformation Module

[0034] VTG0: Shading Module Detailed Implementation

[0035] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same component reference numerals are used in the drawings and description to denote the same or similar parts.

[0036] The term "coupled (or connected)" as used throughout this specification (including the claims) may refer to any direct or indirect means of connection. For example, if the text describes a first device coupled (or connected) to a second device, it should be interpreted as the first device being directly connected to the second device, or the first device being indirectly connected to the second device through other devices or some means of connection. The terms "first," "second," etc., used throughout this specification (including the claims) are used to name components, and are not intended to limit the upper or lower limit of the number of components, nor to limit the order of components. Furthermore, wherever possible, components / components / steps using the same reference numerals in the drawings and embodiments represent the same or similar parts. Components / components / steps using the same reference numerals or the same terms in different embodiments may be referred to mutually in the relevant descriptions.

[0037] GPU rendering tasks typically include draw calls, Direct Memory Access (DMA), synchronization, and cache flushing. Drivers usually chain multiple draw calls together to form a job chain. Each draw call is responsible for rendering one object in the scene. Objects are typically composed of a set of primitives, each usually consisting of three vertices, each containing its corresponding attributes. Objects often have mutual occlusion relationships. When the object's material is semi-transparent or transparent, the rendering order must be strictly maintained to achieve the desired effect when rendering effects are superimposed on mutually occluding objects. The following embodiments illustrate methods and hardware architectures for multi-geometry processing unit concurrency and bucket sorting to allow primitives within a draw call in a job chain to be fully concurrent at a certain granularity across different geometry processing units, while ensuring the order of primitives on tiles. Simultaneously, it maintains good hardware scalability. The following embodiments will use multiple geometry pipeline (GP) circuits as examples of geometry processing units.

[0038] Figure 1 This is a schematic diagram of a circuit block of a graphics processing unit (GPU) 100 according to an embodiment of the present invention. Figure 1The GPU 100 shown includes a command processor (CP) circuit CP1 and multiple geometry pipeline circuits (e.g., Figure 1 The circuits shown are GP1_0, GP1_1, and GP1_N, and multiple streaming processor clusters (SPCs) (e.g., Figure 1 The diagram shows SPC1_0, SPC1_4, and SPC1_N*4, as well as memory MEM1. Memory MEM1 is a broad concept that can include various levels of on-chip memory, such as cache, high-bandwidth memory (HBM), and double-data-rate (DDR) memory. The number of geometry pipeline circuits and the number of stream processor cluster circuits can be determined according to the actual design. The command processor circuit, geometry pipeline circuit, stream processor cluster circuit, memory, and other subsystems can be connected in any interconnection manner to transmit information. For example, one implementation of interconnection between the subsystems is a network on chip (NOC). Depending on different design requirements, in some embodiments, the above-mentioned command processor circuit, geometry pipeline circuit, and / or stream processor cluster circuit can be implemented as hardware circuits. In other embodiments, the command processor circuit, geometry pipeline circuit, and / or stream processor cluster circuit can be implemented as firmware, software, or a combination of the two. In some other embodiments, the command processor circuitry, geometry pipeline circuitry, and / or stream processor cluster circuitry may be implemented as a combination of hardware, firmware, and software.

[0039] In hardware terms, the aforementioned command processor circuit, geometry pipeline circuit, and / or stream processor cluster circuit can be implemented as logic circuits on integrated circuits. For example, the functions of the command processor circuit, geometry pipeline circuit, and / or stream processor cluster circuit can be implemented in various logic blocks, modules, and circuits within one or more controllers, microcontrollers, microprocessors, application-specific integrated circuits (ASICs), digital signal processors (DSPs), field-programmable gate arrays (FPGAs), central processing units (CPUs), and / or other processing units. The functions of the command processor circuit, geometry pipeline circuit, and / or stream processor cluster circuit can be implemented as hardware circuits, such as various logic blocks, modules, and circuits within integrated circuits, using hardware description languages ​​(e.g., Verilog HDL or VHDL) or other suitable programming languages.

[0040] In software and / or firmware form, the functions of the aforementioned command processor circuit, geometry pipeline circuit, and / or stream processor cluster circuit can be implemented as programming codes. For example, the command processor circuit, geometry pipeline circuit, and / or stream processor cluster circuit can be implemented using general programming languages ​​(such as C, C++, or assembly language) or other suitable programming languages. The programming code can be recorded / stored in a non-transitory machine-readable storage medium. In some embodiments, the machine-readable storage medium includes, for example, semiconductor memory and / or storage devices. The semiconductor memory includes memory cards, read-only memory (ROM), flash memory, programmable logic circuits, or other semiconductor memory. The storage device includes tape, disk, hard disk drive (HDD), solid-state drive (SSD), or other storage devices. Electronic devices (e.g., CPUs, controllers, microcontrollers, or microprocessors) can read and execute the programming code from the machine-readable storage medium to implement the functions of command processor circuits, geometry pipeline circuits, and / or stream processor cluster circuits. Alternatively, the programming code can be provided to the electronic device via any transmission medium (e.g., communication networks or broadcast radio waves). The communication network is, for example, the Internet, wired communication networks, wireless communication networks, or other communication media.

[0041] The primary function of the command processor circuit CP1 is to issue task commands to other subsystems within the GPU 100 for execution. Depending on the specific design, CP1 may also include global synchronization, task scheduling, and / or other functions. Geometry pipeline circuits GP1_0 to GP1_N are coupled to CP1. CP1 can divide a job chain into rendering tasks for multiple primitive blocks (PBs), where each primitive block includes multiple primitives. CP1 sends these primitive blocks to GP1_0 to GP1_N for geometry processing according to their order in the job chain. The number of primitives in each primitive block can be determined based on the specific design. In some embodiments, each primitive block includes a draw call. CP1 sends tasks to GP1_0 to GP1_N in parallel, with the draw call as the granularity. For example, the first drawing call is sent to geometry pipeline circuit GP1_0, and the second drawing call is sent to geometry pipeline circuit GP1_1. This continues until the (N+1)th drawing call is sent to geometry pipeline circuit GP1_N. In other embodiments, each primitive block has the same number of primitives. The command processor circuit CP1 divides the task into primitive blocks at a granularity based on the number of primitives, sending tasks in parallel to geometry pipeline circuits GP1_0 through GP1_N. For example, a task chain or drawing call can be divided into multiple primitive blocks at a granularity of 512 primitives (or another number of primitives, determined by the actual design). The first primitive block is sent to geometry pipeline circuit GP1_0, and the second primitive block is sent to geometry pipeline circuit GP1_1. This continues until the (N+1)th primitive block is sent to geometry pipeline circuit GP1_N.

[0042] The geometry pipeline circuits GP1_0 to GP1_N are responsible for geometry-related task processing, such as the task constructors for vertex shading, geometry shading, and tessellation shading tasks. GP1_0 to GP1_N also generate geometry processing results for the pixel pipeline (not shown in the diagram) in the stream processor cluster circuit. Each stream processor cluster circuit mainly includes an arithmetic logic unit (ALU), special function units, load-store units, and tensor cores (not shown in the diagram). The command processor circuit CP1 issues task commands to other subsystems in the GPU 100. Typically, a draw call includes both geometry processing tasks and pixel processing tasks. Command processor circuit CP1 sends geometry processing tasks to geometry pipeline circuits GP1_0 to GP1_N for execution. Then, geometry pipeline circuits GP1_0 to GP1_N generate pixel processing tasks according to tile partitioning and send them to the stream processor cluster circuit (e.g., ...). Figure 1 (SPC1_0, SPC1_4, and SPC1_N*4 are shown). The stream processor cluster circuit performs pixel processing at the granularity of one or more tiles.

[0043] Figure 2 This diagram illustrates, according to an embodiment of the present invention, a rendered screen divided into multiple tiles. Depending on the actual design, each tile can be 32x32 pixels, 64x64 pixels, or other numbers of pixels. Typically, the size of the tiles can be set according to the architecture; larger or smaller tiles are both feasible implementations. Figure 2 In the illustrated embodiment, a screen is divided into 4x4 tiles TILE0, TILE1, TILE2, TILE3, TILE4, TILE5, TILE6, TILE7, TILE8, TILE9, TILE10, TILE11, TILE12, TILE13, TILE14, and TILE15. Primitives are ultimately rendered onto the screen. Primitives can fall within a single tile or span multiple tiles. Figure 2The diagram illustrates primitives T0, T1, T2, and T3. Primitive T0 covers tiles TILE2, TILE3, TILE8, and TILE9; primitive T1 covers tiles TILE3 and TILE9; primitive T2 covers tile TILE0; and primitive T3 covers tile TILE1. Figure 2 As shown in the embodiment, if different primitives fall on different blocks and these primitives do not overlap (e.g., primitive T2 and primitive T3), the execution order of the geometry pipeline circuits GP1_0 to GP1_N on these primitives has no impact on the final rendering result. What truly needs to be sorted are the primitives that fall on the same block (e.g., primitive T0 and primitive T1).

[0044] Figure 3 This is a circuit block diagram of geometric pipeline circuits GP1_0 to GP1_3, drawn according to an embodiment of the present invention. Figure 3 The geometric pipeline circuits GP1_0 to GP1_3 shown can be used as Figure 1 This is one of many embodiments of the geometry pipeline circuits GP1_0 to GP1_N. The command processor circuit CP1 sends a draw call or a primitive block (PB) to a geometry pipeline circuit (one of GP1_0 to GP1_3) for geometry processing. Figure 3 In the illustrated embodiment, each of the geometry pipeline circuits GP1_0 to GP1_3 includes a geometry pipeline front end and a geometry pipeline back end. For example, geometry pipeline circuit GP1_0 includes a geometry pipeline front end GPFE0 and a geometry pipeline back end GPBE0; geometry pipeline circuit GP1_1 includes a geometry pipeline front end GPFE1 and a geometry pipeline back end GPBE1; geometry pipeline circuit GP1_2 includes a geometry pipeline front end GPFE2 and a geometry pipeline back end GPBE2; and geometry pipeline circuit GP1_3 includes a geometry pipeline front end GPFE3 and a geometry pipeline back end GPBE3. The terms "front end" and "back end" are clearer from a functional perspective, but other names can also be used in practice.

[0045] Figure 4 This is a schematic flowchart illustrating an operation method of a graphics processor according to an embodiment of the present invention. In some embodiments, Figure 4 The operation method of the graphics processor shown can be implemented in firmware or software (i.e., program). For example, Figure 4The operations of the graphics processor operation method shown can be implemented as non-transitory machine-readable instructions (programming code or program), and these non-transitory machine-readable instructions can be stored in a machine-readable storage medium. When the non-transitory machine-readable instructions are executed by a computer, they can be implemented... Figure 4 The diagram illustrates the operation method of the graphics processor. In other embodiments, [the diagram shows the operation method of the graphics processor]. Figure 4 The operation method of the graphics processor shown can be implemented in hardware, for example, implemented in... Figure 1 The GPU shown is 100.

[0046] Please refer to Figure 3 and Figure 4 In step S410, the command processor circuit CP1 divides a job chain into rendering tasks for multiple primitive blocks (e.g., drawing calls), where each primitive block includes multiple primitives. In step S420, the command processor circuit CP1 sends the primitive blocks to the geometry pipeline circuits GP1_0 to GP1_3 for geometry processing according to the order of the multiple primitive blocks in the job chain. For example, the first primitive block is sent to geometry pipeline circuit GP1_0, the second primitive block to geometry pipeline circuit GP1_1, the third primitive block to geometry pipeline circuit GP1_2, and the fourth primitive block to geometry pipeline circuit GP1_3. The geometry processing includes the following operations.

[0047] Please refer to Figure 3 The front-end GPFE0 of geometry pipeline circuit GP1_0 establishes the mapping relationship between the bucket group BB0 of geometry pipeline circuit GP1_0 and multiple tiles on the screen; the front-end GPFE1 of geometry pipeline circuit GP1_1 establishes the mapping relationship between the bucket group BB1 of geometry pipeline circuit GP1_1 and multiple tiles on the screen; the front-end GPFE0 of geometry pipeline circuit GP1_2 establishes the mapping relationship between the bucket group BB2 of geometry pipeline circuit GP1_2 and multiple tiles on the screen; and the front-end GPFE3 of geometry pipeline circuit GP1_3 establishes the mapping relationship between the bucket group BB3 of geometry pipeline circuit GP1_3 and multiple tiles on the screen. For example (but not limited to this), based on the case of four concurrent geometry pipeline circuits... Figure 3 The illustrated embodiment assumes a bucket group includes a first bucket B0, a second bucket B1, a third bucket B2, and a fourth bucket B3. In actual design, the number of buckets in a bucket group can be any other number that matches the architecture.

[0048] Figure 5 This is a schematic diagram illustrating the mapping relationship between bucket groups and blocks according to an embodiment of the present invention. Figure 5 Continue Figure 2 The screen example shown is a 4x4 grid of tiles TILE0 to TILE15. Bucket B0 corresponds to tiles TILE0, TILE4, TILE8, and TILE12; bucket B1 corresponds to tiles TILE1, TILE5, TILE9, and TILE13; bucket B2 corresponds to tiles TILE2, TILE6, TILE10, and TILE14; and bucket B3 corresponds to tiles TILE3, TILE7, TILE11, and TILE15. Based on the fact that non-overlapping primitives in different tiles can be processed concurrently, bucket groups are used to sort the primitives processed by multiple geometry pipeline circuits. A bucket group can be viewed as a memory container storing primitive information. The number of buckets in a bucket group is always related to the number of concurrent geometry pipeline circuits. For example, assuming four geometry pipeline circuits are running concurrently, the software can define four buckets B0 to B3 in memory. Bucket groups can exist in the form of a ring buffer or other formats. Figure 5 This demonstrates the mapping relationship between bucket groups and screen tiles. Figure 5 In the illustrated embodiment, the bucket is the same size as the tile.

[0049] Please refer to Figure 3 and Figure 5 After receiving a task, the geometry pipeline front-ends GPFE0 to GPFE3 of each geometry pipeline circuit GP1_0 to GP1_3 can concurrently execute vertex shading, tessellation shading, and geometry shading corresponding to their respective primitives. For example, geometry pipeline front-end GPFE0 performs the first front-end processing on the primitive block sent to geometry pipeline circuit GP1_0 by command processor circuit CP1. Geometry pipeline front-end GPFE0 sends the front-end processing result to the corresponding bucket in bucket group BB0 based on the mapping relationship between bucket group and block. Figure 2Taking primitive T2 as an example, the geometry pipeline front-end GPFE0 performs front-end processing on primitive T2 sent by command processor circuit CP1 to geometry pipeline circuit GP1_0. Based on the mapping relationship between bucket groups B0~B3 and blocks TILE0~TILE15, geometry pipeline front-end GPFE0 sends the front-end processing result of primitive T2 to the first bucket B0 in bucket group BB0. Similarly, geometry pipeline front-end GPFE1 performs second front-end processing on primitive blocks sent by command processor circuit CP1 to geometry pipeline circuit GP1_1, and then sends the front-end processing result to the corresponding bucket in bucket group BB1 based on the mapping relationship. Geometry pipeline front-end GPFE2 performs third front-end processing on primitive blocks sent by command processor circuit CP1 to geometry pipeline circuit GP1_2, and then sends the front-end processing result to the corresponding bucket in bucket group BB2 based on the mapping relationship. Geometry pipeline front-end GPFE3 performs fourth front-end processing on primitive blocks sent by command processor circuit CP1 to geometry pipeline circuit GP1_3, and then sends the front-end processing result to the corresponding bucket in bucket group BB3 based on the mapping relationship.

[0050] The first front-end processing of the geometry pipeline front-end GPFE0 can include constructing shading tasks, viewport transformation, and coverage testing. The geometry pipeline front-end GPFE0 can construct shading tasks and send them to the streaming processor cluster circuitry of the GPU 100. Figure 3 Not displayed, for example Figure 1The shading task is executed using SPC1_0, SPC1_4, or SPC1_N*4 as shown. Based on the actual design, the shading task includes task constructors for vertex shaders, tessellation shaders, and geometry shaders. The geometry pipeline front-end GPFE0 can retrieve post-vertex information for further viewport transformation. Post-vertex information refers to vertex information after processing by the shaders (such as vertex shaders or other shaders) in the stream processor cluster circuit, typically including position information and other vertex attributes (such as normal vectors, texture coordinates, etc.). Based on the actual design, the viewport transformation typically includes one or more primitive culling circuits, such as backface culling, small triangle culling, etc. Primitives that meet multiple culling conditions will not be sent to the geometry processor back-end. Using the coordinates of surviving primitives after viewport transformation, the geometry pipeline front-end GPFE0 can perform coverage tests on the surviving primitives and the multiple blocks, and send the surviving primitives as the front-end processing result to the corresponding bucket in the bucket group BB0. Other geometry pipeline front-ends GPFE1 to GPFE3 can be described by analogy to the relevant description of geometry pipeline front-end GPFE0, and therefore will not be elaborated further.

[0051] As an example, the geometry pipeline front-end GPFE0 includes the shading module VTG0, the viewport transformation module VPT0, and the bucket generation module BG0. The shading module VTG0 takes the vertices corresponding to the primitives in the received drawing calls (or primitive blocks) and sends them to the stream processor cluster circuitry (...). Figure 3 Not displayed, for example Figure 1 The SPC1_0, SPC1_4, or SPC1_N*4 shown are executed. The viewport transformation module VPT0 sequentially reads the post-vertex information corresponding to the drawing call (or primitive block) from memory MEM1 for further standard graphics operations such as occlusion culling and perspective transformation. The bucket generation module BG0 performs a coverage test between the surviving primitives and multiple tiles on the screen based on the coordinates of the surviving primitives processed by VPT0.

[0052] The geometry pipeline back-end GPBE0 of geometry pipeline circuit GP1_0 retrieves the front-end processing results from the first bucket B1 of all bucket groups BB0 to BB3 for first back-end processing. The first back-end processing of geometry pipeline back-end GPBE0 includes: retrieving the front-end processing results from the first bucket B1 of all bucket groups BB0 to BB3 for coarse-grained depth test rejection; and performing tileization to place the primitives rejected by the coarse-grained depth test into the corresponding tile list. The geometry pipeline back-end GPBE1 of geometry pipeline circuit GP1_1 retrieves the front-end processing results from the second bucket B1 of all bucket groups BB0 to BB3 for second back-end processing. The geometry pipeline back-end GPBE2 of geometry pipeline circuit GP1_2 retrieves the front-end processing results from the third bucket B2 of all bucket groups BB0 to BB3 for third back-end processing. The geometry pipeline back-end GPBE3 of geometry pipeline circuit GP1_3 retrieves the front-end processing results from the fourth bucket B3 of all bucket groups BB0 to BB3 for fourth back-end processing. The back-end processing of other geometries GPBE1 to GPBE3 can be referred to the relevant description of the first back-end processing of geometries GPBE0 and deduced by analogy, so it will not be repeated here.

[0053] As an example, the geometry pipeline backend GPBE0 includes a coarse-grained depth test module CZ0 and a tiling module TIL0. In GPBE0, the coarse-grained depth test module CZ0 performs coarse-grained depth test culling on primitives. The tiling module TIL0 places primitives that pass the coarse-grained depth test module CZ0 into the corresponding tile list, which is used as input for subsequent pixel processing. The geometry pipeline frontends GPFE1 to GPFE3 of other geometry pipeline circuits GP1_1 to GP1_3 can be deduced by referring to the relevant description of the geometry pipeline frontend GPFE0, and the geometry pipeline backends GPBE1 to GPBE3 of other geometry pipeline circuits GP1_1 to GP1_3 can also be deduced by referring to the relevant description of the geometry pipeline backend GPBE0, so they will not be elaborated further.

[0054] The key point here is that the results of each geometry pipeline circuit GP1_0 to GP1_3 generate corresponding bucket groups BB0 to BB3 based on the bucket generation in the geometry pipeline front-ends GPFE0 to GPFE3 (e.g., bucket generation module BG0). The geometry pipeline front-ends GPFE0 to GPFE3 then send the front-end processing results to the corresponding buckets in memory MEM1. In one implementation, each geometry pipeline back-end GPBE0 to GPBE3 is responsible for processing only one bucket. For example, the back-end GPBE0 of the geometry pipeline circuit GP1_0 is only responsible for processing the task of bucket B0 in all bucket groups BB0 to BB3; the back-end GPBE1 of the geometry pipeline circuit GP1_1 is only responsible for processing the task of bucket B1 in all bucket groups BB0 to BB3; the back-end GPBE2 of the geometry pipeline circuit GP1_2 is only responsible for processing the task of bucket B2 in all bucket groups BB0 to BB3; and the back-end GPBE3 of the geometry pipeline circuit GP1_3 is only responsible for processing the task of bucket B3 in all bucket groups BB0 to BB3. In this way, it is only necessary to read the bucket data corresponding to the geometry pipeline according to the identifier (ID) of the primitive block (PB), which can always guarantee the order on a tile. Another implementation is to perform bucket sorting only for the coarse-grained depth test (coarseZ test), and output the tiled data after synchronizing with the coarse-grained depth test. Any of the geometry pipeline front-ends GPFE0 to GPFE3 can send a request corresponding to the identifier (ID) of a primitive block (PB) to one of the corresponding geometry pipeline back-ends GPBE0 to GPBE3. Therefore, the geometry pipeline front-ends GPFE0 to GPFE3 and the geometry pipeline back-ends GPBE0 to GPBE3 are decoupled.

[0055] For example, Figure 6 This is a schematic diagram illustrating a scenario in which the front-end processing result is sent to the corresponding bucket in memory MEM1 according to an embodiment of the present invention. Figure 6 Continue Figure 3 The example shown is a bucket group BB0 to BB3. Please refer to it. Figure 3 and Figure 6If all primitive block data corresponding to geometry pipeline circuit GP1_0 belongs to bucket 0, then geometry pipeline front-end GPFE0 will write all the front-end processing results of the primitives to bucket B0 of bucket group BB0. If all primitive block data corresponding to geometry pipeline circuit GP1_1 belongs to bucket B0, then geometry pipeline front-end GPFE1 will write all the front-end processing results of the primitives to bucket B0 of bucket group BB1. If the primitive block data corresponding to geometry pipeline circuit GP1_2 belongs to buckets B0 and B3, then geometry pipeline front-end GPFE2 will write the front-end processing results of the primitives to buckets B0 and B2 of bucket group BB2. If all primitive block data corresponding to geometry pipeline circuit GP1_3 belongs to bucket B0, then geometry pipeline front-end GPFE3 will write all the front-end processing results of the primitives to bucket B0 of bucket group BB3. Since all four geometry pipeline circuits GP1_0 to GP1_3 write data to bucket B0, the corresponding primitives may overwrite the same tiles. At this point, the geometry pipeline backend GPBE0 reads data from bucket B0 of bucket group BB0 first, then from bucket B0 of bucket group BB1, then from bucket B0 of bucket group BB2, and finally from bucket B0 of bucket group BB3, based on the primitive block (PB) identifier (ID). The geometry pipeline backend GPBE2 handles bucket B2. Based on the primitive block identifier, GPBE2 first reads data from bucket B2 of bucket group BB2. Geometry pipeline backends GPBE1 and GPBE3 do not read data because they do not have corresponding primitive block requests. In this way, the geometry pipeline frontends GPFE0 to GPFE3 can always concurrently complete vertex shading, tessellation shading, and geometry shading for each primitive block. The geometry pipeline backends GPBE0 to GPBE3 then maintain the order of requests with the same bucket identifier through buckets B0 to B3. This ensures that primitives falling on the same tile are always rendered in sequence.

[0056] In summary, each geometry pipeline circuit GP1_0 to GP1_3 of the GPU 100 has its own bucket group. For example, geometry pipeline circuit GP1_0 has bucket group BB0, geometry pipeline circuit GP1_1 has bucket group BB1, geometry pipeline circuit GP1_2 has bucket group BB2, and geometry pipeline circuit GP1_3 has bucket group BB3. Based on the current primitive's position on the screen, the front-end of any geometry pipeline circuit GPFE0 to GPFE3 sends the front-end processing result of its current primitive to the corresponding bucket in its own bucket group. Each front-end of any geometry pipeline circuit GPFE0 to GPFE3 sends the request corresponding to the primitive block (PB) identifier (ID) to the corresponding back-end of all geometry pipeline circuits GPBE0 to GPBE3. Each back-end of any geometry pipeline circuit GPBE0 to GPBE3 specifically processes one corresponding bucket from all bucket groups BB0 to BB3. For example, the geometry pipeline backend GPBE0 retrieves the front-end processing results from the first bucket B0 of all buckets BB0 to BB3 for back-end processing; the geometry pipeline backend GPBE1 retrieves the front-end processing results from the second bucket B1 of all buckets BB0 to BB3 for back-end processing; the geometry pipeline backend GPBE2 retrieves the front-end processing results from the third bucket B2 of all buckets BB0 to BB3 for back-end processing; and the geometry pipeline backend GPBE3 retrieves the front-end processing results from the fourth bucket B3 of all buckets BB0 to BB3 for back-end processing. Therefore, GPU 100 can concurrently distribute primitive blocks (multiple primitives) to different geometry pipeline circuits GP1_0 to GP1_3 for geometry processing at a certain granularity, while ensuring that primitives on the same block are kept in order.

[0057] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A graphics processor, characterized in that, The graphics processor includes: Command processor circuitry for dividing a task chain into rendering tasks for multiple primitive blocks, where each primitive block comprises multiple primitives; and Multiple geometry pipeline circuits are coupled to the command processor circuit, wherein the command processor circuit sends the multiple primitive blocks to the multiple geometry pipeline circuits for geometry processing according to the order of the multiple primitive blocks in the task chain. Each of the multiple geometry pipeline circuits includes a geometry pipeline front end and a geometry pipeline back end, and the multiple geometry pipeline circuits include a first geometry pipeline circuit and a second geometry pipeline circuit. The first geometric pipeline front-end of the first geometric pipeline circuit establishes a first mapping relationship between the first bucket group of the first geometric pipeline circuit and multiple tiles on the screen. The first geometric pipeline front-end performs first front-end processing on the first primitive blocks sent by the command processor circuit to the first geometric pipeline circuit among the multiple primitive blocks. Based on the first mapping relationship, the first geometric pipeline front-end sends the front-end processing result of the first front-end processing to the corresponding bucket in the first bucket group. The second geometric pipeline front-end of the second geometric pipeline circuit constructs a second mapping relationship between the second bucket group of the second geometric pipeline circuit and the plurality of primitive blocks. The second geometric pipeline front-end performs second front-end processing on the second primitive blocks sent to the second geometric pipeline circuit by the command processor circuit in the plurality of primitive blocks. Based on the second mapping relationship, the second geometric pipeline front-end sends the front-end processing result of the second front-end processing to the corresponding bucket in the second bucket group. The first geometric pipeline back end of the first geometric pipeline circuit takes the front-end processing results from the first bucket in the first bucket group and the first bucket in the second bucket group to perform first back-end processing, and The second geometric pipeline back end of the second geometric pipeline circuit takes the front-end processing result from the second bucket in the first bucket group and the second bucket in the second bucket group to perform the second back-end processing; The first front-end processing includes: Construct a shading task and send the shading task to the stream processor cluster circuit of the graphics processor for execution; Retrieve the vertex information processed by the stream processor cluster circuitry for further viewport transformation; and Using the coordinates of the surviving primitives after the viewport transformation, a coverage test is performed on the surviving primitives and the multiple blocks, so that the surviving primitives are sent as the front-end processing result to the corresponding bucket in the first bucket group.

2. The graphics processor according to claim 1, characterized in that, Each of the plurality of primitive blocks includes a drawing call, and the drawing call is responsible for rendering an object.

3. The graphics processor according to claim 1, characterized in that, The shading tasks include task constructor tasks for vertex shaders, tessellation shaders, and geometry shaders.

4. The graphics processor according to claim 1, characterized in that, The viewport transformation includes backface culling or small primitive culling.

5. The graphics processor according to claim 1, characterized in that, The first geometric pipeline front end sends the request corresponding to the identification number of a primitive block to the corresponding geometric pipeline back end of the plurality of geometric pipeline circuits.

6. The graphics processor according to claim 1, characterized in that, The first backend processing includes: The front-end processing results are taken from the first bucket in the first bucket group and the first bucket in the second bucket group to perform coarse-grained depth testing and rejection; and Tiling is performed to add primitives that have been rejected by the coarse-grained depth test to the corresponding tile list.

7. A method for operating a graphics processor, characterized in that, The operation method includes: Divide a task chain into rendering tasks for multiple primitive blocks, where each primitive block includes multiple primitives; and According to the order of the plurality of primitive blocks in the task chain, the plurality of primitive blocks are sent to a plurality of geometry pipeline circuits of the graphics processor for geometry processing, wherein each of the plurality of geometry pipeline circuits includes a geometry pipeline front end and a geometry pipeline back end, the plurality of geometry pipeline circuits includes a first geometry pipeline circuit and a second geometry pipeline circuit, and the geometry processing includes: The first geometric pipeline front end of the first geometric pipeline circuit constructs a first mapping relationship between the first bucket group of the first geometric pipeline circuit and multiple graphics blocks on the screen. The first geometric pipeline front end performs first front-end processing on the first graphics blocks sent by the command processor circuit to the first geometric pipeline circuit in the multiple graphics blocks. The first geometric pipeline front end sends the front-end processing result of the first front-end processing to the corresponding bucket in the first bucket group based on the first mapping relationship. The second geometric pipeline front end of the second geometric pipeline circuit constructs a second mapping relationship between the second bucket group of the second geometric pipeline circuit and the plurality of primitive blocks. The second geometric pipeline front end performs second front-end processing on the second primitive blocks sent by the command processor circuit to the second geometric pipeline circuit in the plurality of primitive blocks. The second geometric pipeline front end sends the front-end processing result of the second front-end processing to the corresponding bucket in the second bucket group based on the second mapping relationship. The first geometric pipeline back end of the first geometric pipeline circuit retrieves the front-end processing results from the first bucket in the first bucket group and the first bucket in the second bucket group for first back-end processing; and The second geometric pipeline back end of the second geometric pipeline circuit takes the front-end processing result from the second bucket in the first bucket group and the second bucket in the second bucket group to perform the second back-end processing. The first front-end processing includes: Construct a shading task and send the shading task to the stream processor cluster circuit of the graphics processor for execution; Retrieve the vertex information processed by the stream processor cluster circuitry for further viewport transformation; and Using the coordinates of the surviving primitives after the viewport transformation, a coverage test is performed on the surviving primitives and the multiple blocks, so that the surviving primitives are sent as the front-end processing result to the corresponding bucket in the first bucket group.

8. The operating method according to claim 7, characterized in that, Each of the plurality of primitive blocks includes a drawing call, and the drawing call is responsible for rendering an object.

9. The operating method according to claim 7, characterized in that, The shading tasks include task constructor tasks for vertex shaders, tessellation shaders, and geometry shaders.

10. The operating method according to claim 7, characterized in that, The viewport transformation includes backface culling or small primitive culling.

11. The operating method according to claim 7, characterized in that, The operation method further includes: The first geometric pipeline front end sends a request corresponding to the identification number of a primitive block to the corresponding geometric pipeline back end of the plurality of geometric pipeline circuits.

12. The operating method according to claim 7, characterized in that, The first backend processing includes: The front-end processing results are taken from the first bucket in the first bucket group and the first bucket in the second bucket group to perform coarse-grained depth testing and rejection; and Tiling is performed to add primitives that have been rejected by the coarse-grained depth test to the corresponding tile list.

13. A machine-readable storage medium for storing non-transitory machine-readable instructions that, when executed by a computer, implement the operation method of the graphics processor according to any one of claims 7-12.

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