A display panel and display device

Abstract

This invention provides a display panel and a display device to reduce the time length of the display preparation phase and the screen refresh time. The display panel includes multiple scan lines and multiple data lines. The scan lines are configured to transmit scan signals, which include scan enable levels and scan disable levels. The data lines are configured to transmit data signals. The display panel includes a display cycle, which includes a display preparation phase and a display phase. The display preparation phase occurs before the display phase. The scan lines extend along a first direction. The scan lines include a first scan line electrically connected to a first pixel group and a second scan line electrically connected to a second pixel group. The first and second scan lines are arranged along a second direction, which intersects the first direction. During the display preparation phase, the time period in which the scan enable level transmitted on the first scan line is located at least partially overlaps with the time period in which the scan enable level transmitted on the second scan line is located.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a display panel and display device. Background Technology

[0002] Display panels have been widely used in daily life. Currently, electronic paper display panels are widely used due to their advantages such as low power consumption and eye-friendliness. Most electronic paper display panels currently employ active matrix driving methods.

[0003] During the display process, the display panel needs to continuously refresh the screen. The display panel refreshes line by line, scanning from the first line to the last, and each refresh takes a relatively long time to complete. Summary of the Invention

[0004] The present invention provides a display panel and a display device to reduce the time length of the display preparation stage and the screen refresh time.

[0005] In a first aspect, embodiments of the present invention provide a display panel including multiple scan lines and multiple data lines. The scan lines are configured to transmit scan signals, the scan signals including scan enable level and scan disable level; the data lines are configured to transmit data signals, the data signals including data enable level and data disable level.

[0006] The display panel includes a display cycle, which includes a display preparation stage and a display stage. The display preparation stage is located before the display stage. The scan lines extend along a first direction. The scan lines include a first scan line electrically connected to a first pixel group and a second scan line electrically connected to a second pixel group. The first scan line and the second scan line are arranged along a second direction, which intersects the first direction.

[0007] During the display preparation phase, the time period in which the scan enable level transmitted on the first scan line is located at least partially overlaps with the time period in which the scan enable level transmitted on the second scan line is located.

[0008] In a second aspect, embodiments of the present invention provide a display device, including the display panel described in the first aspect, and a driver chip, wherein the driver chip is electrically connected to data lines and scan lines.

[0009] This invention provides a display panel in which, during the display preparation phase, the time periods of the scan enable levels transmitted on at least two scan lines at least partially overlap. The scan enable levels transmitted on different scan lines can appear within the same time period, thereby reducing the duration of the display preparation phase and the screen refresh time. Attached Figure Description

[0010] Figure 1 This is a top view structural diagram of a display panel provided in an embodiment of the present invention;

[0011] Figure 2 This is a cross-sectional structural diagram of a display panel provided in an embodiment of the present invention;

[0012] Figure 3 A driving timing diagram for a display panel provided in an embodiment of the present invention;

[0013] Figure 4 This is a driving timing diagram for another display panel provided in an embodiment of the present invention;

[0014] Figure 5 This is a driving timing diagram for another display panel provided in an embodiment of the present invention;

[0015] Figure 6 This is a driving timing diagram for another display panel provided in an embodiment of the present invention;

[0016] Figure 7 This is a driving timing diagram for another display panel provided in an embodiment of the present invention;

[0017] Figure 8 This is a driving timing diagram for another display panel provided in an embodiment of the present invention;

[0018] Figure 9 This is a driving timing diagram for another display panel provided in an embodiment of the present invention;

[0019] Figure 10 This is a driving timing diagram for another display panel provided in an embodiment of the present invention;

[0020] Figure 11 This is a driving timing diagram for another display panel provided in an embodiment of the present invention;

[0021] Figure 12 This is a driving timing diagram for another display panel provided in an embodiment of the present invention;

[0022] Figure 13 This is a driving timing diagram for another display panel provided in an embodiment of the present invention;

[0023] Figure 14 This is a driving timing diagram for another display panel provided in an embodiment of the present invention;

[0024] Figure 15 This is a driving timing diagram for another display panel provided in an embodiment of the present invention;

[0025] Figure 16This is a driving timing diagram for another display panel provided in an embodiment of the present invention;

[0026] Figure 17 This is a driving timing diagram for another display panel provided in an embodiment of the present invention;

[0027] Figure 18 This is a driving timing diagram for another display panel provided in an embodiment of the present invention;

[0028] Figure 19 This is a top view schematic diagram of another display panel provided in an embodiment of the present invention;

[0029] Figure 20 This is a driving timing diagram for another display panel provided in an embodiment of the present invention;

[0030] Figure 21 This is a top view schematic diagram of another display panel provided in an embodiment of the present invention;

[0031] Figure 22 This is a driving timing diagram for another display panel provided in an embodiment of the present invention;

[0032] Figure 23 This is a cross-sectional view of another display panel provided in an embodiment of the present invention;

[0033] Figure 24 This is a driving timing diagram for another display panel provided in an embodiment of the present invention;

[0034] Figure 25 This is a top view schematic diagram of another display panel provided in an embodiment of the present invention;

[0035] Figure 26 This is a driving timing diagram for another display panel provided in an embodiment of the present invention;

[0036] Figure 27 This is a driving timing diagram for another display panel provided in an embodiment of the present invention;

[0037] Figure 28 This is a top view of a display device provided in an embodiment of the present invention. Detailed Implementation

[0038] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, the accompanying drawings show only the parts relevant to the present invention, and not all of the structures.

[0039] Figure 1 This is a top view schematic diagram of a display panel provided in an embodiment of the present invention. Figure 2 This is a cross-sectional view of a display panel provided in an embodiment of the present invention. Figure 3 This is a driving timing diagram of a display panel provided in an embodiment of the present invention, with reference to... Figures 1-3 The display panel includes multiple scan lines 21 and multiple data lines 22. The scan lines 21 are configured to transmit scan signals (e.g., a first scan signal Gate1, a second scan signal Gate2, ..., an i-th scan signal Gatei, where i is a positive integer greater than 1). The scan signals include scan enable and scan disable levels. During the scan enable level period, data signals can be written to the pixel electrodes 30. During the scan disable level period, data signals cannot be written to the pixel electrodes 30.

[0040] Data line 22 is configured to transmit data signals, including a data enable level and a data disable level. The data enable level changes the display grayscale of a sub-pixel, while the data disable level does not change the display grayscale of the sub-pixel. In one embodiment, when data line 22 transmits a data disable level, there is no voltage difference between the pixel electrode 30 and the common electrode COM; that is, the pixel electrode 30 and the common electrode COM have the same voltage. When data line 22 transmits a data enable level, there is a non-zero voltage difference between the pixel electrode 30 and the common electrode COM. In another embodiment, when data line 22 transmits a data disable level, the voltage difference between the pixel electrode 30 and the common electrode COM is within a certain threshold range. When data line 22 transmits a data enable level, the voltage difference between the pixel electrode 30 and the common electrode COM exceeds the threshold range.

[0041] The display panel includes a display cycle T10. The display cycle T10 includes a display preparation stage T21 and a display stage T22, with the display preparation stage T21 preceding the display stage T22. In the display preparation stage T21, a non-differentiated operation, such as a reset operation, is performed on all sub-pixels. In a pixel group (including a first pixel group 401 and a second pixel group 402) extending along a first direction X, the pixel group includes multiple sub-pixels arranged along the first direction X, and the data lines 22 connecting each sub-pixel transmit the same data signal. In the display preparation stage T21, each data line 22 transmits the same data signal. It can be understood that the non-differentiated operation performed on all sub-pixels in the display preparation stage T21 can also be reflected in different pixel groups, where the data lines 22 connecting sub-pixels in different pixel groups transmit the same data signal. In the display stage T22, a differentiated operation is performed on at least two sub-pixels, thereby achieving image display. In a pixel group extending along the first direction X, the data lines 22 connecting two sub-pixels respectively transmit different data signals. In the display stage T22, each data line 22 transmits different data signals.

[0042] The display phase T22 includes the time period in which the data enable level is located. During the display phase T22, the scan enable levels transmitted on each scan line 21 have the same duration. The time periods in which the scan enable levels transmitted on different scan lines 21 are located do not overlap. During the display phase T22, the data lines 22 transmit either the data enable level or the data disable level, which is then transmitted to the pixel driving circuit. The pixel driving circuit then controls the display grayscale of the sub-pixels based on the magnitude of the data enable level or the data disable level. Therefore, the display panel provided in this embodiment of the invention performs data signal writing and light emission display during the display phase T22.

[0043] Scan line 21 extends along a first direction X, and includes a first scan line 211 and a second scan line 212. The first scan line 211 is electrically connected to a first pixel group 401, and the second scan line 212 is electrically connected to a second pixel group 402. The first scan line 211 and the second scan line 212 are arranged along a second direction Y, which intersects the first direction X. The first direction X and the second direction Y can be perpendicular or not perpendicular, and form an angle greater than 0 degrees and less than 90 degrees. It should be noted that the first scan line 211 and the second scan line 212 can be adjacent or not adjacent along the second direction Y.

[0044] During the display preparation phase, the time period in which the scan enable level transmitted on the first scan line 211 is located overlaps at least partially with the time period in which the scan enable level transmitted on the second scan line 212 is located.

[0045] For example, the first scan line 211 transmits the first scan signal Gate1, the second scan line 212 transmits the second scan signal Gate2, and the i-th scan line 21 transmits the i-th scan signal Gatei. During the display preparation phase T21, the scan enable level of the first scan signal Gate1 at least partially overlaps with the scan enable level of the second scan signal Gate2. In known progressive scanning techniques, the scan enable level of the second scan signal Gate2 is located after the scan enable level of the first scan signal Gate1, and the scan enable level of the second scan signal Gate2 does not overlap with the scan enable level of the first scan signal Gate1. Compared to known techniques, the at least partial overlap of the scan enable levels of the first scan signal Gate1 and the second scan signal Gate2 during the display preparation phase T21 reduces the time length of the display preparation phase T21.

[0046] This invention provides a display panel in which, during the display preparation phase T21, the time periods of the scan enable levels transmitted on at least two scan lines 21 at least partially overlap. The scan enable levels transmitted on different scan lines 21 can appear within the same time period, thereby reducing the duration of the display preparation phase and the screen refresh time.

[0047] For example, refer to Figure 1 Multiple scan lines 21 extend along a first direction X and are arranged along a second direction Y; multiple data lines 22 extend along the second direction Y and are arranged along the first direction X. It is understood that the extension directions of the scan lines 21 and data lines 22 can be interchanged; that is, in other embodiments, multiple scan lines 21 extend along the second direction Y and are arranged along the first direction X; multiple data lines 22 extend along the first direction X and are arranged along the second direction Y.

[0048] For example, refer to Figure 1 The display panel also includes a first substrate 11, on which scan lines 21 and data lines 22 are located. In other embodiments, at least one of the scan lines 21 and data lines 22 may be located on other substrates.

[0049] For example, refer to Figure 23 At least one of the scan line 21 and the data line 22 may be located on the second substrate 12, wherein the first substrate 11 and the second substrate 12 are disposed opposite to each other.

[0050] Optionally, refer to Figures 1-2 The display panel includes a pixel driving circuit, which includes a first functional transistor 20. A scan line 21 is electrically connected to the gate of the first functional transistor 20, and the scan line 21 is configured to control the conduction or cutoff of the first functional transistor 20. When the scan line 21 transmits a scan enable level, the first functional transistor 20 is turned on, and the data enable or data disable level transmitted by the data line 22 is transmitted through the turned-on first functional transistor 20 to the pixel electrode 30. When the scan line 21 transmits a scan disable level, the first functional transistor 20 is turned off.

[0051] For example, refer to Figure 2The pixel driving circuit also includes a storage capacitor C. The first plate C1 of the storage capacitor C is disposed on the same layer as the source 201 and drain 204 of the first functional transistor 20, and the second plate C2 of the storage capacitor C is disposed on the same layer as the gate 203 of the first functional transistor 20. The first plate C1 of the storage capacitor C is electrically connected to the drain 204 of the first functional transistor 20, and is also electrically connected to the pixel electrode 30. The storage capacitor C is mainly used to ensure that the charged voltage is maintained until the next frame update. It is understood that the source 201 and drain 204 of the first functional transistor 20 can be interchanged.

[0052] For example, refer to Figure 2 The display panel also includes a gate insulating layer 301, a passivation layer 302, and a planarization layer 303. The gate insulating layer 301 is located between the gate 203 and the source 201. The source 201 and the drain 204 are on the same layer and stacked on the semiconductor layer 202. The passivation layer 302 is located between the planarization layer 303 and the source 301, and the planarization layer 303 is located between the pixel electrode 30 and the passivation layer 302. The pixel electrode 30 is electrically connected to the drain 204 through a via penetrating the planarization layer 303 and the passivation layer 302.

[0053] For example, for the sake of simplicity, Figure 1 In the diagram, a first functional transistor 20 is illustrated in a pixel driving circuit. A pixel driving circuit may include two first functional transistors 20 connected in series. (Reference) Figure 2 The display is controlled by two series-connected first functional transistors 20. These two series-connected first functional transistors 20 can reduce leakage current and improve display quality. The two series-connected first functional transistors 20 form a dual-gate transistor.

[0054] Figure 4 This is a driving timing diagram for another display panel provided in an embodiment of the present invention, with reference to... Figure 1 and Figure 4 In the display preparation phase T21, the time period during which the scan enable level transmitted on the first scan line 211 is the same as the time period during which the scan enable level transmitted on the second scan line 212 is transmitted. That is, at least two scan lines 21 transmit scan enable levels within the same time period. Therefore, the duration occupied by the scan enable levels of the two scan signals transmitting scan enable levels within the same time period is halved compared to known techniques. This reduces the length of the display preparation phase and the screen refresh time.

[0055] In known technologies, during the display preparation phase T21, scanning is performed line by line. After completing an operation (e.g., a reset operation) within the time period of the scan enable level transmitted by the first scan line 211, the operation is completed within the time period of the scan enable level transmitted by the second scan line 212. The first scan line 211 and the second scan line 212 control the sub-pixels to complete the same operation sequentially within different time periods. Differences in the timing of the same operation can lead to differences in display effects. However, in the embodiment of this invention, at least two scan enable levels of scan signals are transmitted within the same time period, reducing the time difference for the same operation. That is, during the display preparation phase T21, non-differentiated operations are performed on all sub-pixels as much as possible within the same time period. This contributes to display uniformity.

[0056] Figure 5 This is a driving timing diagram for another display panel provided in an embodiment of the present invention, with reference to... Figure 5 The display preparation phase T21 includes a reset phase T31 and an oscillation phase T32. Within the same display cycle T10, the write frequency of the enable level of the data signal Source during the oscillation phase T32 is greater than the write frequency of the enable level of the data signal Source during the reset phase T31. The write frequency of the enable level refers to the number of times the enable level is written per unit time.

[0057] For example, the display panel is an electrophoretic display panel, which includes electrophoretic particles. During the reset phase T31, the enable level is low, and the voltage change frequency is low, thus providing sufficient movement time for the electrophoretic particles. This allows the particles to move to a preset position under the control of an electric field for a longer period, reducing the difference in grayscale between all sub-pixels. For example, after reset, the display panel can display a white or black background. During the oscillation phase T32, the enable level is high, and the voltage change frequency is high, allowing electrophoretic particles with different charges to separate from each other in a high-frequency changing electric field, preventing the aggregation of electrophoretic particles with different charges.

[0058] In other embodiments, the preparation phase T21 may include only one of the reset phase T31 and the oscillation phase T32.

[0059] Optionally, refer to Figure 5 The preparation phase T21 includes a reset phase T31, and the reset phase T31 includes at least one sub-reset phase T310. Figure 5In an exemplary embodiment, reset phase T31 includes a sub-reset phase T310. Data enable levels include a first data enable level V1 and a second data enable level V2 with opposite polarities. Sub-reset phase T310 includes a time period T41 containing the first data enable level V1 and a time period T42 containing the second data enable level V2. In other embodiments, sub-reset phase T310 may also include only a time period T41 containing the first data enable level V1 or a time period T42 containing the second data enable level V2.

[0060] For example, refer to Figure 5 The data enable level is not equal to 0V, and the data disable level is equal to 0V. The first data enable level V1 is less than 0V, and the second data enable level V2 is greater than 0V. The first data enable level V1 is configured to make the display panel display a black image (i.e., a black background), and the second data enable level V2 is configured to make the display panel display a white image (i.e., a white background). The negative voltage is for the black writing process, and the positive voltage is for the white writing process.

[0061] It should be noted that the color of the displayed image (black or white) resulting from the positive or negative signal level of the data enable level also depends on the polarity of the particles. That is, under the same voltage polarity, positive and negative black particles will produce different images.

[0062] Figure 6 This is a driving timing diagram for another display panel provided in an embodiment of the present invention, with reference to... Figure 6 The first data enable level V1 is greater than 0V, and the second data enable level V2 is less than 0V. The first data enable level V1 is configured to make the display panel display a black image (i.e., a black background), and the second data enable level V2 is configured to make the display panel display a white image (i.e., a white background). The positive voltage is for writing black, and the negative voltage is for writing white.

[0063] It is understood that resetting the image displayed on the display panel will result in an image that is not limited to black and white; the final color of the image is determined by the color, polarity, and type of the particles. In other embodiments, resetting the image displayed on the display panel may also result in an image that includes brown and white.

[0064] For example, refer to Figure 1 and Figure 5The display stage T22 includes a first sub-display stage T221 and a second sub-display stage T222. The first sub-display stage T221 is located between the display preparation stage T21 and the second sub-display stage T222. In the first sub-display stage T221, the time periods of the scan enable levels transmitted on the two scan lines 21 do not overlap. The time periods of the scan enable levels transmitted on each scan line 21 are arranged sequentially at intervals. In the first sub-display stage T221, during the time period of the scan enable level, at least one of the data enable level and the data disable level is transmitted on the data line 22. At least one of the data enable level and the data disable level is written to the pixel driving circuit, and then the pixel driving circuit controls the display grayscale of the sub-pixel according to the magnitude of the data enable level or according to the data disable level. In the second sub-display stage T221, the display panel can be powered off, that is, no data signal and scan signal are applied; or, a scan disable level is applied to the scan line 21; or, a data disable level is applied to the data line 22. Specifically, the way to apply a data disable level to the data line 22 may include: floating the data line 22, or applying the same voltage as the common electrode COM to the data line 22, so that there is no voltage difference between the common electrode COM and the pixel electrode 30.

[0065] It is understood that in the first sub-display stage T221, while data signals are being written line by line, the pixel driving circuits that have received the written data signals control the sub-pixels to emit light. In the second sub-display stage T221, the pixel driving circuits for all rows of the entire display panel have finished writing data signals, and all sub-pixels in the display panel emit light under the control of their respective pixel driving circuits. This invention does not limit the duration relationship between the first sub-display stage T221 and the second sub-display stage T221. The duration of the first sub-display stage T221 can be greater than or less than the duration of the second sub-display stage T221.

[0066] For example, refer to Figure 5 During the period when the scan enable level of the first scan signal Gate1 is located, the voltage of the data signal Source is partly at the data enable level and partly at the data disable level.

[0067] Optionally, refer to Figure 1 and Figure 5 During the sub-reset phase T310, the time period in which the scan enable level transmitted on the first scan line 211 overlaps with the time period in which the scan enable level transmitted on the second scan line 212 occurs. The scan enable levels transmitted on different scan lines 21 can appear in the same time period, thereby reducing the duration of the sub-reset phase T310, reducing the duration of the reset phase T31, and reducing the duration of the display preparation phase T21.

[0068] Optionally, refer to Figure 5 The preparation phase T21 also includes an oscillation phase T32. The oscillation phase T32 includes at least one sub-oscillation phase T320. Figure 5 For example, oscillation phase T32 includes a sub-oscillation phase T320. Data enable levels include a third data enable level V3 and a fourth data enable level V4 with opposite polarities. Sub-oscillation phase T320 includes multiple time periods of the third data enable level V3 and multiple time periods of the fourth data enable level V4. The time periods of the third data enable level V3 and the time periods of the fourth data enable level V4 are adjacent. A time period of the fourth data enable level V4 is spaced between two time periods of the third data enable level V3, and a time period of the third data enable level V3 is spaced between two time periods of the fourth data enable level V4.

[0069] Optionally, refer to Figure 1 and Figure 5 During the sub-oscillation phase T320, the time period in which the scan enable level transmitted on the first scan line 211 overlaps with the time period in which the scan enable level transmitted on the second scan line 212 occurs. The scan enable levels transmitted on different scan lines 21 can appear in the same time period, thereby reducing the duration of the sub-oscillation phase T320, the duration of the oscillation phase T32, and the duration of the display preparation phase T21.

[0070] Optionally, refer to Figure 1 and Figure 5 Within the same display cycle T10, the duration of the oscillation phase T32 is shorter than the duration of the reset phase T31.

[0071] For example, refer to Figure 5 During the reset phase T31, time period T41 is a balancing period. The polarity of the data enable level during this balancing period is the same as the polarity of the data enable level during the display phase T22 of the previous display cycle T10. The balancing period is used to balance the previous display cycle T10. The balancing period will be described in detail later. Because the reset phase T31 includes the balancing period, the reset phase T31 has a longer duration than the oscillation phase T32.

[0072] Optionally, refer to Figure 4 and Figure 5 The display preparation phase T21 includes a period of time during which a scan enable level is present. For a scan signal, the display preparation phase T21 includes a scan signal pulse, and the number of high-level and low-level switching in the scan signal is minimized, which helps to reduce the power consumption of the display panel.

[0073] Figure 7 This is a driving timing diagram for another display panel provided in an embodiment of the present invention, with reference to... Figure 1and Figure 7 In the display preparation phase T21, multiple scan enable levels are included in the time period. For a single scan signal, the display preparation phase T21 includes at least two scan signal pulses, reducing the duration of a single scan enable level. This is beneficial for the shift register that provides the scan signal to scan line 21. Figure 1 As shown in the diagram (not shown), the voltage at the output of the shift register will not remain at a high level for an extended period, reducing the offset caused by the shift register output voltage, improving the stability of the shift register output voltage, and thus improving the stability of the scan signal. The shift register can be located within the driver chip.

[0074] For example, refer to Figure 7 In the display preparation stage T21, the first scan signal Gate1 includes two time periods containing scan enable levels, the second scan signal Gate2 includes two time periods containing scan enable levels, and the i-th scan signal Gatei includes two time periods containing scan enable levels. It should be noted that, in this embodiment of the invention, the number of scan enable levels transmitted on a single scan line 21 during the display preparation stage T21 is not limited.

[0075] Optionally, refer to Figure 7 The duration of a scan enable level in the display preparation phase T21 is equal to the duration of a scan enable level in the display phase T22. Therefore, the scan enable levels in the display preparation phase T21 and the display phase T22 can be generated by the same set of shift registers, eliminating the need for multiple sets of different shift registers and simplifying shift register setup.

[0076] Figure 8 This is a driving timing diagram for another display panel provided in an embodiment of the present invention, with reference to... Figure 1 and Figure 8 Both the reset phase T31 and the oscillation phase T32 include a time period containing at least one scan enable level. The duration of the scan enable level within the reset phase T31 will not exceed the duration of the reset phase T31. The duration of the scan enable level within the oscillation phase T32 will not exceed the duration of the oscillation phase T32. This reduces the duration of a single scan enable level.

[0077] For example, refer to Figure 8 During the reset phase T31, the first scan signal Gate1 includes a scan enable level. During the oscillation phase T32, the first scan signal Gate1 includes a scan enable level. Similarly, during the reset phase T31, the second scan signal Gate2 includes a scan enable level. During the oscillation phase T32, the second scan signal Gate2 includes a scan enable level.

[0078] For example, refer to Figure 1 and Figure 8 During the reset phase T31, the scan enable levels transmitted on any two scan lines 21 occur during the same time period. During the oscillation phase T32, the time periods of the scan enable levels transmitted on the two scan lines 21 do not overlap. The time periods of the scan enable levels transmitted on each scan line 21 are arranged sequentially at intervals. In this embodiment of the invention, the duration of the reset phase T31 is reduced, while the duration of the oscillation phase T32 remains unchanged, thereby reducing the overall duration of the display preparation phase T21.

[0079] Figure 9 This is a driving timing diagram for another display panel provided in an embodiment of the present invention, with reference to... Figure 1 and Figure 9 The reset phase T31 includes a period of time during which a scan enable level is present. The oscillation phase T32 includes a period of time during which a scan enable level is present. In the reset phase T31, the scan enable level transmitted on any two scan lines 21 is present for the same period of time. In the oscillation phase T32, the scan enable level transmitted on any two scan lines 21 is present for the same period of time.

[0080] Figure 10 This is a driving timing diagram for another display panel provided in an embodiment of the present invention, with reference to... Figure 1 and Figure 10 The reset phase T31 includes a time period containing one scan enable level. The oscillation phase T32 includes multiple time periods containing scan enable levels. During the oscillation phase T32, any two scan lines 21 transmit scan enable levels within the same time period, and all scan lines 21 transmit scan enable levels simultaneously.

[0081] In other implementations, the reset phase T31 includes the time periods of multiple scan enable levels. The oscillation phase T32 includes the time period of one scan enable level.

[0082] Figure 11 This is a driving timing diagram for another display panel provided in an embodiment of the present invention, with reference to... Figure 1 and Figure 11 The reset phase T31 includes the time periods of multiple scan enable levels. The oscillation phase T32 includes the time periods of multiple scan enable levels. The duration of the scan enable level within the reset phase T31 will not exceed half the duration of the reset phase T31. The duration of the scan enable level within the oscillation phase T32 will not exceed half the duration of the oscillation phase T32. This reduces the duration of a single scan enable level. In the reset phase T31 and the oscillation phase T32, the scan enable levels transmitted by any two scan lines 21 within the same time period are transmitted simultaneously by all scan lines 21.

[0083] For example, refer to Figure 5 Within the same display cycle T10, the reset phase T31 is located between the oscillation phase T32 and the display phase. Within the same display cycle T10, the oscillation phase T32 is located before the reset phase T31, and the reset phase T31 is located before the display phase T22. In this embodiment of the invention, the aggregation of electrophoretic particles with different charges is first eliminated, and then the electrophoretic particles are moved to a preset position to achieve the same display grayscale for all sub-pixels. When the reset phase T31 is located between the oscillation phase T32 and the display phase, the main focus is on balancing the voltage of the current display cycle T10, but the voltage of the previous display cycle T10 can also be balanced.

[0084] Figure 12 This is a driving timing diagram for another display panel provided in an embodiment of the present invention, with reference to... Figure 12 Within the same display cycle T10, the oscillation phase T32 is located between the reset phase T31 and the display phase T22. Within the same display cycle T10, the reset phase T31 precedes the oscillation phase T32, and the oscillation phase T32 precedes the display phase T22. In this embodiment of the invention, the electrophoretic particles are first moved to a preset position to achieve the same display grayscale for all sub-pixels, and then the aggregation of electrophoretic particles with different charges is eliminated. When the reset phase T31 is located between the oscillation phase T32 and the display phase, the main function is to balance the voltage of the previous display cycle T10, and it can also balance the voltage of the current display cycle T10.

[0085] Optionally, refer to Figure 12 The sub-reset phase T310 of the (M+1)th display cycle T10 is adjacent to the display phase T22 in the Mth display cycle T10, where M is a positive integer. That is, after the display phase T22 in the Mth display cycle T10, the phase adjacent to the display phase T22 in the Mth display cycle T10 is the sub-reset phase T310.

[0086] Optionally, refer to Figure 12 In the (N+1)th display cycle T10, the sub-reset phase T310, which is closest in time to the display phase T22 within the Nth display cycle T10, includes a balancing period, where N is a positive integer. The polarity of the data enable level during the balancing period of the (N+1)th display cycle T10 is the same as the polarity of the data enable level during the display phase T22 within the Nth display cycle T10.

[0087] For example, refer to Figure 5 The sub-reset phase T310 of the (N+1)th display cycle T10 is not adjacent to the display phase T22 in the Nth display cycle T10, and there is a sub-oscillation phase T320 between the sub-reset phase T310 of the (N+1)th display cycle T10 and the display phase T22 in the Nth display cycle T10. (Reference) Figure 12When the sub-reset phase T310 is adjacent to the display phase T22 in the previous display cycle T10, it can be described in two equivalent ways. One way is that the sub-reset phase T310 of the (N+1)th display cycle T10 is adjacent to the display phase T22 in the Nth display cycle T10. The other way is that the sub-reset phase T310 of the (M+1)th display cycle T10 is adjacent to the display phase T22 in the Mth display cycle T10. Therefore, when the sub-reset phase T310 of the (M+1)th display cycle T10 is adjacent to the display phase T22 in the Mth display cycle T10, N and M can be considered to be the same value.

[0088] For example, refer to Figure 12 In the Nth display cycle T10, during display phase T22, the data enable level is negative, meaning the data enable level is a negative voltage. Taking electrophoretic particles, including black and white particles, as an example: In the Nth display cycle T10, during display phase T22, by moving the white electrophoretic particles away from the display side and moving the black electrophoretic particles towards the display side, the displayed image on the panel is black text on a white background. In the (N+1)th display cycle T10, during the balance period, the data enable level is negative. In the (N+1)th display cycle T10, by continuing to move the white electrophoretic particles away from the display side and moving the black electrophoretic particles towards the display side, the display panel displays a black image (i.e., a black background). Therefore, the balance period continues the black-writing process of the previous display cycle T10 and continues writing black until the display panel displays a black image. In other implementations, the balancing period continues the white-writing process of the previous display cycle T10 and continues until the display panel shows a white image. In summary, the balancing period continues the polarity of the data enable level within the display phase T22 of the previous display cycle T10, and continues the movement direction of the electrophoretic particles within the display phase T22 of the previous display cycle T10, thereby achieving a reset. After the reset, the electrophoretic particles can start moving from the same starting point.

[0089] Optionally, refer to Figure 1 and Figure 12The sub-reset phase T310 also includes a leveling phase T50. During the leveling phase T50, data line 22 transmits data at a non-enabled level. No electric field is formed between the pixel electrode 30 and the common electrode COM to drive the electrophoretic particles. Because an electric field is formed between the pixel electrode 30 and the common electrode COM during the period when data line 22 transmits data at an enabled level, the electrophoretic particles move under the drive of this electric field. The particles require a buffer time to return to rest. The leveling phase T50 provides this buffer time. Furthermore, the leveling phase T50 is configured to adjust the duration of the sub-reset phase T310, i.e., to supplement the duration of the sub-reset phase T310 so that its duration matches the pulse period of the driver chip.

[0090] For example, refer to Figure 12 In the (N+1)th display cycle T10, the sub-reset stage T310 that is closest in time to display stage T22 within the Nth display cycle T10 includes the leveling segment T50. In the (N+1)th display cycle T10, the sub-reset stage T310 that is closest in time to display stage T22 within the Nth display cycle T10 includes the balancing period. The balancing period (segment T41) and the leveling segment T50 are located within the same sub-reset stage T310.

[0091] It should be noted that, in the above embodiments, the reset stage T31 includes a sub-reset stage T310 and the oscillation stage T32 includes a sub-oscillation stage T320 as an example. However, this is not a limitation. In other embodiments, the reset stage T31 may include multiple sub-reset stages T310, and / or the oscillation stage T32 may include multiple sub-oscillation stages T320.

[0092] Figure 13 This is a driving timing diagram for another display panel provided in an embodiment of the present invention, with reference to... Figure 13 The sub-reset stage T310 includes a first sub-reset stage T311 and a second sub-reset stage T312. The sub-oscillation stage T320 includes a first sub-oscillation stage T321. In the same display preparation stage T21, the first sub-oscillation stage T321 is located between the first sub-reset stage T311 and the second sub-reset stage T312, and the second sub-reset stage T312 is located between the first sub-oscillation stage T321 and the display stage T22. In this embodiment of the invention, the process of combining the sub-reset stage T310 and the sub-oscillation stage T320 to make all sub-pixels have the same display grayscale is alternated with the process of eliminating the aggregation of electrophoretic particles with different charges, in multiple cycles. After resetting, the electrophoretic particles can start moving from the same starting point.

[0093] For example, refer to Figure 13The sub-reset phase T310 of the (N+1)th display cycle T10 includes a first sub-reset phase T311 and a second sub-reset phase T312. The first sub-reset phase T311 in the (N+1)th display cycle T10 is closest in time to the display phase T22 in the Nth display cycle T10. The first sub-reset phase T311 is adjacent to the display phase T22 in the Nth display cycle T10.

[0094] For example, refer to Figure 13 The first sub-reset phase T311 in the (N+1)th display cycle T10 includes a balancing period. The polarity of the data enable level during the balancing period of the (N+1)th display cycle T10 is the same as the polarity of the data enable level during the display phase T22 in the Nth display cycle T10.

[0095] For example, refer to Figure 13 The first sub-reset stage T311 in the (N+1)th display cycle T10 includes a leveling section T50. The second sub-reset stage T312 in the (N+1)th display cycle T10 includes a leveling section T50.

[0096] Optionally, refer to Figure 13 Within the same display cycle T10, the sub-reset phase T310 is adjacent to the display phase T22. Within the same display cycle T10, the sub-reset phase T310 is the closest in time to the display phase T22. By resetting the display phase just before it begins, the electrophoretic particles can start moving from the same starting point in the display phase T22, thereby improving display quality.

[0097] For example, refer to Figure 13 Within the same display cycle T10, the number of sub-reset phases T310 is greater than the number of sub-oscillation phases T320. Sub-oscillation phases T320 are configured to activate electrophoretic particles, preventing the aggregation of electrophoretic particles with different charges. Appropriately reducing the number of sub-oscillation phases T320 will not affect the display effect of the display panel and can reduce the duration of oscillation phases T32.

[0098] For example, refer to Figure 13 In the first sub-reset phase T311 of the N+1th display cycle T10, the data enable levels include a first data enable level V1 and a second data enable level V2 with opposite polarities. During the period of the first data enable level V1, the display panel resets to display a black screen. During the period of the second data enable level V2, the display panel resets to display a white screen. In the second sub-reset phase T312 of the N+1th display cycle T10, the data enable levels include a first data enable level V1 and a second data enable level V2 with opposite polarities. The display panel once again displays a white screen and a black screen.

[0099] Figure 14 This is a driving timing diagram for another display panel provided in an embodiment of the present invention, with reference to... Figure 14 In the first sub-reset stage T311 of the N+1th display cycle T10, the data enable level includes the first data enable level V1. The display panel resets to display a black screen. In the second sub-reset stage T312 of the N+1th display cycle T10, the data enable level includes the second data enable level V2, and the display panel resets to display a white screen.

[0100] Figure 15 This is a driving timing diagram for another display panel provided in an embodiment of the present invention, with reference to... Figure 15 In the (N+1)th display cycle T10, the second sub-reset phase T312 includes a time period T42 and a leveling phase T50, which is located between the first sub-oscillation phase T321 and the time period T42. Therefore, after the first sub-oscillation phase T321, the data signal Source inputs a de-enabled level (e.g., 0V) in the leveling phase T50, and then the display panel resets to display a white image within the time period T42. The setting of the leveling phase T50 provides a buffer time for the particles to move from motion to stillness, thus providing a buffer time after oscillation and before reset to stabilize the particle motion state of the first sub-oscillation phase T321.

[0101] Figure 16 This is a driving timing diagram for another display panel provided in an embodiment of the present invention, with reference to... Figure 16 The sub-oscillation stage T320 includes a first sub-oscillation stage T321 and a second sub-oscillation stage T322. Within the same display preparation stage T21, the second sub-oscillation stage T322 is located between the second sub-reset stage T312 and the display stage T22. In this embodiment of the invention, the sub-reset stage T310 and the sub-oscillation stage T320 are combined, with the first sub-reset stage T311, the first sub-oscillation stage T321, the second sub-reset stage T312, and the second sub-oscillation stage T322 performed sequentially. This combination of two rounds of reset and oscillation allows the electrophoretic particles to begin moving from the same starting point.

[0102] Figure 17 This is a driving timing diagram for another display panel provided in an embodiment of the present invention, with reference to... Figure 17The first sub-reset phase T311 includes a balancing period (i.e., period T41). The polarity of the data enable level during the balancing period of the (M+1)th display cycle T10 is the same as the polarity of the data enable level during display phase T22 in the Mth display cycle T10. The second sub-reset phase T312 includes a first period T51 and a second period T52. The first period T51 is located between the second period T52 and the first sub-reset phase T311. The polarity of the data enable level during the first period T51 is opposite to the polarity of the data enable level during the balancing period (i.e., period T41), while the polarity of the data enable level during the second period T52 is the same as the polarity of the data enable level during the balancing period. The polarity of the data enable level during the first period T51 is opposite to the polarity of the data enable level during the second period T52. Within the same display cycle T10, the polarity of the data enable level during display phase T22 is opposite to the polarity of the data enable level during the balancing period. In this embodiment of the invention, during the display stage T22 of the Mth display cycle T10, the polarity of the data enable level is negative. The displayed image on the display panel is black text on a white background. During the display stage T22 of the (M+1)th display cycle T10, the polarity of the data enable level is positive. The displayed image on the display panel is white text on a black background. If only the first sub-reset stage T311 is set in the display preparation stage T21 of the (M+1)th display cycle T10, although the image displayed on the display panel is reset to a black image (i.e., a black background) in the first sub-reset stage T311, the display effect of the display panel in the (M+1)th display cycle T10 is poor. Therefore, a second sub-reset stage T312 is set in the display preparation stage T21 of the M+1th display cycle T10. In the first time period T51 of the second sub-reset stage T312, the image displayed on the display panel is reset to a white image (i.e., white background). Then, in the second time period T52 of the second sub-reset stage T312, the image displayed on the display panel is reset to a black image (i.e., black background) to improve the display effect of the display panel in the M+1th display cycle T10.

[0103] Optionally, refer to Figure 17 During the balancing period, it is not necessary to start from a black screen and reset to a white screen; or vice versa. The balancing period continues the polarity of the data enable level in display phase T22 of the previous display cycle T10, and continues the movement direction of the electrophoretic particles in display phase T22 of the previous display cycle T10, thereby reducing the time required for reset. Therefore, the duration of the balancing period (i.e., period T41) is shorter than the duration of the second period T52.

[0104] Figure 18 This is a driving timing diagram for another display panel provided in an embodiment of the present invention, with reference to... Figure 18The first sub-reset phase T311 includes a third time period T53 and a fourth time period T54. The fourth time period T54 is located between the third time period T53 and the first sub-oscillation phase T321. The second sub-reset phase T312 includes a fifth time period T55 and a sixth time period T56. The fifth time period T55 is located between the sixth time period T56 and the first sub-oscillation phase T321. The polarity of the data enable level in the third time period T53 is the same as that in the fifth time period T55, and the polarity of the data enable level in the third time period T53 is opposite to that in the fourth time period T54. The polarity of the data enable level in the fourth time period T54 is the same as that in the sixth time period T56. The ratio of the duration of the third time period T53 to the duration of the fourth time period T54 is not equal to the ratio of the duration of the fifth time period T55 to the duration of the sixth time period T56.

[0105] For example, refer to Figure 18 In the third time period T53, the data enable level is negative, resetting the image displayed on the display panel to a black image (i.e., black background). In the fourth time period T54, the data enable level is positive, resetting the image displayed on the display panel to a white image (i.e., white background). In the fifth time period T55, the data enable level is negative, resetting the image displayed on the display panel to a black image again. In the sixth time period T56, the data enable level is positive, resetting the image displayed on the display panel to a white image again.

[0106] For example, refer to Figure 18 The first sub-reset phase T311 includes a balancing period (i.e., the third period T53). The balancing period continues the polarity of the data enable level from the display phase T22 of the previous display cycle T10, and also continues the direction of electrophoretic particle movement from the display phase T22 of the previous display cycle T10. Therefore, the duration of the third period T53 is shorter. Consequently, the ratio of the duration of the third period T53 to the duration of the fourth period T54 is less than the ratio of the duration of the fifth period T55 to the duration of the sixth period T56.

[0107] Optionally, since the sub-reset phase T310 includes at least one period of resetting to a black image, or at least one period of resetting to a white image, the duration of the sub-reset phase T310 has a minimum time requirement; the duration of the sub-reset phase T310 cannot be too short. Therefore, with a fixed duration for the sub-reset phase T310, the more sub-reset phases T310 there are, the longer the reset phase T31 will be, and the longer the screen refresh time will be. Thus, within the same display cycle T10, if the number of sub-reset phases T310 is less than or equal to 3, the duration of the reset phase T31 can be reduced, thereby reducing the screen refresh time.

[0108] Optionally, refer to Figure 1 and Figure 5 Within the same display cycle T10, an interval stage T60 is provided between the display preparation stage T21 and the display stage T22. During the interval stage T60, a scan disable level is transmitted on scan line 21, and a data disable level is transmitted on data line 22. The driver chip writes the data signal Source to data line 22, and then data line 22 writes it to the pixel driver circuit. Therefore, the writing of the data signal Source to the pixel driver circuit is not instantaneous and requires a certain amount of time. To prevent images generated during the display stage T22 due to the data signal Source being written to the pixel driver circuit during the display preparation stage T21, the interval stage T60 is provided between the display preparation stage T21 and the display stage T22.

[0109] Furthermore, during the interval phase T60, a scan disable level is transmitted on scan line 21, preventing the data signal Source from being written to the pixel driving circuit and thus hindering control of the sub-pixel's display grayscale. During the interval phase T60, a data disable level is applied to data line 22, thereby saving power consumption of the display panel. The data disable level can be, for example, 0V.

[0110] For example, refer to Figure 5 The display preparation phase T21 is for resetting the particles and is not used for screen display. Therefore, the accuracy requirement for the written data signal Source is not as stringent in the display preparation phase T21. Thus, an interval phase T60 is not required between the reset phase T31 and the oscillation phase T32 within the display preparation phase T21. The reset phase T31 and the oscillation phase T32 can share the same scan enable level, thereby reducing the duration of the display preparation phase T21.

[0111] Optionally, refer to Figure 1 and Figure 5 The display phase T22 includes an interval phase T60, which occurs between scan enable levels transmitted on the two scan lines 21. A scan enable level is transmitted on one scan line 21, and after the interval phase T60, a scan enable level is transmitted on the other scan line 21. During the interval phase T60, a scan disable level is transmitted on the scan lines 21, and a data disable level is transmitted on the data lines 22, thereby saving power consumption of the display panel.

[0112] For example, refer to Figure 5 The interval phase T60 is greater than or equal to 1 microsecond and less than or equal to 10 microseconds.

[0113] Optionally, refer to Figure 5The higher the absolute value of the data enable level, the stronger the electric field generated by the pixel electrode 30 and the common electrode COM, and the faster the electrophoretic particles move; conversely, the lower the absolute value of the data enable level, the weaker the electric field generated by the pixel electrode 30 and the common electrode COM, and the slower the electrophoretic particles move. In this embodiment of the invention, the absolute value of the data enable level in the display stage T22 is less than the absolute value of the data enable level in the display preparation stage T21. This increases the absolute value of the data enable level in the display preparation stage T21, increases the speed of the electrophoretic particles in the display preparation stage T21, and reduces the duration of the display preparation stage T21.

[0114] For example, refer to Figure 5 In the display phase T22, the data enable level is denoted as V0, where |V0| is less than any one of |V1|, |V2|, |V3|, and |V4|.

[0115] Figure 19 This is a top view schematic diagram of another display panel provided in an embodiment of the present invention. Figure 20 This is a driving timing diagram for another display panel provided in an embodiment of the present invention, with reference to... Figure 1 , Figure 19 and Figure 20 The display panel includes a first display area 101 and a second display area 102. The display cycle T10 includes a first type of display cycle and a second type of display cycle. During the display preparation phase T21 of the first type of display cycle, the data line 22 transmits at least one of a data disable level and a data enable level. The first type of display cycle can be the display cycle T10 in the above embodiments. During the display preparation phase T21, the time periods of the scan enable levels transmitted on at least two scan lines 21 at least partially overlap. During the display preparation phase T21 and the display phase T22 of the second type of display cycle, the data line 22 transmits a data disable level. During the second type of display cycle, no data enable level is written, no screen refresh is performed, and the screen displayed in the previous display cycle T10 is maintained. The first display area 101 includes the first type of display cycle, and the second display area 102 includes the second type of display cycle. The display cycle T10 in the first display area 101 has a shorter refresh duration, and no screen refresh is performed in the second display area 102, thereby saving power consumption of the display panel.

[0116] For example, refer to Figure 4 and Figure 20 The scanning signal setting method in the second type of display cycle is the same as that in the first type of display cycle, so that the same set of shift registers can be used to generate the scanning signals in the first display area 101 and the second display area 102.

[0117] For example, refer to Figure 1 and Figure 19 The first display area 101 and the second display area 102 are arranged along the second direction Y.

[0118] Figure 21 This is a top view schematic diagram of another display panel provided in an embodiment of the present invention. Figure 22 This is a driving timing diagram for another display panel provided in an embodiment of the present invention, with reference to... Figure 1 , Figure 21 and Figure 22 The display panel includes a first display area 101 and a third display area 103. The display cycle T10 includes a first type of display cycle and a third type of display cycle. During the display preparation phase T21 of the first type of display cycle, the data line transmits at least one of a data disable level and a data enable level. During the display preparation phase T21 of the third type of display cycle, a scan enable level is transmitted on the same scan line 21, and the scan enable levels transmitted on each scan line 21 have the same duration. The time periods of the scan enable levels transmitted on different scan lines 21 do not overlap. During the display preparation phase T1 of the third type of display cycle, the screen is refreshed according to a line-by-line scanning method in the known art. The first display area 101 includes the first type of display cycle, and the third display area 103 includes the third type of display cycle. The display cycle T10 in the first display area 101 has a shorter refresh duration, while the display cycle T10 in the third display area 103 has a longer refresh duration.

[0119] For example, refer to Figure 1 and Figure 21 The first display area 101 and the third display area 103 are arranged along the second direction Y.

[0120] In other embodiments, the display panel may also include a first display area 101, a second display area 102, and a third display area 103.

[0121] Figure 23 This is a cross-sectional view of another display panel provided in an embodiment of the present invention, with reference to... Figure 1 , Figure 2 and Figure 23 The display panel includes a first substrate 11, a second substrate 12, and electrophoretic particles 13. The first substrate 11 and the second substrate 12 are disposed opposite to each other, and the electrophoretic particles 13 are located between the first substrate 11 and the second substrate 12. Scan lines 21 are located on at least one of the first substrate 11 and the second substrate 12, and data lines 22 are located on at least one of the first substrate 11 and the second substrate 12. The display panel provided in this embodiment of the invention is an electrophoretic display panel. In other embodiments, the display panel may be other types of display panels besides electrophoretic display panels.

[0122] For example, refer to Figure 23The electrophoretic particles 13 include black electrophoretic particles 132 and white electrophoretic particles 131. When the black electrophoretic particles 132 are located on the display side of the display panel (e.g., the side of the second substrate 12 away from the first substrate 11), light is absorbed by the black electrophoretic particles 132, resulting in less light being reflected to the human eye, which appears as a dark area to the human eye. When the white electrophoretic particles 131 are located on the display side of the display panel, light is reflected by the white electrophoretic particles 131, resulting in more light being reflected to the human eye, which appears as a bright area to the human eye. This embodiment of the invention is explained using a two-particle system, but is not limited thereto. In other embodiments, the electrophoretic particles 13 may include a multi-particle system, which may include at least three types of electrophoretic particles.

[0123] Optionally, refer to Figure 1 and Figure 5 During the display phase T22, a scan enable level is transmitted on the same scan line 21. The scan enable levels transmitted on each scan line 21 have the same duration, and the time periods of the scan enable levels transmitted on different scan lines 21 do not overlap. During the time period of the scan enable level in the display phase T22, at least one of the data enable level and the data disable level is transmitted on the data line 22. At least one of the data enable level and the data disable level is written to the pixel driving circuit, and then the pixel driving circuit controls the display grayscale of the sub-pixel according to the magnitude of the data enable level or according to the data disable level.

[0124] Figure 24 This is a driving timing diagram for another display panel provided in an embodiment of the present invention, with reference to... Figure 1 and Figure 24 Display stage T22 includes P secondary display stages T220 ( Figure 24 For example, P = 2), where P is a positive integer greater than 1. In each sub-display stage T220, the same data signal Source is transmitted on the same data line 22. In the same sub-display stage T220, a scan enable level is transmitted on the same scan line 21. The scan enable levels transmitted on each scan line 21 have the same duration, and the time periods of the scan enable levels transmitted on different scan lines 21 do not overlap. In this embodiment of the invention, each sub-display stage T220 is refreshed line by line, and P sub-display stages T220 are repeated to achieve image display.

[0125] For example, refer to Figure 5 and Figure 24 , Figure 5 The duration of the single scan enable level within the display phase T22 is shown to be Figure 24 The display shows P times the duration of the single scan enable level within stage T22, where P is a positive integer greater than 1. For the same scan signal, in Figure 5During the period of a single scan enable level within the display phase T22 shown, it is equivalent to setting P consecutive scan signal pulses.

[0126] Figure 25 FIG. 4 is a top view structural schematic diagram of another display panel provided by an embodiment of the present invention. Figure 26 FIG. 5 is a driving timing diagram of another display panel provided by an embodiment of the present invention. Refer to Figure 1 、 Figure 25 and Figure 26 , the display phase T22 includes P sub-display phases T220 ( Figure 25 Exemplarily in FIG. 6, P = 2). In each sub-display phase T220, the same data signal Source is transmitted on the same data line 22. In the same sub-display phase T220, a scan enable level is transmitted on the same scan line 21, and the scan enable levels transmitted on each scan line 21 have the same duration, and the periods of the scan enable levels transmitted on different scan lines 21 do not overlap.

[0127] The scan signals include a first scan signal Gate1, a j-th scan signal Gatej,..., a k-th scan signal Gatek,..., an i-th scan signal Gatei, where 2 ≤ j < k, k ≤ i, and i is a positive integer greater than 1. The P sub-display phases T220 include a first sub-display phase T2201 and a second sub-display phase T2202. In the first sub-display phase T2201, during the period of the scan enable levels of the first scan signal Gate1 to the i-th scan signal Gatei, at least one of a data enable level and a data non-enable level is transmitted on the data line 22, and at least one of the data enable level and the data non-enable level is written into the pixel driving circuit, and then the pixel driving circuits of each row control the display gray level of the sub-pixels according to the magnitude of the data enable level or according to the data non-enable level. In the second sub-display phase T2202, during the period of the scan enable levels of the first scan signal Gate1 to the j-th scan signal Gatej, a data non-enable level is transmitted on the data line 22, and then the pixel driving circuits of the 1st to the j-th rows do not write a data enable level and do not change the display gray level of the sub-pixels. During the period of the scan enable levels of the j-th scan signal Gatej to the k-th scan signal Gatek ( Figure 26 Exemplarily in FIG. 7, taking k = i as an example), at least one of a data enable level and a data non-enable level is transmitted on the data line 22, and at least one of the data enable level and the data non-enable level is written into the pixel driving circuit, and then the pixel driving circuits of the j-th to the k-th rows control the display gray level of the sub-pixels according to the magnitude of the data enable level or according to the data non-enable level.

[0128] Exemplarily, refer to Figure 25 and Figure 26The first sub-display stage T2201 is located between the display preparation stage T21 and the second sub-display stage T2202. The second sub-display stage T2202 is located between the first sub-display stage T2201 and the second sub-display stage T222.

[0129] For example, refer to Figure 1 , Figure 25 and Figure 26 The display panel includes a fourth display area 104 and a fifth display area 105. Scan lines 21 in the fourth display area 104 transmit first scan signals Gate1 to the j-th scan signal Gatej, and scan lines 21 in the fifth display area 105 transmit the j-th scan signal Gatej to the k-th scan signal Gatek. Data signals are input to the display panel in sections, meaning that different sub-display stages T220 write data signals to different areas. The image displayed in the fourth display area 104 is determined by the data signals written in the first sub-display stage T2201, and the image displayed in the fifth display area 105 is jointly determined by the data signals written in the first sub-display stage T2201 and the second sub-display stage T2202.

[0130] It is understandable that when data signals are input to the display panel in sections and in batches, the number of sections of the display panel is denoted as Q, where Q is less than or equal to P, and Q is a positive integer greater than 1.

[0131] Figure 27 This is a driving timing diagram for another display panel provided in an embodiment of the present invention, with reference to... Figure 27 The absolute value of the data enable level in the display stage T22 is equal to the absolute value of the data enable level in the display preparation stage T21.

[0132] For example, refer to Figure 27 V0 = V1 = V3.

[0133] Figure 28 This is a top view schematic diagram of a display device provided in an embodiment of the present invention, with reference to... Figure 28 The display device includes a display panel and a driver chip 40. The driver chip 40 is electrically connected to the data line 22 and the scan line 21. The driver chip 40 provides a scan signal to the scan line 21 and a data signal source to the data line 22. Since the display device in this embodiment includes the display panel described in the above embodiment, it has the beneficial effects of the display panel, namely, reducing the time length of the display preparation stage and reducing the screen refresh time.

[0134] For example, the display device may include at least one of electronic billboards, computers, mobile phones, e-readers, etc.

[0135] For example, refer to Figure 28 The display device further includes a first lead 210 and a second lead 220. One end of the first lead 210 is electrically connected to the scan line 21, and the other end of the first lead 210 is electrically connected to the driver chip 40. The first lead 210 is configured to connect the scan line 21 and the driver chip 40. One end of the second lead 220 is electrically connected to the data line 22, and the other end of the second lead 220 is electrically connected to the driver chip 40. The second lead 220 is configured to connect the data line 22 and the driver chip 40.

[0136] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, combinations, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.

Claims

1. A display panel, characterized in that, It includes multiple scan lines and multiple data lines. The scan lines are configured to transmit scan signals, which include scan enable levels and scan disable levels. The data lines are configured to transmit data signals, which include data enable levels and data disable levels. The display panel includes a display cycle, which includes a display preparation stage and a display stage, wherein the display preparation stage is located before the display stage. The scan line extends along a first direction, and the scan line includes a first scan line electrically connected to a first pixel group and a second scan line electrically connected to a second pixel group. The first scan line and the second scan line are arranged along a second direction, and the second direction intersects the first direction. In the display preparation stage, the time period in which the scan enable level transmitted on the first scan line is located overlaps at least partially with the time period in which the scan enable level transmitted on the second scan line is located. The display preparation stage includes a reset stage and an oscillation stage; the display panel includes electrophoretic particles, in which the electrophoretic particles move to a preset position under the control of an electric field during the reset stage; and in the oscillation stage, the electrophoretic particles carrying different charges separate from each other in a changing electric field.

2. The display panel according to claim 1, characterized in that, During the display preparation phase, the time period in which the scan enable level transmitted on the first scan line occurs is the same as the time period in which the scan enable level transmitted on the second scan line occurs.

3. The display panel according to claim 1, characterized in that, Within the same display cycle, the write frequency of the enable level of the data signal during the oscillation phase is greater than the write frequency of the enable level of the data signal during the reset phase.

4. The display panel according to claim 1, characterized in that, The reset phase includes at least one sub-reset phase; The data enable level includes a first data enable level and a second data enable level with opposite polarities; The sub-reset phase includes a time period in which the first data enable level is located and / or a time period in which the second data enable level is located.

5. The display panel according to claim 4, characterized in that, During the sub-reset phase, the time period in which the scan enable level transmitted on the first scan line is located overlaps with the time period in which the scan enable level transmitted on the second scan line is located.

6. The display panel according to claim 4, characterized in that, The oscillation phase includes at least one sub-oscillation phase; The data enable level includes a third data enable level and a fourth data enable level with opposite polarities; The sub-oscillation phase includes multiple time periods in which the third data enable level is located and multiple time periods in which the fourth data enable level is located.

7. The display panel according to claim 6, characterized in that, During the sub-oscillation phase, the time period in which the scan enable level transmitted on the first scan line is located overlaps with the time period in which the scan enable level transmitted on the second scan line is located.

8. The display panel according to claim 6, characterized in that, Within the same display cycle, the duration of the oscillation phase is shorter than the duration of the reset phase.

9. The display panel according to claim 1, characterized in that, The display preparation phase includes a time period in which the scan enable level is located.

10. The display panel according to claim 1, characterized in that, The display preparation phase includes multiple time periods in which the scan enable level is located.

11. The display panel according to claim 10, characterized in that, The duration of one scan enable level in the display preparation phase is equal to the duration of one scan enable level in the display phase.

12. The display panel according to claim 3, characterized in that, Both the reset phase and the oscillation phase include at least one time period in which the scan enable level is located.

13. The display panel according to claim 6, characterized in that, The sub-reset phase of the (M+1)th display cycle is adjacent to the display phase in the Mth display cycle, where M is a positive integer.

14. The display panel according to claim 3, characterized in that, Within the same display cycle, the oscillation phase is located between the reset phase and the display phase.

15. The display panel according to claim 6, characterized in that, The sub-reset phase includes a first sub-reset phase and a second sub-reset phase; The sub-oscillation phase includes a first sub-oscillation phase; Within the same display preparation phase, the first sub-oscillation phase is located between the first sub-reset phase and the second sub-reset phase, and the second sub-reset phase is located between the first sub-oscillation phase and the display phase.

16. The display panel according to claim 15, characterized in that, The sub-oscillation phase also includes a second sub-oscillation phase; Within the same display preparation phase, the second sub-oscillation phase is located between the second sub-reset phase and the display phase.

17. The display panel according to claim 15, characterized in that, The first sub-reset phase includes a balancing period; The polarity of the data enable level during the balance period of the (M+1)th display cycle is the same as the polarity of the data enable level during the display phase of the Mth display cycle. The second sub-reset phase includes a first time period and a second time period. The first time period is located between the second time period and the first sub-reset phase. The polarity of the data enable level during the first time period is opposite to the polarity of the data enable level during the balance time period. The polarity of the data enable level during the second time period is the same as the polarity of the data enable level during the balance time period. Within the same display cycle, the polarity of the data enable level during the display phase is opposite to the polarity of the data enable level during the balance period.

18. The display panel according to claim 17, characterized in that, The duration of the balancing period is shorter than the duration of the second period.

19. The display panel according to claim 15, characterized in that, The first sub-reset phase includes a third time period and a fourth time period, with the fourth time period located between the third time period and the first sub-oscillation phase; the second sub-reset phase includes a fifth time period and a sixth time period, with the fifth time period located between the sixth time period and the first sub-oscillation phase; The polarity of the data enable level in the third time period is the same as that in the fifth time period, and opposite to that in the fourth time period. The polarity of the data enable level during the fourth time period is the same as the polarity of the data enable level during the sixth time period; The ratio of the duration of the third time period to the duration of the fourth time period is not equal to the ratio of the duration of the fifth time period to the duration of the sixth time period.

20. The display panel according to claim 4, characterized in that, Within the same display cycle, the number of sub-reset stages is less than or equal to three.

21. The display panel according to claim 4, characterized in that, Within the same display cycle, the sub-reset phase is adjacent to the display phase.

22. The display panel according to claim 4, characterized in that, In the (N+1)th display cycle, the sub-reset phase that is closest in time to the display phase in the Nth display cycle includes the balance period, where N is a positive integer; The polarity of the data enable level during the balance period is the same as the polarity of the data enable level during the display phase in the previous display cycle.

23. The display panel according to claim 22, characterized in that, The sub-reset stage further includes a leveling period, during which the data line transmits the data non-enable level.

24. The display panel according to claim 23, characterized in that, In the (N + 1)-th display cycle, the sub-reset stage that is closest in time distance to the display stage in the N-th display cycle includes the leveling period.

25. The display panel according to claim 1, characterized in that, In the same display cycle, an interval stage is provided between the display preparation stage and the display stage; During the interval stage, the scan non-enable level is transmitted on the scan line, and the data non-enable level is transmitted on the data line.

26. The display panel according to claim 1, characterized in that, The display stage includes an interval stage, which is located between the scan enable levels transmitted on two scan lines; During the interval stage, the scan non-enable level is transmitted on the scan line, and the data non-enable level is transmitted on the data line.

27. The display panel according to claim 1, characterized in that, The absolute value of the data enable level in the display stage is less than the absolute value of the data enable level in the display preparation stage.

28. The display panel according to claim 1, characterized in that, It includes a first display area and a second display area; The display cycle includes a first type of display cycle and a second type of display cycle; during the display preparation stage of the first type of display cycle, the data line transmits at least one of the data non-enable level and the data enable level; During the display preparation stage and the display stage of the second type of display cycle, the data line transmits the data non-enable level; The first display area includes the first type of display cycle, and the second display area includes the second type of display cycle.

29. The display panel according to claim 1, characterized in that, It includes a first display area and a third display area; The display cycle includes a first type of display cycle and a third type of display cycle; during the display preparation stage of the first type of display cycle, the data line transmits at least one of the data non-enable level and the data enable level; During the display preparation stage of the third type of display cycle, a scan enable level is transmitted on the same scan line, and the scan enable levels transmitted on each scan line have the same duration; The first display area includes the first type of display cycle, and the third display area includes the third type of display cycle.

30. The display panel according to claim 1, characterized in that, It includes a first substrate and a second substrate; The scan line is located on at least one of the first substrate and the second substrate; The data line is located on at least one of the first substrate and the second substrate; The electrophoretic particles are located between the first substrate and the second substrate.

31. The display panel according to claim 1, characterized in that, It includes a pixel driving circuit, and the pixel driving circuit includes a first functional transistor; The scan line is electrically connected to the gate of the first functional transistor and is configured to control the conduction or cut-off of the first functional transistor.

32. The display panel according to claim 1, characterized in that, The display stage includes P sub-display stages, where P is a positive integer greater than 1; In each sub-display stage, the same data signal is transmitted on the same data line.

33. The display panel according to claim 32, characterized in that, The scan signal includes a first scan signal, a j-th scan signal, ……, a k-th scan signal, ……, an i-th scan signal, where 2 ≤ j < k, k ≤ i, and i is a positive integer greater than 1; The P sub-display stages include a first sub-display stage and a second sub-display stage; in the first sub-display stage, during the time period when the scan enable level of the first scan signal to the i-th scan signal is located, at least one of the data transmission data enable level and the data disable level is transmitted on the data line. During the second sub-display phase, during the period when the scan enable level of the first scan signal to the j-th scan signal is present, the data transmission level on the data line is disabled; during the period when the scan enable level of the j-th scan signal to the k-th scan signal is present, at least one of the data transmission enable level and the data disable level is transmitted on the data line.

34. The display panel according to claim 1, characterized in that, During the display phase, a scan enable level is transmitted on the same scan line, and the scan enable levels transmitted on each scan line have the same duration.

35. The display panel according to claim 1, characterized in that, During the display phase, the time periods of the scan enable levels transmitted on different scan lines do not overlap.

36. A display device, characterized in that, The display panel includes any one of claims 1-35, and a driver chip, the driver chip being electrically connected to a data line and a scan line.

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