Electrostatic protection circuit and chip

Abstract

The application provides an electrostatic protection circuit and a chip. The chip comprises at least one probe point and a ground pad. The electrostatic protection circuit comprises a monitoring unit, a discharge unit and a controllable voltage division unit. The monitoring unit is connected to the at least one probe point, the discharge unit and the controllable voltage division unit respectively, and is used to generate a first trigger signal when there is an electrostatic pulse in any probe point. The discharge unit is connected between the at least one probe point and the ground pad, and is used to form at least one path under the control of the first trigger signal, and discharge the electrostatic charge to the ground pad. The controllable voltage division unit is connected to the discharge unit, and is used to share part of the voltage of the first trigger signal for the discharge unit. The application can effectively protect the ESD phenomenon between the probe points of the chip, thereby reducing the risk of chip damage and improving the yield of the chip.

Description

Technical Field

[0001] This application relates to, but is not limited to, an electrostatic discharge protection circuit and chip. Background Technology

[0002] During the chip manufacturing process, ESD (Electro-Static Discharge) phenomena can occur, which may cause irreversible damage to the chip and reduce its yield.

[0003] To prevent ESD (electrostatic discharge) phenomena, electrostatic protection circuits are required. However, current technologies lack effective protection against ESD phenomena between chip probe points. Summary of the Invention

[0004] This application aims to provide an electrostatic discharge (ESD) protection circuit and chip that can effectively protect against ESD phenomena between chip probe points, thereby reducing the risk of chip damage and improving chip yield.

[0005] The technical solution of this application is implemented as follows:

[0006] This application provides an electrostatic discharge (ESD) protection circuit for a chip. The chip includes at least one probe point and a grounding pad. The ESD protection circuit includes a monitoring unit, a discharge unit, and a controllable voltage divider unit.

[0007] The monitoring unit is connected to the at least one probe point, the discharge unit and the controllable voltage divider unit respectively, and is used to generate a first trigger signal when there is an electrostatic pulse at any probe point;

[0008] The discharge unit is connected between the at least one probe point and the grounding pad, and is used to form at least one path under the control of the first trigger signal to discharge electrostatic charge to the grounding pad;

[0009] The controllable voltage divider unit is connected to the discharge unit and is used to share part of the voltage of the first trigger signal with the discharge unit.

[0010] This application also provides a chip that includes the electrostatic discharge protection circuit described in the above solution.

[0011] Therefore, this application provides an electrostatic discharge (ESD) protection circuit and chip. The ESD protection circuit includes a monitoring unit, a discharge unit, and a controllable voltage divider unit. The monitoring unit is connected to at least one probe point, the discharge unit, and the controllable voltage divider unit, respectively, and generates a first trigger signal when an ESD pulse occurs at any probe point. The discharge unit is connected between at least one probe point and a ground pad, and forms at least one path under the control of the first trigger signal to discharge the ESD charge to the ground pad. The controllable voltage divider unit is connected to the discharge unit and shares part of the voltage of the first trigger signal with the discharge unit. The monitoring unit generates the first trigger signal under ESD pulse triggering, forming a path in the discharge unit to discharge the ESD charge at the probe point. This effectively protects against ESD phenomena between chip probe points. Furthermore, since the first trigger signal may have a large voltage peak, the controllable voltage divider unit shares part of the voltage of the first trigger signal with the discharge unit, preventing the first trigger signal from damaging the discharge unit, thereby reducing the risk of chip damage and improving chip yield. Attached Figure Description

[0012] Figure 1 This is a schematic diagram of the structure of an electrostatic protection circuit provided in an embodiment of this application. Figure 1 ;

[0013] Figure 2 This is a schematic diagram of the structure of an electrostatic protection circuit provided in an embodiment of this application. Figure 2 ;

[0014] Figure 3 This is a schematic diagram of the structure of an electrostatic protection circuit provided in an embodiment of this application. Figure 3 ;

[0015] Figure 4 This is a schematic diagram of the structure of an electrostatic protection circuit provided in an embodiment of this application. Figure 4 ;

[0016] Figure 5 This is a schematic diagram of the structure of a chip provided in an embodiment of this application. Detailed Implementation

[0017] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application are further described in detail below with reference to the accompanying drawings and embodiments. The described embodiments should not be regarded as limitations on this application. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0018] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0019] If the application documents contain similar descriptions such as "first / second", the following explanation shall be added: In the following description, the terms "first / second / third" are used only to distinguish similar objects and do not represent a specific order of objects. It is understood that "first / second / third" may be interchanged in a specific order or sequence where permitted, so that the embodiments of this application described herein can be implemented in an order other than that illustrated or described herein.

[0020] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0021] ESD refers to the phenomenon where static electricity accumulated in a person, device, or component becomes conductive due to a discharge path formed by contact, generating an extremely high instantaneous voltage. In testing unpackaged bare chips, multiple probe pads are typically used as test interfaces. The testing equipment connects to the bare chip through these probe pads, transmitting test signals to the chip for parameter testing.

[0022] Although probe points differ from bonding pads, and no pins are set for probe points on packaged chips, meaning that the probe points on packaged chips are not at risk of ESD, it is still essential to add ESD protection between probe points because wafers are also prone to ESD during testing.

[0023] Because the instantaneous voltage generated by ESD is relatively high, using a conventional power clamp circuit can cause the gate oxide layer of the MOSFET to break down, resulting in permanent damage to the device. Therefore, it is necessary to design a new electrostatic protection circuit.

[0024] Figure 1 This is a schematic diagram of the electrostatic discharge (ESD) protection circuit for a chip provided in an embodiment of this application, as shown below. Figure 1As shown, the chip includes a ground pad VSS and at least one probe point P1 to Pn. The electrostatic discharge protection circuit 01 includes a monitoring unit 101, a discharge unit 102, and a controllable voltage divider unit 103. The monitoring unit 101 is connected to the discharge unit 102, the controllable voltage divider unit 103, and at least one probe point P1 to Pn, and is used to generate a first trigger signal when there is an electrostatic pulse at any probe point. The discharge unit 102 is connected between the ground pad VSS and at least one probe point, and is used to form at least one path under the control of the first trigger signal to discharge electrostatic charge to the ground pad VSS. The controllable voltage divider unit 103 is connected to the discharge unit and is used to share part of the voltage of the first trigger signal with the discharge unit 102.

[0025] In this embodiment of the application, the chip includes at least one probe point P1 to Pn. During the testing of the unpackaged chip, the probe of the test machine will contact one or more of the probe points P1 to Pn to transmit test signals to the chip for parameter testing.

[0026] Before chip packaging, if ESD occurs at any of the probe points P1 to Pn, an electrostatic pulse will be generated at that probe point, that is, a short-term fluctuating voltage will be generated at that probe point. The peak value of this voltage is determined by the amount of electrostatic charge that caused the ESD, and can be much greater than the breakdown voltage of the device inside the chip, thus potentially causing permanent damage to the device.

[0027] In this embodiment, the monitoring unit 101, when subjected to an electrostatic pulse, can generate a first trigger signal. When the peak voltage of the electrostatic pulse is large, the first trigger signal also has a large peak voltage. Therefore, a controllable voltage divider unit 103 is needed to share part of the voltage of the first trigger signal with the discharge unit 102 to prevent the first trigger signal from damaging the discharge unit 102.

[0028] Understandably, the monitoring unit 101 generates a first trigger signal under the triggering of an electrostatic pulse, forming a path in the discharge unit 102 to discharge the electrostatic charge at the probe point. In this way, it can effectively protect against ESD phenomena between chip probe points.

[0029] Meanwhile, since the first trigger signal may have a large voltage peak, the controllable voltage divider unit 103 shares part of the voltage of the first trigger signal with the discharge unit 102, which can prevent the first trigger signal from damaging the discharge unit 102, thereby reducing the risk of chip damage and improving the chip yield.

[0030] In some embodiments of this application, the discharge unit 102 includes at least one transistor; the controllable voltage divider unit 103 includes a first voltage divider element and a second voltage divider element; the first voltage divider element and the second voltage divider element are used to share part of the voltage of the first trigger signal for at least one transistor, and each has a first terminal and a second terminal; wherein the first terminal of the first voltage divider element and the second voltage divider element are respectively connected to the gate of at least one transistor; the second terminal of the first voltage divider element is connected to the monitoring unit 101, and the second terminal of the second voltage divider element is connected to the ground terminal VSS.

[0031] In some embodiments of this application, such as Figure 2 As shown, at least one transistor includes a second transistor M2 and a fourth transistor M4; a first voltage divider element includes a first resistor R1 and a third resistor R3, and a second voltage divider element includes a second resistor R2 and a fourth resistor R4; wherein, the first terminal of the first resistor R1 and the first terminal of the second resistor R2 are both connected to the gate of the second transistor M2, and the first terminals of the third resistor R3 and the fourth resistor R4 are both connected to the gate of the fourth transistor M4; the second terminals of the first resistor R1 and the third resistor R3 are respectively connected to the monitoring unit 101. The second terminals of the second resistor R2 and the fourth resistor R4 are both connected to the ground terminal VSS.

[0032] like Figure 2 As shown, the discharge unit 102 further includes a first transistor M1 and a third transistor M3; wherein the drain of the first transistor M1 and the drain of the third transistor M3 are respectively connected to at least one probe point. The gate of the first transistor M1 and the gate of the third transistor M3 are respectively connected to the monitoring unit 101. The source of the first transistor M1 is connected to the drain of the second transistor M2. The source of the third transistor M3 is connected to the drain of the fourth transistor M4.

[0033] In this embodiment, the gate of the second transistor M2 is connected to the junction of the first resistor R1 and the second resistor R2. Therefore, the gate voltage V1 of the second transistor M2 is affected by the resistance values ​​of the first resistor R1 and the second resistor R2. That is, the ratio of the resistance values ​​of the first resistor R1 and the second resistor R2 determines the voltage division ratio of the gate voltage V1. Similarly, the gate of the fourth transistor M4 is connected between the third resistor R3 and the fourth resistor R4. Therefore, the ratio of the resistance values ​​of the third resistor R3 and the fourth resistor R4 determines the voltage division ratio of the gate voltage V2.

[0034] The monitoring unit 101 transmits a first trigger signal to the controllable voltage divider unit 103, which triggers the gate voltages V1 and V2 to rise. By adjusting the resistance values ​​of the first resistor R1 and the second resistor R2 to a suitable range, the risen gate voltage V1 can be made greater than the turn-on voltage of the second transistor M2 and less than the breakdown voltage of the second transistor M2. In this way, the source and drain of the second transistor M2 are turned on to discharge electrostatic charge to the ground pad VSS, while preventing the gate oxide layer of the second transistor M2 from breaking down.

[0035] Similarly, by adjusting the values ​​of the third resistor R3 and the fourth resistor R4 to a suitable range, the increased gate voltage V2 can reach the turn-on voltage of the fourth transistor M4, while remaining below its breakdown voltage. This ensures that the source and drain of the fourth transistor M4 are turned on to discharge static charge to the ground pad VSS, while also preventing gate oxide breakdown in the fourth transistor M4.

[0036] It should be noted that the first and second voltage divider elements may include other implementations; for example, the first and second voltage divider elements may be composed of multiple sub-resistors connected in series or parallel, and the equivalent resistance value can be adjusted by changing the number of series or parallel connections; or, for example, the first and second voltage divider elements may be adjustable resistors, and the resistance can be adjusted by sliding a pointer. The above implementations, as well as other simple variations or substitutions made based on the embodiments of this application, should all be considered within the scope of protection of this application.

[0037] Understandably, by adjusting the parameters of each voltage divider element in the controllable voltage divider unit 103, the voltage division ratio of the transistor gate voltage in the discharge unit 102 can be controlled, keeping the transistor gate voltage within a suitable range. This ensures that the transistor in the discharge unit 102 can turn on to form a circuit when ESD occurs, while also preventing gate oxide breakdown in the transistor in the discharge unit 102, thus reducing the risk of chip damage.

[0038] In some embodiments of this application, the monitoring unit 101 includes: a capacitor module, used to generate a first trigger signal through resistor-capacitor coupling when there is an electrostatic pulse at any probe point; wherein, the first end of the capacitor module is connected to at least one probe point, the second end of the capacitor module is connected to the discharge unit 102, and the third end of the capacitor module is connected to the controllable voltage divider unit 103.

[0039] In some embodiments of this application, such as Figure 3As shown, the capacitor module includes: a first capacitor C1, a second capacitor C2, a third capacitor C3, and a fourth capacitor C4; at least one probe point includes: a first probe point P1 and a second probe point P2; wherein, the second end of the first capacitor C1 and the second end of the second capacitor C2 are both connected to the gate of the first transistor M1, the second end of the third capacitor C3 and the second end of the fourth capacitor C4 are both connected to the gate of the third transistor M3, and the connection end of the first capacitor C1 and the second capacitor C2, as well as the connection end of the third capacitor C3 and the fourth capacitor C4, serve as the second end of the capacitor module.

[0040] The first terminal of the first capacitor C1 and the first terminal of the third capacitor C3 are each connected to at least one probe point. Specifically, the drain of the first transistor M1 and the first terminal of the first capacitor C1 are both connected to the first probe point P1, and the drain of the third transistor M3 and the first terminal of the third capacitor C3 are both connected to the second probe point P2. The first terminals of the first capacitor C1 and the first terminals of the third capacitor C3 serve as the first terminals of the capacitor module.

[0041] The first terminals of the second capacitor C2 and the fourth capacitor C4 are respectively connected to the controllable voltage divider unit 103. Specifically, the first terminal of the second capacitor C2 is connected to the second terminal of the first resistor R1, and the first terminal of the fourth capacitor C4 is connected to the second terminal of the third resistor R3. The first terminals of the second capacitor C2 and the fourth capacitor C4 serve as the third terminals of the capacitor module.

[0042] In this embodiment, during the testing of the unpackaged chip, the first probe point P1 and the second probe point P2 can maintain a fixed voltage, such as 6V for the first probe point P1 and 3V for the second probe point P2. At this time, the first capacitor C1, the second capacitor C2, and the third capacitor C3 are disconnected, thus the second transistor M2, the third transistor M3, and the fourth transistor M4 are in the off state; the gate voltage V3 of the first transistor M1 is 3V, and the source voltage V5 of the first transistor M1 is clamped at (3V-Vth), where Vth is the turn-on voltage of the first transistor M1. Thus, the electrostatic discharge protection circuit does not form a closed circuit and does not function.

[0043] In this embodiment, when the first probe point P1 contacts electrostatic charge and generates an electrostatic pulse, since the electrostatic pulse is a short-lived voltage fluctuation, equivalent to an AC voltage, the first capacitor C1 can conduct, increasing the gate voltage V3 of the first transistor M1. When the gate voltage V3 is increased to the turn-on voltage of the first transistor M1, the source and drain of the first transistor M1 are turned on. Simultaneously, the short-term increase in the gate voltage V3 is also equivalent to an AC voltage, therefore, the second capacitor C2 can conduct, increasing the gate voltage V1 of the second transistor M2. When the gate voltage V1 is increased to the turn-on voltage of the second transistor M2, the source and drain of the second transistor M2 are turned on. In this way, the first transistor M1 and the second transistor M2 form a path, discharging the electrostatic charge from the first probe point P1 to the ground pad VSS.

[0044] On the other hand, a short-term increase in gate voltage V3 can turn on the third capacitor C3, thereby increasing the gate voltage V4 of the third transistor M3. When the gate voltage V4 reaches the turn-on voltage of the third transistor M3, the source and drain of the third transistor M3 are turned on. Simultaneously, a short-term increase in gate voltage V4 can turn on the fourth capacitor C4, thereby increasing the gate voltage V2 of the fourth transistor M4. When the gate voltage V2 reaches the turn-on voltage of the fourth transistor M4, the source and drain of the fourth transistor M4 are turned on. In this way, the first capacitor C1, the third transistor M3, and the fourth transistor M4 form another path, discharging electrostatic charge from the first probe point P1 to the ground pad VSS.

[0045] In this embodiment, when the second probe point P2 contacts electrostatic charge and generates an electrostatic pulse, since the electrostatic pulse is a short-lived voltage fluctuation, equivalent to an AC voltage, the third capacitor C3 can conduct, increasing the gate voltage V4 of the third transistor M3. When the gate voltage V4 is increased to the turn-on voltage of the third transistor M3, the source and drain of the third transistor M3 are turned on. Simultaneously, the short-term increase in the gate voltage V4 is also equivalent to an AC voltage, therefore, the fourth capacitor C4 can conduct, increasing the gate voltage V2 of the fourth transistor M4. When the gate voltage V2 is increased to the turn-on voltage of the fourth transistor M4, the source and drain of the fourth transistor M4 are turned on. Thus, the third transistor M3 and the fourth transistor M4 form a path, discharging the electrostatic charge from the second probe point P2 to the ground pad VSS.

[0046] In this embodiment, the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4 can all be NMOS transistors, used to discharge positive electrostatic charges at the first probe point P1 and the second probe point P2. Alternatively, the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4 can all be PMOS transistors, used to discharge negative electrostatic charges at the first probe point P1 and the second probe point P2.

[0047] In this embodiment, since the electrostatic pulse is a short-lived voltage fluctuation, its equivalent AC voltage has a relatively high frequency, and the capacitive reactance when the capacitor is conducting is inversely proportional to the frequency of the electrical signal. Therefore, when the first capacitor C1 and the third capacitor C3 are conducting, their capacitive reactance is small. As a result, the voltage drop across the first capacitor C1 and the third capacitor C3 is small, while the voltage drop across the gate voltages V3 and V4 is large, making it easier to reach the turn-on voltage of the first transistor M1 and the third transistor M3.

[0048] Understandably, by utilizing the electrical characteristics of capacitors, the monitoring unit 101 can remain in an open state when a constant detection voltage is applied to the probe point, thus preventing the electrostatic discharge protection circuit from affecting the chip testing process; while when ESD occurs at the probe point, the monitoring unit 101 can be turned on to discharge the electrostatic charge and protect the chip from damage.

[0049] Meanwhile, when ESD occurs, the capacitive reactance of the capacitor is small, which makes the voltage division ratio of the transistor gate voltage higher, making it easier to reach the turn-on voltage to form a discharge path, and helps to avoid a large voltage difference between the transistor gate and drain, thereby preventing the transistor from being reverse-broken.

[0050] In some embodiments of this application, the chip further includes a power pad. The monitoring unit 101, also connected to the power pad, is further configured to generate a second trigger signal when an electrostatic pulse occurs on the power pad. The discharge unit 102, also connected between the power pad and the ground pad, is further configured to be turned on under the control of the second trigger signal to discharge electrostatic charge to the ground pad.

[0051] In some embodiments of this application, such as Figure 4 As shown, the monitoring unit 101 also includes a fifth capacitor C5 and a fifth resistor R5; the discharge unit 102 also includes a fifth transistor M5.

[0052] In this configuration, the first terminal of the fifth capacitor C5 is connected to the power pad VDD, the second terminal of the fifth capacitor C5 is connected to the first terminal of the fifth resistor R5, and the second terminal of the fifth resistor R5 is connected to the ground pad VSS. The fifth capacitor C5 is used to generate a second trigger signal through RC coupling when there is an electrostatic pulse on the power pad VDD.

[0053] The drain of the fifth transistor M5 is connected to the power pad VDD; the source of the fifth transistor M5 is connected to the ground pad VSS; the second terminal of the fifth capacitor C5 and the first terminal of the fifth resistor R5 are also connected to the gate of the fifth transistor M5. The fifth transistor M5 is used to turn on under the control of the second trigger signal to discharge electrostatic charge to the ground pad.

[0054] In this embodiment, when the power pad VDD comes into contact with electrostatic charge and generates an electrostatic pulse, since the electrostatic pulse is a short-lived voltage fluctuation, equivalent to an AC voltage, the fifth capacitor C5 can conduct, increasing the gate voltage V6 of the fifth transistor M5. When the gate voltage V6 is increased to the turn-on voltage of the fifth transistor M5, the source and drain of the fifth transistor M5 conduct, forming a path to discharge the electrostatic charge from the power pad VDD to the ground pad VSS.

[0055] In this embodiment, when the first probe point P1 contacts electrostatic charge and generates an electrostatic pulse, the first capacitor C1 and the third capacitor C3 are turned on, and the gate voltage V4 is briefly increased. This turns on the fifth capacitor C5, increasing the gate voltage V6 of the fifth transistor M5. When the gate voltage V6 reaches the turn-on voltage of the fifth transistor M5, the source and drain of the fifth transistor M5 are turned on. Thus, the first capacitor C1, the third capacitor C3, and the fifth transistor M5 form a circuit, discharging the electrostatic charge from the first probe point P1 to the ground pad VSS.

[0056] Similarly, when the second probe point P2 comes into contact with electrostatic charge and generates an electrostatic pulse, it will turn on the third capacitor C3 and briefly boost the gate voltage V4. This will turn on the fifth capacitor C5, boosting the gate voltage V6 of the fifth transistor M5. When the gate voltage V6 is boosted to the turn-on voltage of the fifth transistor M5, the source and drain of the fifth transistor M5 will turn on. In this way, the third capacitor C3 and the fifth transistor M5 also form a circuit, discharging the electrostatic charge from the second probe point P2 to the ground pad VSS.

[0057] In this embodiment, the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, and the fifth transistor M5 can all be NMOS, which are used to discharge positive electrostatic charges at the first probe point P1, the second probe point P2, and the power pad VDD.

[0058] It is understandable that when ESD occurs on the power pad VDD, the fifth capacitor C5 and the fifth resistor R5 generate a second trigger signal, which triggers the fifth transistor M5 to conduct and form a path to discharge the electrostatic charge on the power pad VDD.

[0059] Meanwhile, when ESD occurs at the probe point, the fifth transistor M5 can also be triggered to conduct, providing an additional path and thus improving the discharge efficiency of electrostatic charge.

[0060] This application also provides a chip 02, such as... Figure 5 As shown, chip 02 includes electrostatic discharge protection circuit 01.

[0061] In some embodiments of this application, chip 02 includes at least a semiconductor memory.

[0062] In some embodiments of this application, the semiconductor memory includes at least dynamic random access memory (DRAM).

[0063] It should be noted that, in this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0064] The sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments. The methods disclosed in the several method embodiments provided in this application can be arbitrarily combined to obtain new method embodiments without conflict. The features disclosed in the several product embodiments provided in this application can be arbitrarily combined to obtain new product embodiments without conflict. The features disclosed in the several method or device embodiments provided in this application can be arbitrarily combined to obtain new method or device embodiments without conflict.

[0065] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. An electrostatic discharge (ESD) protection circuit for a chip, characterized in that, The chip includes a grounding pad and at least one probe point, and the electrostatic discharge protection circuit includes: a monitoring unit, a discharge unit, and a controllable voltage divider unit; wherein... The monitoring unit is connected to the discharge unit, the controllable voltage divider unit and the at least one probe point respectively, and is used to generate a first trigger signal when there is an electrostatic pulse at any probe point; The discharge unit is connected between the grounding pad and the at least one probe point, and is used to form at least one path under the control of the first trigger signal to discharge electrostatic charge to the grounding pad; The controllable voltage divider unit is connected to the discharge unit and is used to share part of the voltage of the first trigger signal with the discharge unit. The discharge unit includes at least one transistor; the controllable voltage divider unit includes a first voltage divider element and a second voltage divider element; the first voltage divider element and the second voltage divider element are used to share part of the voltage of the first trigger signal for the at least one transistor, and each element has a first terminal and a second terminal; wherein... The first ends of the first voltage divider element and the second voltage divider element are respectively connected to the gate of the at least one transistor, the second end of the first voltage divider element is connected to the monitoring unit, and the second end of the second voltage divider element is connected to the ground terminal; The at least one transistor includes: a second transistor and a fourth transistor; the first voltage divider element includes: a first resistor and a third resistor, and the second voltage divider element includes: a second resistor and a fourth resistor; wherein... The first end of the first resistor and the first end of the second resistor are both connected to the gate of the second transistor, and the first end of the third resistor and the first end of the fourth resistor are both connected to the gate of the fourth transistor. The second end of the first resistor and the second end of the third resistor are respectively connected to the monitoring unit; the second end of the second resistor and the second end of the fourth resistor are both connected to the grounding terminal.

2. The circuit according to claim 1, characterized in that, The discharge unit further includes: a first transistor and a third transistor; The drain of the first transistor and the drain of the third transistor are respectively connected to the at least one probe point; The gate of the first transistor and the gate of the third transistor are respectively connected to the monitoring unit; The source of the first transistor is connected to the drain of the second transistor; the source of the third transistor is connected to the drain of the fourth transistor.

3. The circuit according to claim 2, characterized in that, The monitoring unit includes a capacitor module, used to generate the first trigger signal through resistor-capacitor coupling when there is an electrostatic pulse at any probe point; The first end of the capacitor module is connected to the at least one probe point, the second end of the capacitor module is connected to the discharge unit, and the third end of the capacitor module is connected to the controllable voltage divider unit.

4. The circuit according to claim 3, characterized in that, The capacitor module includes: a first capacitor, a second capacitor, a third capacitor, and a fourth capacitor; The first terminal of the first capacitor and the first terminal of the third capacitor are respectively connected to the at least one probe point, and the first terminal of the first capacitor and the first terminal of the third capacitor serve as the first terminal of the capacitor module. The second terminals of the first capacitor and the second capacitor are both connected to the gate of the first transistor, and the second terminals of the third capacitor and the fourth capacitor are both connected to the gate of the third transistor. The connection terminals of the first capacitor and the second capacitor, as well as the connection terminals of the third capacitor and the fourth capacitor, serve as the second terminals of the capacitor module. The first terminal of the second capacitor and the first terminal of the fourth capacitor are respectively connected to the controllable voltage divider unit, and the first terminal of the second capacitor and the first terminal of the fourth capacitor serve as the third terminal of the capacitor module.

5. The circuit according to claim 4, characterized in that, The at least one probe point includes: a first probe point and a second probe point; The drain of the first transistor and the first terminal of the first capacitor are both connected to the first probe point; The drain of the third transistor and the first terminal of the third capacitor are both connected to the second probe point.

6. The circuit according to claim 4, characterized in that, The first terminal of the second capacitor is connected to the second terminal of the first resistor; the first terminal of the fourth capacitor is connected to the second terminal of the third resistor.

7. The circuit according to claim 1, characterized in that, The chip also includes power pads; The monitoring unit is also connected to the power pad and is also used to generate a second trigger signal when there is an electrostatic pulse on the power pad. The discharge unit is also connected between the power pad and the ground pad, and is also used to conduct under the control of the second trigger signal to discharge electrostatic charge to the ground pad.

8. The circuit according to claim 7, characterized in that, The monitoring unit also includes: a fifth capacitor and a fifth resistor; The first terminal of the fifth capacitor is connected to the power pad; the second terminal of the fifth capacitor is connected to the first terminal of the fifth resistor; the second terminal of the fifth resistor is connected to the ground pad; wherein... The fifth capacitor is used to generate the second trigger signal through RC coupling when there is an electrostatic pulse on the power pad.

9. The circuit according to claim 8, characterized in that, The discharge unit further includes: a fifth transistor; The drain of the fifth transistor is connected to the power pad; the source of the fifth transistor is connected to the ground pad; the second terminal of the fifth capacitor and the first terminal of the fifth resistor are both connected to the gate of the fifth transistor; wherein, The fifth transistor is turned on under the control of the second trigger signal to discharge the electrostatic charge to the grounding pad.

10. The circuit according to claim 2, characterized in that, The first transistor, the second transistor, the third transistor, and the fourth transistor are all NMOS.

11. The circuit according to claim 9, characterized in that, The second transistor, the fourth transistor, and the fifth transistor are all NMOS.

12. A chip, characterized in that, Includes the electrostatic discharge protection circuit as described in any one of claims 1 to 11.

13. The chip according to claim 12, characterized in that, The chip includes at least a semiconductor memory.

14. The chip according to claim 13, characterized in that, The semiconductor memory includes at least dynamic random access memory (DRAM).

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