Semiconductor structure and method of manufacturing the same

Abstract

The embodiment of the present disclosure relates to the semiconductor field, and provides a semiconductor structure and a manufacturing method thereof, which comprises the following steps: providing a substrate, a gate dielectric film on the surface of the substrate, and a gate conductive layer on part of the surface of the gate dielectric film; forming an insulating layer covering the exposed surface of the gate dielectric film, the top surface and the side surface of the gate conductive layer; dry etching the insulating layer and the gate dielectric film to expose part of the substrate, and retaining the insulating layer on the side surface of the gate conductive layer as a first side wall and the remaining gate dielectric film as a first gate dielectric layer; performing cleaning treatment on the first side wall and the substrate to remove part of the width of the first gate dielectric layer, and retaining the remaining first gate dielectric layer as a second gate dielectric layer, and the first side wall, the second gate dielectric layer and the substrate form a gap, wherein the width of the gap is smaller than the maximum width of the first side wall; etching to remove the first side wall directly above the gap, and retaining the remaining first side wall as a second side wall. At least the leakage of the semiconductor structure can be reduced.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to the field of semiconductor, and in particular, to a semiconductor structure and a manufacturing method thereof. BACKGROUND

[0002] In modern process Metal-Oxide-Semiconductor (MOS) transistor structure, when the device channel size enters the micron era, in the process of active operation of the device, the critical voltage will be reduced due to the barrier near the junction of high concentration drain region and well region under the action of high drain bias, causing the drain-induced barrier lowering (DIBL) effect, so that the short channel effect becomes more serious, and therefore the lightly doped drain (LDD) design is introduced.

[0003] However, the process method for manufacturing the lightly doped drain structure still has certain problems. SUMMARY

[0004] Embodiments of the present disclosure provide a manufacturing method of a semiconductor structure, which at least reduces the leakage of the semiconductor structure.

[0005] According to some embodiments of the present disclosure, the present disclosure provides a manufacturing method of a semiconductor structure, which includes: providing a substrate, a gate dielectric film located on the surface of the substrate, and a gate conductive layer located on part of the surface of the gate dielectric film; forming an insulating layer, which covers the exposed surface of the gate dielectric film of the gate conductive layer, and also covers the top surface and side surface of the gate conductive layer; using a dry etching process to etch the insulating layer and the gate dielectric film, to expose part of the substrate, and to retain the insulating layer located on the side surface of the gate conductive layer as a first side wall, and the remaining gate dielectric film as a first gate dielectric layer; performing a cleaning process on the first side wall and the substrate, in which part of the width of the first gate dielectric layer is removed, the remaining first gate dielectric layer is used as a second gate dielectric layer, and the first side wall, the second gate dielectric layer, and the substrate form a gap, wherein the width of the gap is less than the maximum width of the first side wall; using an etching process to etch and remove the first side wall located directly above the gap, and the remaining first side wall is used as a second side wall.

[0006] According to some other embodiments of the present disclosure, the etching selectivity of the cleaning process to the first side wall and the first gate dielectric layer is greater than or equal to 50.

[0007] According to some other embodiments of the present disclosure, the etching selectivity is between 100-200.

[0008] According to some embodiments of the present disclosure, the material of the first sidewall comprises silicon nitride; the material of the first gate dielectric layer comprises silicon oxide; and the cleaning solution used in the cleaning process comprises H3PO4 solution.

[0009] According to some embodiments of the present disclosure, the temperature of the cleaning solution is 80-130℃.

[0010] According to some embodiments of the present disclosure, the solute concentration of H3PO4 in the H3PO4 solution is 40-65%.

[0011] According to some embodiments of the present disclosure, the thickness of the insulating layer is 1.2-1.5 times of the maximum width of the second sidewall.

[0012] According to some embodiments of the present disclosure, the thickness of the insulating layer is 8-15 nm; and the maximum width of the second sidewall is 6-12 nm.

[0013] According to some embodiments of the present disclosure, the ratio of the width of the gap to the maximum width of the first sidewall is less than or equal to 2 / 3 before the etching process.

[0014] According to some embodiments of the present disclosure, the ratio of the width of the gap to the maximum width of the first sidewall is less than or equal to 2 / 3 before the wet etching process.

[0015] According to some embodiments of the present disclosure, another aspect of the embodiments of the present disclosure further provides a semiconductor structure, comprising: a substrate, a second gate dielectric layer located on a part of the surface of the substrate, and a gate conductive layer located on a part of the surface of the second gate dielectric layer, wherein the width of the second gate dielectric layer is greater than the width of the gate conductive layer; a second sidewall located on a part of the surface of the second gate dielectric layer, and the second sidewall is located on the side of the gate conductive layer, and the second sidewall and the gate conductive layer together cover the top surface of the second gate dielectric layer away from the substrate.

[0016] According to some embodiments of the present disclosure, the distance difference between the side surface of the second gate dielectric layer and the side surface of the second sidewall away from the gate conductive layer is less than or equal to 2 nm.

[0017] According to some embodiments of the present disclosure, the side surface of the second gate dielectric layer is flush with the side surface of the second sidewall away from the gate conductive layer.

[0018] According to some embodiments of the present disclosure, further comprising: a main sidewall located on a part of the surface of the substrate, and further covering the side surface of the second sidewall and the side surface of the second gate dielectric layer.

[0019] According to another embodiment of the present disclosure, the semiconductor structure further comprises a gate cap layer on the top surface of the gate conductive layer away from the substrate, and the second sidewall covers the side surface of the gate cap layer.

[0020] The technical solution provided by the embodiments of the present disclosure has at least the following advantages.

[0021] In the method for manufacturing the semiconductor structure provided by the embodiments of the present disclosure, first, a substrate, a gate dielectric film on the surface of the substrate, and a gate conductive layer on part of the surface of the gate dielectric film are provided; an insulating layer is formed, which covers the exposed surface of the gate dielectric film of the gate conductive layer and the top surface and side surface of the gate; the insulating layer and the gate dielectric film are dry-etched to expose part of the substrate and retain the insulating layer on the side surface of the gate conductive layer as a first sidewall, and the remaining gate dielectric film is a first gate dielectric layer; the first sidewall and the substrate are subjected to cleaning treatment, so that part of the width of the first gate dielectric layer is removed, the remaining first gate dielectric layer is a second gate dielectric layer, and the first sidewall, the second gate dielectric layer, and the substrate enclose a gap, the width of the gap being smaller than the maximum width of the first sidewall; the first sidewall directly above the gap is etched and removed, and the remaining first sidewall is used as a second sidewall. In the related art, part of the width of the first gate dielectric layer is removed when the first sidewall and the substrate are subjected to cleaning treatment, and the cleaning environment causes side etching of the first gate dielectric layer to form a gap enclosed by the first sidewall, the second gate dielectric layer, and the substrate. The occurrence of this gap is likely to cause the semiconductor structure to be broken down and leak current during operation. In the method for manufacturing the semiconductor structure provided by the embodiments of the present disclosure, after the first sidewall and the substrate are etched and cleaned to form a gap, wet etching is performed to remove the first sidewall directly above the gap, thereby obtaining a second sidewall. Even if the cleaning step causes the edge of the second gate dielectric layer to form a side-etched gap, the side-etched condition of the gate dielectric layer can still be balanced after the first sidewall is etched, and the edge of the second gate dielectric layer after wet etching does not have a gap. Thus, the leakage of the semiconductor structure can be reduced. BRIEF DESCRIPTION OF DRAWINGS

[0022] One or more embodiments are illustrated by way of example in the drawings and are described in detail below, which do not constitute a limitation on the embodiments, unless otherwise specified. The drawings in the drawings do not constitute a proportional limit; in order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or in the prior art, a brief introduction will be made to the drawings required in the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art without creative labor.

[0023] Figures 1 to 3 A structural schematic diagram of each step of a method for manufacturing a semiconductor structure;

[0024] Figures 4 to 13 A structure diagram of each step of a manufacturing method of a semiconductor structure is provided for an embodiment of the present disclosure. DETAILED DESCRIPTION

[0025] As known from the background, the semiconductor structure manufactured by the current manufacturing method of a semiconductor structure has certain leakage problems.

[0026] Reference Figures 1 to 3 , Figures 1 to 3 A structure diagram of each step of a manufacturing method of a semiconductor structure is provided for an embodiment of the present disclosure.

[0027] Reference Figure 1 , a substrate 10 is provided and a gate dielectric film 20 and a gate conductive layer 30 located on a part of the surface of the gate dielectric film 20 are formed on the surface of the substrate 10, an insulating layer 40 covering the surface of the gate dielectric film 20 exposed by the gate conductive layer 30 is formed, and the insulating layer 40 also covers the top surface and side surface of the gate conductive layer 30. The gate conductive layer 30 can include a gate layer 31, a first conductive layer 32, and a second conductive layer 33. A gate cap layer 34 located on the top surface of the gate conductive layer 30 is also formed. Reference Figure 2 , the insulating layer 40 and the gate dielectric film 20 are dry etched to expose a part of the substrate 10, and the insulating layer 40 located on the side surface of the gate conductive layer 30 is reserved as a side wall 41, and the remaining gate dielectric film 20 is reserved as a first gate dielectric layer 21, and the first gate dielectric layer 21 is located on the bottom surface of the side wall 41 and the bottom surface of the gate conductive layer 30. Reference Figure 3 , the side wall 41 and the surface of the substrate 10 are subjected to a cleaning process. In the cleaning process, since the first gate dielectric layer 21 is also exposed to the cleaning environment, the cleaning environment will remove a part of the first gate dielectric layer 21 to form a side notch, the remaining first gate dielectric layer 21 is reserved as a second gate dielectric layer 22, and the side wall 41, the second gate dielectric layer 22, and the substrate 10 form a gap. This makes the semiconductor structure prone to breakdown and leakage when working.

[0028] Analysis shows that in the above manufacturing method of a semiconductor structure, when the side wall 41 is subjected to a cleaning process, the first gate dielectric layer 21 located on the bottom surface of the side wall 41 forms a gap by side notching, and this gap is prone to breakdown and leakage when the semiconductor structure is working. If a manufacturing method of a semiconductor structure can be provided, so that the semiconductor structure manufactured by the manufacturing method of a semiconductor structure does not have a gap in the gate dielectric layer located on the bottom surface of the side wall, and the gate dielectric layer can cover the entire bottom surface of the side wall, the above problem can be improved.

[0029] The embodiment of the present disclosure provides a manufacturing method of a semiconductor structure, which comprises the following steps: providing a substrate, a gate dielectric film located on the surface of the substrate, and a gate conductive layer located on part of the surface of the gate dielectric film; forming an insulating layer, wherein the insulating layer covers the exposed surface of the gate dielectric film of the gate conductive layer, and also covers the top surface and the side surface of the gate conductive layer; dry etching the insulating layer and the gate dielectric film, so as to expose part of the substrate, and retain the insulating layer located on the side surface of the gate conductive layer as a first side wall, and retain the remaining gate dielectric film as a first gate dielectric layer; performing a cleaning process on the first side wall and the substrate, so as to remove part of the width of the first gate dielectric layer, retain the remaining first gate dielectric layer as a second gate dielectric layer, and form a gap surrounded by the first side wall, the second gate dielectric layer and the substrate, wherein the width of the gap is smaller than the maximum width of the first side wall; and etching and removing the first side wall located directly above the gap, so as to retain the remaining first side wall as a second side wall. In this way, the side gap formed in the cleaning process can be balanced by the subsequent step of etching the first side wall, and the second gate dielectric layer formed finally in the semiconductor structure does not have a gap, and the second gate dielectric layer can cover the entire bottom surface of the second side wall, thereby reducing the leakage of the semiconductor structure.

[0030] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the embodiments of the present disclosure will be described in detail below with reference to the drawings. However, those skilled in the art can understand that, in the embodiments of the present disclosure, many technical details are proposed in order to make the readers better understand the present disclosure. However, the technical solutions claimed by the present disclosure can be implemented even if there are no such technical details and various changes and modifications based on the following embodiments.

[0031] Figures 4 to 13 The structure schematic diagram corresponding to each step of the manufacturing method of the semiconductor structure provided by the embodiments of the present disclosure is shown in the following figure.

[0032] Reference Figure 4 The substrate 100, the gate dielectric film 110 located on the surface of the substrate 100, and the gate conductive layer 120 located on part of the surface of the gate dielectric film 110 are provided.

[0033] In some embodiments, the substrate 100 can include active regions 101 and isolation regions 102 that separate adjacent active regions 101. The material of the active regions 101 can include monocrystalline silicon (Si), monocrystalline germanium (Ge), or silicon germanium (GeSi), silicon carbide (SiC), and can also be silicon-on-insulator (SOI), germanium-on-insulator (GOI), or other materials such as Group III-V compounds, e.g., gallium arsenide, etc. In embodiments of the present disclosure, the material of the substrate 100 can be monocrystalline silicon (Si). The isolation regions 102 use insulating materials, and the material of the isolation regions 102 can include silicon oxide. The isolation regions can include a first isolation structure 1021, a second isolation structure 1022, and a third isolation structure 1023, the first isolation structure 1021 is adjacent to the active regions 101, the second isolation structure 1022 covers the surface of the first isolation structure 1021, and the third isolation structure 1023 covers the surface of the second isolation structure 1022. The material of the second isolation structure 1022 can be different from the material of the first isolation structure 1021. The multi-layered isolation regions 102 can enhance the isolation effect between adjacent active regions 101.

[0034] The isolation regions 102 in the semiconductor structure can be a shallow trench isolation (STI) structure. The shallow trench isolation structure can be an effective isolation device for DRAM devices, effectively electrically insulating adjacent transistors, and the shallow trench isolation structure occupies a small device surface area, making the integrated circuit better integrated. The shallow trench isolation structure has strong latch protection capability to achieve electrical insulation, and there is no erosion of the trench for forming the shallow trench isolation structure.

[0035] In some embodiments, the material of the gate dielectric film 110 can include silicon oxide. The arrangement of the gate dielectric film 110 can improve the electron conduction performance of the semiconductor structure, making the conduction of electrons in the semiconductor structure more smooth, and the gate dielectric film 110 can also control the current, prevent the device from overheating or short circuit caused by excessive current, form a charge channel to control the flow of electrons in the device, and improve the stability of the device, improve the efficiency of the device, and to a certain extent, protect the device from environmental factors. In addition, the gate dielectric film 110 also has a certain surface activity, which can be used as a surface active layer in the semiconductor structure, and can be used to receive or place other substances.

[0036] In some embodiments, the gate conductive layer 120 can include a plurality of film layer structures. Continuing to refer to Figure 4The gate conductive layer 120 can include a gate layer 121, a first conductive layer 122, and a second conductive layer 123. The gate layer 121 is located on the surface of the gate conductive layer 122 away from the substrate 100, the first conductive layer 122 is located on the surface of the gate layer 121 away from the substrate 100, the second conductive layer 123 is located on the surface of the first conductive layer 122 away from the substrate 100, and the width of the second conductive layer 123 can be greater than the width of the first conductive layer 122.

[0037] The material of the gate layer 121 can include polysilicon, the material of the first conductive layer 122 can include titanium nitride, and the material of the second conductive layer 123 can include tungsten. The conductivity of the gate conductive layer 120 can be improved to some extent, and the signal transmission speed of the semiconductor structure can be improved.

[0038] A gate cap layer 132 can also be formed on the top surface of the gate conductive layer 120. The material of the gate cap layer 132 can include silicon nitride. The gate cap layer 132 can protect the gate conductive layer 120.

[0039] Referring to Figure 5 An insulating layer 130 is formed to cover the exposed surface of the gate dielectric film 110 of the gate conductive layer 120, and also cover the top surface and side surface of the gate conductive layer 120. The insulating layer 130 located in the area of the top surface of the gate conductive layer 120 covers the top surface of the gate cap layer 132.

[0040] In some embodiments, the material of the insulating layer 130 can include silicon nitride. The insulating layer 130 formed in this step can act as a side wall structure of the gate conductive layer 120 after subsequent processing. When the insulating layer 130 is formed in this step, the width of the insulating layer 130 formed on both sides of the gate conductive layer 120 can be greater than the width of the required side wall structure in the semiconductor structure.

[0041] Referring to Figure 6 A dry etching process is used to etch the insulating layer 130 (see Figure 5 ) and the gate dielectric film 110, expose part of the substrate 100, and retain the insulating layer 130 located on the side surface of the gate conductive layer 120 as a first side wall 131, and the remaining gate dielectric film 110 as a first gate dielectric layer 111.

[0042] The width of the first side wall 131 at each position in the direction perpendicular to the surface of the substrate 100 can not be consistent, and the maximum width of the first side wall 131 is less than or equal to the width of the insulating layer 130 located on the side surface of the gate conductive layer 120. The material of the first side wall 131 can include silicon nitride. In addition, the first side wall 131 also needs to form the required side wall structure in the semiconductor structure through subsequent steps, and the maximum width of the first side wall 131 is greater than the thickness of the required side wall structure in the semiconductor structure.

[0043] The width of the first gate dielectric layer 111 can be greater than or equal to the width of the first sidewall 131, and the side surface of the first gate dielectric layer 111 can be flush with the side surface of the first sidewall 131 away from the gate conductive layer 120, that is, the width of the first gate dielectric layer 111 can be the same as the maximum width of the first sidewall 131. The material of the first gate dielectric layer 111 is the same as that of the gate dielectric film 110, and the material of the first gate dielectric layer 111 can include silicon oxide.

[0044] Since the dry etching process can cause the surface of the substrate 100 and the surface of the first sidewall 131 to have a certain residue, in the subsequent step, the residue needs to be removed.

[0045] Reference Figure 7 The first sidewall 131 and the substrate 100 are subjected to cleaning treatment, and in the cleaning treatment step, part of the width of the first gate dielectric layer 111 is removed, and the remaining first gate dielectric layer 111 serves as a second gate dielectric layer 112, and the first sidewall 131, the second gate dielectric layer 112 and the substrate 100 form a gap 113, wherein the width of the gap 113 is less than the maximum width of the first sidewall 131.

[0046] In the cleaning process, the cleaning solution not only contacts the surface of the substrate 100 and the surface of the first sidewall 131, but also contacts the outer surface of the first gate dielectric layer 111. The cleaning solution etches the first gate dielectric layer 111, so that the first gate dielectric layer 111 is removed in part, and the first gate dielectric layer 111 after cleaning treatment becomes the second gate dielectric layer 112. But the width of the second gate dielectric layer 112 formed after cleaning treatment is still greater than the width of the gate conductive layer 120, and the gap 113 is only located at the bottom of the first sidewall 131 and does not extend to the bottom of the gate conductive layer 120.

[0047] In some embodiments, the etching selectivity of the cleaning process to the first sidewall 131 and the first gate dielectric layer 111 can be greater than or equal to 50. For example, the etching selectivity of the cleaning process to the first sidewall 131 and the first gate dielectric layer 111 can be 50, 60, 70, 80, 85, 90, 100, 120, 150, 200, etc. In this way, the cleaning process can remove the residues on the surface of the first sidewall 131 and the surface of the substrate 100 while minimizing the etching of the first gate dielectric layer 111 by the cleaning solution, thereby reducing the width of the gap 113. If the etching selectivity of the cleaning process to the first sidewall 131 and the first gate dielectric layer 111 is too small, the etching rate of the cleaning process to the first gate dielectric layer 111 can be too large, the cleaning process can etch the first gate dielectric layer 111 too deeply, the width of the gap 113 can be too large, and the gap 113 can even extend to the bottom of the gate conductive layer 120. Therefore, the etching selectivity of the cleaning process to the first sidewall 131 and the first gate dielectric layer 111 should be selected within an appropriate range. When the etching selectivity of the cleaning process to the first sidewall 131 and the first gate dielectric layer 111 is greater than or equal to 50, the cleaning process can remove the residues on the surface of the first sidewall 131 and the surface of the substrate 100 while minimizing the impact on the first gate dielectric layer 111.

[0048] In some embodiments, the etching selectivity can be between 100 and 200. For example, the etching selectivity can be 100, 110, 130, 150, 170, 200, etc. When the etching selectivity is within this range, the cleaning process can remove the residues on the surface of the first sidewall 131 and the surface of the substrate 100 more efficiently while minimizing the impact on the first gate dielectric layer 111. If the etching selectivity is too small, the cleaning process can have a greater impact on the first gate dielectric layer 111, and the width of the gap 113 can be too large. When the etching selectivity is between 100 and 200, the cleaning process can further improve the efficiency of removing the residues on the surface of the first sidewall 131 and the surface of the substrate 100, and further minimize the impact of the cleaning process on the first gate dielectric layer 111.

[0049] In some embodiments, the material of the first sidewall 131 can include silicon nitride, the material of the first gate dielectric layer 111 can include silicon oxide, and the cleaning solution used in the cleaning process can include an H3PO4 solution. When the material of the first sidewall 131 and the material of the first gate dielectric layer 111 are determined, based on the above content, a certain cleaning solution should be selected so that the etching selectivity of the cleaning solution to the first sidewall 131 and the first gate dielectric layer 111 is within a certain range. The H3PO4 solution can be selected as the cleaning solution. The H3PO4 solution can efficiently remove the residues on the surface of the first sidewall 131 and the surface of the substrate 100 while minimizing the impact on the first gate dielectric layer 111.

[0050] In some embodiments, the temperature of the cleaning solution can be 80-130 °C. For example, the temperature of the cleaning solution can be 80 °C, 90 °C, 100 °C, 110 °C, 120 °C, 130 °C, etc. The temperature of the cleaning solution has a greater impact on the etching selectivity of the cleaning solution to the first sidewall 131 and the first gate dielectric layer 111. When the temperature of the cleaning solution is too low or too high, the etching selectivity of the cleaning solution to the first sidewall 131 and the first gate dielectric layer 111 is low, and the cleaning process can have a greater impact on the first gate dielectric layer 111 when cleaning and removing the residues on the surface of the substrate 100 and the surface of the first sidewall 131, and in addition, it can also make it difficult for the cleaning process to efficiently remove the residues completely. Therefore, the temperature of the cleaning solution needs to be selected in an appropriate range, and when the temperature of the cleaning solution is 80-130 °C, the etching selectivity of the cleaning process to the first sidewall 131 and the first gate dielectric layer 111 is high, which can enable the cleaning process to efficiently remove residues while further reducing the impact on the first gate dielectric layer 111. When the temperature of the cleaning solution is 120 °C, the etching selectivity of the cleaning solution to the first sidewall and the first gate dielectric layer 111 is the highest, which can further improve the effect of the cleaning process and make the impact of the cleaning process on the first gate dielectric layer 111 smaller.

[0051] In some embodiments, the solute concentration of H3PO4 in the H3PO4 solution can be 40-65%. For example, the solute concentration of H3PO4 can be 40%, 45%, 50%, 60%, 65%, etc. If the solute concentration of H3PO4 is too low, the removal efficiency of the H3PO4 solution to the residues on the surface of the substrate 100 and the surface of the first sidewall 131 is too low; if the solute concentration of H3PO4 is too high, the H3PO4 solution can produce certain over-etching during the cleaning process, for example, the H3PO4 solution can damage the surface of the substrate 100, the surface of the first sidewall 131, or the H3PO4 solution can have a greater impact on the first gate dielectric layer 111, making the width of the notch 113 too wide. Therefore, the solute concentration of H3PO4 in the H3PO4 solution needs to be selected in an appropriate range, and when the solute concentration of H3PO4 is 40-65%, the H3PO4 solution can efficiently remove residues and reduce the impact of the H3PO4 solution on the first gate dielectric layer 111, reducing the risk of over-etching of the H3PO4 solution damaging the surface of the substrate 100 and the surface of the first sidewall 131.

[0052] In some embodiments, the ratio of the width of the gap 113 to the maximum width of the first sidewall 131 can be less than or equal to 2 / 3 before a subsequent etching process is performed, i.e. after the cleaning process. For example, the ratio of the width of the gap 113 to the maximum width of the first sidewall 131 can be 2 / 3, 3 / 5, 1 / 2, 1 / 3, 1 / 4, etc. If the ratio of the width of the gap 113 to the maximum width of the first sidewall 131 is too large, the width of the gap 113 is too large, and the cleaning process has a large impact on the first gate dielectric layer 111, which can affect the processing of the sidewall structure in subsequent steps and the performance of the semiconductor structure. Therefore, the ratio of the width of the gap 113 to the maximum width of the first sidewall 131 should have a suitable range. When the ratio of the width of the gap 113 to the maximum width of the first sidewall 131 is less than or equal to 2 / 3, the sidewall structure can be processed in subsequent processes to form a semiconductor structure without a gap, the remaining width of the second gate dielectric layer 112 can still be greater than the width of the gate conductive layer 120, and the second gate dielectric layer 112 is at least 1 / 3 wider than the gate conductive layer 120 than the maximum width of the first sidewall 131, which can enable the sidewall structure formed by processing the first sidewall 131 in subsequent steps to still have a certain thickness, improving the performance of the semiconductor structure.

[0053] Reference Figure 8 An etching process is performed to remove the first sidewall 131 directly above the gap 113 (refer to Figure 7 ), and the remaining first sidewall 131 serves as the second sidewall 133.

[0054] It can be understood that after the etching process removes the first sidewall 131 directly above the gap 113, the outer surface of the remaining second sidewall 133 should be flush with the side surface of the second gate dielectric layer 112. The semiconductor structure after the etching process does not have the gap 113, which can avoid the risk of electric leakage caused by the gap 113, so that the semiconductor structure is less likely to have electric leakage during operation, reducing the risk of electric leakage of the semiconductor structure and improving the performance of the semiconductor structure.

[0055] The second sidewall 133 is the sidewall structure required for fabricating a lightly doped region in the semiconductor structure, and the material of the second sidewall 133 is the same as the material of the insulating layer 130 (refer to Figure 5 ) and the material of the first sidewall 131 (refer to Figure 7 ). The material of the second sidewall 133 can include silicon nitride. The width of the second sidewall 133 is less than the width of the first sidewall 131, and the width of the second sidewall 133 is less than the width of the insulating layer 130.

[0056] In some embodiments, the insulating layer 130 (refer to Figure 5The thickness of the insulating layer 130 can be 1.2-1.5 times the maximum width of the second sidewall 133. For example, the thickness of the insulating layer 130 can be 1.2 times, 1.3 times, 1.4 times, 1.5 times, etc. the maximum width of the second sidewall 133. Since the size of the gap 113 generated by the cleaning process does not change when the process parameters of the cleaning process remain unchanged regardless of the thickness of the insulating layer 130, the difference between the width of the insulating layer 130 and the width of the second sidewall 133 should also not have a large change. If the thickness of the insulating layer 130 is too large relative to the maximum width of the second sidewall 133, it can cause waste of the insulating layer 130 material, and the maximum width of the second sidewall 133 formed ultimately can also be too large, which is not conducive to the development of semiconductor structures in the direction of miniaturization and microfabrication; if the thickness of the insulating layer 130 is too small relative to the maximum width of the second sidewall 133, it can result in the maximum width of the second sidewall 133 formed ultimately being too small, which cannot meet the width requirement of the sidewall structure in the semiconductor structure. Therefore, the relative relationship between the thickness of the insulating layer 130 and the maximum width of the second sidewall 133 should be selected in an appropriate range, and when the thickness of the insulating layer 130 is 1.2-1.5 times the maximum width of the second sidewall 133, the maximum width of the second sidewall 133 formed ultimately can be within the range of the required sidewall width of the semiconductor structure, and the maximum width of the second sidewall 133 is neither too large nor too small. Moreover, it can also avoid causing waste of materials and achieve green production.

[0057] In some embodiments, the thickness of the insulating layer 130 can be 8-15 nm; the maximum width of the second sidewall 133 can be 6-12 nm. For example, the thickness of the insulating layer 130 can be 8 nm, 9 nm, 11 nm, 13 nm, 15 nm, etc.; the maximum width of the second sidewall 133 can be 6 nm, 7 nm, 9 nm, 11 nm, 12 nm, etc. As can be seen from the above description, when the process parameters of the cleaning process remain unchanged, the size of the gap generated by the cleaning process also remains unchanged, and the difference between the width of the insulating layer 130 and the maximum width of the second sidewall 133 also does not have a large change. The thickness range of the insulating layer 130 depends on the width range of the sidewall structure required in the semiconductor structure, i.e., the range of the maximum width of the second sidewall 133. If the maximum width of the second sidewall 133 is too large, it can make the overall size of the semiconductor structure too large, or cause redundancy of the sidewall structure in the semiconductor structure, resulting in waste beyond the functional requirement range. If the maximum width of the second sidewall 133 is too small, it can not meet the width requirement of the sidewall structure in the semiconductor structure, affecting the performance of the semiconductor structure. Therefore, the maximum width of the second sidewall 133 needs to be selected in an appropriate range. When the maximum width of the second sidewall 133 is 6-12 nm, the change range of the maximum width of the second sidewall 133 formed finally can be further reduced, so that the maximum width of the second sidewall 133 is more in line with the width requirement of the sidewall structure in the semiconductor structure, further improving the performance of the semiconductor structure. Correspondingly, when the maximum width of the second sidewall 133 is 6-12 nm, the thickness of the insulating layer 130 can be 8-15 nm.

[0058] At this time, in the semiconductor structure formed with the second sidewall 133 and the second gate dielectric layer 112, theoretically, the width of the second gate dielectric layer 112 is equal to the sum of the width of the gate conductive layer 120 and the maximum width of the two second sidewalls 133, that is, the side surface of the second gate dielectric layer 112 is flush with the side surface of the second sidewall 133. There is no gap 113 between the second sidewall 133, the second gate dielectric layer 112 and the substrate 100, which solves the electric leakage hidden danger in the semiconductor structure, reduces the electric leakage risk of the semiconductor structure, reduces the electric leakage in the semiconductor structure, and improves the performance of the semiconductor structure.

[0059] Reference Figure 9 After the formation of the second sidewall 133, the substrate 100 on both sides of the gate conductive layer 120 can be doped to form a lightly doped region 140. The introduction of the lightly doped region 140 can effectively prevent the semiconductor structure from generating a short channel effect. The shallow junction formed by the combination of the large mass material and the surface amorphous state is also beneficial to reduce the current leakage effect between the source and the drain.

[0060] The doping of the substrate 100 on both sides of the gate conductive layer 120 to form the lightly doped region 140 can be performed by ion implantation. If N-type doping is needed, N-type ions such as nitrogen ions, phosphorus ions, etc. can be implanted. If P-type doping is needed, P-type ions such as boron ions, aluminum ions, etc. can be implanted. It can be understood that the concentration of the doping ions of the lightly doped region 140 is different according to different threshold voltages of different semiconductor devices.

[0061] Referring to Figure 10 An isolation layer 150 can be formed on part of the surface of the substrate 100 and also cover the side surface of the second side wall 133 and the side surface of the second gate dielectric layer 112. The isolation layer can be etched to form another side wall structure around the second side wall 133 in a subsequent step. The second side wall 133 with a single layer of silicon nitride has a large stress, which can affect the electrical properties of the semiconductor structure and cause problems such as leakage of the device and reduction of saturation current. The introduction of the isolation layer 150 can solve the above problems to some extent.

[0062] Referring to Figure 11 In some embodiments, the step of forming the isolation layer 150 can include forming a silicon oxide layer 151 on part of the surface of the substrate 100, and the silicon oxide layer 151 covers the side surface of the second side wall 133 and the side surface of the second gate dielectric layer 112. The silicon oxide layer 151 can alleviate the stress effect of the second side wall 133, thereby improving the performance of the semiconductor structure.

[0063] In some embodiments, the method used to form the silicon oxide layer 151 can be an atomic layer deposition method. The atomic layer deposition method can accurately control the thickness of the film layer at the atomic layer level, which is beneficial to form a silicon oxide layer 151 with a certain thickness range, making the semiconductor structure more fine and standardized. It can also prevent the problem of over-deposition or under-deposition during the formation of the silicon oxide layer 151, which requires subsequent removal or filling steps.

[0064] Continuing to refer to Figure 11 In some embodiments, the step of forming the isolation layer 150 can also include forming a silicon nitride layer 152 covering the surface of the silicon oxide layer 151. Since the silicon nitride material has a high dielectric constant and good isolation effect, the introduction of the outer silicon nitride layer 152 can further strengthen the isolation effect of the semiconductor structure.

[0065] Referring to Figure 12 After the isolation layer 150 is formed (refer to Figure 11 ), the isolation layer 150 can also be etched to expose part of the substrate 100, and the isolation layer 150 on the side surface of the gate conductive layer 120 is retained as a main side wall 153.

[0066] Reference Figure 13 In some embodiments, after the formation of the main side wall 153, the substrate 100 on both sides of the gate conductive layer 120 can be doped to form a heavily doped region 160. If N-type doping is needed, N-type ions such as nitrogen ions, phosphorus ions, etc. can be implanted. If P-type doping is needed, P-type ions such as boron ions, aluminum ions, etc. can be implanted.

[0067] The manufacturing method of the semiconductor structure provided by the embodiments of the present disclosure comprises the following steps. A substrate, a gate dielectric film and a gate conductive layer are provided. An insulating layer covering the surface of the gate conductive layer and the surface of the gate dielectric film is formed. The insulating layer and the gate dielectric film are dry etched to expose part of the substrate and retain the insulating layer on the side of the gate conductive layer as a first side wall and the remaining gate dielectric film as a first gate dielectric layer. The first side wall and the substrate are cleaned to remove part of the width of the first gate dielectric layer, and the remaining first gate dielectric layer is retained as a second gate dielectric layer. The first side wall, the second gate dielectric layer and the substrate form a gap, and the width of the gap is smaller than the maximum width of the first side wall. The first side wall above the gap is removed by wet etching, and the remaining first side wall is retained as a second side wall. The gap formed in the semiconductor structure can be avoided, and the leakage of the semiconductor structure can be reduced.

[0068] Correspondingly, another embodiment of the present disclosure also provides a semiconductor structure manufactured by the above-mentioned manufacturing method of the semiconductor structure. The semiconductor structure provided by another embodiment of the present disclosure will be described in detail below with reference to the drawings. The same or corresponding parts of the semiconductor structure provided by another embodiment of the present disclosure can refer to the corresponding description of the foregoing embodiment, and will not be described in detail below.

[0069] Figure 13 A schematic diagram of a cross-sectional structure of a semiconductor structure provided by an embodiment of the present disclosure is shown in FIG. 1.

[0070] Reference Figure 13 The semiconductor structure comprises a substrate 100, a second gate dielectric layer 112 on part of the surface of the substrate 100, and a gate conductive layer 120 on part of the surface of the second gate dielectric layer 112. The width of the second gate dielectric layer 112 is greater than the width of the gate conductive layer 120. The semiconductor structure comprises a second side wall 133 on part of the surface of the second gate dielectric layer 112 and on the side of the gate conductive layer 120. The second side wall 133 and the gate conductive layer 120 together cover the top surface of the second gate dielectric layer 112 away from the substrate 100.

[0071] In theory, according to the above-mentioned manufacturing method of the semiconductor structure, the first side wall 131 above the second gate dielectric layer 112 is removed after the formation of the second gate dielectric layer 112 (refer to FIG. 2). The remaining part of the first side wall 131 is retained as the second side wall 133. The second side wall 133 and the gate conductive layer 120 together cover the top surface of the second gate dielectric layer 112 away from the substrate 100. Figure 8), the remaining first side wall 131 as the second side wall 133, and the distance difference between the side surface of the second gate dielectric layer 112 and the side surface of the second side wall 133 away from the gate conductive layer 120 should be 0. However, in the actual production process, it is inevitable to have some errors, and there may still be a certain distance difference between the side surface of the second gate dielectric layer 112 and the side surface of the second side wall 133 away from the gate conductive layer 120.

[0072] In some embodiments, the distance difference between the side surface of the second gate dielectric layer 112 and the side surface of the second side wall 133 away from the gate conductive layer 120 can be less than or equal to 2 nm. For example, the distance difference between the side surface of the second gate dielectric layer 112 and the side surface of the second side wall 133 away from the gate conductive layer 120 can be 2 nm, 1.5 nm, 1 nm, 0.5 nm, 0 nm, etc. If the distance difference between the side surface of the second gate dielectric layer 112 and the side surface of the second side wall 133 away from the gate conductive layer 120 is too large, there may still be a risk of leakage, and it is difficult to solve the leakage problem in the semiconductor structure. Therefore, the distance difference between the side surface of the second gate dielectric layer 112 and the side surface of the second side wall 133 in the semiconductor structure needs to have a certain range, and when the distance difference is less than or equal to 2 nm, there will be no leakage risk, and the leakage problem in the semiconductor structure can be reduced.

[0073] In some embodiments, the side surface of the second gate dielectric layer 112 and the side surface of the second side wall 133 away from the gate conductive layer 120 can be flush. When the distance difference between the side surface of the second gate dielectric layer 112 and the side surface of the second side wall 133 away from the gate conductive layer 120 is 0, the side surface of the second gate dielectric layer 112 and the side surface of the second side wall 133 away from the gate conductive layer 120 are flush. This can further reduce the risk of leakage and further reduce the leakage problem in the semiconductor structure.

[0074] In some embodiments, a main side wall 153 can also be included, which is located on part of the surface of the substrate 100 and also covers the side surface of the second side wall 133 and the side surface of the second gate dielectric layer 112. The main side wall 153 can optimize the isolation effect and stress influence of the side wall structure, thereby improving the performance of the semiconductor structure. The main side wall 153 can include a first main side wall 1531 covering the side surface of the second side wall 133 and the side surface of the second gate dielectric layer 112, and a second main side wall 1532 covering the side surface of the first main side wall 1531. The material of the first main side wall 1531 can include silicon oxide, and the material of the second main side wall 1532 can include silicon nitride.

[0075] In some embodiments, a gate cap layer 132 can also be included on the top surface of the gate conductive layer 120 away from the substrate 100, and the second sidewall 133 covers the side surface of the gate cap layer 132. The material of the gate cap layer 132 can include silicon nitride, which can protect the gate conductive layer 120.

[0076] The embodiments of the present disclosure provide a semiconductor structure, which includes a substrate and a second gate dielectric layer on a part of the surface of the substrate and a gate conductive layer on a part of the surface of the second gate dielectric layer, wherein the width of the second gate dielectric layer is greater than the width of the gate conductive layer; a second sidewall is on a part of the surface of the second gate dielectric layer, and the second sidewall is on the side surface of the gate conductive layer, and the second sidewall and the gate conductive layer together cover the top surface of the second gate dielectric layer away from the substrate. In this way, there is no gap between the second sidewall, the second gate dielectric layer and the substrate, and the semiconductor structure does not have the hidden danger of easy leakage, and the leakage of the semiconductor structure can be reduced.

[0077] Those skilled in the art can understand that the above-mentioned embodiments are specific embodiments for implementing the present disclosure, and in actual application, various changes can be made in form and details without departing from the spirit and scope of the present disclosure. Any person skilled in the art can make respective changes and modifications without departing from the spirit and scope of the present disclosure, therefore the protection scope of the present disclosure should be limited by the scope defined in the claims.

Claims

1. A method for manufacturing a semiconductor structure, comprising: providing a substrate, a gate dielectric layer on a surface of the substrate, and a gate conductive layer on a portion of the surface of the gate dielectric layer; forming an insulating layer covering a surface of the gate dielectric layer exposed by the gate conductive layer, and further covering a top surface and side surfaces of the gate conductive layer; etching the insulating layer and the gate dielectric layer to expose a portion of the substrate using a dry etching process, and leaving the insulating layer on the side surfaces of the gate conductive layer as a first side wall, and leaving the remaining gate dielectric layer as a first gate dielectric layer; performing a cleaning process on the first side wall and the substrate, wherein a portion of the first gate dielectric layer is removed during the cleaning process, leaving the remaining first gate dielectric layer as a second gate dielectric layer, and the first side wall, the second gate dielectric layer, and the substrate form a gap, wherein a width of the gap is less than a maximum width of the first side wall; and etching and removing the first side wall directly above the gap using an etching process, leaving the remaining first side wall as a second side wall.

2. The method of claim 1, wherein: an etching selectivity of the cleaning process on the first side wall and the first gate dielectric layer is greater than or equal to 50.

3. The method of claim 2, wherein: the etching selectivity is between 100 and 200.

4. The method of any one of claims 1 to 3, wherein: a material of the first side wall comprises silicon nitride; a material of the first gate dielectric layer comprises silicon oxide; and a cleaning solution used in the cleaning process comprises a H3PO4 solution.

5. The method of claim 4, wherein: a temperature of the cleaning solution is between 80°C and 130°C.

6. The method of claim 4, wherein: a solute concentration of H3PO4 in the H3PO4 solution is between 40% and 65%.

7. The method of claim 1, wherein: a thickness of the insulating layer is between 1.2 and 1.5 times a maximum width of the second side wall.

8. The method of claim 1 or 7, wherein: the thickness of the insulating layer is between 8 nm and 15 nm; and the maximum width of the second side wall is between 6 nm and 12 nm.

9. The method of claim 1, wherein: a ratio of the width of the gap to the maximum width of the first side wall is less than or equal to 2 / 3 before the etching process is performed.

10. A semiconductor structure manufactured using the method of any one of claims 1 to 9, comprising: a substrate, a second gate dielectric layer on a portion of a surface of the substrate, and a gate conductive layer on a portion of a surface of the second gate dielectric layer, wherein a width of the second gate dielectric layer is greater than a width of the gate conductive layer. ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ A second side wall is located on a part of the surface of the second gate dielectric layer, and the second side wall is located on the side of the gate conductive layer, and the second side wall and the gate conductive layer together cover the top surface of the second gate dielectric layer away from the substrate.

11. The semiconductor structure of claim 10, wherein, The distance difference between the side of the second gate dielectric layer and the side of the second side wall away from the gate conductive layer is less than or equal to 2 nm.

12. The semiconductor structure of claim 11, wherein, The side of the second gate dielectric layer is flush with the side of the second side wall away from the gate conductive layer.

13. The semiconductor structure of claim 10, wherein, Further comprising: A main side wall is located on a part of the surface of the substrate, and further covers the side of the second side wall and the side of the second gate dielectric layer.

14. The semiconductor structure of claim 10, wherein, Further comprising: A gate cap layer is located on the top surface of the gate conductive layer away from the substrate, and the second side wall covers the side of the gate cap layer.

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