A back gate type oxide semiconductor device and a method for manufacturing the same

Abstract

This invention proposes a back-gate oxide semiconductor device and its fabrication method. The device uses a natural oxidation method to form the natural oxide layer of the source and drain electrodes, achieving electrical isolation between the source, drain, and metal passivation layer. This eliminates the need for offsets between the source / drain electrodes and the passivation layer, thus enabling size miniaturization. Simultaneously, since offsets are no longer required between the source / drain electrodes and the passivation layer, the metal passivation layer can cover the entire upper surface of the OS channel, thereby capturing more oxygen from the OS material. This generates a large number of oxygen vacancies in the OS channel, increasing the carrier concentration in the contact areas with the source and drain electrodes, resulting in excellent carrier mobility.

Description

Technical Field

[0001] This invention relates to the field of semiconductors, and in particular to a back-gate oxide semiconductor device and its fabrication method. Background Technology

[0002] Oxide semiconductor (OS) thin-film transistors (OS-TFTs) have attracted widespread attention in monolithic 3D integration technology, especially in 3D dynamic random access memory (3D-DRAM), due to their considerable mobility, CMOS back-end process compatibility, and excellent uniformity.

[0003] A typical back-gate OS-TFT includes, for example: a gate electrode disposed on an insulating substrate; a gate insulating film disposed in such a way as to cover the gate electrode; a semiconductor layer disposed in an island-like manner on the gate insulating film in such a way as to overlap with the gate electrode; and a source electrode and a drain electrode disposed on the semiconductor layer in such a way as to be opposite to each other.

[0004] In OS-TFTs, charge carriers are primarily supplied by ionized oxygen vacancies, but precise control of shallow donor-state oxygen vacancies remains a challenge in this field. (See existing technology...) Figure 1 Researchers have used a device structure with an active metal capping layer (CL) to generate more shallow donor oxygen vacancies in the OS material through the redox reaction between the metal and the OS material. However, a certain offset is required between the CL and the source / drain electrodes to ensure electrical isolation between them. Due to this offset, this existing approach prevents device miniaturization and results in a large series resistance in the OS below the offset, as the oxygen vacancies cannot be modulated, thus affecting device characteristics.

[0005] Therefore, this invention proposes a back-gate oxide semiconductor device and its fabrication method. Compared with the traditional OS-TFT fabrication process, the fabrication process of this invention is simple. The metal passivation layer can control oxygen vacancies throughout the channel, which greatly improves the device mobility and switching characteristics. Compared with devices with capping layers, the size of the device of this invention is easier to miniaturize. Summary of the Invention

[0006] The main objective of this invention is to provide a method for fabricating a back-gate oxide semiconductor device. To achieve this objective, this invention provides the following technical solution: a back-gate oxide semiconductor device and its fabrication method, as follows:

[0007] A back-gate oxide semiconductor device comprises, from bottom to top: a substrate, a back gate layer, a channel layer, and a passivation layer. The back gate layer includes a back gate and a gate dielectric layer disposed from bottom to top. The channel layer includes a source, a drain, and an OS channel electrically in contact with the source, drain, and passivation layer. An insulating layer is disposed on the contact surface between the source, drain, and passivation layer. An adjustment layer is disposed on the contact surface between the OS channel and the source, drain, and passivation layer 109.

[0008] A method for fabricating a back-gate oxide semiconductor device includes the following steps:

[0009] S1. Deposit a gate conductive layer on the substrate and pattern it to form a back gate electrode;

[0010] S2. Deposit a gate dielectric layer on the upper surface of the back gate electrode and pattern it;

[0011] S3. Deposit a channel layer on the gate dielectric layer and pattern it to form the OS channel, so that the OS channel is located above the back gate electrode.

[0012] S4. Deposit and pattern source and drain metal layers on both sides of the OS channel to form source and drain electrodes respectively. One end of the source and drain electrodes is electrically contacted with the OS channel.

[0013] S5. The sample is placed in the atmospheric environment for the first time. The source and drain are fully exposed to the air and undergo natural oxidation to form an insulating layer. At the same time, the area where the source and drain are in contact with the OS channel will undergo a redox reaction to form the first conditioning layer.

[0014] S6. Deposit a metal passivation layer on the upper surface of the device, the metal passivation layer covering the upper surfaces of the source and drain and the upper surface of the OS channel;

[0015] S7. Place the sample in the atmospheric environment for the second time to allow the metal passivation layer to fully undergo a redox reaction in the contact area with the OS channel, forming a second conditioning layer.

[0016] S8. The metal passivation layer is patterned, thereby bringing out the three electrodes of the sample, and the device fabrication is completed.

[0017] Compared with the prior art, the present invention achieves the following technical effects:

[0018] This invention proposes a back-gate oxide semiconductor device and method thereof. The device uses a natural oxidation method to form the natural oxide layer of the source and drain electrodes, achieving electrical isolation between the source, drain, and metal passivation layer. This eliminates the need for offset between the source / drain and the passivation layer, thus enabling size miniaturization. Simultaneously, since the offset between the source / drain and the passivation layer is no longer required, the metal passivation layer can cover the entire upper surface of the OS channel, thereby capturing more oxygen from the OS material. This generates a large number of oxygen vacancies in the OS channel, increasing the carrier concentration in the contact area with the source and drain, resulting in excellent carrier mobility. Attached Figure Description

[0019] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the invention.

[0020] Figure 1 A schematic diagram of the structure of a current back-gate oxide semiconductor device.

[0021] Figure 2 This is a schematic diagram of the back-gate oxide semiconductor device structure of the present invention. Detailed Implementation

[0022] Embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0023] The accompanying drawings illustrate various structural schematics according to embodiments of the present disclosure. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0024] In the context of this disclosure, when a layer / element is referred to as being "above" another layer / element, the layer / element may be directly above the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "above" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element.

[0025] See Figure 2First, a gate conductive layer is deposited on the substrate 100 and patterned to form the back gate electrode 103.

[0026] In one embodiment, the lower layer of the substrate 100 may be a rigid silicon wafer 101, and the upper layer may be an insulating oxide layer 102, which may be a SiO2 layer. In other embodiments, the substrate 100 may also be made of a flexible material, such as flexible glass, polyimide (PI), polyethylene naphthalate (PEN), or polyethylene terephthalate (PET).

[0027] A gate conductive layer is deposited on the surface of the insulating oxide layer 102. The gate conductive layer can be made of at least one of a metal, a conductive metal oxide, or other conductive materials, such as Mo, Al, Ti, TiN, W, etc., and its thickness can range from 20 to 90 nm. The deposition process of the gate conductive layer can be magnetron sputtering, PECVD, etc. In another embodiment, the gate conductive layer can also be a multilayer structure, in which materials such as Mo, Al, Ti, TiN, and W can be selected.

[0028] After the gate conductive layer is deposited, the gate conductive layer is patterned by photolithography and etching processes to form the back gate electrode 103, which can be located in the middle of the substrate 100. The rest of the gate conductive layer is etched away to expose the insulating oxide layer 102.

[0029] Then, a gate dielectric layer 104 is deposited on the upper surface of the insulating oxide layer 102 and the back gate electrode 103, and the gate dielectric layer 104 covers the upper surface of the back gate electrode 103 and the exposed upper surface of the SiO2 layer 102.

[0030] In one embodiment, the gate dielectric layer 104 can be a single-layer structure or a multilayer structure composed of one or more high-k dielectric materials such as HfO2 and Al2O3, and its thickness can range from 5 to 20 nm. The gate dielectric layer 104 can be deposited using processes such as magnetron sputtering, PECVD, and ALD.

[0031] Next, a channel layer is deposited on the gate dielectric layer 104 and patterned to form the OS channel 105.

[0032] The channel layer can be a single-layer structure or a multilayer structure composed of oxide semiconductor (OS) thin film materials. Compared with transistors with silicon-based channels, transistors using OS materials as conductive channels exhibit superior driving performance and very low leakage current, thus enabling them to retain stored data for a relatively long time. In this invention, the OS material can be IGZO, ITO, IWO, ZnO, InO, or a combination of several materials, and the channel layer thickness can be 3-30 nm. The channel layer can be deposited using processes such as magnetron sputtering or ALD deposition.

[0033] After the channel layer is deposited, the channel layer is patterned using photolithography and etching processes to form OS channel 105, so that OS channel 105 is located in the middle position on the upper surface of the gate dielectric layer 104 corresponding to the back gate electrode 103. The remaining channel layers are etched away to expose the gate dielectric layer 104.

[0034] See Figure 1 Steps are formed on both sides of the OS channel 105. Then, source and drain metal layers are deposited and patterned at these two steps to form source 106-1 and drain 106-2, respectively. One end of source 106-1 and drain 106-2 is electrically contacted with the OS channel 105. The source and drain metal layers can be made of materials with good conductivity, such as Au, Pd, and Ag.

[0035] After completing the above steps, place the sample in an atmospheric environment (sample stage, sample box, etc.) for 1 to 3 days. During this period, the source electrode 106-1 and drain electrode 106-2 metals of the sample will be fully exposed to the air and undergo natural oxidation to form a natural oxide layer (metal oxide) of 5 to 10 nanometers, namely the insulating layer 107. This thickness of the insulating layer 107 forms an insulating protection for the surface of the source electrode 106-1 and drain electrode 106-2.

[0036] Simultaneously, a redox reaction occurs in the region where the source electrode 106-1, drain electrode 106-2 metals contact with the OS channel 105. The active metals remove oxygen from the OS material, generating a large number of oxygen vacancies in the OS channel 105. This increases the carrier concentration in the region where the source electrode 106-1, drain electrode 106-2 contact with the OS channel 105. A 1 to 3 nanometer metal oxide, i.e., the first conditioning layer, is formed at the interface between the source electrode 106-1, drain electrode 106-2 and the OS channel 105.

[0037] It should be noted that, due to the thin metal oxide at the interface between the source 106-1, drain 106-2 and OS channel 105, and the increased carrier concentration in the contact area between OS channel 105 and source 106-1 and drain 106-2, the contact resistance of the source and drain of the sample will not change significantly, thus affecting the electrical characteristics of the sample.

[0038] After the natural oxidation process of the source electrode 106-1 and the drain electrode 106-2 is completed, a metal passivation layer 109 is deposited on the upper surface of the device. The metal passivation layer 109 covers the upper surfaces of the source electrode 106-1, the drain electrode 106-2, and the upper surface of the OS channel 105. In one embodiment, active metals such as Al, Ti, and W are deposited on the sample as passivation layers. The deposition method can be evaporation, sputtering, chemical vapor deposition (CVD), atomic layer deposition (ALD), etc.

[0039] Because the natural oxide layers of source 106-1 and drain 106-2 are relatively thick, i.e., the insulating layer 107 provides effective physical isolation between source 106-1, drain 106-2 and metal passivation layer 109, the source 106-1 and drain 106-2 of the sample will not be connected through metal passivation layer 109.

[0040] After depositing the metal passivation layer 109, the sample is exposed to the atmosphere for 1 to 2 days, allowing a full redox reaction to occur in the contact area between the metal passivation layer 109 and the OS channel 105. Oxygen in the OS channel 105 region is removed by the metal passivation layer, generating a large number of oxygen vacancies, significantly increasing the carrier concentration, and consequently, significantly improving the sample's mobility and turn-on current. The redox reaction occurring in the contact area between the metal passivation layer 109 and the OS channel 105 also forms a 1 to 3 nanometer-sized metal oxide layer at the interface, creating a second conditioning layer. Therefore, the area where the OS channel 105 contacts the source 106-1, drain 106-2, and metal passivation layer 109 together forms the conditioning layer 108.

[0041] The conditioning layer 108 is a product of the redox reaction between the metal and the OS channel 105. Because of its thinness, it does not have a significant impact on the contact resistance between the metal and the OS channel 105. It is precisely because the redox reaction between the metal and the OS channel 105 removes oxygen from the OS channel 105 that a large number of oxygen vacancies are generated, and the carrier concentration is greatly improved. Therefore, the sample mobility and turn-on current are also greatly improved.

[0042] Then, the metal passivation layer is patterned using dry etching methods such as ICP, thereby bringing out the three electrodes of the sample and completing the device fabrication.

[0043] This completes the fabrication of the back-gate oxide semiconductor device.

[0044] Depend on Figure 2As shown in the publicly available device schematic diagram, the back-gate oxide semiconductor device of the present invention comprises, from bottom to top, a substrate 101, a back gate layer, a channel layer, and a passivation layer 109. The back gate layer includes, from bottom to top, a back gate 103 and a gate dielectric layer 104. The channel layer includes a source 106-1, a drain 106-2, and an OS channel 105 that is electrically in contact with the source 106-1, the drain 106-2, and the passivation layer 109. An insulating layer 107 is disposed on the contact surface between the source 106-1, the drain 106-2, and the passivation layer 109. An adjustment layer 108 is disposed on the contact surface between the OS channel 105 and the source 106-1, the drain 106-2, and the passivation layer 109.

[0045] In the fabrication process of the back-gate oxide semiconductor device disclosed in this invention, the natural oxide layer of the source and drain electrodes is formed by natural oxidation, which realizes the electrical isolation between the source 106-1, drain 106-2 and metal passivation layer 109. It is no longer necessary to set an offset between the source and drain electrodes and the passivation layer, which has the potential for size reduction. At the same time, since it is no longer necessary to set an offset between the source and drain electrodes and the passivation layer, the metal passivation layer 109 can cover the entire upper surface of the OS channel 105, thereby capturing more oxygen in the OS material. A large number of oxygen vacancies are generated in the OS channel 105, which increases the carrier concentration in the contact area with the source 106-1 and drain 106-2, thus exhibiting excellent carrier mobility.

[0046] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A back-gate oxide semiconductor device, characterized in that: From bottom to top, it includes: a substrate, a back gate layer, a channel layer, and a passivation layer. The back gate layer includes a back gate and a gate dielectric layer disposed from bottom to top. The channel layer includes a source, a drain, and an OS channel that is electrically in contact with the source and drain. An insulating layer formed by the natural oxidation of the source and drain metals in air is disposed on the contact surface between the source and drain and the passivation layer. An adjustment layer formed by the oxidation-reduction reaction of the source and drain metals in the area in contact with the OS channel is disposed on the contact surface between the OS channel and the source, drain, and passivation layer.

2. The back-gate oxide semiconductor device according to claim 1, characterized in that: The material for the OS channel is any one or a combination of several of IGZO, ITO, IWO, ZnO, and InO.

3. The back-gate oxide semiconductor device according to claim 1, characterized in that: The insulation layer has a thickness of 5-10 nm, and the adjustment layer has a thickness of 1-3 nm.

4. The back-gate oxide semiconductor device according to claim 1, characterized in that: The gate dielectric layer is a single-layer structure composed of HfO2 or Al2O3, or a multilayer structure composed of both.

5. The back-gate oxide semiconductor device according to claim 1, characterized in that: The source and drain electrodes use any one or a combination of Mo, Al, Ti, TiN, and W.

6. A method for fabricating a back-gate oxide semiconductor device: characterized in that: Includes the following steps: S1. Deposit a gate conductive layer on the substrate and pattern it to form a back gate electrode; S2. Deposit a gate dielectric layer on the upper surface of the back gate electrode and pattern it; S3. Deposit a channel layer on the gate dielectric layer and pattern it to form the OS channel, so that the OS channel is located above the back gate electrode. S4. Deposit and pattern source and drain metal layers on both sides of the OS channel to form source and drain electrodes respectively. One end of the source and drain electrodes is electrically contacted with the OS channel. S5. The sample is placed in the atmospheric environment for the first time. The source and drain are fully exposed to the air and undergo natural oxidation to form an insulating layer. At the same time, the area where the source and drain are in contact with the OS channel will undergo a redox reaction to form the first conditioning layer. S6. Deposit a metal passivation layer on the upper surface of the device, the metal passivation layer covering the upper surfaces of the source and drain and the upper surface of the OS channel; S7. Place the sample in the atmospheric environment for the second time to allow the metal passivation layer to fully undergo a redox reaction in the contact area with the OS channel, forming a second conditioning layer. S8. The metal passivation layer is patterned, thereby bringing out the three electrodes of the sample, and the device fabrication is completed.

7. The preparation method according to claim 6, characterized in that: The material for the OS channel is any one or a combination of several of IGZO, ITO, IWO, ZnO, and InO.

8. The preparation method according to claim 6, characterized in that: The insulation layer has a thickness of 5-10 nm, and the first and second adjustment layers have a thickness of 1-3 nm.

9. The preparation according to claim 6, characterized in that: The gate dielectric layer is a single-layer structure composed of HfO2 or Al2O3, or a multilayer structure composed of both.

10. The preparation method according to claim 6, characterized in that: The source and drain electrodes use any one or a combination of Mo, Al, Ti, TiN, and W.

11. The method according to claim 6, characterized in that: The samples were first placed in the atmosphere for 1 to 3 days, and then placed in the atmosphere a second time for 1 to 2 days.

12. An electronic device, characterized in that: It includes at least the back-gate oxide semiconductor device as described in any one of claims 1-5.

13. The electronic device according to claim 12, characterized in that: The electronic device is a smartphone, computer, tablet computer, artificial intelligence, wearable device, or smart mobile terminal.

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