Successive approximation analog-to-digital converter and method thereof

Abstract

The disclosure provides a successive approximation type analog-to-digital converter, comprising: a capacitor array comprising N groups of differential capacitors and a switch array; a comparator, a first input end is connected with a differential positive end capacitor in each group of differential capacitors to respectively receive the voltage of the differential positive end capacitor, a second input end is connected with a differential negative end capacitor in each group of differential capacitors to respectively receive the voltage of the differential negative end capacitor, and an output voltage measurement value of each group of differential capacitors; a Sigma-Delta modulator, obtaining a calibration weight value of each group of differential capacitors of the N groups of differential capacitors; and a logic module, receiving the voltage measurement value of each group of differential capacitors output by the comparator, and calibrating the voltage measurement value of each group of differential capacitors according to the calibration weight value of each group of differential capacitors obtained by the Sigma-Delta modulator to generate a conversion output value.

Description

Technical Field

[0001] This disclosure relates to a successive approximation analog-to-digital converter. Background Technology

[0002] Successive approximation analog-to-digital converters (ADCs) are widely used due to their advantages such as low power consumption and small size. However, the accuracy of high-precision successive approximation ADCs is often limited by capacitor mismatch. In recent years, various solutions have been proposed to enhance the dynamic performance of successive approximation ADCs.

[0003] Due to capacitor mismatch, the weights between capacitors are not exact binary. In existing technologies, the converted signal obtained by directly using binary weighting in the digital domain deviates from the actual analog voltage, causing a decrease in the accuracy of successive approximation analog-to-digital converters. Therefore, it is necessary to calibrate the capacitor mismatch in successive approximation analog-to-digital converters. Summary of the Invention

[0004] To address one of the aforementioned technical problems, this disclosure provides a successive approximation analog-to-digital converter and its method.

[0005] According to one aspect of this disclosure, a successive approximation analog-to-digital converter includes:

[0006] A capacitor array, comprising N groups of differential capacitors and a switch array, wherein each group of differential capacitors comprises a differential positive terminal capacitor and a differential negative terminal capacitor, and the switch array is configured to connect the differential positive terminal capacitor and the differential negative terminal capacitor of the N groups of differential capacitors to a positive reference voltage and an anti-phase reference voltage, respectively, wherein N > 1;

[0007] A comparator, wherein the first input terminal of the comparator is connected to the differential positive terminal capacitor of each group of differential capacitors to receive the voltage of the differential positive terminal capacitor respectively, the second input terminal of the comparator is connected to the differential negative terminal capacitor of each group of differential capacitors to receive the voltage of the differential negative terminal capacitor respectively, and outputs the voltage measurement value of each group of differential capacitors.

[0008] A Sigma-Delta modulator is used to obtain the calibration weight value for each of the N groups of differential capacitors; and

[0009] A logic module is configured to receive the voltage measurement values ​​of each group of differential capacitors output by the comparator, and calibrate the voltage measurement values ​​of each group of differential capacitors according to the calibration weight values ​​of each group of differential capacitors obtained by the Sigma-Delta modulator, so as to generate a conversion output value.

[0010] A successive approximation analog-to-digital converter according to at least one embodiment of the present disclosure further includes a memory for storing calibration weight values ​​obtained from the Sigma-Delta modulator, so as to recall the calibration weight values ​​to calibrate the voltage measurements of each group of differential capacitors during actual operation of the analog-to-digital converter.

[0011] According to at least one embodiment of the present disclosure, in a successive approximation analog-to-digital converter, the calibration weight value of each group of differential capacitors is multiplied by the voltage measurement value of each group of differential capacitors, and the products of each group of differential capacitors are added together to obtain the conversion output value.

[0012] According to at least one embodiment of the successive approximation analog-to-digital converter of this disclosure, during the calibration of a set of differential capacitors,

[0013] The base plate of the positive differential capacitor in this group is connected to a positive-inverting reference voltage, and the base plate of the negative differential capacitor is connected to an inverting reference voltage. All other groups of differential capacitors are connected to inverting reference voltages. The voltage of this group of differential capacitors is converted by the Sigma-Delta modulator to obtain the first calibration value.

[0014] The base plate of the positive differential capacitor in this group is connected to an inverting reference voltage, and the base plate of the negative differential capacitor is connected to a positive reference voltage. All other groups of differential capacitors are connected to an inverting reference voltage. The voltage of this group of differential capacitors is converted by the Sigma-Delta modulator to obtain the second calibration value.

[0015] The calibration weight value is obtained by subtracting the second calibration value from the first calibration value.

[0016] According to at least one embodiment of the present disclosure, a successive approximation analog-to-digital converter obtains calibration weight values ​​corresponding to each group of differential capacitors in order from the lowest capacitance to the highest capacitance for N groups of differential capacitors.

[0017] According to at least one embodiment of the successive approximation analog-to-digital converter of the present disclosure, the Sigma-Delta modulator includes:

[0018] An amplifier, wherein the two input terminals of the amplifier are respectively connected to the voltages of the positive differential capacitor and the negative differential capacitor of the differential capacitor;

[0019] A quantizer, used to quantize the output of the amplifier;

[0020] A digital filter is used to filter the quantization result of the quantizer in order to obtain the calibration weight value.

[0021] According to another aspect of this disclosure, a successive approximation analog-to-digital conversion method is provided, comprising:

[0022] Connect the base plate of the positive differential capacitor of a group of differential capacitors to the positive reference voltage and the base plate of the negative differential capacitor to the inverted reference voltage. Connect all other groups of differential capacitors to the inverted reference voltage. Convert the voltage of this group of differential capacitors through a Sigma-Delta modulator to obtain the first calibration value.

[0023] The base plate of the positive differential capacitor of this group of differential capacitors is connected to an inverting reference voltage, and the base plate of the negative differential capacitor is connected to a positive reference voltage. All other groups of differential capacitors are connected to an inverting reference voltage. The voltage of this group of differential capacitors is converted by the Sigma-Delta modulator to obtain the second calibration value.

[0024] The calibration weight value is obtained by subtracting the second calibration value from the first calibration value; and

[0025] The conversion output value is generated by multiplying the calibration weight value by the voltage measurement of the group of differential capacitors.

[0026] The successive approximation analog-to-digital conversion method according to at least one embodiment of the present disclosure includes N groups of differential capacitors, and obtains calibration weight values ​​corresponding to each group of differential capacitors in order from the low-order capacitor to the high-order capacitor of the N groups of differential capacitors.

[0027] According to at least one embodiment of the successive approximation analog-to-digital conversion method of the present disclosure, the calibration weight value of each group of differential capacitors is multiplied by the voltage measurement value of each group of differential capacitors, and the products of each group of differential capacitors are added together to obtain the conversion output value of the analog-to-digital conversion.

[0028] According to at least one embodiment of the successive approximation analog-to-digital conversion method of this disclosure, the corresponding calibration weight values ​​of each group of differential capacitors are stored in a memory so that the corresponding calibration weight values ​​of each group of differential capacitors can be called during actual conversion. Attached Figure Description

[0029] The accompanying drawings illustrate exemplary embodiments of the present disclosure and, together with the description thereof, serve to explain the principles of the present disclosure. These drawings are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this specification.

[0030] Figure 1 A schematic diagram of a successive approximation analog-to-digital converter according to an embodiment of the present disclosure is shown.

[0031] Figure 2 A schematic diagram of a capacitor array for a successive approximation analog-to-digital converter according to an embodiment of the present disclosure is shown.

[0032] Figure 3A schematic diagram of a successive approximation analog-to-digital converter according to an embodiment of the present disclosure is shown.

[0033] Figure 4 A schematic diagram of a successive approximation analog-to-digital converter according to an embodiment of the present disclosure is shown.

[0034] Figure 5 A schematic diagram of a Sigma-Delta modulator according to an embodiment of the present disclosure is shown.

[0035] Figure 6 A schematic diagram of a successive approximation analog-to-digital conversion method according to an embodiment of the present disclosure is shown. Detailed Implementation

[0036] The present disclosure will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the scope of the disclosure. Furthermore, it should be noted that, for ease of description, only the parts relevant to the present disclosure are shown in the accompanying drawings.

[0037] It should be noted that, where there is no conflict, the embodiments and features described in this disclosure can be combined with each other. The technical solutions of this disclosure will now be described in detail with reference to the accompanying drawings and embodiments.

[0038] Unless otherwise stated, the exemplary implementations / embodiments shown are to be understood as providing exemplary features of various details that provide ways in which the technical concepts of this disclosure can be implemented in practice. Therefore, unless otherwise stated, the features of various implementations / embodiments may be additionally combined, separated, interchanged and / or rearranged without departing from the technical concepts of this disclosure.

[0039] The use of crosshairs and / or shading in the accompanying drawings is generally used to clarify the boundaries between adjacent components. Thus, unless otherwise stated, the presence or absence of crosshairs or shading does not convey or indicate any preference or requirement for the specific material, material properties, dimensions, proportions, commonalities between the illustrated components, or any other characteristics, properties, etc., of the components. Furthermore, in the accompanying drawings, the dimensions and relative dimensions of components may be exaggerated for clarity and / or descriptive purposes. When exemplary embodiments can be implemented differently, a specific process sequence may be performed in a different order than that described. For example, two consecutively described processes may be performed substantially simultaneously or in the reverse order of their description. Furthermore, the same reference numerals denote the same components.

[0040] When a component is referred to as being "on" or "above" another component, "connected to," or "joined to" another component, the component may be directly on, directly connected to, or directly joined to the other component, or there may be intermediate components. However, when a component is referred to as being "directly on" another component, "directly connected to," or "directly joined to" another component, there are no intermediate components. Therefore, the term "connection" can refer to a physical connection, an electrical connection, etc., and may or may not have intermediate components.

[0041] For descriptive purposes, this disclosure may use spatial relative terms such as “below,” “under,” “below,” “down,” “above,” “above,” “higher,” and “side (e.g., in a “sidewall”)” to describe the relationship between one component and another component as shown in the accompanying drawings. In addition to the orientations depicted in the drawings, the spatial relative terms are also intended to encompass different orientations of the device during use, operation, and / or manufacture. For example, if the device in the drawings is flipped, a component described as “below” or “under” another component or feature would subsequently be positioned “above” said other component or feature. Thus, the exemplary term “below” can encompass both “above” and “below” orientations. Furthermore, the device may be otherwise positioned (e.g., rotated 90 degrees or in other orientations), thus interpreting the spatial relative descriptive terms used herein accordingly.

[0042] The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting. As used herein, unless the context clearly indicates otherwise, the singular forms “a” and “the” are intended to include the plural forms as well. Furthermore, when the terms “comprising” and / or “including” and variations thereof are used in this specification, it indicates the presence of the stated features, integrals, steps, operations, parts, components, and / or groups thereof, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, parts, components, and / or groups thereof. It should also be noted that, as used herein, the terms “substantially,” “about,” and other similar terms are used as approximate terms rather than as terms of degree, thus explaining the inherent biases in measurements, calculated values, and / or provided values ​​that would be recognized by one of ordinary skill in the art.

[0043] According to one embodiment of this disclosure, a successive approximation analog-to-digital converter (SAR ADC) is provided.

[0044] like Figure 1 As shown, the successive approximation analog-to-digital converter may include a first capacitor array 100, a second capacitor array 200, a comparator 300, and a logic module 400.

[0045] The first capacitor array 100 is a differential positive-terminal capacitor array, and the first input terminal of the comparator 300 is connected to the first capacitor array 100. The second capacitor array 200 is a differential negative-terminal capacitor array, and the second input terminal of the comparator 300 is connected to the second capacitor array 200. The comparator 300 compares the voltages between the first capacitor array 100 and the second capacitor array 200 and provides the comparison result to the logic module 400. That is, the capacitor array includes N groups of differential capacitors and a switch array. Each group of differential capacitors includes differential positive-terminal capacitors and differential negative-terminal capacitors. The switch array is configured to connect the differential positive-terminal capacitors and differential negative-terminal capacitors of the N groups of differential capacitors to a positive-inverting reference voltage and an anti-inverting reference voltage, respectively, where N > 1. The first capacitor array 100 and the second capacitor array 200 include capacitors and switches connected to the capacitors. Each switch switches between voltage VRN (anti-inverting reference voltage) and VRP (positive reference voltage). Figure 2 As shown. The first input terminal of the comparator is connected to the positive differential capacitor in each group of differential capacitors to receive the voltage of the positive differential capacitor, and the second input terminal of the comparator is connected to the negative differential capacitor in each group of differential capacitors to receive the voltage of the negative differential capacitor, and outputs the voltage measurement value of each group of differential capacitors.

[0046] The logic module 400 controls the switches in the first capacitor array 100 or the second capacitor array 200 based on the comparison result. Additionally, it receives the voltage measurement values ​​of each group of differential capacitors output by the comparator and calibrates the voltage measurement values ​​of each group of differential capacitors according to the calibration weight values ​​of each group of differential capacitors obtained from the Sigma-Delta modulator to generate a conversion output value.

[0047] The first capacitor array 100 includes a first low-order capacitor array 110 and a first high-order capacitor array 120, wherein the first low-order capacitor array 110 and the first high-order capacitor array 120 are connected through a first capacitor 1C. The second capacitor array 200 includes a second low-order capacitor array 210 and a second high-order capacitor array 220, wherein the second low-order capacitor array 210 and the second high-order capacitor array 220 are connected through a second capacitor 1C.

[0048] SAR ADCs are widely used due to their advantages such as small area. However, the accuracy of high-precision SAR ADCs is often limited by capacitor mismatch. This disclosure proposes a calibration technique for the capacitor array of a SAR ADC, which measures the capacitor weight error after power-on to avoid accuracy loss caused by capacitor mismatch.

[0049] This disclosure employs a 9+7 segmentation structure. That is, there can be 9 high-order capacitors and 7 low-order capacitors. Thus, each SAR ADC conversion yields 16 digital codes: D16, D15, D14, ..., D2, D1. Without calibration, the digital domains are weighted according to the following formula:

[0050] Dout=D16*2^16+D15*2^15+D14*2^14+……+D2*2^2+D1*2^1.

[0051] However, due to capacitor mismatch, the weights between capacitors are not accurate binary. The output Dout obtained by directly using binary weighting in the digital domain will deviate from the actual analog voltage, causing a decrease in ADC accuracy. Therefore, it is necessary to calibrate the capacitor mismatch of the SAR ADC.

[0052] To address the issue of random mismatch in calibration capacitors, this disclosure calculates the weights of the actual capacitors and incorporates these actual weights into the calculation when performing digital weighting.

[0053] The calibration weight value of each capacitor is measured using a Sigma-Delta modulator, and the result is stored in a programmable memory (efuse). In actual operation, the measured weight values ​​are called up and added in the digital domain.

[0054] The specific calibration process will be described in detail below. The first capacitor array comprises N capacitors, and the second capacitor array comprises N capacitors, where N is an integer greater than 1, preferably ≥16.

[0055] In this application, the capacitors of the first capacitor array are referred to as differential positive terminal capacitors, and the capacitors of the second capacitor array are referred to as differential negative terminal capacitors.

[0056] The first capacitor array comprises N differential positive terminal capacitors, numbered B1, B2, ..., BN-1, BN from least to most significant bit. The second capacitor array comprises N differential positive terminal capacitors, numbered B1, B2, ..., BN-1, BN from least to most significant bit. The actual weights of B1, B2, ..., BN-1, BN are measured using a Sigma-Delta modulator.

[0057] In this disclosure, when calibrating capacitor B1, the base plate of the differential positive capacitor B1 is first connected to VRP, the base plate of the differential negative capacitor B1 is connected to VRN, and the base plates of the differential positive and differential negative capacitors B2 to BN are all connected to VRN. Then, the voltage of capacitor B1 is converted using a Sigma-Delta modulator, and the conversion result is B1_p. For example... Figure 3 As shown.

[0058] Next, connect the base plate of differential positive capacitor B1 to VRN, and the base plate of differential negative capacitor B1 to VRP, keeping the connections of other capacitors unchanged. Then, use a Sigma-Delta modulator to convert the voltage of capacitor B1, obtaining the conversion result as B1_n. Then calculate the calibration weight of capacitor B1 as B1_cal = B1_p - B1_n, and store this value in programmable memory. B1_cal is then called every time digital domain weighting is performed. For example... Figure 4 As shown.

[0059] When calibrating capacitor B2, first connect the base plate of the differential positive capacitor B2 to VRP, and the base plate of the differential negative capacitor B2 to VRN. Connect the base plates of all differential positive and differential negative capacitors B1, B3, and so on, to VRN. Then, convert the voltage of capacitor B2 using a Sigma-Delta modulator, resulting in B2_p. Next, connect the base plate of differential positive capacitor B2 to VRN, and the base plate of differential negative capacitor B2 to VRP, keeping the connections of the other capacitors unchanged. Then, convert the voltage of capacitor B2 again using a Sigma-Delta modulator, resulting in B2_n. Calculate the calibration weight value for capacitor B2 as B2_cal = B2_p - B2_n, and store this value in programmable memory. B2_cal is then called every time digital domain weighting is performed.

[0060] Then, capacitors B3 to BN are calibrated using the same method described above. For example, when calibrating capacitor BN, first connect the base plate of the differential positive capacitor BN to VRP, the base plate of the differential negative capacitor BN to VRN, and the base plates of all differential positive and differential negative capacitors B1 to BN-1 to VRN. Then, the voltage of capacitor BN is converted using a Sigma-Delta modulator, and the conversion result is BN_p. Next, connect the base plate of differential positive capacitor BN to VRN, and the base plate of differential negative capacitor BN to VRP, keeping the connections of other capacitors unchanged. Then, the voltage of capacitor BN is converted using a Sigma-Delta modulator, and the conversion result is BN_n. The calibration weight value of capacitor BN is then calculated as BN_cal = BN_p - BN_n, and this value is stored in the programmable memory. BN_cal is then called every time digital domain weighting is performed.

[0061] After similar operations, we can obtain the calibration weight value B1_cal for B1, the calibration weight value B2_cal for B2, the calibration weight value B3_cal for B3, ..., the calibration weight value BN_cal for BN.

[0062] In summary, during the calibration of a group of differential capacitors, the base plate of the positive differential capacitor is connected to a positive-inverting reference voltage, and the base plate of the negative differential capacitor is connected to an inverting reference voltage. All other differential capacitors are connected to an inverting reference voltage. The voltage of this group of differential capacitors is converted by the Sigma-Delta modulator to obtain a first calibration value. The base plate of the positive differential capacitor is then connected to an inverting reference voltage, and the base plate of the negative differential capacitor is connected to a positive-inverting reference voltage. All other differential capacitors are connected to an inverting reference voltage. The voltage of this group of differential capacitors is converted by the Sigma-Delta modulator to obtain a second calibration value. The calibration weight value is obtained by subtracting the second calibration value from the first calibration value.

[0063] After calibration, the SAR ADC enters normal analog-to-digital conversion mode. Each time the SAR ADC completes a conversion, it obtains N digital codes DN, DN-1, DN-2, ..., D2, D1. The digital domains are weighted according to the following formula:

[0064] Dout = DN*BN_cal + DN-1*BN-1_cal + ... + D2*B2_cal + D1*B1_cal. Where BN_cal is the calibration weight value of the Nth group of differential capacitors, DN is the digital code of the Nth group of differential capacitors, BN-1_cal is the calibration weight value of the (N-1)th group of differential capacitors, DN-1 is the digital code (voltage measurement value) of the (N-1)th group of differential capacitors, B2_cal is the calibration weight value of the 2nd group of differential capacitors, D2 is the digital code of the 2nd group of differential capacitors, B1_cal is the calibration weight value of the 1st group of differential capacitors, and D1 is the digital code of the 1st group of differential capacitors.

[0065] Because BN_cal, BN-1_cal, ..., B1_cal are calculated based on the actual capacitance values, the output Dout can better approximate the analog input voltage, thus achieving a high-precision SAR ADC.

[0066] In summary, during the calibration process, a Sigma-Delta modulator is used to measure the actual weights of B1 to BN. The calibration order can be B1 --> BN, yielding B1_cal to BN_cal, which are stored in memory. During the actual conversion, B1_cal to BN_cal are called to perform weight addition in the digital domain.

[0067] Figure 5 A schematic diagram of a Sigma-Delta modulator according to one embodiment of the present disclosure is shown. Figure 5As shown, the Sigma-Delta modulator may include an amplifier and a quantizer, wherein the two input terminals of the amplifier are connected to the voltages of the differential positive and differential negative terminals of a differential capacitor, respectively. The quantizer is used to quantize the output of the amplifier and control the switching array to turn on and off based on the quantization result. Furthermore, the Sigma-Delta modulator may also include a digital filter to filter the quantization result from the quantizer to obtain calibration weight values.

[0068] According to a further embodiment of this disclosure, a successive approximation analog-to-digital conversion method is also provided. Figure 6 A flowchart based on this method is shown.

[0069] In step S102, the base plate of the positive differential capacitor of a group of differential capacitors is connected to the positive reference voltage and the base plate of the negative differential capacitor is connected to the inverted reference voltage. All other groups of differential capacitors are connected to the inverted reference voltage. The voltage of the group of differential capacitors is converted by the Sigma-Delta modulator to obtain the first calibration value.

[0070] In step S104, the base plate of the differential positive terminal capacitor of the group of differential capacitors is connected to an inverting reference voltage, and the base plate of the differential negative terminal capacitor is connected to a positive reference voltage. All other groups of differential capacitors are connected to an inverting reference voltage. The voltage of the group of differential capacitors is converted by the Sigma-Delta modulator to obtain the second calibration value.

[0071] In step S106, the calibration weight value is obtained by subtracting the second calibration value from the first calibration value.

[0072] In step S108, the conversion output value is generated by multiplying the calibration weight value by the voltage measurement value of the group of differential capacitors.

[0073] It should be noted that, Figures 1 to 5 The relevant descriptions can be incorporated into the method description, which will not be repeated here for the sake of brevity. For example, it includes N groups of differential capacitors, and the calibration weight values ​​corresponding to each group of differential capacitors are obtained sequentially from the lowest to the highest capacitance value. The calibration weight value of each group of differential capacitors is multiplied by the voltage measurement value of each group, and the products of each group are summed to obtain the conversion output value of the analog-to-digital converter. The corresponding calibration weight value of each group of differential capacitors is stored in memory so that the corresponding calibration weight value of each group of differential capacitors can be called during actual conversion.

[0074] As described above, the N differential positive terminal capacitors in the first capacitor array are named B1, B2, ..., BN-1, BN from least to most significant bit. The N differential positive terminal capacitors in the second capacitor array are named B1, B2, ..., BN-1, BN from least to most significant bit. The actual weights of B1, B2, ..., BN-1, BN are measured using a Sigma-Delta modulator.

[0075] In this disclosure, when calibrating capacitor B1, the base plate of the differential positive capacitor B1 is first connected to VRP, the base plate of the differential negative capacitor B1 is connected to VRN, and the base plates of the differential positive and differential negative capacitors B2 to BN are all connected to VRN. Then, the voltage of capacitor B1 is converted using a Sigma-Delta modulator, and the conversion result is B1_p. For example... Figure 3 As shown.

[0076] Next, connect the base plate of differential positive capacitor B1 to VRN, and the base plate of differential negative capacitor B1 to VRP, keeping the connections of other capacitors unchanged. Then, use a Sigma-Delta modulator to convert the voltage of capacitor B1, obtaining the conversion result as B1_n. Then calculate the calibration weight of capacitor B1 as B1_cal = B1_p - B1_n, and store this value in programmable memory. B1_cal is then called every time digital domain weighting is performed. For example... Figure 4 As shown.

[0077] When calibrating capacitor B2, first connect the base plate of the differential positive capacitor B2 to VRP, and the base plate of the differential negative capacitor B2 to VRN. Connect the base plates of all differential positive and differential negative capacitors B1, B3, and so on, to VRN. Then, convert the voltage of capacitor B2 using a Sigma-Delta modulator, resulting in B2_p. Next, connect the base plate of differential positive capacitor B2 to VRN, and the base plate of differential negative capacitor B2 to VRP, keeping the connections of the other capacitors unchanged. Then, convert the voltage of capacitor B2 again using a Sigma-Delta modulator, resulting in B2_n. Calculate the calibration weight value for capacitor B2 as B2_cal = B2_p - B2_n, and store this value in programmable memory. B2_cal is then called every time digital domain weighting is performed.

[0078] Then, capacitors B3 to BN are calibrated using the same method described above. For example, when calibrating capacitor BN, first connect the base plate of the differential positive capacitor BN to VRP, the base plate of the differential negative capacitor BN to VRN, and the base plates of all differential positive and differential negative capacitors B1 to BN-1 to VRN. Then, the voltage of capacitor BN is converted using a Sigma-Delta modulator, and the conversion result is BN_p. Next, connect the base plate of differential positive capacitor BN to VRN, and the base plate of differential negative capacitor BN to VRP, keeping the connections of other capacitors unchanged. Then, the voltage of capacitor BN is converted using a Sigma-Delta modulator, and the conversion result is BN_n. The calibration weight value of capacitor BN is then calculated as BN_cal = BN_p - BN_n, and this value is stored in the programmable memory. BN_cal is then called every time digital domain weighting is performed.

[0079] After similar operations, we can obtain the calibration weight value B1_cal for B1, the calibration weight value B2_cal for B2, the calibration weight value B3_cal for B3, ..., the calibration weight value BN_cal for BN.

[0080] After calibration, the SAR ADC enters normal analog-to-digital conversion mode. Each time the SAR ADC completes a conversion, it obtains N digital codes DN, DN-1, DN-2, ..., D2, D1. The digital domains are weighted according to the following formula:

[0081] Dout = DN*BN_cal + DN-1*BN-1_cal + ... + D2*B2_cal + D1*B1_cal. Where BN_cal is the calibration weight value of the Nth group of differential capacitors, DN is the digital code of the Nth group of differential capacitors, BN-1_cal is the calibration weight value of the (N-1)th group of differential capacitors, DN-1 is the digital code (voltage measurement value) of the (N-1)th group of differential capacitors, B2_cal is the calibration weight value of the 2nd group of differential capacitors, D2 is the digital code of the 2nd group of differential capacitors, B1_cal is the calibration weight value of the 1st group of differential capacitors, and D1 is the digital code of the 1st group of differential capacitors.

[0082] In the description of this specification, the references to terms such as "one embodiment / mode," "some embodiments / modes," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment / mode or example is included in at least one embodiment / mode or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment / mode or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments / modes or examples. Furthermore, without contradiction, those skilled in the art can combine and integrate the different embodiments / modes or examples described in this specification, as well as the features of different embodiments / modes or examples.

[0083] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0084] Those skilled in the art should understand that the above embodiments are merely for illustrating the present disclosure and are not intended to limit the scope of the disclosure. Those skilled in the art can make other changes or modifications based on the above disclosure, and these changes or modifications still fall within the scope of the present disclosure.

Claims

1. A successive approximation analog-to-digital converter, characterized by, The application comprises: a capacitor array, which comprises N groups of differential capacitors and a switch array, each group of differential capacitors comprising a differential positive end capacitor and a differential negative end capacitor, and the switch array being configured to connect the differential positive end capacitors and the differential negative end capacitors of the N groups of differential capacitors to a positive phase reference voltage and an inverted phase reference voltage respectively, wherein N>1; a comparator, a first input terminal of the comparator being connected to the differential positive end capacitors in each group of differential capacitors to receive the voltages of the differential positive end capacitors respectively, a second input terminal of the comparator being connected to the differential negative end capacitors in each group of differential capacitors to receive the voltages of the differential negative end capacitors respectively, and the comparator outputting voltage measurement values of each group of differential capacitors; a Sigma-Delta modulator, which is used to obtain calibration weight values of each group of differential capacitors of the N groups of differential capacitors; and a logic module, which is used to receive the voltage measurement values of each group of differential capacitors output by the comparator, and calibrate the voltage measurement values of each group of differential capacitors according to the calibration weight values of each group of differential capacitors obtained by the Sigma-Delta modulator to generate a conversion output value. The Sigma-Delta modulator comprises: an amplifier, two input terminals of the amplifier being connected to the voltages of the differential positive end capacitors and the differential negative end capacitors of the differential capacitors respectively; a quantizer, which is used to quantize the output of the amplifier; a digital filter, which filters the quantization results of the quantizer to obtain the calibration weight values.

2. The successive approximation analog-to-digital converter of claim 1, wherein, Further comprising a memory, which is used to store the calibration weight values obtained by the Sigma-Delta modulator, so as to call the calibration weight values to calibrate the voltage measurement values of each group of differential capacitors when the analog-to-digital converter actually works.

3. The successive approximation analog-to-digital converter of claim 1, wherein, The calibration weight values of each group of differential capacitors are multiplied by the voltage measurement values of each group of differential capacitors respectively, and the products of each group of differential capacitors are added to obtain the conversion output value.

4. The successive approximation analog-to-digital converter of any one of claims 1 to 3, wherein, In the process of calibrating a group of differential capacitors, the bottom plate of the differential positive end capacitor of the group of differential capacitors is connected to the positive phase reference voltage and the bottom plate of the differential negative end capacitor is connected to the inverted phase reference voltage, and the bottom plates of the differential positive end capacitors and the differential negative end capacitors of the other groups of differential capacitors are all connected to the inverted phase reference voltage, the voltage of the group of differential capacitors is converted by the Sigma-Delta modulator to obtain a first calibration value, the bottom plate of the differential positive end capacitor of the group of differential capacitors is connected to the inverted phase reference voltage and the bottom plate of the differential negative end capacitor is connected to the positive phase reference voltage, and the bottom plates of the differential positive end capacitors and the differential negative end capacitors of the other groups of differential capacitors are all connected to the inverted phase reference voltage, the voltage of the group of differential capacitors is converted by the Sigma-Delta modulator to obtain a second calibration value, the calibration weight value is obtained by subtracting the second calibration value from the first calibration value.

5. The successive approximation analog-to-digital converter of claim 4, wherein, The calibration weight values corresponding to the N groups of differential capacitors are obtained in order from low bit capacitors to high bit capacitors.

6. A successive approximation type analog-digital conversion method based on the successive approximation type analog-digital converter according to any one of claims 1 to 5, characterized in that, comprises: connecting the bottom plate of the differential positive end capacitor of a group of differential capacitors to the positive phase reference voltage and the bottom plate of the differential negative end capacitor to the inverted phase reference voltage, and connecting the bottom plates of the differential positive end capacitors and the differential negative end capacitors of the other groups of differential capacitors to the inverted phase reference voltage, and converting the voltage of the group of differential capacitors by the Sigma-Delta modulator to obtain a first calibration value; The bottom plate of the differential positive end capacitor of the group of differential capacitors is connected to an inverted reference voltage and the bottom plate of the differential negative end capacitor is connected to a positive reference voltage, all other group of differential capacitors are connected to an inverted reference voltage, the voltage of the group of differential capacitors is converted by the Sigma-Delta modulator to obtain a second calibration value; The calibration weight value is obtained by subtracting the second calibration value from the first calibration value; And The conversion output value is generated by multiplying the calibration weight value by the voltage measurement value of the group of differential capacitors.

7. The method of claim 6, wherein, N groups of differential capacitors are included, and calibration weight values corresponding to each group of differential capacitors are obtained in order from low to high capacitors of the N groups of differential capacitors.

8. The method of claim 7, wherein, The calibration weight value of each group of differential capacitors is multiplied by the voltage measurement value of each group of differential capacitors, and the products of each group of differential capacitors are added to obtain the conversion output value of the analog-to-digital conversion.

9. The method of claim 7 or 8, wherein, The corresponding calibration weight value of each group of differential capacitors is stored in the memory, so that the corresponding calibration weight value of each group of differential capacitors can be called when actual conversion is performed.

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