A CS-DCSK-Based Reference-Free Modem and Modulation / Demodulation Method

Abstract

The present invention discloses a reference-free modem and a modulation and demodulation method based on CS-DCSK. The modem includes a modulator and a demodulator. A reference-free modulation and demodulation method is implemented through the modem. The modulation and demodulation method includes: at the sending end, for each data bit corresponding to each data information to be sent, it successively passes through a binary-to-decimal converter, a polarity converter, an index selector, a Walsh code matrix register, a modulation multiplier, and a modulation adder and then is sent to the demodulator. At the receiving end, the demodulator successively uses a demodulation multiplier, an averager, a correlation multiplier, an energy detector, a decimal-to-binary converter, and a threshold decision maker to recover each data bit in the data information to be sent. Through the technical solution of the present invention, the energy efficiency and bit error performance of the system are improved by removing the step of sending a reference signal in the code-shift differential chaos shift keying system.

Description

Technical Field

[0001] The present invention relates to the field of communication technologies, and in particular to a reference-free modem and a modulation and demodulation method based on CS-DCSK. Background Art

[0002] Chaotic signals have characteristics such as non-periodicity, wide spectrum, and good autocorrelation. Considering that traditional wireless communication systems, including radio, wireless personal area network (WPAN), and indoor communication systems, are extremely vulnerable to multipath fading and signal distortion, a chaotic communication scheme using broadband aperiodic chaotic signals as carriers has become a more effective communication scheme due to its low power consumption, low complexity, and excellent anti-fading performance. In addition, as a spread spectrum communication system, the aperiodic characteristics of chaotic signals also contribute to enhancing the security of chaotic-based communication systems in terms of anti-interference ability and intercept probability. Therefore, in the past three decades, chaotic communication has attracted extensive interest from communication researchers.

[0003] Due to the lack of reliable and effective methods to achieve chaotic synchronization at the receiving end, most of the existing chaotic digital modulation and demodulation methods are based on the transmission reference method. That is, both the carrier signal and the information-carrying signal are sent to the receiving end. Among them, the differential chaos shift keying (DCSK) modulation and demodulation method does not require channel estimation and can obtain good bit error performance. However, a large number of radio frequency delay circuits are inevitably required in the transceiver of this method. And it is difficult to implement these delay circuits through CMOS technology and integrate them, so it limits its application in ultra-wideband (UWB) systems. Summary of the Invention

[0004] The purpose of the present invention is to provide a reference-free modem and a modulation and demodulation method based on CS-DCSK to solve the problems in the prior art. For the above problems, the code-shifted differential chaos shift keying (CS-DCSK) modulation and demodulation method uses the orthogonality between different Walsh code sequences to modulate the reference signal and the information signal respectively and transmits them in the same time slot. Although the use of delay circuits is avoided at the receiving end, CS-DCSK has a low utilization rate of the Walsh code matrix, and because the reference signal needs to be transmitted, the energy efficiency of the entire modulation and demodulation method is low, and the bit error performance is not outstanding enough.

[0005] To achieve the above object, the present invention provides the following technical solutions:

[0006] A CS-DCSK-based reference-free modem is used to collect a preset number of data bits to be transmitted within a symbol period. Based on each data bit included in the information signal to be transmitted, for each data bit to be transmitted, the last data bit is used as the polarity modulation bit, and the remaining data bits except the polarity modulation bit are evenly divided to obtain two sets of data bits. The modem includes a modulator and a demodulator. The modulator modulates the data information to be transmitted and then sends it to the demodulator;

[0007] The modulator includes a chaotic signal generator, a pulse shaping filter, a binary-to-decimal converter, a polarity converter, an index selector, a Walsh code matrix register, a modulation multiplier, and a modulation adder;

[0008] The chaotic signal generator is used to generate a discrete chaotic signal sequence for transmitting data bits for each data bit corresponding to the data information to be transmitted within a symbol period. The discrete chaotic signal sequence is subjected to pulse shaping filtering through a pulse shaping filter to obtain the chaotic signal within this symbol period;

[0009] The binary-to-decimal converter is used to convert the data bits corresponding to the two sets of data bits into decimal numbers, and the polarity modulation bit is modulated from a data bit to a modulation bit through a polarity converter;

[0010] The Walsh code matrix register is used to store the Walsh code sequence matrix for modulating the chaotic signal. Two Walsh code matrix sequences with the decimal numbers corresponding to the data bit sets are selected from the Walsh code matrix register through an index selector. The two sequences are respectively used to modulate the chaotic signal by a modulation multiplier, and one of the modulated signals is further modulated by the modulation bit. The two signals are added by a modulation adder and then sent to the demodulator;

[0011] The demodulator receives the information signal after being added by the modulation adder sent by the modulator and demodulates the information signal. It includes a demodulation multiplier, an averager, a correlation multiplier, an energy detector, a decimal-to-binary converter, and a threshold decision maker;

[0012] The demodulation multiplier demodulates the received information signal using the Walsh code sequence. The demodulated information signal is averaged and denoised by an averager, and then the information signal is sequentially sent to a correlation multiplier, an energy detector, and a decimal-to-binary converter to obtain the data bit sets sent by the modulator. The threshold decision maker restores the modulation bit to the polarity modulation bit.

[0013] Another aspect of the present invention provides a reference-free modulation and demodulation method based on CS-DCSK, which performs reference-free modulation and demodulation on the information signal to be transmitted within the symbol period, including a transmitter and a receiver. The transmitter modulates the chaotic signal by using the data bits to be transmitted within the symbol period through a modulator. Specifically, it includes the following steps:

[0014] Step A: Collect a preset number of data bits to be transmitted within the symbol period. For each data bit corresponding to the information signal to be transmitted, use the last data bit as the polarity modulation bit, and divide the remaining data bits except the polarity modulation bit into two groups of data bit sets;

[0015] Step B: The chaotic signal generator generates a discrete chaotic signal sequence for transmitting data bits within the symbol period, and the discrete chaotic signal sequence forms a chaotic signal through a pulse shaping filter;

[0016] Step C: Convert the data bits corresponding to the two groups of data bit sets into decimal through a binary-to-decimal converter, and then convert the polarity modulation bit from a data bit to a modulation bit through a polarity converter;

[0017] Select two Walsh code matrix sequences with the decimal numbers corresponding to the data bit sets from the Walsh code matrix register through an index selector, modulate the chaotic signal with the two sequences respectively by a modulation multiplier, and modulate one of the modulated signals with the modulation bit again. Add the two signals to be transmitted through a modulation adder and then send them to the demodulator.

[0018] Further, the Walsh code matrix corresponding to the Walsh code matrix register includes upper and lower parts. The receiver is used to receive the data information sent by the transmitter and demodulate the data information through a demodulator, including the following steps:

[0019] Step D: The demodulator receives the information signal sent by the modulator, multiplies the received information signal with the upper and lower parts of the Walsh code matrix respectively through a modulation multiplier to obtain the corresponding demodulation matrices, and further performs average noise reduction on the demodulation matrices through an averager;

[0020] Step E: Transpose and multiply the two obtained demodulation matrices through a correlation multiplier to obtain a correlation matrix. Based on the correlation matrix, successively pass through an energy detector and a decimal-to-binary converter to recover the data bits corresponding to the two information signals corresponding to the transmitter respectively;

[0021] Step F: The threshold decision maker obtains the polarity modulation bit based on the data bits recovered from the two-way information.

[0022] Further, in the aforementioned step C, the Walsh code matrix register generates a Walsh code matrix of order N using a function and divides it vertically into two matrices of N / 2 rows, which are respectively called matrix A and matrix B; the two information signals to be transmitted respectively convert the data bits into decimal numbers through a binary-to-decimal converter and obtain index numbers, and two Walsh code matrix sequences with the decimal numbers corresponding to the data bit sets are selected from the Walsh code matrix register through an index selector, and the chaotic signal is modulated using the two sequences, and one of the modulated signals is further modulated using the modulation bits to obtain two information signals to be transmitted. After addition, the information signals are sent out.

[0023] Further, in the aforementioned step D, after obtaining the demodulation matrix, each row in the demodulation matrix is segmented according to a preset length, and the sum of each segment in each row is averaged to serve as the secondary demodulation matrix, completing average noise reduction.

[0024] The present invention, using the above technical solution, compared with the prior art, has the following technical effects:

[0025] The method of the present invention inherits the advantage of the code-shift differential chaos shift keying modulation and demodulation method of avoiding using a delay unit at the receiving end, and makes full use of the Walsh code matrix. More importantly, since the present invention does not require transmitting a reference signal, the energy efficiency of the system is higher and the bit error performance is also more excellent. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 is a schematic structural diagram of a modulator according to an exemplary embodiment of the present invention;

[0027] Figure 2 is a schematic structural diagram of a demodulator according to an exemplary embodiment of the present invention;

[0028] Figure 3 is a schematic flowchart of a modulation and demodulation method according to an exemplary embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0029] In order to better understand the technical content of the present invention, specific embodiments are hereby given and described in conjunction with the accompanying drawings as follows.

[0030] Aspects of the present invention are described with reference to the accompanying drawings, in which a number of illustrative embodiments are shown. Embodiments of the present disclosure do not necessarily define all aspects of the present invention. It should be understood that the various concepts and embodiments introduced above, as well as those described in more detail below, can be implemented in any of a number of ways, because the concepts and embodiments disclosed in the present invention are not limited to any particular implementation. Additionally, some aspects of the present disclosure can be used alone or in any suitable combination with other aspects of the present disclosure.

[0031] Referring to Figure 1 , Figure 2 , the present invention provides a reference-free modem based on CS-DCSK, which is used to collect a preset number of data bits to be transmitted within a symbol period. Based on each data bit included in the information signal to be transmitted, for each data bit to be transmitted, the last data bit is used as the polarity modulation bit, and the remaining data bits except the polarity modulation bit are evenly divided to obtain two sets of data bit sets. The modem includes a modulator and a demodulator. The modulator modulates the data information to be transmitted and then sends it to the demodulator;

[0032] The modulator includes a chaotic signal generator, a pulse shaping filter, a binary-to-decimal converter, a polarity converter, an index selector, a Walsh code matrix register, a modulation multiplier, and a modulation adder;

[0033] The chaotic signal generator is used to generate a discrete chaotic signal sequence for transmitting data bits for each data bit corresponding to the data information to be transmitted within a symbol period. The discrete chaotic signal sequence is subjected to pulse shaping filtering by the pulse shaping filter to obtain the chaotic signal within the symbol period;

[0034] The binary-to-decimal converter is used to convert the data bits corresponding to the two sets of data bit sets into decimal numbers, and the polarity modulation bit is modulated from a data bit to a modulation bit through the polarity converter;

[0035] The Walsh code matrix register is used to store the Walsh code sequence matrix for modulating the chaotic signal. Two Walsh code matrix sequences with decimal numbers corresponding to the data bit sets are selected from the Walsh code matrix register through the index selector. The two sequences are respectively used to modulate the chaotic signal by the modulation multiplier, and one of the modulated signals is further modulated by the modulation bit. The two signals are added by the modulation adder and then sent to the demodulator;

[0036] The demodulator receives the information signal sent by the modulator and demodulates the information signal. The [demodulator] includes a demodulation multiplier, an averager, a correlation multiplier, an energy detector, a decimal-to-binary converter, and a threshold decision maker;

[0037] The demodulation multiplier demodulates the received information signal using the Walsh code sequence. The demodulated information signal is averaged and denoised by the averager, and then the information signal is sequentially sent to the correlation multiplier, the energy detector, and the decimal-to-binary converter to obtain the data bit set sent by the modulator. The threshold decision maker restores the polarity of the modulation bit for the modulation bit.

[0038] Based on a reference-free modem provided by the present invention, referring to Figure 3 , in combination with the modem, the present invention exemplarily provides a reference-free modulation and demodulation method based on CS-DCSK. Combining steps A to C, the modulation process specifically includes the following steps:

[0039] Step 1: According to the 2n + 1 data bits to be sent in the current symbol period, divide them into two groups in sequence, with each group having n index bits, and polar-modulate the (2n + 1)-th data bit into a modulation bit. The specific rule of polar modulation is: if the data bit is 0, the modulation bit is -1; if the data bit is 1, the modulation bit remains 1.

[0040] Step 2: Use the logistic map, that is, to generate a discrete chaotic sequence of length β;

[0041] Step 3: Perform pulse shaping filtering on the discrete chaotic sequence generated in Step 2 to obtain the chaotic signal in the current symbol period;

[0042] Step 4: Use the Hadamard function to generate a Walsh code matrix of order N and divide it into two matrices of N / 2 rows each, which are respectively called matrix A = {W1, W2,... W N / 2} T and matrix B = {W N / 2+1 , W N / 2+2 ,... W N}, where N = 2 T ; n+1 ;

[0043] Step 5: Respectively convert the two groups of n bits generated in Step 1 from binary to decimal to obtain p and q, thereby determining the index numbers p + 1 and q + 1;

[0044] Step 6: The Walsh code sequence with index number p + 1 in matrix A is called W p+1, the Walsh code sequence with index number q + 1 in matrix B is called W q+1 ;

[0045] Step 7: Use the Walsh code sequence W with index number p + 1 in Step 6 p+1 to perform Kronecker product modulation on the chaotic signal and use it as the first information signal to be transmitted;

[0046] Step 8: Use the Walsh code sequence W with index number q + 1 in Step 6 q+1 to perform Kronecker product and multiply by the modulation bit on the chaotic signal for modulation, and use it as the second information signal to be transmitted;

[0047] Step 9: Add the two information signals generated in Step 7 and Step 8 and send them through the channel to the receiving end.

[0048] Combined with Step D to Step F, the demodulation process specifically includes the following steps:

[0049] Step 10: Perform Kronecker product on each row of the Walsh code sequence in matrix A with a 1-row and β-column all-ones matrix to obtain matrix Perform Hadamard product on the signal received at the receiving end with each row in matrix to obtain the first demodulation signal matrix Segment each row in the demodulation signal matrix by length β, and sum and average each segment in each row to obtain the second demodulation matrix

[0050] Step 11: Perform Kronecker product on each row of the Walsh code sequence in matrix B with a 1-row and β-column all-ones matrix to obtain matrix Perform Hadamard product on the signal received at the receiving end with each row in matrix to obtain the first demodulation signal matrix Segment each row in the demodulation signal matrix by length β, and sum and average each segment in each row to obtain the second demodulation matrix

[0051] Step 12: Multiply the demodulation matrix X by the transpose of the demodulation matrix Y to obtain a correlation matrix

[0052] Step 13: Judge the magnitude of the absolute value of the correlation matrix. The row and column numbers of the term with the largest absolute value are the two index numbers to be recovered and

[0053] Step 14: Restore the two groups of 2n index bits sent by respectively converting the two index numbers obtained in Step 13 from decimal to binary;

[0054] Step 15: Perform a threshold decision on the term with the largest absolute value obtained in Step 13 to restore the 2n + 1-th modulated bit sent. The rule of the threshold decision is: if the term value is greater than 0, the restored data bit is 1; if the term value is less than 0, the restored data bit is 0.

[0055] The above method uses two information signals to simultaneously transmit 2n + 1 data bits, where the first information signal transmits the n index bits carried by the first index number; the second information signal transmits the n index bits carried by the second index number and a polar modulation bit.

[0056] In the receiving end of the above method, multiply the received signal by the N / 2 row Walsh code sequences in matrix A and matrix B respectively and perform an averaging process. The obtained demodulated signals can be divided into two demodulation matrices X and Y with N / 2 rows. Multiply matrix X by the transpose of matrix Y to obtain a correlation matrix Z. Detect the row and column numbers of the term with the largest absolute value in the correlation matrix Z and convert them into binary to restore the first 2n index bits sent within the current symbol period; perform a threshold decision on the term with the largest absolute value to restore the 2n + 1-th modulated bit sent.

[0057] On this basis, the present invention also proposes a differential chaos shift keying modem without a reference code, which can modulate and demodulate signals by using the above method. Specifically, the modulator divides the 2n data bits to be sent into two groups of n index bits, respectively performs a binary-to-decimal conversion to determine the binary expressions p and q, and changes the 2n + 1-th data bit to be sent into a modulation bit through polar modulation. Modulate and add the chaos signal by using the Walsh code sequences with index numbers p + 1 and q + 1 and the polar modulation bit and then send it in the channel. The demodulator multiplies different Walsh code sequences by the received signal and performs an averaging and noise reduction process, obtains a correlation matrix by performing a correlation between different demodulated signals and detects it to restore the first 2n index bits sent within the current symbol period, and performs a threshold decision on the term with the largest absolute value in the correlation matrix to restore the 2n + 1-th modulation bit.

[0058] The structure of the modulator in the modem is as Figure 1As shown in the figure, it specifically includes: a chaotic signal generator, a pulse shaping filter, a Walsh code matrix register, a binary-to-decimal converter, a polarity converter, an index selector, a modulation multiplier, and an adder; the chaotic signal generator generates a discrete chaotic sequence, and after passing through the pulse shaping filter for pulse shaping filtering, a chaotic signal within the current symbol period is obtained; the Walsh code matrix register is used to store the Walsh code sequence matrix for modulating the chaotic signal and divide it into matrix A and matrix B; the binary-to-decimal converter converts two groups of n index bits to be transmitted into corresponding decimal expressions p and q respectively; the polarity converter converts the (2n + 1)-th data bit to be transmitted into a polarity modulation bit; the index selector selects the Walsh code sequence W with index number p + 1 from matrix A p+1 , and selects the Walsh code sequence W with index number q + 1 from matrix B q+1 ; the modulation multiplier uses the Walsh code sequence W p+1 to modulate the chaotic signal as the first transmitted signal, and uses the Walsh code sequence W q+1 and the modulation bit to modulate the chaotic signal simultaneously as the second transmitted signal; the adder adds the two generated information signals and then transmits them.

[0059] The structure of the demodulator in the modem is as shown in Figure 2 the figure, and specifically includes N demodulation multipliers; N averagers; a correlation multiplier, an energy detector, a decimal-to-binary converter, and a threshold decision maker; the demodulation multipliers use matrix A and matrix B to demodulate the received information signal respectively; the averager performs averaging processing on the demodulated signal to achieve the purpose of noise reduction; the correlation multiplier multiplies the demodulated signal matrix X by the transpose of the demodulation matrix Y to obtain the correlation matrix Z; the energy detector detects the term with the largest absolute value in the correlation matrix Z; the decimal-to-binary converter performs decimal-to-binary conversion on the row and column numbers of the term with the largest absolute value in the correlation matrix Z to determine the index number and to recover the first 2n index bits transmitted; the threshold decision maker performs threshold decision on the term with the largest absolute value to recover the (2n + 1)-th modulation bit transmitted.

[0060] As a preferred solution, in order to verify that the reference-code-removed differential chaotic shift keying modulation and demodulation method provided by the present invention can reduce the bit error rate. The present invention lists a verification example for verification and description. The method of this verification example includes the following steps:

[0061] Step 1: Select the bit signal-to-noise ratio E in the channel bWhen / N0 = 10 dB, the length β of the discrete chaotic signal sequence within one symbol period is 50, and the order of the generated Walsh code matrix is 16, that is, 7 data bits are transmitted within the symbol period. The method based on the present invention is implemented under these conditions.

[0062] Step 2: Within one symbol period [0, T s , the chaotic signal generator outputs a discrete chaotic sequence {x1, x2…x 50} of length 50.

[0063] Step 3: The discrete chaotic signal generated in Step 2 is passed through pulse shaping filtering to obtain the chaotic signal within the current symbol period:

[0064]

[0065] where t represents time; T c represents the chip time.

[0066] Step 4: The first 6 data bits to be transmitted are divided into two groups denoted as {a1, a2, a3} and {b1, b2, b3}, and the decimal expressions p and q are determined through binary conversion, and the index numbers p + 1 and q + 1 are obtained; the 7th data bit to be transmitted is modulated by polarity to become a modulation bit denoted as d.

[0067] Step 5: Generate a 16-order Walsh code matrix, and denote the first 8 rows as matrix A, that is, [W1, W2…W8] T , and the last 8 rows as matrix B, that is, [W9, W 10 …W 16 , T and determine the Walsh code sequences W p+1 and W q+1 used to modulate the chaotic signal through the two index numbers p + 1 and q + 1 determined in Step 4.

[0068] Step 6: Modulate the chaotic signal c(t) with the Walsh code sequence W p+1 to obtain the first information signal to be transmitted; modulate the chaotic signal c(t) with the Walsh code sequence W q+1 and the modulation bit d simultaneously to obtain the second information signal to be transmitted.

[0069] Step 7: Add the two information signals and transmit them through the channel.

[0070] At the receiving end, the signal is received and demodulated, specifically including:

[0071] Step 8: Multiply the received information signal by each row of the Walsh code sequence in matrix A respectively and take the average to obtain the demodulation matrix X 8×50 .

[0072] Step 9: Multiply the received information signal by each row Walsh code sequence in matrix B respectively and take the average to obtain the demodulation matrix Y 8×50 .

[0073] Step 10: Multiply demodulation matrix X by the transpose of demodulation matrix Y to obtain the correlation matrix Z 8×8 .

[0074] Step 11: Judge the magnitude of the absolute value of the correlation matrix. The row and column where the term with the largest absolute value is located are the first index number and the second index number respectively;

[0075] Step 12: Respectively restore two groups of 6 data bits in total through the conversion from decimal to binary for the two index numbers obtained in Step 11;

[0076] Step 13: Perform a threshold decision on the term with the largest absolute value obtained in Step 11 to restore the 7th data bit sent; its demodulation rule is that when the maximum energy > threshold value 0, the demodulated data bit is "1", otherwise, the demodulated data bit is "0".

[0077] In summary, based on code index modulation and code shift differential chaos shift keying modulation. Divide the first 2n data bits to be transmitted into two groups of n index bits and respectively perform the conversion from binary to decimal to determine two index numbers p + 1 and q + 1, and turn the (2n + 1)th data bit into a modulation bit through polarity modulation. Generate an N - order Walsh code matrix and divide the first N / 2 rows into matrix A and the last N / 2 rows into matrix B. The first - path information signal is modulated by the Walsh code sequence W with the index number p + 1 in matrix A p+1 and the chaotic signal; the second - path information signal is modulated by the Walsh code sequence W with the index number q + 1 in matrix B q+1 and the modulation bit and the chaotic signal simultaneously. Since using different Walsh code sequences for modulation ensures the orthogonality between the two - path information signals, they can be sent out through addition in the same time slot over the channel. During demodulation, respectively use each row Walsh code sequence in matrix A and each row Walsh code sequence in matrix B to modulate the received information signal and perform average processing to reduce the noise component in the demodulated signal, obtaining two demodulation signal matrices X and Y. Multiply the demodulation signal matrix X by the transpose of the demodulation signal matrix Y to obtain a correlation matrix Z, and restore the index numbers by performing the conversion from decimal to binary on the numbers of the row and column where the term with the largest absolute value in the correlation matrix is located and Thus, the first 2n transmitted index bits are restored; a threshold decision is made on the term with the largest absolute value in the correlation matrix Z to restore the (2n + 1)-th transmitted modulation bit. Based on inheriting the advantage of the traditional CS-DCSK method of avoiding using a delay unit at the receiving end, the present invention omits the step of transmitting a reference signal, thereby obtaining higher energy efficiency and better bit error performance.

[0078] Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Those with ordinary knowledge in the technical field to which the present invention pertains may make various modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the scope defined in the claims.

Claims

1. A CS-DCSK-based differential modem for collecting a preset number of data bits to be transmitted within a symbol period. Based on each data bit included in the information signal to be transmitted, for each data bit to be transmitted, the last data bit is used as the polarity modulation bit, and the remaining data bits except the polarity modulation bit are evenly divided to obtain two sets of data bits. It is characterized in that, The modem includes a modulator and a demodulator, wherein the modulator modulates the data information to be sent and then sends it to the demodulator; The modulator includes a chaotic signal generator, a pulse shaping filter, a binary to decimal converter, a polarity converter, an index selector, a Walsh code matrix register, a modulation multiplier, and a modulation adder; The chaotic signal generator is used to generate a discrete chaotic signal sequence for transmitting data bits for each data bit corresponding to the data information to be sent within a symbol period, and the discrete chaotic signal sequence is subjected to pulse shaping filtering by a pulse shaping filter to obtain a chaotic signal within the symbol period; The binary to decimal converter is used to convert the data bits corresponding to the two data bit sets into decimal, and modulate the polarity modulation bits from data bits to modulation bits through the polarity converter; The Walsh code matrix register is used to store the Walsh code sequence matrix of the modulated chaotic signal. Two Walsh code matrix sequences with decimal numbers corresponding to the data bit set are selected from the Walsh code matrix register through the index selector. The two sequences are respectively modulated on the chaotic signal by the modulation multiplier, and one of the modulated signals is modulated again by the modulation bit. The two signals are added by the modulation adder and sent to the demodulator. The demodulator receives a channel of information signal sent by the modulator after being added by the modulation adder, and demodulates the information signal, and includes a demodulation multiplier, an averager, a correlation multiplier, an energy detector, a decimal to binary converter, and a threshold decision device; The demodulation multiplier demodulates the received information signal using the Walsh code sequence, and the demodulated information signal is averaged and denoised by an averager, and then the information signal is sent to the correlation multiplier, the energy detector, and the decimal to binary converter in sequence to obtain the data bit set sent by the modulator, and the threshold decision device restores the modulated bit to the polarity modulation bit.

2. A reference-removed modulation and demodulation method based on CS-DCSK, which performs reference-removed modulation and demodulation on the information signal to be transmitted within the symbol period, is characterized in that, The method comprises a transmitting end and a receiving end. The transmitting end modulates a chaotic signal by using a data bit to be sent in a symbol period through a modulator, and specifically comprises the following steps: Step A, collecting a preset number of data bits to be sent within a symbol period, taking the last data bit as a polarity modulation bit for each data bit corresponding to the information signal to be sent, and dividing the remaining data bits except the polarity modulation bit into two data bit sets; Step B: a chaotic signal generator generates a discrete chaotic signal sequence for transmitting data bits within a symbol period, and the discrete chaotic signal sequence is formed into a chaotic signal through a pulse shaping filter; Step C, converting the data bits corresponding to the two data bit sets into decimal through a binary to decimal converter, and then modulating the polarity modulation bits from data bits to modulation bits through a polarity converter; Select two Walsh code matrix sequences with the corresponding decimal numbers of the data bit sets from the Walsh code matrix register through the index selector, modulate the chaotic signal with the two sequences respectively by using the modulation multiplier, and modulate one of the modulated signals with the modulation bit again. After adding the two signals to be transmitted through the modulation adder, send them to the demodulator.

3. A reference-free modulation and demodulation method based on CS-DCSK according to claim 2, characterized in that, The Walsh code matrix corresponding to the Walsh code matrix register includes upper and lower parts. The receiving end is used to receive the data information sent by the sending end and demodulate the data information through the demodulator, including the following steps: Step D: The demodulator receives the information signal sent by the modulator, multiplies the received information signal with the upper and lower parts of the Walsh code matrix respectively through the modulation multiplier to obtain the corresponding demodulation matrices, and further performs average noise reduction on the demodulation matrices through the averager. Step E: Transpose and multiply the two obtained demodulation matrices through the correlation multiplier to obtain the correlation matrix. Based on the correlation matrix, successively pass through the energy detector and the decimal-to-binary converter to recover the data bits corresponding to the two information signals at the sending end respectively. Step F: The threshold decision maker obtains the polarity modulation bit based on the data bits recovered from the two-way information.

4. A reference-free modulation and demodulation method based on CS-DCSK according to claim 2, characterized in that, In step C, the Walsh code matrix register generates a Walsh code matrix of order N by using a function and divides it into two matrices with N / 2 rows each, which are called matrix A and matrix B respectively. The two information signals to be transmitted respectively convert the data bits to decimal through the binary-to-decimal converter and obtain the index numbers. Select two Walsh code matrix sequences with the corresponding decimal numbers of the data bit sets from the Walsh code matrix register through the index selector, modulate the chaotic signal with the two sequences, and modulate one of the modulated signals with the modulation bit again to obtain two information signals to be transmitted. After adding them, send the information signal.

5. A reference-free modulation and demodulation method based on CS-DCSK according to claim 3, characterized in that In step D, after obtaining the demodulation matrix, segment each row of the demodulation matrix according to the preset length, and sum and average each segment in each row as the secondary demodulation matrix to complete the average noise reduction.

Images