Network switches and circuit boards

Abstract

A network switch and a circuit board, the network switch may include a high-precision time protocol module and a circuit board. The high-precision time protocol module can provide a first clock signal and includes a predetermined interface. The circuit board may include a slot, an oscillator and a selection unit. The slot can be inserted by the predetermined interface to receive the first clock signal. The oscillator can provide a second clock signal. The selection unit may include a first end, a second end, an output end and a selection end. When the predetermined interface is inserted into the slot, the first end can receive the first clock signal. The second end can receive the second clock signal. The output end can output one of the first clock signal and the second clock signal. The selection end can receive a selection signal to control the output end to output the first clock signal or the second clock signal.

Description

Technical Field

[0001] The present disclosure relates to a network switch and a circuit board, and more particularly to a network switch and a circuit board using a pluggable high-precision time protocol module. Background Art

[0002] In the traditional Ethernet network architecture, asynchronous signals can be used for control. According to the Ethernet network protocol, control can be performed through a retry mechanism. However, for high-speed applications, such as 5G and 6G communications, the above-mentioned traditional asynchronous mechanism is no longer applicable. For high-speed applications, precise synchronous control solutions must be adopted to meet the needs of telecommunications.

[0003] However, if hardware for precise synchronization control, such as circuit elements related to the precision time protocol (PTP), is installed indiscriminately in devices for telecommunication applications, the hardware cost will increase and the hardware design complexity will be too high. In addition, network devices in different application scenarios do not necessarily need to perform precise synchronization control. If the aforementioned hardware with precise synchronization control is not directly adopted, the hardware that does not require precise synchronization control must be redesigned separately, such as a circuit board designed for a non-precision synchronization protocol. This will increase the circuit board design cost. As for the application of circuit boards, there is currently no universal circuit board that can support both the precision time protocol and the non-precision time protocol requirements.

[0004] In view of the above problems, there is a lack of solutions in the art that can support synchronous control and asynchronous control and reduce the difficulty of operation and design. Summary of the invention

[0005] An embodiment provides a network switch, comprising a high-precision time protocol module and a circuit board. The high-precision time protocol module is used to provide a first clock signal and comprises a predetermined interface. The circuit board comprises a slot, an oscillator and a selection unit. The slot is used to allow the predetermined interface to be inserted to receive the first clock signal. The oscillator is used to provide a second clock signal. The selection unit comprises a first end, a second end, an output end and a selection end, wherein the first end is used to receive the first clock signal when the predetermined interface is inserted into the slot, the second end is used to receive the second clock signal, the output end is used to output one of the first clock signal and the second clock signal, and the selection end is used to receive a selection signal to control the output end to output the first clock signal or the second clock signal.

[0006] Another embodiment provides a circuit board, comprising a slot, a first oscillator and a selection unit. The slot is used to insert a predetermined interface of a high-precision time protocol module to receive a first clock signal. The first oscillator is used to provide a second clock signal. The selection unit comprises a first end, a second end, an output end and a selection end, wherein the first end is used to receive the first clock signal when the predetermined interface is inserted into the slot, the second end is used to receive the second clock signal, the output end is used to output one of the first clock signal and the second clock signal, and the selection end is used to receive a selection signal to control the output end to output the first clock signal or the second clock signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 , Figure 2 and Figure 4 Schematic diagram of a network switch in different embodiments.

[0008] Figure 3 FIG. 4 is a schematic diagram of a logic unit in an embodiment.

[0009]

Explanation of symbols

[0010] 100: Network switch

[0011] 110: High Precision Time Protocol Module

[0012] 112: Reservation interface

[0013] 114, 123: Oscillator

[0014] 116: Phase-locked loop circuit

[0015] 118: Memory

[0016] 120: Circuit board

[0017] 122: Slot

[0018] 124:Selection Unit

[0019] 125: Controller

[0020] 126: Clock fan-out and attenuator circuit

[0021] 127:Logical Unit

[0022] 128: Core switch chip

[0023] 129: Programmable Unit

[0024] 310: Inverter

[0025] 320: XOR gate

[0026] Sc1: First clock signal

[0027] Sc2: Second clock signal

[0028] Ssel: Select signal

[0029] So: Synchronous oscillation signal

[0030] Vi: Internal control signal

[0031] Vr: reference voltage signal

[0032] Vr': reverse phase signal DETAILED DESCRIPTION

[0033] Figure 1 1 is a schematic diagram of a network switch 100 in an embodiment. The network switch 100 may include a precision time protocol (PTP) module 110 and a circuit board 120. The precision time protocol module 110 may include a predetermined interface 112 and may be used to provide a first clock signal Sc1. For example, the circuit board 120 may include a printed circuit board (PCB) and components disposed on the printed circuit board. The circuit board 120 may include a slot 122, an oscillator 123, and a selection unit 124. The slot 122 may be used to allow the predetermined interface 112 to be inserted to receive the first clock signal Sc1. The oscillator 123 may be used to provide a second clock signal Sc2. The selection unit 124 may include a first end, a second end, an output end and a selection end, wherein the first end may be used to receive the first clock signal Sc1 when the predetermined interface 112 is inserted into the slot 122, the second end is used to receive the second clock signal Sc2, the output end may be used to output one of the first clock signal Sc1 and the second clock signal Sc2, and the selection end may be used to receive a selection signal Ssel to control the output end to output the first clock signal Sc1 or the second clock signal Sc2.

[0034] like Figure 1 As shown, the selection unit 124 can output the first clock signal Sc1 or the second clock signal Sc2 to a clock fan-out and attenuator circuit 126 on the circuit board 120 , thereby providing a processed clock signal to the core switch chip 128 and the programmable unit 129 .

[0035] For example, the core switch chip 128 may be an application specific integrated circuit (ASIC). The programmable unit 129 may include a field programmable gate array (FPGA) and / or a complex programmable logic device (CPLD). Figure 1 As shown, a controller 125 may be disposed on the circuit board 120 to control a core switch chip 128 and a programmable unit 129 .

[0036] According to an embodiment, the first clock signal Sc1 may be used to support a high-precision time protocol, and the second clock signal Sc2 may be used to support a non-high-precision time protocol. For example, the first clock signal Sc1 may support high-speed applications such as 5G communication and / or 6G communication, and the second clock signal Sc2 may support Ethernet applications.

[0037] like Figure 1 As shown, when the predetermined interface 112 of the high-precision time protocol module 110 has not been inserted into the slot 122 of the circuit board 120, the oscillator 123 of the circuit board 120 can provide the second clock signal Sc2 to the selection unit 124, so that the output end of the selection unit 124 outputs the second clock signal Sc2. When the predetermined interface 112 of the high-precision time protocol module 110 has been inserted into the slot 122 of the circuit board 120, the high-precision time protocol module 110 can provide the first clock signal Sc1 to the selection unit 124, so that the output end of the selection unit 124 outputs the first clock signal Sc1.

[0038] Figure 2 In the embodiment, Figure 1 A schematic diagram of a network switch 100 is shown. Figure 2 As shown, the high precision time protocol module 110 may include an oscillator 114 and a phase-locked loop circuit 116. The oscillator 114 may be used to provide a synchronous oscillation signal So, and the phase-locked loop circuit 116 may be used to generate a first clock signal Sc1 according to the synchronous oscillation signal So.

[0039] like Figure 2 As shown, the high precision time protocol module 110 may further include a reference voltage terminal for receiving a reference voltage signal Vr. The reference voltage signal Vr may substantially have a fixed level. For example, the reference voltage signal Vr may be a ground voltage signal, and its voltage level may be 0 volts. When the predetermined interface 112 is inserted into the slot 122, the slot 122 may receive the first clock signal Sc1 and the reference voltage signal Vr. Figure 2As shown, the circuit board 120 may further include a logic unit 127. When the predetermined interface 112 is inserted into the slot 122, the logic unit 127 may receive a reference voltage signal Vr from the slot 122 to adjust the level of the selection signal Ssel to control the output end of the selection unit 124 to output the first clock signal Sc1.

[0040] Figure 3 FIG. 1 is a schematic diagram of the logic unit 127 in an embodiment. Figure 3 As shown, the logic unit 127 may include an inverter 310 and an exclusive OR (XOR) gate 320. Figure 2 and Figure 3 As shown, when the predetermined interface 112 is inserted into the slot 122, the inverter 310 can receive the reference voltage signal Vr to generate the inverted signal Vr'. The reference voltage signal Vr can have a first level, and the inverted signal Vr' can have a second level, wherein the first level and the second level can be inverted to each other. The XOR gate 320 can include a first end, a second end, and an output end, wherein the first end can be used to receive the inverted signal Vr', the second end can be used to receive the internal control signal Vi, and the output end can be used to output the selection signal Ssel. For example, the internal control signal Vi can be generated and output by the programmable unit 129.

[0041] Here, the operation of the logic unit 127 is illustrated by taking the first level of the reference voltage signal Vr as a low level and the second level of the inverted signal Vr' as a high level. For example, the reference voltage signal Vr may be a ground signal and corresponds to a low level of logic 0. Therefore, when the predetermined interface 112 is inserted into the slot 122, the inverter 310 may receive the reference voltage signal Vr to generate an inverted signal Vr', wherein the inverted signal Vr' may correspond to a high level of logic 1. The internal control signal Vi may use a suitable level, for example, a low level of logic 0. Therefore, when the first end of the exclusive OR (XOR) gate 320 receives the inverted signal Vr' corresponding to a low level of logic 1, the selection signal Ssel may have an appropriate level (for example, a low level of logic 0) so that the output end of the selection unit 124 outputs the first clock signal Sc1. The signal levels described here are only examples and may be adjusted and set according to design requirements.

[0042] Figure 4 In another embodiment, Figure 1 FIG. 1 is a schematic diagram of a network switch 100 . Figure 4 Similar to Figure 2 , however, if Figure 4 As shown, the circuit board 120 may further include an oscillator 114 for providing a synchronous oscillation signal So. Figure 4The high precision time protocol module 110 may include a phase-locked loop circuit 116 for receiving the synchronous oscillation signal So and generating the first clock signal Sc1 according to the synchronous oscillation signal So when the predetermined interface 112 is inserted into the slot 122 .

[0043] Figure 2 In the embodiment, the oscillator 114 and the phase-locked loop circuit 116 supporting the high precision time protocol can be integrated into the high precision time protocol module 110, so that the relevant circuits of the high precision time protocol can be effectively integrated into the module, which can greatly reduce the cost and complexity of the circuit board 120. Figure 4 In the embodiment, since the oscillator 114 is disposed on the circuit board 120, the size of the high precision time protocol module 110 can be made smaller.

[0044] Figure 1 , Figure 2 and Figure 4 In the embodiment, the oscillator 123 may be a general oscillator. Figure 2 and Figure 4 In the embodiment, the oscillator 114 may include at least one of an oven controlled crystal oscillator (OCXO) and a temperature compensated crystal oscillator (TCXO).

[0045] According to an embodiment, the first clock signal Sc1 generated by the oscillator 114 supporting the high precision time protocol and the second clock signal Sc2 generated by the oscillator 123 on the circuit board 120 are different. The oscillator 123 on the circuit board 120 can be a general oscillator, which is relatively cheap. The oscillator 114 can be an oscillator supporting the high precision time protocol, which is relatively expensive. By using Figure 1 , Figure 2 and Figure 4 The architecture allows a network switch that does not need to support the high-precision time protocol function to use the same motherboard (e.g., circuit board 120) because the network switch can use a clock signal (e.g., second clock signal Sc2) generated by a cheaper oscillator (e.g., oscillator 123) carried by the motherboard.

[0046] Thus, the circuit board 120 can be a universal circuit board, and can be used with or without the high-precision time protocol module 110, and can flexibly support the functions of the high-precision time protocol and the functions of non-high-precision time protocol. Figure 1 , Figure 2 and Figure 4As shown, the circuit board 120 may include a controller 125. When the predetermined interface 112 of the high precision time protocol module 110 is inserted into the slot 122 of the circuit board 120, the controller 125 may be used to execute a control program to perform a synchronization control operation, wherein the control program may correspond to the oscillator 114 and the phase-locked loop circuit 116. For example, the controller 125 may execute the control related to the oscillator 114 and the phase-locked loop circuit 116 through appropriate software and / or firmware. For example, the controller 125 may be a central processing unit (CPU).

[0047] like Figure 1 , Figure 2 and Figure 4 As shown, the high precision time protocol module 110 may further include a memory 118 for storing identification data. The controller 125 may also be used to read the identification data. When the controller 125 determines that the identification data is correct, the controller 125 may execute a related control program to perform synchronization control. For example, the memory 118 may include an electrically-erasable programmable read-only memory (EEPROM).

[0048] Since the oscillator 114 and the phase-locked loop circuit 116 supporting the high-precision time protocol must pass relevant certifications, and the oscillator 114 and the phase-locked loop circuit 116 provided by each supplier must be controlled by a specific program, they must cooperate with each other during operation. If the oscillator 114 and the phase-locked loop circuit 116 are selected separately, the complexity and difficulty of design and control will increase. In addition, it is difficult to design a circuit board that can support both the high-precision time protocol and the non-high-precision time protocol. By integrating the relevant components of the high-precision time protocol into the high-precision time protocol module 110, such as Figure 1 , Figure 2 and Figure 4 As shown, the complexity and difficulty of design and use can be effectively reduced.

[0049] By using Figure 1 , Figure 2 and Figure 4The architecture shown can support non-PTP asynchronous control when the predetermined interface 112 of the high-precision time protocol module 110 has not been inserted into the slot 122 of the circuit board 120. When the predetermined interface 112 of the high-precision time protocol module 110 is inserted into the slot 122 of the circuit board 120, it can support high-precision time protocol synchronous control. The architecture disclosed in the embodiment can provide a universal motherboard design. Whether it is a telecommunications (Telco) or 5G edge network switch that needs to be equipped with a high-precision time protocol function, or an enterprise-level network switch or data center switch that does not need to be equipped with a high-precision time protocol function, they can share the same motherboard design without having to design a motherboard that supports non-PTP. Therefore, the embodiment of the present invention can greatly simplify the complexity of design and operation.

[0050] The above descriptions are only preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.

Claims

1. A network switch, comprising: A high-precision time protocol module, used for providing a first clock signal, comprising a predetermined interface; and Circuit board, including: A slot, for inserting the predetermined interface to receive the first clock signal; A first oscillator, used to provide a second clock signal; and The selection unit comprises a first end for receiving the first clock signal when the predetermined interface is inserted into the slot, a second end for receiving the second clock signal, an output end for outputting one of the first clock signal and the second clock signal, and a selection end for receiving a selection signal to control the output end to output the first clock signal or the second clock signal, comprising: when the predetermined interface is inserted into the slot, receiving a first selection signal to control the output end to output the first clock signal; And when the predetermined interface is not inserted into the slot, it is used to receive a second selection signal to control the output end to output the second clock signal.

2. The network switch of claim 1, wherein: The first clock signal is used to support a high precision time protocol; and The second clock signal is used to support a non-high-precision time protocol.

3. The network switch of claim 1, wherein the high precision time protocol module further comprises: A second oscillator, configured to provide a synchronous oscillation signal; and A phase-locked loop circuit, used for generating the first clock signal according to the synchronous oscillation signal; The second oscillator supports a high-precision time protocol.

4. The network switch of claim 3, wherein: The high-precision time protocol module also includes a reference voltage terminal for receiving a reference voltage signal, wherein the reference voltage signal substantially has a fixed level; The slot is also used to receive the reference voltage signal when the predetermined interface is inserted; and The circuit board also includes a logic unit for receiving the reference voltage signal from the slot to adjust the level of the selection signal when the predetermined interface is inserted into the slot, so as to control the output end of the selection unit to output the second clock signal.

5. The network switch of claim 4, wherein the logic unit comprises: an inverter, for receiving the reference voltage signal to generate an inverted signal when the predetermined interface is inserted into the slot; and The XOR gate comprises a first terminal for receiving the inverted signal, a second terminal for receiving an internal control signal, and an output terminal for outputting the selection signal. 6 . The network switch as claimed in claim 5 , wherein the reference voltage signal has a first level, the inverted signal has a second level, and the first level and the second level are inverted to each other.

7. The network switch of claim 1, wherein: The circuit board also includes a second oscillator for providing a synchronous oscillation signal; and The high-precision time protocol module also includes a phase-locked loop circuit for generating the first clock signal according to the synchronous oscillation signal when the predetermined interface is inserted into the slot; The second oscillator supports a high-precision time protocol.

8. The network switch as claimed in claim 3 or 7, wherein the second oscillator comprises at least one of an oven controlled crystal oscillator (OCXO) and a temperature compensated crystal oscillator (TCXO).

9. The network switch as claimed in claim 3 or 7, wherein the circuit board further comprises: A controller for executing a control program to perform a synchronous control operation; The control program corresponds to the second oscillator and the phase-locked loop circuit.

10. The network switch of claim 9, wherein: The high-precision time protocol module also includes a memory for storing identification data; The controller is also used to read the identification data, and when the identification data is correct, the controller executes the control program.

11. A circuit board, comprising: A slot, for inserting a predetermined interface of a high-precision time protocol module to receive a first clock signal; A first oscillator, used to provide a second clock signal; and The selection unit comprises a first end for receiving the first clock signal when the predetermined interface is inserted into the slot, a second end for receiving the second clock signal, an output end for outputting one of the first clock signal and the second clock signal, and a selection end for receiving a selection signal to control the output end to output the first clock signal or the second clock signal, including: When the predetermined interface is inserted into the slot, it is used to receive a first selection signal to control the output end to output the first clock signal; And when the predetermined interface is not inserted into the slot, it is used to receive a second selection signal to control the output end to output the second clock signal.

12. The circuit board of claim 11, wherein: The first clock signal is used to support a high precision time protocol; and The second clock signal is used to support a non-high-precision time protocol.

13. The circuit board of claim 11, wherein: The slot is also used to receive a reference voltage signal when the predetermined interface is inserted; and The circuit board also includes a logic unit for receiving the reference voltage signal from the slot to adjust the level of the selection signal when the predetermined interface is inserted into the slot, so as to control the output end of the selection unit to output the second clock signal.

14. The circuit board of claim 13, wherein the logic unit comprises: an inverter, for receiving the reference voltage signal to generate an inverted signal when the predetermined interface is inserted into the slot; and The XOR gate comprises a first terminal for receiving the inverted signal, a second terminal for receiving an internal control signal, and an output terminal for outputting the selection signal.

15. The circuit board of claim 13, wherein: The circuit board also includes a second oscillator for providing a synchronous oscillation signal; and for providing the synchronous oscillation signal and receiving the first clock signal when the predetermined interface is inserted into the slot; The second oscillator supports a high-precision time protocol.

Images