Dynamic random access memory and forming method thereof

Abstract

A dynamic random access memory (DRAM) and a method for forming the same include: a plurality of first trenches and a plurality of second trenches within a substrate, wherein the first trenches and the second trenches both extend along a second direction through an active region and a first isolation structure, extending from a first surface to a second surface, the first trenches extending through the channel region, and the second trenches extending through the wordline region; a shielding layer within the first trenches, wherein, perpendicular to the substrate surface, the shielding layer within the first isolation structure has a first dimension, and the shielding layer within the active region has a second dimension, the second dimension being smaller than the first dimension; and a wordline gate structure located on the sidewalls of the second trenches, the wordline gate structure comprising two wordline layers located on the sidewalls of each second trench and a second isolation structure located between the two wordline layers, the second isolation structure isolating the two wordline layers from each other. This reduces parasitic capacitance between adjacent wordline layers within the first isolation structure and also reduces wordline surge effects.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a dynamic random access memory and a forming method thereof. Background Art

[0002] With the rapid development of technology, semiconductor memory is widely used in electronic devices. Dynamic random access memory (DRAM) is a type of volatile memory and is the most commonly used solution for storing large amounts of data.

[0003] The basic memory cell of a dynamic random access memory is composed of a memory transistor and a storage capacitor, and the memory array is composed of multiple memory cells. The storage capacitor is used to store charges representing the stored information. The storage transistor is a switch that controls the flow and release of charges from the storage capacitor. The storage transistor is also connected to the internal circuit in the memory and receives control signals from the internal circuit. Among them, an active region, a drain region and a gate are formed in the memory transistor. The gate is used to control the flow of current between the source region and the drain region and is connected to the word line. The drain region is used to form a bit line contact region to connect to the bit line. The source region is used to form a storage node contact region to connect to the storage capacitor. With the continuous development of integrated circuit manufacturing technology, it is necessary to further improve the device density of memory chips to obtain a larger data storage capacity.

[0004] However, existing dynamic random access memories still have many problems. Summary of the Invention

[0005] The technical problem solved by the present invention is to provide a dynamic random access memory and a forming method thereof, which can improve the stability of device performance.

[0006] To solve the above problems, the present invention provides a dynamic random access memory, comprising: a substrate having a first surface and a second surface opposite to each other, the substrate comprising a plurality of active areas arranged along a first direction and a first isolation structure, the first isolation structure being located between adjacent active areas, the plurality of active areas being parallel to a second direction, the first direction being perpendicular to the second direction, each of the active areas comprising a plurality of channel areas separated from each other and arranged along the second direction, and a word line area located between adjacent channel areas, the word line areas located in different active areas being arranged along the first direction; a plurality of first trenches and a plurality of second trenches located in the substrate, the first trenches and the second trenches both extending along the second direction. The first trench passes through the active area and the first isolation structure and extends from the first surface to the second surface, the first trench passes through the channel area, and the second trench passes through the word line area; the shielding layer is located in the first trench, in a direction perpendicular to the substrate surface, the shielding layer in the first isolation structure has a first size, and the shielding layer in the active area has a second size, and the second size is larger than the first size; the word line gate structure is located on the sidewall of the second trench, the word line gate structure includes two word line layers located on the sidewalls of each second trench and a second isolation structure located between the two word line layers, and the second isolation structure isolates the two word line layers from each other.

[0007] Optionally, both the first surface and the second surface expose the first isolation structure.

[0008] Optionally, the first surface exposes the first isolation structure; the structure also includes: a third groove located between adjacent active areas, the third groove extending from the second surface to the first surface, the bottom of the third groove exposing the first isolation structure and the shielding layer; and a first dielectric layer located in the third groove.

[0009] Optionally, the surface of the shielding layer in the first isolation structure has a first distance from the second surface, the surface of the shielding layer in the active area has a second distance from the second surface, and the first distance is greater than the second distance; or the surface of the shielding layer in the first isolation structure has a third distance from the first surface, the surface of the shielding layer in the active area has a fourth distance from the first surface, and the third distance is greater than the fourth distance; or the first distance is greater than the second distance, and the third distance is greater than the fourth distance.

[0010] Optionally, it also includes: a first insulating layer, the first insulating layer is located between the shielding layer and the sidewalls and bottom of the first trench; a second insulating layer, the second insulating layer is located on the surface of the shielding layer; the material of the first insulating layer includes a dielectric material, the dielectric material includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and carbon silicon oxynitride; the material of the second insulating layer includes a dielectric material, the dielectric material includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and carbon silicon oxynitride.

[0011] Optionally, the word line gate structure also includes a third insulating layer located between the two word line layers and the bottom of the second isolation structure and the bottom of the second trench; the top surface of the word line layer is lower than the first surface; the word line gate structure also includes a fourth insulating layer located on the top surface of the word line layer.

[0012] Optionally, it further includes: a shielding lead-out layer located on the first surface, the shielding lead-out layer being electrically interconnected with the shielding layer.

[0013] Optionally, it further includes: a shielding lead-out layer located on the second surface, the shielding lead-out layer being electrically interconnected with the shielding layer.

[0014] Optionally, the material of the shielding layer includes a conductor material; the conductor material includes metal.

[0015] Optionally, it further includes: a plurality of first source-drain doped regions located within the first surface of each of the active regions; and a plurality of capacitor structures located on the first surface, each of the capacitor structures being electrically connected to one of the first source-drain doped regions.

[0016] Optionally, it also includes: a second source-drain doped region located within the second surface of each of the active areas; a plurality of bit lines located on the second surface and parallel to the first direction, each of the bit lines being electrically connected to the second source-drain doped region in one of the active areas; a metal interconnection layer located on the second surface, the metal interconnection layer being electrically interconnected with the plurality of the bit lines; and a logic wafer bonded to the substrate from the surface of the metal interconnection layer, the logic wafer having a plurality of logic devices therein.

[0017] Accordingly, the present invention provides another method for forming a dynamic random access memory, comprising: providing a substrate, the substrate having a first surface and a second surface relative to each other, the substrate comprising a plurality of active areas and an initial first isolation structure arranged along a first direction, the first surface exposing a surface of the initial first isolation structure, the initial first isolation structure being located between adjacent active areas, the plurality of active areas being parallel to a second direction, the first direction being perpendicular to the second direction, each of the active areas comprising a plurality of channel areas separated from each other and arranged along the second direction, and a word line area located between adjacent channel areas, the word line areas located in different active areas being arranged along the first direction; forming a plurality of first trenches and a plurality of second trenches in the substrate, the first trenches and the second trenches both penetrating the active areas and the initial first isolation structure along the second direction and extending from the first surface to the second surface, the first trenches and the second trenches both penetrating the active areas and the initial first isolation structure along the second direction and extending from the first surface to the second surface, the first trenches and the second trenches A trench runs through the channel region, and a second trench runs through the word line region; an initial shielding layer is formed in the first trench; a word line gate structure is formed in the second trench, the word line gate structure includes two word line layers located on the sidewalls of each second trench and a second isolation structure located between the two word line layers, and the second isolation structure isolates the two word line layers from each other; after forming the word line gate structure and the initial shielding layer, the substrate is thinned from the second surface toward the first surface until the initial first isolation structure is exposed; after the thinning process, the initial first isolation structure and the initial shielding layer are etched from the second surface to reduce the size of the initial shielding layer in the initial first isolation structure in a direction perpendicular to the substrate surface, forming a shielding layer with the initial shielding layer, and forming a first isolation structure with the initial first isolation structure.

[0018] Optionally, the method for forming the shielding layer further includes: performing a first etching process on the initial first isolation structure until the initial shielding layer within the initial first isolation structure is exposed; and performing a second etching process on the exposed initial shielding layer.

[0019] Optionally, the first etching process includes one or both of a dry etching process and a wet etching process; and the second etching process includes one or both of a dry etching process and a wet etching process.

[0020] Optionally, after forming the shielding layer, it also includes: forming a second source-drain doped region in the second surface of each active area; forming a plurality of bit lines parallel to the first direction on the second surface, each of the bit lines being electrically connected to the second source-drain doped region in one of the active areas.

[0021] Optionally, the method further includes: etching the initial first isolation structure and the initial shielding layer to form a third trench in the substrate; and forming a first dielectric layer in the third trench.

[0022] Optionally, the method further includes: before forming the initial shielding layer, forming a first insulating layer on the sidewalls and bottom of the first trench.

[0023] Optionally, the method for forming the first insulating layer and the initial shielding layer includes: forming a first insulating material layer and a shielding material layer located on the surface of the first insulating material layer in the first groove and on the surface of the first surface; flattening the first insulating material layer and the shielding material layer until the first surface is exposed, forming the first insulating layer with the first insulating material layer, and forming the initial shielding layer with the shielding material layer.

[0024] Optionally, the top surface of the initial shielding layer is lower than the first surface; the method for forming the initial shielding layer also includes: after the planarization process, etching back the shielding material layer; after forming the initial shielding layer, it also includes: forming a second insulating layer on the surface of the initial shielding layer in the first groove.

[0025] Optionally, the method further includes: after forming the plurality of bit lines, forming a metal interconnection layer on the second surface, the metal interconnection layer being electrically interconnected with the plurality of bit lines; providing a logic wafer having a plurality of logic device layers therein; after forming the metal interconnection layer, facing the second surface toward the surface of the logic device layer, so that the substrate and the logic wafer are bonded to each other.

[0026] Optionally, the surface of the initial shielding layer in the initial first isolation structure has a third distance from the first surface, and the surface of the initial shielding layer in the active area has a fourth distance from the first surface, and the third distance is greater than the fourth distance; the method for forming the initial shielding layer includes: forming a shielding material layer in the first groove, exposing the surface of the shielding material layer on the first surface; forming a mask layer on the first surface, exposing the surface of the shielding material layer in the initial first isolation structure; using the mask layer as a mask, etching the shielding material layer from the first surface, so that the size of the initial shielding layer in the initial first isolation structure in the direction perpendicular to the substrate surface is reduced to form the initial shielding layer.

[0027] Optionally, the word line gate structure also includes a third insulating layer located between the two word line layers and the bottom of the second isolation structure and the bottom of the second trench; the top surface of the word line layer is lower than the first surface, and the word line gate structure also includes a fourth insulating layer located on the top surface of the word line layer.

[0028] Optionally, the method for forming the word line gate structure includes: forming the third insulating layer in the second trench; after forming the third insulating layer, forming an initial word line layer in the second trench, the top surface of the initial word line layer is flush with the first surface; etching part of the initial word line layer from the first surface to the second surface, forming a plurality of fourth trenches parallel to the second direction in the substrate, the fourth trenches passing through the initial word line layer from the first surface to the second surface, forming the two transition word line layers; forming the second isolation structure in the fourth trench; etching back the transition word line layer to form the word line layer; after forming the word line layer, forming the fourth insulating layer in the second trench.

[0029] Optionally, after forming the word line gate structure and the initial shielding layer, and before the thinning process, it also includes: forming a plurality of first source-drain doping regions within the first surface of each of the active areas; after forming the plurality of first source-drain doping regions, forming a plurality of capacitor structures on the first surface, each of the capacitor structures being electrically connected to one of the first source-drain doping regions.

[0030] Optionally, after forming the shielding layer, the method further includes: forming a shielding lead-out layer, wherein the shielding lead-out layer is electrically interconnected with the shielding layer.

[0031] Optionally, after forming the initial shielding layer and before the thinning process, the method further includes: forming a shielding lead layer on the first surface, wherein the shielding lead layer is electrically interconnected with the initial shielding layer.

[0032] Optionally, the initial shielding layer is formed first, and then the word line gate structure is formed; the method for forming the first trench, the second trench, the initial shielding layer and the word line gate structure includes: forming a plurality of initial trenches in the substrate, with the initial trench passing through the channel region being the first trench, and the initial trench passing through the word line region being the initial second trench; forming a protective layer in the initial second trench; after forming the protective layer, forming the initial shielding layer in the first trench; after forming the initial shielding layer, removing the protective layer to expose the initial second trench; etching the initial second trench to increase the size of the initial second trench to form the second trench; and forming the word line gate structure in the second trench.

[0033] Optionally, the material of the shielding layer includes a conductor material; the conductor material includes metal.

[0034] Optionally, the surface of the initial shielding layer is at a fifth distance from the second surface, the word line layer is at a sixth distance from the second surface, and the fifth distance is smaller than the sixth distance.

[0035] Accordingly, the present invention provides another method for forming a dynamic random access memory, comprising: providing a substrate, the substrate having a first surface and a second surface opposite to each other, the substrate comprising a plurality of active areas and a first isolation structure arranged along a first direction, the first surface exposing a surface of the first isolation structure, the first isolation structure being located between adjacent active areas, the plurality of active areas being parallel to a second direction, the first direction being perpendicular to the second direction, each of the active areas comprising a plurality of channel areas separated from each other and arranged along the second direction, and a word line area located between adjacent channel areas, the word line areas located in different active areas being arranged along the first direction; forming a plurality of first trenches and a plurality of second trenches in the substrate, the first trenches and the second trenches both penetrating the active areas and the first isolation structure along the second direction, and automatically The first surface extends toward the second surface, the first trench penetrates the channel region, and the second trench penetrates the word line region; a shielding layer is formed in the first trench, the surface of the shielding layer in the first isolation structure has a third distance from the first surface, and the surface of the shielding layer in the active area has a fourth distance from the first surface, and the third distance is greater than the fourth distance; a word line gate structure is formed in the second trench, the word line gate structure includes two gate layers located on the sidewalls of the second trench and a second isolation structure located between the two word line layers, and the second isolation structure isolates the two word line layers from each other; after forming the word line gate structure and the shielding layer, the substrate is thinned from the second surface toward the first surface until the first isolation structure is exposed.

[0036] Optionally, the method for forming the shielding layer includes: forming an initial shielding layer in the first groove, exposing the initial shielding layer on the first surface; forming a mask layer on the first surface, exposing the surface of the initial shielding layer in the first isolation structure; and etching the initial shielding layer using the mask layer as a mask to form the shielding layer.

[0037] Optionally, after forming the shielding layer and before the thinning process, the method further includes: forming a shielding lead-out layer on the first surface, wherein the shielding lead-out layer is electrically interconnected with the shielding layer.

[0038] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0039] In the dynamic random access memory provided by the technical solution of the present invention, the shielding layer located in the first trench has a first size in the direction perpendicular to the substrate surface, the shielding layer in the first isolation structure has a first size, and the shielding layer in the active area has a second size, and the second size is larger than the first size. The design of the shielding layer not only reduces the parasitic capacitance between adjacent word line layers in the first isolation structure, but also plays a shielding role, reduces the coupling between the word line layers on both sides of the channel area, thereby reducing the word line shock effect and improving the device performance as a whole.

[0040] The technical solution of the present invention provides a method for forming a dynamic random access memory. After thinning, the initial first isolation structure and the initial shielding layer are etched from the second surface to form a shielding layer, so that the size of the initial shielding layer in the initial first isolation structure is reduced in a direction perpendicular to the substrate surface. Therefore, the size of the shielding layer in the first isolation structure is smaller than the size of the shielding layer in the active area. The design of the shielding layer not only reduces the parasitic capacitance between adjacent word line layers in the first isolation structure, but also plays a shielding role, reduces the coupling between the word line layers on both sides of the channel area, thereby reducing the word line shock effect and improving the device performance as a whole.

[0041] Furthermore, the initial shielding layer in the initial first isolation structure has a third distance from the first surface, and the initial shielding layer in the active area has a fourth distance from the first surface, and the third distance is smaller than the fourth distance, so that in the dynamic random access memory finally formed, the size of the shielding layer in the first isolation structure is further reduced, while reducing the coupling effect between the word line layers on both sides of the channel region, further reducing the parasitic capacitance between adjacent word line layers in the first isolation structure, and further improving the overall device performance.

[0042] In another method for forming a dynamic random access memory provided by the technical solution of the present invention, a shielding layer is formed in the first groove, the surface of the shielding layer in the first isolation structure has a third distance from the first surface, and the surface of the shielding layer in the active area has a fourth distance from the first surface, and the third distance is greater than the fourth distance. Therefore, the size of the shielding layer in the first isolation structure is smaller than the size of the shielding layer in the active area. The design of the shielding layer not only reduces the parasitic capacitance between adjacent word line layers in the first isolation structure, but also plays a shielding role, reduces the coupling between the word line layers on both sides of the channel area, thereby reducing the word line shock effect and improving the device performance as a whole. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1It is a structural diagram of a dynamic random access memory;

[0044] Figures 2 to 30 1 is a schematic structural diagram of each step of a method for forming a dynamic random access memory according to an embodiment of the present invention;

[0045] Figures 31 to 41 It is a structural diagram of each step of a method for forming a dynamic random access memory according to another embodiment of the present invention. DETAILED DESCRIPTION

[0046] It should be noted that the terms “surface” and “on” in this specification are used to describe relative positional relationships in space and are not limited to whether there is direct contact.

[0047] As described in the background art, existing dynamic random access memories still have many problems, which will be described in detail below.

[0048] Figure 1 It is a structural diagram of a dynamic random access memory.

[0049] Please refer to Figure 1The dynamic random access memory comprises: a substrate having a first surface 100 and a second surface 101 opposite to each other, the substrate comprising a plurality of active areas separated from each other and parallel to a first direction X, and the plurality of active areas arranged along a second direction Y, the first direction X and the second direction Y being perpendicular to each other, each of the active areas comprising a plurality of word line regions I and a plurality of channel regions II, and the plurality of word line regions I and the plurality of channel regions II in each active area being arranged at intervals along the first direction X; a word line gate trench (not shown) located within each word line region I, the word line gate trench extending from the first surface 100 to the second surface 101 and penetrating the active area along the second direction Y; a first insulating layer 102 located at the bottom of the word line gate trench; two separate word line gate structures 103 located within each word line gate trench and on the first insulating layer 102; and a first insulating layer 102 located between the two word line gate structures 103. a first isolation trench (not shown in the figure) between the two channels; an isolation structure 104 located in the first isolation trench; a second insulating layer 105 located in the word line gate trench and on the word line gate structure 103 and the isolation structure 104; a second isolation trench (not shown in the figure) located in each of the channel regions II; a shielding structure 106 located in the second isolation trench; a first source-drain doped region 107 located in the first surface 100 of each of the channel regions II; a plurality of capacitor structures 108 located on the first surface 100, each of the capacitor structures 108 being electrically connected to one of the first source-drain doped regions 107; a second source-drain doped region 109 located in the active region, the second source-drain doped region 109 extending from the second surface 101 to the first surface 100; and a plurality of bit lines 110 located on the second surface 101 and parallel to the first direction X, each of the bit lines 110 being electrically connected to one of the second source-drain doped regions 109 in the active region.

[0050] The above structure is a vertical channel memory, and the shielding structure 106 is an air gap structure for shielding the coupling between the two word line gate structures 103 on both sides of the channel region II. However, the coupling is still large, and the resulting word line hammer effect cannot meet the performance requirements of the product.

[0051] In order to solve the above problems, the technical solution of the present invention provides a dynamic random access memory and a method for forming the same. The shielding layer is located in the first trench. In the direction perpendicular to the surface of the substrate, the shielding layer in the first isolation structure has a first size, and the shielding layer in the active area has a second size, and the second size is larger than the first size. The design of the shielding layer not only helps to reduce the parasitic capacitance between adjacent word line layers in the first isolation structure, but also plays a shielding role, reduces the coupling between the two word line layers on both sides of the channel area, thereby reducing the word line shock effect and improving the device performance as a whole.

[0052] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0053] Figures 2 to 30 It is a structural diagram of each step of a method for forming a dynamic random access memory according to an embodiment of the present invention.

[0054] Please refer to Figures 2 to 4 , Figure 2 for Figure 3 and Figure 4 Schematic diagram of the structure from the top view of the first side, Figure 3 yes Figure 2 Schematic diagram of the cross-section structure along DD1, Figure 4 yes Figure 2 EE1 is a schematic cross-sectional structure diagram, providing a substrate 200, the substrate 200 having a first surface 200a and a second surface 200b opposite to each other, the substrate 200 including a plurality of active areas 201 arranged along a first direction X and an initial first isolation structure 202, the first surface 200a exposing the surface of the initial first isolation structure 202, the initial first isolation structure 202 being located between adjacent active areas 201, the plurality of active areas 201 being parallel to a second direction Y, the first direction X being perpendicular to the second direction Y, each of the active areas 201 including a plurality of channel areas I separated from each other and arranged along the second direction Y, and a word line area II located between adjacent channel areas I, and the word line areas II located in different active areas 201 being arranged along the first direction X.

[0055] The initial first isolation structure 202 is used to form a first isolation structure.

[0056] Subsequently, a plurality of first trenches and a plurality of second trenches are formed in the substrate 200, wherein both the first trenches and the second trenches penetrate the active area 201 and the initial first isolation structure 202 along the second direction Y, and extend from the first surface 200a to the second surface 200b, wherein the first trenches penetrate the channel area I, and the second trenches penetrate the word line area II; an initial shielding layer is formed in the first trench; and a word line gate structure is formed in the second trench, wherein the word line gate structure includes two word line layers located on the sidewalls of each second trench and a second isolation structure located between the two word line layers, wherein the second isolation structure isolates the two word line layers from each other.

[0057] In this embodiment, the initial shielding layer is formed first, and then the word line gate structure is formed.

[0058] In this embodiment, the formation method of the first trench, the second trench, the initial shielding layer and the word line gate structure can be found in Figures 5 to 16 .

[0059] Please refer to Figures 5 to 8 , Figure 5 for Figures 6 to 8 Schematic diagram of the structure from the top view of the first side, Figure 6 yes Figure 5 Schematic diagram of the cross-sectional structure along the DD1 direction, Figure 7 yes Figure 5 The cross-sectional structure diagram along EE1 is shown in the figure. Figure 8 yes Figure 5 In the schematic cross-sectional structure diagram along the FF1 direction, a plurality of initial trenches are formed in the substrate 200, wherein the initial trenches penetrating the channel region I are the first trenches 203, and the initial trenches penetrating the word line region II are the initial second trenches 204.

[0060] Please refer to Figures 9 to 12 , Figure 9 for Figures 10 to 12 A schematic diagram of the structure viewed from the top of the first surface 200a, Figure 10 yes Figure 9 Schematic diagram of the cross-sectional structure along the DD1 direction, Figure 11 yes Figure 9 The cross-sectional structure diagram along EE1 is shown in the figure. Figure 12 yes Figure 9 In the cross-sectional structural diagram along the FF1 direction, a protection layer 205 is formed in the initial second trench 204 ; after the protection layer 205 is formed, the initial shielding layer 206 is formed in the first trench 203 .

[0061] In this embodiment, the material of the initial shielding layer 206 includes metal, and the metal includes titanium nitride. The initial shielding layer 206 is used to form a shielding layer.

[0062] In this embodiment, before forming the initial shielding layer 206 , a first insulating layer 207 is formed on the sidewalls and bottom of the first trench 203 .

[0063] In this embodiment, the method for forming the first insulating layer 207 and the initial shielding layer 206 includes: forming a first insulating material layer (not shown in the figure) and a shielding material layer (not shown in the figure) located on the surface of the first insulating material layer in the first groove 203 and on the surface of the first surface 200a; and flattening the first insulating material layer and the shielding material layer until the surface of the first surface 200a is exposed.

[0064] In this embodiment, the top surface of the initial shielding layer 206 is lower than the first surface 200 a.

[0065] In this embodiment, the method for forming the initial shielding layer 206 further includes: etching back the shielding material layer after the planarization process.

[0066] In this embodiment, after the initial shielding layer 206 is formed, a second insulating layer 208 is further formed on the surface of the initial shielding layer 206 in the first trench 203 .

[0067] In another embodiment, the initial shielding layer within the initial first isolation structure is at a third distance from the first surface, and the initial shielding layer within the active area is at a fourth distance from the first surface, wherein the third distance is less than the fourth distance. The different sizes of the initial shielding layer within the initial first isolation structure and the active area further reduce the size of the shielding layer within the first isolation structure in the resulting dynamic random access memory. This reduces coupling between word line layers on both sides of the channel region and further reduces parasitic capacitance between adjacent word line layers within the first isolation structure, thereby further improving overall device performance.

[0068] In another embodiment, the method for forming the initial shielding layer includes: forming a shielding material layer in the first groove, the first surface exposing the surface of the shielding material layer; forming a mask layer on the first surface, the mask layer exposing the surface of the shielding material layer in the initial first isolation structure; using the mask layer as a mask, etching the shielding material layer from the first surface, so that the size of the initial shielding layer in the initial first isolation structure in a direction perpendicular to the substrate surface is reduced to form the initial shielding layer.

[0069] Please Figure 12Continue to refer to Figure 13 After forming the initial shielding layer 206 , the protective layer 205 is removed to expose the initial second trench 204 ; and the initial second trench 204 is etched to increase the size of the initial second trench 204 to form the second trench 209 .

[0070] Please refer to Figures 14 to 16 , Figure 14 for Figure 15 and Figure 16 Schematic diagram of the structure from the top view of the first side, Figure 15 yes Figure 14 Schematic diagram of the cross-sectional structure along the EE1 direction, Figure 16 yes Figure 15 In the cross-sectional structural diagram along FF1, the word line gate structure is formed in the second trench 209.

[0071] The word line gate structure includes two word line layers located on the sidewalls of each second trench 209 and a second isolation structure 210 located between the two word line layers. The second isolation structure 210 isolates the two word line layers from each other.

[0072] In this embodiment, the surface of the initial shielding layer 206 is at a fifth distance from the second surface 200b, and the word line layer is at a sixth distance from the second surface 200b, where the fifth distance is smaller than the sixth distance. The purpose of making the fifth distance smaller than the sixth distance is to prevent etching damage to the word line layer due to exposure of the word line layer during subsequent etching of the initial shielding layer 206 from the second surface 200b.

[0073] In this embodiment, the word line layer includes a gate dielectric layer (not shown in the figure), a work function layer 211 located on a sidewall of the gate dielectric layer, and a gate 212 located on a sidewall of the work function layer 211 .

[0074] In this embodiment, the word line gate structure further includes a third insulating layer 213 located between the two word line layers and the bottom of the second isolation structure and the bottom of the second trench 209; the top surface of the word line layer is lower than the surface of the first surface 200a.

[0075] In this embodiment, the word line gate structure further includes a fourth insulating layer 214 located on the top surface of the word line layer.

[0076] In this embodiment, the method for forming the word line gate structure includes: forming the third insulating layer 213 in the second trench 209; after forming the third insulating layer 213, forming an initial word line layer (not shown in the figure) in the second trench 209, and the top surface of the initial word line layer is flush with the first surface 200a; etching a portion of the initial word line layer from the first surface 200a to the second surface 200b, and forming a plurality of fourth trenches (not shown in the figure) parallel to the second direction Y in the substrate 200, and the fourth trenches penetrate the initial word line layer from the first surface 200a to the second surface 200b to form the two transition word line layers (not shown in the figure); forming the second isolation structure 210 in the fourth trench; etching back the transition word line layer to form the word line layer; after forming the word line layer, forming the fourth insulating layer 214 in the second trench 209.

[0077] It should be noted that, in this embodiment, the fourth trench is formed by etching the initial word line layer from the first surface 200a toward the second surface 200b. In another embodiment, the fourth trench can be formed by etching the active area and the initial word line layer from the second surface toward the first surface.

[0078] In this embodiment, the initial word line layer and the method for forming the word line layer include: after forming the third insulating layer 213, forming a gate dielectric material layer (not shown in the figure), a work function material layer (not shown in the figure) located on the gate dielectric material layer, and a gate material layer (not shown in the figure) located on the work function material layer in the second trench 209 and the first surface 200a; planarizing the gate material layer, the work function material layer and the gate dielectric material layer to form the initial word line layer; after the planarization process, etching back the initial word line layer to form the word line layer, forming the gate dielectric layer with the gate dielectric material layer, forming the work function layer 211 with the work function material layer, and forming the gate 212 with the gate material layer.

[0079] In this embodiment, the gate 212 is made of metal, including copper, tungsten, or gold.

[0080] Subsequently, after the word line gate structure and the initial shielding layer 206 are formed, the substrate 200 is thinned from the second surface 200 b toward the first surface 200 a until the initial first isolation structure 202 is exposed.

[0081] In this embodiment, after forming the word line gate structure and the initial shielding layer 206, and before the thinning process, please refer to Figures 17 and 18 .

[0082] Please refer to Figure 17 and Figure 18 , Figure 17 is Figure 15 The structural diagram of the foundation, Figure 18 is Figure 16 Based on the structural schematic diagram, a number of first source-drain doped regions 215 are formed in the first surface 200a of each active area 201; after the formation of the number of first source-drain doped regions 215, a number of capacitor structures 216 are formed on the first surface 200a, and each of the capacitor structures 216 is electrically connected to one of the first source-drain doped regions 215.

[0083] In this embodiment, a capacitor plug 217 is further provided between the capacitor structure 216 and the first source / drain doped region 215. In other embodiments, the capacitor structure 216 is directly connected to the first source / drain doped region 215 without a capacitor plug.

[0084] In this embodiment, the plurality of capacitor structures 216 and the capacitor plugs 217 are located in the second dielectric layer 218. A method for forming the plurality of capacitor structures 216 and the capacitor plugs 217 includes: forming a second dielectric layer 218 on the first surface 200a; forming a plurality of first openings (not shown in the figure) in the second dielectric layer 218, wherein the first openings expose the surface of the first source-drain doped region 215; and forming the capacitor structures 216 and the capacitor plugs 217 in the plurality of first openings.

[0085] Please refer to Figures 19 to 22 , Figure 19 yes Figures 20 to 22 From the top view of the second surface 200b, Figure 20 yes Figure 19 Schematic diagram of the cross-sectional structure along the ee1 direction, Figure 21 yes Figure 19 Schematic diagram of the cross-sectional structure along the ff1 direction, Figure 22 yes Figure 19 A schematic cross-sectional structural diagram along the dd1 direction shows that after the capacitor structure 216 is formed, the substrate 200 is thinned from the second surface 200b toward the first surface 200a until the initial first isolation structure 202 is exposed.

[0086] The thinning process includes a chemical mechanical polishing process.

[0087] It should be noted that a fixed voltage needs to be applied to the formed shielding layer so that the shielding layer can play a shielding role. To this end, the circuit of the shielding layer can be led out from the first surface or the second surface.

[0088] In this embodiment, the circuitry of the shielding layer is subsequently led out from the second surface 200b; in another embodiment, the circuitry of the shielding layer is led out from the first surface. That is, after forming the initial shielding layer and before the thinning process, the method further includes forming a shielding lead-out layer on the first surface, the shielding lead-out layer being electrically interconnected with the initial shielding layer. Specifically, the shielding lead-out layer can be formed on the first surface after forming the capacitor structure.

[0089] Please refer to Figures 23 to 25 , Figure 23 yes Figures 24 and 25 From the top view of the second surface 200b, Figure 24 yes Figure 23 Schematic diagram of the cross-sectional structure along the dd1 direction, Figure 25 yes Figure 23 The schematic diagram of the cross-sectional structure along the ff1 direction shows that after the thinning process, the initial first isolation structure 202 and the initial shielding layer 206 are etched from the second surface 200b, so that the size of the initial shielding layer 206 in the initial first isolation structure 202 in the direction perpendicular to the surface of the substrate 200 is reduced, and the shielding layer 219 is formed by the initial shielding layer 206, and the first isolation structure 220 is formed by the initial first isolation structure 202.

[0090] The size of the initial shielding layer 206 in the initial first isolation structure 202 in the direction perpendicular to the surface of the substrate 200 is reduced, so that the size of the shielding layer 219 in the first isolation structure 220 is smaller than the size of the shielding layer 219 in the active area 201. The design of the shielding layer 219 not only reduces the parasitic capacitance between adjacent word line layers in the first isolation structure 220, but also plays a shielding role, reducing the coupling between the word line layers on both sides of the channel area, thereby reducing the word line impact effect and improving the device performance as a whole.

[0091] In this embodiment, the word line layer is at a sixth distance from the second surface 200b, and the shielding layer 219 within the first isolation structure 220 is at a seventh distance from the second surface 200b, the seventh distance being greater than the sixth distance. The seventh distance being greater than the sixth distance is intended to reduce device leakage.

[0092] The shielding layer 219 is made of a conductive material, which includes metal. In this embodiment, the shielding layer 219 is made of titanium nitride.

[0093] In this embodiment, the method for forming the shielding layer 219 further includes: performing a first etching process on the initial first isolation structure 202 until the initial shielding layer 206 within the initial first isolation structure 202 is exposed; and performing a second etching process on the exposed initial shielding layer 206 .

[0094] The first etching process includes one or both of a dry etching process and a wet etching process. In this embodiment, the first etching process is a dry etching process.

[0095] The second etching process includes one or both of a dry etching process and a wet etching process. In this embodiment, the second etching process is a dry etching process.

[0096] In this embodiment, the initial first isolation structure 202 and the initial shielding layer 206 are etched to form a third trench 221 in the substrate 200 .

[0097] In this embodiment, after forming the shielding layer 219, please refer to Figures 26 to 29 .

[0098] Please refer to Figures 26 to 29 , Figure 26 yes Figures 28 to 29 From the top view of the second surface 200b, Figure 27 yes Figure 26 Schematic diagram of the cross-sectional structure along the ee1 direction, Figure 28 yes Figure 26 Schematic diagram of the cross-sectional structure along the ff1 direction, Figure 29 yes Figure 26 As shown in the cross-sectional structural diagram along the dd1 direction, a second source-drain doped region 222 is formed in the second surface 200b of each active area 201; a plurality of bit lines 223 parallel to the second direction Y are formed on the second surface 200b, and each of the bit lines 223 is electrically connected to the second source-drain doped region 222 in one of the active areas 201.

[0099] In this embodiment, after forming the shielding layer 219 and before forming the bit lines 223 , the method further includes forming a first dielectric layer 224 in the third trench 221 .

[0100] In this embodiment, the bit line 223 is located in the third dielectric layer 225. The method for forming the bit line 223 includes: forming the third dielectric layer 225 on the first dielectric layer 224; forming a plurality of second openings (not shown in the figure) in the third dielectric layer 225, wherein the plurality of second openings expose the surface of the second source-drain doped region 222; and forming a plurality of the bit lines 223 in the plurality of second openings.

[0101] Please Figure 27 Based on this, continue to refer to Figure 30 After forming the bit lines 223, a metal interconnection layer 300 is formed on the second surface 200b, and the metal interconnection layer 300 is electrically interconnected with the bit lines 223; a logic wafer 400 is provided, and the logic wafer 400 has a plurality of logic device layers 401; after forming the metal interconnection layer 300, the second surface 200b is directed toward the surface of the logic device layer 401, so that the substrate 200 and the logic wafer 400 are bonded to each other.

[0102] In this embodiment, after forming the shielding layer 219, the method further includes forming a shielding lead layer (not shown), which is electrically interconnected with the shielding layer 219. A fixed voltage is applied to the shielding layer 219 via the shielding lead layer, so that the shielding layer 219 performs a shielding function.

[0103] In this embodiment, the shielding layer 219 is led out from the second surface 200a. In another embodiment, the shielding layer is led out from the first surface.

[0104] Accordingly, an embodiment of the present invention further provides a dynamic random access memory formed by the above method, please continue to refer to Figures 26 to 30 , comprising: a substrate 200, the substrate 200 having a first surface 200a and a second surface 200b opposite to each other, the substrate 200 comprising a plurality of active regions 201 arranged along a first direction X and a first isolation structure 220 (such as Figure 23 As shown, the first isolation structure 220 is located between adjacent active areas 201, the plurality of active areas 201 are parallel to the second direction Y, the first direction X is perpendicular to the second direction Y, each of the active areas 201 includes a plurality of channel areas I separated from each other and arranged along the second direction Y, and a word line area II located between adjacent channel areas I, and the word line areas II located in different active areas 201 are arranged along the first direction X; a plurality of first trenches 203 (as shown) located in the substrate 200 Figure 8 as shown) and a plurality of second grooves 209 (as shown Figure 8As shown), the first trench 203 and the second trench 209 both penetrate the active area 201 and the first isolation structure 220 along the second direction Y, and extend from the first surface 200a to the second surface 200b, the first trench 203 penetrates the channel area I, and the second trench 209 penetrates the word line area II; the shielding layer 219 located in the first trench 203, in a direction perpendicular to the surface of the substrate 200, the shielding layer 219 in the first isolation structure 220 has a first size d1, and the shielding layer 219 in the active area 201 has a second size d2, and the second size d2 is smaller than the first size d1; the word line gate structure is located on the sidewalls of the second trench 209, the word line gate structure includes two word line layers located on the sidewalls of each second trench 209 and a second isolation structure 210 located between the two word line layers, and the second isolation structure 210 isolates the two word line layers from each other.

[0105] The shielding layer 219 located in the first groove 203 has a first size in a direction perpendicular to the surface of the substrate 200. The shielding layer 219 in the first isolation structure 220 has a first size, and the shielding layer 219 in the active area 201 has a second size, and the second size is larger than the first size. The design of the shielding layer 219 not only helps to reduce the parasitic capacitance between adjacent word line layers in the first isolation structure, but also plays a shielding role, reducing the coupling between the word line layers on both sides of the channel area, thereby reducing the word line shock effect and improving the device performance as a whole.

[0106] In this embodiment, the first surface 200 a exposes the first isolation structure 220 .

[0107] In this embodiment, the dynamic random access memory further includes: a third groove 221 (such as Figure 23 As shown, the third groove 221 extends from the second surface 200b toward the first surface 200a. The bottom of the third groove 221 exposes the first isolation structure 220 and the shielding layer 219. The first dielectric layer 224 is located within the third groove 221. In other words, the third groove 221 within the second surface 200b exposes the first isolation structure 220. In another embodiment, both the first and second surfaces expose the first isolation structure.

[0108] In this embodiment, the surface of the shielding layer 219 within the first isolation structure 220 is at a first distance from the second surface 200b, and the surface of the shielding layer 219 within the active area 201 is at a second distance from the second surface 200b, wherein the first distance is greater than the second distance. In another embodiment, the surface of the shielding layer within the first isolation structure is at a third distance from the first surface, and the surface of the shielding layer within the active area is at a fourth distance from the first surface, wherein the third distance is greater than the fourth distance. In yet another embodiment, the first distance is greater than the second distance, and the third distance is greater than the fourth distance.

[0109] In this embodiment, the dynamic random access memory further includes: a first insulating layer 207 located between the shielding layer 219 and the sidewalls and bottom of the first trench 203; and a second insulating layer 208 located on the surface of the shielding layer 219.

[0110] The material of the first insulating layer 207 includes a dielectric material, which includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbon oxynitride. In this embodiment, the material of the first insulating layer 207 is silicon oxide.

[0111] The material of the second insulating layer 208 includes a dielectric material, which includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbon oxynitride. In this embodiment, the material of the second insulating layer 208 is silicon oxide.

[0112] In this embodiment, the word line gate structure also includes a third insulating layer 213 located between the two word line layers and the bottom of the second isolation structure 210 and the bottom of the first trench 203; the top surface of the word line layer is lower than the surface of the first surface 200a; the word line gate structure also includes a fourth insulating layer 214 located on the top surface of the word line layer.

[0113] In this embodiment, the word line layer includes a gate dielectric layer (not shown in the figure), a work function layer 211 located on a sidewall of the gate dielectric layer, and a gate 212 located on a sidewall of the work function layer 211 .

[0114] In this embodiment, the dynamic random access memory further includes a shielding lead layer (not shown) located on the second side 200b, electrically interconnected with the shielding layer 219. In another embodiment, the dynamic random access memory further includes a shielding lead layer located on the first side, electrically interconnected with the shielding layer.

[0115] The shielding layer 219 is made of a conductive material, which includes metal. In this embodiment, the shielding layer 219 is made of titanium nitride.

[0116] In this embodiment, the dynamic random access memory further includes: a plurality of first source-drain doped regions 215 located within the first surface 200a of each active region 201; and a plurality of capacitor structures 216 located on the first surface 200a, each capacitor structure 216 being electrically connected to one of the first source-drain doped regions 215.

[0117] In this embodiment, the dynamic random access memory further includes: a second source-drain doped region 222 located within the second surface 200b of each active area 201; a plurality of bit lines 223 located on the second surface 200b and parallel to the first direction X, each of the bit lines 223 being electrically connected to the second source-drain doped region 222 in one of the active areas 201; a metal interconnection layer 300 located on the second surface 200b, the metal interconnection layer 300 being electrically interconnected with the plurality of bit lines 223; and a logic wafer 400 bonded to the substrate 200 from the surface of the metal interconnection layer 300, the logic wafer 400 having a plurality of logic devices 401 therein.

[0118] Figures 31 to 41 It is a structural diagram of each step in a method for forming a dynamic random access memory according to another embodiment of the present invention.

[0119] The main difference between this embodiment and the previous embodiment lies in the method for forming the shielding layer. In the previous embodiment, the initial shielding layer was etched from the second side, thereby reducing the size of the initial shielding layer within the first isolation structure in a direction perpendicular to the substrate surface. In this embodiment, the initial shielding layer is etched from the first side, thereby reducing the size of the initial shielding layer within the first isolation structure in a direction perpendicular to the substrate surface.

[0120] Please refer to Figures 31 to 33 , Figure 31 for Figure 32 and Figure 33 A schematic diagram of the structure viewed from the top of the first surface 500a, Figure 32 yes Figure 31 Schematic diagram of the cross-section structure along DD1, Figure 33 yes Figure 31EE1 is a schematic cross-sectional structural diagram, providing a substrate 500, the substrate 500 having a first surface 500a and a second surface 500b opposite to each other, the substrate 500 including a plurality of active areas 501 and a first isolation structure 502 arranged along a first direction X, the first surface 500a exposing a surface of the first isolation structure 502, the first isolation structure 502 being located between adjacent active areas 501, the plurality of active areas 501 being parallel to a second direction Y, the first direction X being perpendicular to the second direction Y, each of the active areas 501 including a plurality of channel areas A separated from each other and arranged along the second direction Y, and word line areas B located between adjacent channel areas A, and the word line areas B located in different active areas 501 being arranged along the first direction X.

[0121] Subsequently, a plurality of first trenches and a plurality of second trenches are formed in the substrate, wherein both the first trenches and the second trenches penetrate the active area and the first isolation structure along the second direction and extend from the first surface to the second surface, the first trenches penetrate the channel area, and the second trenches penetrate the word line area; a shielding layer is formed in the first trench, the surface of the shielding layer in the first isolation structure has a third distance from the first surface, and the surface of the shielding layer in the active area has a fourth distance from the first surface, and the third distance is greater than the fourth distance; a word line gate structure is formed in the second trench, the word line gate structure includes two gate layers located on the sidewalls of the second trench and a second isolation structure located between the two word line layers, and the second isolation structure isolates the two word line layers from each other.

[0122] In this embodiment, the formation method of the first trench, the second trench, the initial shielding layer and the word line gate structure can be found in Figures 34 to 37 .

[0123] Please refer to Figures 34 to 37 , Figure 34 for Figures 35 to 37 A schematic diagram of the structure viewed from the top of the first surface 500a, Figure 35 yes Figure 34 Schematic diagram of the cross-section structure along DD1, Figure 36 yes Figure 34 Schematic diagram of the cross-sectional structure along the EE1 direction, Figure 37 yes Figure 34 Schematic diagram of the cross-sectional structure along the FF1 direction, wherein a plurality of initial trenches are formed in the substrate 500, wherein the initial trenches penetrating the channel region A are referred to as the first trenches 503, and the initial trenches penetrating the word line region B are referred to as the initial second trenches (not shown in the figure); a protective layer 505 is formed in the initial second trenches;

[0124] Please refer to Figures 38 to 41 , Figure 38 for Figures 39 to 41 A schematic diagram of the structure viewed from the top of the first surface 500a (the second insulating layer is omitted), Figure 39 yes Figure 38 Schematic diagram of the cross-section structure along DD1, Figure 40 yes Figure 38 Schematic diagram of the cross-sectional structure along the EE1 direction, Figure 41 yes Figure 38 , which is a schematic cross-sectional structural diagram along the FF1 direction, after the protection layer 505 is formed, the shielding layer 506 is formed in the first groove 503.

[0125] In this embodiment, the method for forming the shielding layer 506 includes: forming an initial shielding layer (not shown in the figure) in the first groove 503, and exposing the initial shielding layer through the first surface 500a; forming a mask layer (not shown in the figure) on the first surface 500a, and exposing the surface of the initial shielding layer in the first isolation structure 502; and etching the initial shielding layer using the mask layer as a mask to form the shielding layer 506.

[0126] In this embodiment, before forming the initial shielding layer, a first insulating layer 507 is further formed on the sidewalls and bottom of the first trench 503 .

[0127] In this embodiment, the top surface of the initial shielding layer is lower than the first surface 500a.

[0128] For the method of forming the initial shielding layer and the first insulating layer, please refer to the description of the previous embodiment and will not be repeated here.

[0129] In this embodiment, after the shielding layer 506 is formed, a second insulating layer 508 is further formed on the surface of the shielding layer 506 .

[0130] Subsequently, after forming the shielding layer 506 , the protective layer 505 is removed to expose the initial second trench 504 ; the initial second trench 504 is etched to increase the size of the initial second trench 504 to form the second trench; and the word line gate structure is formed in the second trench.

[0131] For the method of forming the second trench and the word line gate structure, please refer to the description of the previous embodiment and will not be repeated here.

[0132] In this embodiment, after the shielding layer is formed and before the thinning process, a shielding lead layer (not shown in the figure) is further formed on the first surface 500 a , and the shielding lead layer is electrically interconnected with the shielding layer.

[0133] In this embodiment, after the word line gate structure and the shielding layer are formed, the substrate 500 is thinned from the second surface 500 b toward the first surface 500 a until the first isolation structure 502 is exposed.

[0134] Accordingly, an embodiment of the present invention further provides a dynamic random access memory formed by the above method, please continue to refer to Figures 38 to 41 .

[0135] The structural differences between this embodiment and the previous embodiment are:

[0136] In the previous embodiment, the surface of the shielding layer in the first isolation structure has a first distance from the second surface, and the surface of the shielding layer in the active area has a second distance from the second surface, and the first distance is greater than the second distance; the first surface exposes the first isolation structure, and the third groove in the second surface exposes the first isolation structure.

[0137] In this embodiment, the surface of the shielding layer in the first isolation structure is at a third distance from the first surface, and the surface of the shielding layer in the active area is at a fourth distance from the first surface, and the third distance is greater than the fourth distance; both the first surface and the second surface expose the first isolation structure.

[0138] The design of the shielding layer 506 not only helps reduce the parasitic capacitance between adjacent word line layers within the first isolation structure 502, but also plays a shielding role, reducing the coupling between the word line layers on both sides of the channel region A, thereby reducing the word line shock effect and improving the overall device performance.

[0139] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A dynamic random access memory, characterized in that: include: A substrate having a first surface and a second surface opposite to each other, the substrate comprising a plurality of active regions arranged along a first direction and a first isolation structure, the first isolation structure being located between adjacent active regions, the plurality of active regions being parallel to a second direction, the first direction being perpendicular to the second direction, each of the active regions comprising a plurality of channel regions separated from each other and arranged along the second direction, and a word line region located between adjacent channel regions, the word line regions located in different active regions being arranged along the first direction; a plurality of first trenches and a plurality of second trenches located in the substrate, wherein the first trenches and the second trenches both penetrate the active area and the first isolation structure along a first direction and extend from the first surface to the second surface, the first trenches penetrate the channel area, and the second trenches penetrate the word line area; a shielding layer located in the first trench, wherein in a direction perpendicular to the substrate surface, the shielding layer in the first isolation structure has a first size, and the shielding layer in the active area has a second size, wherein the second size is larger than the first size; A word line gate structure is located on the sidewall of the second trench, and the word line gate structure includes two word line layers located on the sidewall of each second trench and a second isolation structure located between the two word line layers, and the second isolation structure isolates the two word line layers from each other.

2. The dynamic random access memory according to claim 1, wherein: Both the first surface and the second surface expose the first isolation structure.

3. The dynamic random access memory according to claim 1, wherein: The first surface exposes the first isolation structure; the structure further includes: a third groove located between adjacent active areas, the third groove extending from the second surface to the first surface, the bottom of the third groove exposing the first isolation structure and the shielding layer; a first dielectric layer located in the third groove.

4. The dynamic random access memory according to claim 1, wherein: The surface of the shielding layer in the first isolation structure has a first distance from the second surface, the surface of the shielding layer in the active area has a second distance from the second surface, and the first distance is greater than the second distance; or the surface of the shielding layer in the first isolation structure has a third distance from the first surface, the surface of the shielding layer in the active area has a fourth distance from the first surface, and the third distance is greater than the fourth distance; or the first distance is greater than the second distance, and the third distance is greater than the fourth distance.

5. The dynamic random access memory according to claim 1, wherein: Also includes: a first insulating layer, the first insulating layer being located between the shielding layer and the sidewalls and bottom of the first trench; a second insulating layer, the second insulating layer being located on a surface of the shielding layer; The material of the first insulating layer includes a dielectric material, which includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon carbon oxynitride; the material of the second insulating layer includes a dielectric material, which includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon carbon oxynitride.

6. The dynamic random access memory according to claim 1, wherein: The word line gate structure also includes a third insulating layer located between the two word line layers and the bottom of the second isolation structure and the bottom of the second trench; the top surface of the word line layer is lower than the first surface; the word line gate structure also includes a fourth insulating layer located on the top surface of the word line layer.

7. The dynamic random access memory according to claim 1, wherein: Also includes: A shielding lead-out layer is located on the first surface, and the shielding lead-out layer is electrically interconnected with the shielding layer.

8. The dynamic random access memory according to claim 1, wherein: Also includes: A shielding lead-out layer is located on the second surface, and the shielding lead-out layer is electrically interconnected with the shielding layer.

9. The dynamic random access memory according to claim 1, wherein: The material of the shielding layer includes a conductor material; the conductor material includes metal.

10. The dynamic random access memory according to claim 1, wherein: Also includes: A plurality of first source-drain doped regions are located within the first surface of each of the active regions; and a plurality of capacitor structures are located on the first surface, each of the capacitor structures being electrically connected to one of the first source-drain doped regions.

11. The dynamic random access memory according to claim 1, wherein: Also includes: a second source-drain doped region located within the second surface of each active region; a plurality of bit lines located on the second surface and parallel to the second direction, each of the bit lines being electrically connected to the second source-drain doped region in one of the active regions; A metal interconnection layer located on the second surface, the metal interconnection layer being electrically interconnected with the plurality of bit lines; and a logic wafer bonded to the substrate from a surface of the metal interconnection layer, the logic wafer having a plurality of logic devices therein.

12. A method for forming a dynamic random access memory, characterized in that: include: A substrate is provided, wherein the substrate has a first surface and a second surface opposite to each other, the substrate including a plurality of active regions and an initial first isolation structure arranged along a first direction, the first surface exposing a surface of the initial first isolation structure, the initial first isolation structure being located between adjacent active regions, the plurality of active regions being parallel to a second direction, the first direction being perpendicular to the second direction, each of the active regions including a plurality of channel regions separated from each other and arranged along the second direction, and a word line region located between adjacent channel regions, the word line regions located in different active regions being arranged along the first direction; forming a plurality of first trenches and a plurality of second trenches in the substrate, wherein the first trenches and the second trenches both penetrate the active area and the initial first isolation structure along a first direction and extend from the first surface to the second surface, the first trenches penetrate the channel area, and the second trenches penetrate the word line area; forming an initial shielding layer in the first trench; forming a word line gate structure in the second trench, the word line gate structure comprising two word line layers located on sidewalls of each second trench and a second isolation structure located between the two word line layers, wherein the second isolation structure isolates the two word line layers from each other; After forming the word line gate structure and the initial shielding layer, thinning the substrate from the second surface toward the first surface until the initial first isolation structure is exposed; After the thinning process, the initial first isolation structure and the initial shielding layer are etched from the second surface to reduce the size of the initial shielding layer in the initial first isolation structure in a direction perpendicular to the substrate surface, and the initial shielding layer is used to form a shielding layer, and the initial first isolation structure is used to form a first isolation structure.

13. The method for forming a dynamic random access memory according to claim 12, wherein: The method for forming the shielding layer further includes: performing a first etching process on the initial first isolation structure until the initial shielding layer within the initial first isolation structure is exposed; and performing a second etching process on the exposed initial shielding layer.

14. The method for forming a dynamic random access memory according to claim 13, wherein: The first etching process includes one or both of a dry etching process and a wet etching process; the second etching process includes one or both of a dry etching process and a wet etching process.

15. The method for forming a dynamic random access memory according to claim 13, wherein: After forming the shielding layer, the method further includes: forming a second source-drain doped region in the second surface of each active region; forming a plurality of bit lines parallel to the second direction on the second surface, each bit line being electrically connected to the second source-drain doped region in one active region.

16. The method for forming a dynamic random access memory according to claim 15, wherein: Also includes: Etching the initial first isolation structure and the initial shielding layer to form a third trench in the substrate; A first dielectric layer is formed in the third trench.

17. The method for forming a dynamic random access memory according to claim 16, wherein: The method further includes forming a first insulating layer on sidewalls and a bottom of the first trench before forming the initial shielding layer.

18. The method for forming a dynamic random access memory according to claim 17, wherein: The method for forming the first insulating layer and the initial shielding layer includes: forming a first insulating material layer and a shielding material layer located on the surface of the first insulating material layer in the first groove and on the surface of the first surface; flattening the first insulating material layer and the shielding material layer until the first surface is exposed, forming the first insulating layer with the first insulating material layer, and forming the initial shielding layer with the shielding material layer.

19. The method for forming a dynamic random access memory according to claim 18, wherein: The top surface of the initial shielding layer is lower than the first surface; The method for forming the initial shielding layer further includes: etching back the shielding material layer after the planarization process; and after forming the initial shielding layer, further includes: forming a second insulating layer on the surface of the initial shielding layer in the first trench.

20. The method for forming a dynamic random access memory according to claim 19, wherein: The method also includes: after forming the plurality of bit lines, forming a metal interconnection layer on the second surface, the metal interconnection layer being electrically interconnected with the plurality of bit lines; providing a logic wafer having a plurality of logic device layers therein; and after forming the metal interconnection layer, facing the second surface toward the surface of the logic device layer, so that the substrate and the logic wafer are bonded to each other.

21. The method for forming a dynamic random access memory according to claim 12, wherein: The surface of the initial shielding layer in the initial first isolation structure is at a third distance from the first surface, and the surface of the initial shielding layer in the active area is at a fourth distance from the first surface, wherein the third distance is greater than the fourth distance; The method for forming the initial shielding layer includes: forming a shielding material layer in the first groove, the first surface exposing the surface of the shielding material layer; forming a mask layer on the first surface, the mask layer exposing the surface of the shielding material layer in the initial first isolation structure; using the mask layer as a mask, etching the shielding material layer from the first surface, so that the size of the initial shielding layer in the initial first isolation structure in the direction perpendicular to the substrate surface is reduced to form the initial shielding layer.

22. The method for forming a dynamic random access memory according to claim 12, wherein: The word line gate structure further includes a third insulating layer located between the two word line layers and the bottom of the second isolation structure and the bottom of the second trench; The top surface of the word line layer is lower than the first surface, and the word line gate structure further includes a fourth insulating layer located on the top surface of the word line layer.

23. The method for forming a dynamic random access memory according to claim 22, wherein: The method for forming the word line gate structure includes: forming the third insulating layer in the second trench; after forming the third insulating layer, forming an initial word line layer in the second trench, the top surface of the initial word line layer being flush with the first surface; etching a portion of the initial word line layer from the first surface toward the second surface, forming a plurality of fourth trenches parallel to the second direction in the substrate, the fourth trenches penetrating the initial word line layer from the first surface toward the second surface to form two transition word line layers; forming the second isolation structure in the fourth trench; etching back the transition word line layer to form the word line layer; after forming the word line layer, forming the fourth insulating layer in the second trench.

24. The method for forming a dynamic random access memory according to claim 12, wherein: After forming the word line gate structure and the initial shielding layer, and before the thinning process, it also includes: forming a plurality of first source-drain doping regions within the first surface of each of the active areas; after forming the plurality of first source-drain doping regions, forming a plurality of capacitor structures on the first surface, each of the capacitor structures being electrically connected to one of the first source-drain doping regions.

25. The method for forming a dynamic random access memory according to claim 12, wherein: After forming the shielding layer, the method further includes forming a shielding lead-out layer, wherein the shielding lead-out layer is electrically interconnected with the shielding layer.

26. The method for forming a dynamic random access memory according to claim 12, wherein: After forming the initial shielding layer and before the thinning process, the method further includes: forming a shielding lead layer on the first surface, wherein the shielding lead layer is electrically interconnected with the initial shielding layer.

27. The method for forming a dynamic random access memory according to claim 12, wherein: The initial shielding layer is formed first, and then the word line gate structure is formed; the method for forming the first trench, the second trench, the initial shielding layer and the word line gate structure includes: forming a plurality of initial trenches in the substrate, with the initial trench penetrating the channel region being the first trench, and the initial trench penetrating the word line region being the initial second trench; forming a protective layer in the initial second trench; after forming the protective layer, forming the initial shielding layer in the first trench; after forming the initial shielding layer, removing the protective layer to expose the initial second trench; etching the initial second trench to increase the size of the initial second trench to form the second trench; and forming the word line gate structure in the second trench.

28. The method for forming a dynamic random access memory according to claim 12, wherein: The material of the shielding layer includes a conductor material; the conductor material includes metal.

29. The method for forming a dynamic random access memory according to claim 12, wherein: The surface of the initial shielding layer is at a fifth distance from the second surface, the word line layer is at a sixth distance from the second surface, and the fifth distance is smaller than the sixth distance.

30. A method for forming a dynamic random access memory, characterized in that: include: A substrate is provided, wherein the substrate has a first surface and a second surface opposite to each other, the substrate including a plurality of active regions and a first isolation structure arranged along a first direction, the first surface exposing a surface of the first isolation structure, the first isolation structure being located between adjacent active regions, the plurality of active regions being parallel to a second direction, the first direction being perpendicular to the second direction, each of the active regions including a plurality of channel regions separated from each other and arranged along the second direction, and a word line region located between adjacent channel regions, the word line regions located in different active regions being arranged along the first direction; forming a plurality of first trenches and a plurality of second trenches in the substrate, wherein the first trenches and the second trenches both penetrate the active area and the first isolation structure along a first direction and extend from the first surface to the second surface, the first trenches penetrate the channel area, and the second trenches penetrate the word line area; forming a shielding layer in the first trench, wherein a surface of the shielding layer in the first isolation structure is at a third distance from the first surface, and a surface of the shielding layer in the active area is at a fourth distance from the first surface, wherein the third distance is greater than the fourth distance; forming a word line gate structure in the second trench, the word line gate structure comprising two word line layers located on sidewalls of the second trench and a second isolation structure located between the two word line layers, wherein the second isolation structure isolates the two word line layers from each other; After forming the word line gate structure and the shielding layer, the substrate is thinned from the second surface toward the first surface until the first isolation structure is exposed.

31. The method for forming a dynamic random access memory according to claim 30, wherein: The method for forming the shielding layer includes: forming an initial shielding layer in the first groove, exposing the initial shielding layer on the first surface; forming a mask layer on the first surface, exposing the surface of the initial shielding layer in the first isolation structure; and etching the initial shielding layer using the mask layer as a mask to form the shielding layer.

32. The method for forming a dynamic random access memory according to claim 30, wherein: After forming the shielding layer and before the thinning process, the method further includes: forming a shielding lead-out layer on the first surface, wherein the shielding lead-out layer is electrically interconnected with the shielding layer.

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