Interface circuit, memory controller and method of correction of a signal processing device

Abstract

The present invention relates to an interface circuit including a signal processing circuit for processing a receive signal received from a host device and a transmit signal transmitted to the host device. The signal processing circuit includes a plurality of signal processing devices and a correction device. The correction device is coupled to the signal processing devices for sequentially correcting a characteristic value of each signal processing device in a correction procedure.

Description

[Technical Field]

[0001] The present invention relates to a calibration method for calibrating multiple signal processing devices within an interface circuit, and more particularly to a calibration method for calibrating multiple signal processing devices within an interface circuit that provides high-speed data transmission. [Background Technology]

[0002] A serializer-deserializer (SerDes) is a pair of function blocks commonly used in high-speed communication to compensate for limited input / output. The serializer-deserializer converts data between serial data and parallel interfaces in each direction. Its primary purpose is to provide data transmission over a single line or differential pair to minimize the number of input / output pins and interconnects.

[0003] Serializers and deserializers operate at high frequencies. However, high-frequency signal transmission has low tolerance for frequency or voltage jitter. Therefore, if the characteristic values ​​of the signal processing components within the serializer and deserializer deviate, the resulting frequency or voltage jitter can cause a fetal error in the serializer and deserializer's signal processing. Once a fetal error occurs, the system must be powered off or reset, causing considerable inconvenience.

[0004] To avoid fatal errors in high-speed communication systems, a calibration method is needed to efficiently correct the characteristic values ​​of the signal processing components inside the serializer-deserializer. [Summary of the Invention]

[0005] One objective of this invention is to efficiently correct the characteristic values ​​of the internal signal processing components of the serializer-deserializer, so as to avoid fatal errors in the high-speed communication system caused by the deviation of the component characteristic values.

[0006] According to one embodiment of the present invention, an interface circuit includes a signal processing circuit for processing a received signal received from a host device and a transmitted signal transmitted to the host device. The signal processing circuit includes a plurality of signal processing devices and a correction device. The correction device is coupled to the signal processing devices for sequentially correcting a characteristic value of each signal processing device in a correction procedure.

[0007] According to another embodiment of the present invention, a memory controller coupled to a memory device for controlling access operations of the memory device includes a host interface for communicating with a host device. The host interface includes a signal processing circuit for processing a received signal received from the host device and a transmitted signal transmitted to the host device. The signal processing circuit includes a plurality of signal processing devices and a calibration device. The calibration device is coupled to the signal processing devices for sequentially calibrating a characteristic value of each signal processing device in a calibration procedure. In response to a trigger signal, the calibration device acquires a detection result of each signal processing device and calibrates the corresponding characteristic value based on the detection result of each signal processing device.

[0008] According to another embodiment of the present invention, a calibration method for calibrating a plurality of signal processing devices in an interface circuit includes: detecting whether at least one of a plurality of predetermined error events has occurred, and generating a trigger signal when at least one of the predetermined error events is detected; probing each signal processing device in response to the trigger signal to generate a corresponding probing result; and calibrating a characteristic value corresponding to each signal processing device sequentially in a calibration procedure in response to the trigger signal based on the probing result corresponding to each signal processing device. [Attached Image Description]

[0009] Figure 1 This shows a block diagram example of a data storage device according to an embodiment of the present invention.

[0010] Figure 2 This diagram shows a block diagram of an interface circuit according to an embodiment of the present invention.

[0011] Figure 3 This shows an example block diagram of a signal processing circuit according to an embodiment of the present invention.

[0012] Figure 4 This shows a block diagram of a calibration device according to an embodiment of the present invention.

[0013] Figure 5 An exemplary flowchart of a calibration method for calibrating multiple signal processing devices within an interface circuit, according to an embodiment of the present invention, is shown.

[0014] Figure 6 This shows an example flowchart of a calibration procedure according to an embodiment of the present invention.

[0015] Symbol Explanation

[0016] 100: Data storage device

[0017] 110: Memory controller

[0018] 112: Microprocessor

[0019] 112C: Program Code

[0020] 112M: Read-Only Memory

[0021] 114: Memory Interface

[0022] 116: Buffer memory

[0023] 118: Host Interface

[0024] 120: Memory device

[0025] 130,240: Main unit

[0026] 140: Error Correction Code Engine

[0027] 200: Interface Circuit

[0028] 210, 220, 230, 300: Signal processing circuits

[0029] 301: Receiver Circuit

[0030] 302: Equalization Circuit

[0031] 303: Receive Data Buffer Circuit

[0032] 304: Decoder Circuit

[0033] 305: Data transmission buffer circuit

[0034] 306: Serializer

[0035] 307: Swing Control Circuit

[0036] 308: Transmission Circuit

[0037] 309: Low Dropout Voltage Regulator Circuit

[0038] 310: Bandgap filter circuit

[0039] 311: Frequency Synthesis Circuit

[0040] 312: Reference Impedance Module

[0041] 313: Feedback Path

[0042] 330, 400: Calibration device

[0043] 410: Error Event Detection Circuit

[0044] 420: Control Circuit

[0045] 430: Circuit Detection Detailed Implementation

[0046] Numerous specific details are described below to provide a thorough understanding of embodiments of the invention. However, those skilled in the art will appreciate how the invention can be practiced in the absence of one or more specific details or in reliance on other methods, elements, or materials. In other instances, well-known structures, materials, or operations have not been shown or described in detail to avoid obscuring the main concepts of the invention.

[0047] Throughout this specification, references to "an embodiment" or "an example" mean that a particular feature, structure, or characteristic described in connection with that embodiment or example is included in at least one of the various embodiments of the invention. Therefore, the phrases "in an embodiment of the invention," "according to an embodiment of the invention," "in an example," or "according to an example" appearing in various places throughout this specification do not necessarily refer to the same embodiment or example. Furthermore, specific features, structures, or characteristics may be combined in any suitable combination and / or sub-combination in one or more embodiments or examples.

[0048] Furthermore, to make the objectives, features, and advantages of the present invention more apparent and understandable, specific embodiments of the present invention are described below in detail with reference to the accompanying drawings. The purpose is to illustrate the spirit of the present invention and not to limit the scope of protection of the present invention. It should be understood that the following embodiments can be implemented by software, hardware, firmware, or any combination thereof.

[0049] Figure 1 This diagram illustrates a block diagram example of a data storage device according to an embodiment of the present invention. The data storage device 100 may include a memory device 120 and a memory controller 110. The memory controller 110 is used to access the memory device 120 and control its operation. The memory device 120 may be a non-volatile (NV) memory device (e.g., a flash memory) and may include one or more memory elements (e.g., one or more flash memory dies, one or more flash memory chips, or other similar elements).

[0050] Data storage device 100 may be coupled to a host device 130. Host device 130 may include at least a processor, a power supply circuit, and at least one random access memory (RAM), such as at least one dynamic random access memory (DRAM), at least one static random access memory (SRAM), etc. (not shown above). Figure 1The processor and random access memory (RAM) can be interconnected via a bus and coupled to a power supply circuit to obtain power. The processor controls the operation of the host device 130. The power supply circuit can supply power to the processor, RAM, and data storage device 100, for example, by outputting one or more drive voltages to the data storage device 100. The data storage device 100 can obtain the drive voltage from the host device 130 as its power source and provide storage space for the host device 130.

[0051] According to one embodiment of the present invention, the host device 130 may issue instructions to the data storage device 100, such as read instructions or write instructions, to access the data stored in the memory device 120, or the host device 130 may issue instructions to the data storage device 100 to further control and manage the data storage device 100.

[0052] According to one embodiment of the present invention, the memory controller 110 may include a microprocessor 112, a read-only memory (ROM) 112M, a memory interface 114, a buffer memory 116, and a host interface 118. The ROM 112M is used to store program code 112C. The microprocessor 112 is used to execute program code 112C to control access to the memory device 120. Program code 112C may include one or more program modules, such as bootloader program code. When the data storage device 100 receives power from the host device 130, the microprocessor 112 may execute an initialization program of the data storage device 100 by executing program code 112C. In the initialization program, the microprocessor 112 may load a set of in-system programming (ISP) code (not shown) from the memory device 120. Figure 1The microprocessor 112 can execute this set of in-system programming code, enabling the data storage device 100 to possess various functions. According to one embodiment of the invention, this set of in-system programming code may include, but is not limited to: one or more program modules related to memory access (e.g., read, write, and erase), such as a read operation module, a lookup table module, a wear leveling module, a read refresh module, a read reclaim module, a garbage collection module, a Sudden Power Off Recovery (SPOR) module, and an Uncorrectable Error Correction Code (UECC) module, which are respectively provided to perform corresponding read, lookup table, wear leveling, read refresh, read reclaim, garbage collection, unexpected power off recovery, and error handling of detected UECC errors.

[0053] Memory interface 114 includes an error correction code engine 140. The error correction code engine 140 may internally include a data buffer (not shown) for temporarily storing data to assist the engine in performing encoding and decoding operations. During the write process of writing data to memory device 120, the error correction code engine 140 encodes the data to be written to memory device 120, for example, by performing error correction code (ECC) encoding to generate additional parity bits. During the read process of reading data from memory device 120, the error correction code engine 140 decodes the data read from memory device 120 to detect erroneous bits in the data, and, if correctable (e.g., the number of erroneous bits in the data does not exceed the upper limit of the number of erroneous bits that the error correction code engine 140 can correct), corrects the bit values ​​of the erroneous bits.

[0054] In a typical configuration, memory device 120 includes multiple memory elements, such as multiple flash memory dies or multiple flash memory chips, and each memory element may contain multiple memory blocks. Memory controller 110 performs data erasure operations on memory device 120 on a block-by-block basis. Additionally, a memory block may record (contain) a specific number of data pages, such as physical data pages, wherein memory controller 110 performs data write operations on memory device 120 on a page-by-page basis.

[0055] In practice, the memory controller 110 can use its internal components to perform various control operations, such as using the memory interface 114 to control the access operations of the memory device 120 (especially the access operations to at least one memory block or at least one data page), using the buffer memory 116 to perform the necessary buffering operations, and using the host interface 118 to communicate with the host device 130.

[0056] In one embodiment, the memory controller 110 communicates with the host device 130 via the host interface 118 and using a standard communication protocol. For example, the aforementioned standard communication protocol includes (but is not limited to): Universal Serial Bus (USB) standard, SD interface standard, Ultra High Speed-I (UHS-I) interface standard, Ultra High Speed-II (UHS-II) interface standard, CF interface standard, MMC interface standard, eMMC interface standard, UFS interface standard, Advanced Technology Attachment (ATA) standard, Serial ATA (SATA) standard, Peripheral Component Interconnect Express (PCI-E) standard, Parallel Advanced Technology Attachment (PATA) standard, etc.

[0057] In one embodiment, the buffer memory 116 used to provide data buffering is implemented as random access memory. For example, the buffer memory 116 may be static random access memory, but the invention is not limited thereto. In other embodiments, the buffer memory 116 may be dynamic random access memory.

[0058] In one embodiment, the data storage device 100 may be a portable storage device (e.g., a memory card conforming to SD / MMC, CF, MS, XD standards, a USB flash drive, etc.), and the host device 130 may be an electronic device that can be connected to the data storage device, such as a mobile phone, a laptop, a desktop computer, etc. In another embodiment, the data storage device 100 may be a solid-state drive or an embedded storage device conforming to UFS or eMMC specifications, and may be disposed in an electronic device, such as a mobile phone, a laptop, or a desktop computer, in which case the host device 130 may be a processor of the electronic device.

[0059] According to an embodiment of the present invention, the host interface 118 of the memory controller 110 may include a serializer-deserializer (SerDes) for processing a receive signal received from the host device and a transmit signal transmitted to the host device, so as to realize high-speed data transmission between the data storage device 100 and the host device 130.

[0060] Figure 2 This diagram shows a block diagram of an interface circuit according to an embodiment of the present invention. According to an embodiment of the present invention, the interface circuit 200 may be a host interface, configured between a predetermined device (e.g., a data storage device) and a host device, enabling the host device and the predetermined device to communicate with each other and transmit data signals and control signals, etc., through the interface circuit 200. According to an embodiment of the present invention, the interface circuit 200 may be... Figure 1 The host interface 118 is shown in the memory controller 110.

[0061] Interface circuit 200 may include signal processing circuits 210, 220, and 230 operating according to different layer communication protocols. Signal processing circuit 210 may be a physical layer signal processing circuit, used to process a received signal received from host device 240 and a transmitted signal transmitted to host device 240 according to the physical layer communication protocol. For example, signal processing circuit 210 may perform amplification or attenuation, analog-to-digital conversion, mixing, basic encoding or decoding, and physical layer packet decomposition operations on the received and transmitted signals. Signal processing circuit 220 may be a communication protocol layer signal processing circuit, used to perform corresponding signal processing on the transmitted and received signals according to a communication protocol higher than the physical layer. For example, signal processing circuit 220 may perform corresponding signal processing on the transmitted and received signals according to the Unified Protocol (UniPro) developed by the Mobile Industry Processor Interface (MIPI) Alliance. Signal processing circuit 220 can be further subdivided into multiple layers of signal processing circuits, such as a Physical Adapter (PA) layer signal processing circuit connected to the physical layer signal processing circuit, and other layer signal processing circuits. Signal processing circuit 230 can be an application layer signal processing circuit, used to perform higher-level signal processing according to the application layer communication protocol.

[0062] In embodiments of the present invention, the signal processing circuit 210 may be a serializer-deserializer (SerDes) or a physical layer signal processing circuit of SerDes, used to realize high-speed data and signal transmission between the aforementioned predetermined device and the host device.

[0063] Figure 3 This diagram shows an example block diagram of a signal processing circuit according to an embodiment of the present invention. In this embodiment, the signal processing circuit 300 may be a physical layer signal processing circuit configured within an interface circuit, such as a physical layer signal processing circuit within a memory controller host interface, or the signal processing circuit 300 may be a serializer-deserializer (SerDes), or a physical layer signal processing circuit of a SerDes, used to process received signals and transmitted signals to be transmitted.

[0064] The signal processing circuit 300 may include multiple signal processing devices and a correction device 330. The correction device 330 is coupled to the multiple signal processing devices to sequentially correct a characteristic value of each signal processing device in a correction program. The signal processing devices in the signal processing circuit 300 may include: a receiving circuit 301, an equalization circuit 302, a receiving data buffer circuit 303, a decoder circuit 304, a transmitting data buffer circuit 305, a serializer 306, a swing control circuit 307, a transmitting circuit 308, a low dropout regulator circuit 309, a bandgap filter circuit 310, a frequency synthesis circuit 311, and a reference impedance module 312.

[0065] It is worth noting that, Figure 3 This is a simplified schematic diagram of a signal processing circuit, showing only the components relevant to this invention. Those skilled in the art will understand that a physical layer signal processing circuit may also include many components not shown. Figure 3 The components are used to implement the corresponding physical layer signal processing functions.

[0066] In the signal processing path, the receiving circuit 301 is used to receive signals from the host device. The equalization circuit 302 is used to perform equalization processing on the received signal. The equalization circuit 302 may include a continuous-time linear equalizer (CTLE), a clock data recovery (CDR) circuit, and a deserializer (not shown). Figure 3A continuous-time linear equalizer processes the received signal, which is a serial signal. A clock data recovery circuit regenerates a clock signal synchronized with the transmitting end based on the received signal, and accurately recovers the data signal content within the received signal based on the clock signal. A deserializer converts the serial data signal into a parallel signal transmitted in parallel by multiple buses, and outputs the parallel data signal. A receive data buffer circuit 303 buffers the received data output by the equalization circuit 302. A decoder circuit 304 decodes the received data. The decoded received data is further provided to higher-level signal processing circuits, such as the aforementioned physical adaptation layer signal processing circuit.

[0067] On the signal processing path, the data buffer circuit 305 buffers the transmitted data provided by the upper-level signal processing circuit, which can be a parallel data signal. The serializer 306 converts the parallel data signal into a serial data signal. The swing control circuit 307 controls the swing of the transmitted signal, for example, adjusting the voltage of the transmitted signal to an appropriate level. The transmission circuit 308 transmits the transmitted signal to the host device.

[0068] In addition to the signal processing devices along the aforementioned transmit / receive signal processing path, the signal processing circuit 300 also includes some common circuits for providing frequency, current, voltage, power supply, or reference impedance information required by other signal processing devices. A low-dropout regulator 309 provides a stable voltage signal. For example, it provides a stable voltage signal to the bandgap filter circuit 310. The bandgap filter circuit 310 filters voltage noise to provide a clean voltage signal to other signal processing devices (as shown by the thin dashed line in the figure). A frequency synthesis circuit 311 generates the clock signal required within the signal processing circuit 300 and provides the clock signal to other signal processing devices (as shown by the thick dashed line in the figure). In one embodiment of the invention, the frequency synthesis circuit 311 may be implemented by a phase-locked loop (PLL) to generate an oscillation signal to provide the clock signal required within the signal processing circuit 300. The reference impedance module 312 may include a number of passive reference elements that can serve as an impedance reference, such as a reference resistor, a reference capacitor, and a reference inductor. Because the characteristic values ​​of passive components, such as their corresponding resistance, capacitance, and inductance values, can drift due to process variations, the signal processing circuit 300 internally includes a reference impedance module 312 manufactured using the same process to provide reference impedance information. For example, assuming that a resistance value of 10K ohms can be achieved by connecting two reference resistors in series within the reference impedance module 312, this information can be provided as reference impedance information. If one signal processing device within the signal processing circuit 300 requires a 10K ohm resistance value, this information can be used to control its internal switching circuit to connect two resistors in series. If another signal processing device requires a 20K ohm resistance value, this information can be used to control its internal switching circuit to connect four resistors in series. By flexibly controlling the coupling quantity of passive components in each signal processing device using reference impedance information within the same circuit, the characteristic value drift problem caused by process variations can be effectively overcome. The application of other passive components follows the same principle.

[0069] According to one embodiment of the present invention, the calibration device 330 is used to sequentially calibrate a characteristic value of a multi-signal processing device in a calibration procedure. Furthermore, according to one embodiment of the present invention, the calibration procedure is triggered in response to at least one error event. For example, when the signal processing circuit 300 is a signal processing circuit configured within a memory controller, the calibration procedure may be triggered in response to at least one error event occurring in the memory controller.

[0070] Figure 4This diagram shows a block diagram of a correction device according to an embodiment of the present invention. The correction device 400 may include an error event detection circuit 410, a control circuit 420, and a probe circuit 430. The error event detection circuit 410 is used to detect whether at least one of a plurality of predetermined error events has occurred. When at least one predetermined error event is detected, the error event detection circuit 410 may generate a trigger signal. The control circuit 420 is coupled to the error event detection circuit 410 and the probe circuit 430, and is used to start executing a correction procedure in response to the trigger signal. The probe circuit 430 is coupled to the control circuit 420 and a plurality of signal processing devices, such as… Figure 3 The multiple signal processing devices shown can be detected by a detection circuit 430, which receives a trigger signal from a control circuit 420 and detects each signal processing device in response to the trigger signal to generate a corresponding detection result. The control circuit 420 can receive the detection results corresponding to each signal processing device from the detection circuit 430 and adjust a characteristic value of each signal processing device sequentially according to the detection results corresponding to each signal processing device in the calibration procedure.

[0071] According to one embodiment of the present invention, the error event detection circuit 410 can detect the error by monitoring the signal processing device within the signal processing circuit (e.g., ...). Figure 2 The signal processing circuits 210, 220, 230 shown are... Figure 3 The signal processing device within the signal processing circuit 300 (shown in the diagram) determines whether a predetermined error event has occurred by issuing a specific request signal, indication signal, error signal, etc. According to another embodiment of the present invention, the signal processing device within the signal processing circuits 210, 220, 230, and 300 may also issue a notification signal to the correction device simultaneously with issuing a specific request signal, indication signal, error signal, etc., so that the error event detection circuit 410 can determine whether a predetermined error event has occurred in response to receiving this notification signal.

[0072] According to one embodiment of the present invention, the predetermined error event can be an error event that occurs or is detected within the data storage device system, or a fatal error event that would require the data storage device system to be powered off or reset. In one embodiment, the predetermined error event can be an error detected by the physical adaptation layer signal processing circuit during the signal processing flow. For example, when the communication protocol layer signal processing circuit (e.g., a processor within it) detects an error in the packet content while processing a packet, it can issue an error indication signal (e.g., PA_ERROR_IND) through the physical adaptation layer signal processing circuit. In another embodiment, the predetermined error event can also be an error occurring within the physical layer signal processing circuit. For example, when an error occurs in the decoder circuit 304 during the decoding operation, it can issue a symbol error signal (e.g., SYMBOL_ERROR) to the correction device. In another embodiment, the predetermined error event can be an event in which the interface circuit performs an error recovery operation in response to a detected error. For example, in response to a detected error, the physical adapter layer signal processing circuit can issue a power change request signal (e.g., PACP_PWR_REQ) to trigger an error recovery process. When the correction device detects the power change request signal, it can determine that a predetermined error event has occurred.

[0073] In yet another embodiment, the predetermined error event can be an event in which the interface circuit fails to perform an error recovery operation in response to a detected error; that is, the interface circuit is unable to repair the error that has occurred by performing an error recovery operation. For example, when the physical adaptation layer signal processing circuit is unable to repair the error that has occurred by performing an error recovery operation, an error signal (e.g., PA_INIT_ERROR) can be issued.

[0074] In another embodiment, the predetermined error event may also refer to an event of operating mode transition. For example, when the interface circuit or the memory controller containing the interface circuit leaves the hibernation mode, since leaving the hibernation mode can easily cause more frequency or voltage jitter or instability, it may further trigger signal processing-related errors. Therefore, when leaving the hibernation mode, an indication signal to leave the power-saving mode (e.g., Exit_Hibernate) can be sent to the correction device.

[0075] In embodiments of the present invention, the error event detection circuit 410 may determine whether a predetermined error event has occurred in response to the monitoring results of the aforementioned specific request signal, indication signal, error signal, etc., or in response to the receipt of the aforementioned notification signal. When at least one of the predetermined error events is detected, the error event detection circuit 410 may generate a trigger signal to notify the control circuit 420 to start executing a correction procedure, and in the correction procedure, control the detection circuit 430 to detect a parameter value corresponding to each signal processing device to generate a corresponding detection result.

[0076] According to one embodiment of the present invention, the detection circuit 430 may include one or more analog-to-digital conversion circuits for converting the parameter values ​​corresponding to each signal processing device from analog to digital values. Furthermore, the detection circuit 430 may also detect the current power supply voltage value and the ground voltage value for comparison reference.

[0077] In the first embodiment of the present invention, the detection circuit 430 may include only an analog-to-digital converter circuit for sequentially detecting the current power supply voltage value, the current ground voltage value, and the parameter values ​​corresponding to each signal processing device. The detection order of the detection circuit 430 may be designed according to the order in which each signal processing device is calibrated in the calibration procedure (described in the following paragraphs). Therefore, in the first embodiment of the present invention, the analog-to-digital converter circuit in the detection circuit 430 may be shared by multiple signal processing devices.

[0078] In a second embodiment of the present invention, the detection circuit 430 may include a plurality of analog-to-digital conversion circuits, wherein each signal processing device to be corrected in the correction procedure is equipped with a dedicated analog-to-digital conversion circuit for detecting the parameter values ​​corresponding to each signal processing device. Furthermore, at least one of the plurality of analog-to-digital conversion circuits also detects the current power supply voltage value and the current ground voltage value for comparison reference.

[0079] In a third embodiment of the present invention, the detection circuit 430 may include multiple analog-to-digital conversion circuits, wherein the signal processing devices that will be corrected in the correction procedure may be configured with a dedicated analog-to-digital conversion circuit, and some signal processing devices may share an analog-to-digital conversion circuit.

[0080] Reference Figure 3 The signal processing device that will be corrected in the correction procedure may include a low-dropout regulator circuit 309, a bandgap filter circuit 310, a reference impedance module 312, a frequency synthesis circuit 311, a swing control circuit 307, and an equalization circuit 302.

[0081] For the low-dropout regulator circuit 309, the detection circuit 430 can detect the input voltage at the input terminal and the output voltage at the output terminal of the low-dropout regulator circuit 309, and the analog-to-digital converter circuit converts the detected input voltage and output voltage into digital values ​​and provides them as detection results to the control circuit 420.

[0082] For the bandgap filter circuit 310, the detection circuit 430 can detect the output voltage of the bandgap filter circuit 310, and the analog-to-digital conversion circuit converts the detected output voltage into a digital value and provides it as the detection result to the control circuit 420.

[0083] For the reference impedance module 312, the detection circuit 430 can detect the current power supply voltage value, the current ground voltage value, and the current obtained after the power supply voltage is supplied to one or more passive components connected in series by controlling the corresponding switching devices in the reference impedance module 312. The detected voltage and current values ​​are converted into digital values ​​by the analog-to-digital conversion circuit and provided to the control circuit 420 as the detection results.

[0084] For the frequency synthesis circuit 311, the detection circuit 430 can detect an input voltage of a voltage-controlled oscillator inside the frequency synthesis circuit 311, and the detected voltage value is converted into a digital value by the analog-to-digital conversion circuit and provided to the control circuit 420 as the detection result.

[0085] For the swing control circuit 307, the detection circuit 430 can detect the transmission signal voltage output by the swing control circuit 307, and the analog-to-digital conversion circuit converts the detected voltage value into a digital value and provides it to the control circuit 420 as the detection result.

[0086] For equalization circuit 302, detection circuit 430 can detect the data signal voltage output by equalization circuit 302, and the detected voltage value is converted into a digital value by analog-to-digital conversion circuit and provided to control circuit 420 as detection result.

[0087] Figure 5 This diagram illustrates an example flowchart of a calibration method for calibrating multiple signal processing devices within an interface circuit, according to an embodiment of the present invention. The calibration method includes the following steps performed by a calibration device:

[0088] Step S502: Detect whether at least one of a plurality of predetermined error events has occurred, and generate a trigger signal when at least one of the predetermined error events is detected to have occurred.

[0089] Step S504: In response to the trigger signal, probe each signal processing device to generate the corresponding probe result.

[0090] Step S506: In response to the trigger signal, in a calibration procedure, the characteristic value corresponding to each signal processing device is corrected sequentially according to the detection result corresponding to each signal processing device.

[0091] Figure 6 An example flowchart of a calibration procedure according to an embodiment of the present invention is shown. The calibration procedure may include the following operations:

[0092] Operation S601: The error event detection circuit 410 can continuously detect specific signals or wait for a notification signal from the signal processing circuit. The specific signal can be a request signal, indication signal, or error signal issued by the signal processing circuit when an error is detected, or a notification signal issued by the signal processing circuit to the correction device.

[0093] Operation S602: Control circuit 420 determines whether at least one of multiple predetermined error events has occurred based on the received signal. If yes, operation S603 is executed. If no, operation S601 is executed.

[0094] Operation S603: Correct the characteristic value corresponding to the low-dropout regulator circuit 309. More specifically, the detection circuit 430 can detect the input voltage at the input terminal and the output voltage at the output terminal of the low-dropout regulator circuit 309, and convert the detected input and output voltages into digital values ​​before providing them to the control circuit 420. The control circuit 420 can calculate the voltage difference between the input and output voltages and compare the obtained voltage difference with a target value. If the obtained voltage difference does not reach the target value, the control circuit 420 can adjust the gain value of the low-dropout regulator circuit 309 so that the voltage difference between the input and output voltages meets the target value.

[0095] Operation S604: Correct the characteristic value corresponding to the bandgap filter circuit 310. More specifically, the probe circuit 430 can probe the output voltage of the bandgap filter circuit 310 and convert the probed output voltage into a digital value before providing it to the control circuit 420. The control circuit 420 can continuously receive the probe results from the bandgap filter circuit 310 from the probe circuit 430 to analyze whether voltage jitter occurs in the output voltage and to calculate the voltage jitter amplitude. If the voltage jitter amplitude of the output voltage is greater than a critical value, the control circuit 420 can adjust the filter bandwidth or frequency response of the bandgap filter circuit 310 to reduce the voltage jitter amplitude of the output voltage.

[0096] Operation S605: Correct the reference resistance value of the reference impedance module 312. More specifically, the detection circuit 430 can detect the current power supply voltage value, the current ground voltage value, and the voltage value or current value obtained at each terminal of one or more series or parallel resistors after the power supply voltage is supplied, and convert the detected voltage or current value into a digital value and provide it to the control circuit 420. The control circuit 420 can correct the reference impedance information based on the detection results obtained above. For example, the control circuit 420 can correct the reference resistance value to the impedance value or resistance value of a currently calculated reference resistor element, or correct the reference resistance value to the currently calculated number of reference resistor elements required to achieve the target voltage drop.

[0097] Operation S606: Correct the reference capacitance value of the reference impedance module 312. More specifically, the detection circuit 430 can detect the current power supply voltage value, the current ground voltage value, and the voltage value or current value obtained at each terminal of one or more series or parallel capacitors after the power supply voltage is supplied, and convert the detected voltage or current value into a digital value and provide it to the control circuit 420. The control circuit 420 can correct the reference impedance information based on the detection results obtained above. For example, the control circuit 420 can correct the reference capacitance value to the impedance value or capacitance value of a currently calculated reference capacitor element, or correct the reference capacitance value to the currently calculated number of parallel reference capacitor elements required to achieve the target voltage drop.

[0098] Operation S607: Correct the reference inductance value of the reference impedance module 312. More specifically, the probe circuit 430 can probe the current power supply voltage value, the current ground voltage value, and the voltage values ​​or current values ​​obtained at each terminal of the inductor after the power supply voltage is supplied to one or more series or parallel inductors, and convert the probed voltage or current values ​​into digital values ​​and provide them to the control circuit 420. The control circuit 420 can correct the reference impedance information based on the above probe results. For example, the control circuit 420 can correct the reference inductance value to the impedance or inductance value of a currently calculated reference inductor element, or correct the reference inductance value to the currently calculated number of reference inductor elements required to achieve the target voltage drop.

[0099] Operation S608: Correct the characteristic value corresponding to the frequency synthesis circuit 311. More specifically, the detection circuit 430 can detect an input voltage of a voltage-controlled oscillator inside the frequency synthesis circuit 311, and convert the detected input voltage into a digital value and provide it to the control circuit 420. The control circuit 420 calculates the frequency value of the oscillation signal generated by the frequency synthesis circuit 311 based on the detected input voltage, and adjusts the start-up voltage of the voltage-controlled oscillator according to this result and the target frequency value. For example, if the synthesized frequency value has not yet reached the target frequency value, the control circuit 420 can adjust the start-up voltage of the voltage-controlled oscillator so that the frequency of the oscillation signal generated by the frequency synthesis circuit 311 can reach the target frequency value more quickly.

[0100] Operation S609: Correct the characteristic value corresponding to the swing amplitude control circuit 307. More specifically, the detection circuit 430 can detect the transmission signal voltage output by the swing amplitude control circuit 307, convert the detected transmission signal voltage into a digital value, and provide it to the control circuit 420. The control circuit 420 can adjust the level of the transmission signal voltage output by the swing amplitude control circuit 307 according to the difference between the detected transmission signal voltage and the target transmission signal voltage.

[0101] Operation S610: Correct the characteristic value corresponding to the equalization circuit 302. More specifically, the probe circuit 430 can probe the received signal voltage output by the equalization circuit 302 and convert the probed input voltage into a digital value before providing it to the control circuit 420. The control circuit 420 can establish a digital version of the eye diagram based on the measurement results, and correct the parameters used by the continuous-time linear equalizer or the clock data recovery circuit based on the eye diagram content, for example, adaptively adjusting the gain value of the continuous-time linear equalizer.

[0102] According to an embodiment of the present invention, during the calibration procedure, the transmission signal output by the swing control circuit 307 can be transmitted through... Figure 3 The feedback path 313 within the signal processing circuit 300 provides a received signal to the receiving circuit 301 for correction, and the equalization circuit 302 performs equalization processing on the received signal for correction. The detection circuit 430 can detect the received signal voltage output by the equalization circuit 302, and the control circuit 420 can calculate the voltage change between the transmitted signal and the received signal, and further correct the characteristic values ​​corresponding to the equalization circuit 302 and the swing control circuit 307 based on this voltage change, the target transmitted signal voltage, and the eye diagram content. For example, if the control circuit 420 cannot establish a clear eye diagram based on the received signal, it means that the voltage level of the transmitted signal may be insufficient, which may lead to the signal being unable to resist interference or attenuation in the transmission channel. Therefore, the control circuit 420 can increase the voltage level of the transmitted signal.

[0103] In embodiments of the present invention, during the calibration process, the control circuit 420 may first perform calibration operations on signal processing devices that are not easily affected by adjustments to other parameters, and then perform calibration operations on the remaining signal processing devices. For example, the control circuit 420 may first perform calibration operations on the voltage regulator circuit (e.g., low dropout voltage regulator circuit 309) and the bandgap filter circuit (e.g., bandgap filter circuit 310) to obtain an appropriate output voltage, and then perform calibration operations on the frequency synthesis circuit (e.g., frequency synthesis circuit 311, which transmits power signals to the voltage regulator circuit and the bandgap filter circuit).

[0104] In summary, the correction device and correction method proposed in this invention can effectively correct the characteristic values ​​of the signal processing components inside the serializer-deserializer, so as to avoid frequency or voltage jitter caused by the deviation of the characteristic values ​​of each component, which could ultimately lead to fatal errors in the system.

[0105] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made within the scope of the claims of the present invention should be included in the scope of the present invention.

Claims

1. An interface circuit, comprising: A signal processing circuit for processing a received signal received from a host device and a transmitted signal transmitted to the host device, the signal processing circuit comprising: Multiple signal processing devices, each with different functions; and A calibration device, coupled to these signal processing devices, is used to sequentially calibrate different characteristic values ​​of each signal processing device in a calibration procedure, wherein the interface circuit is disposed within a memory controller, and the calibration procedure is triggered in response to at least one error event of the memory controller. The calibration device includes: An error event detection circuit is used to detect whether at least one of a plurality of predetermined error events has occurred in the memory controller, and to generate a trigger signal when at least one of these predetermined error events is detected; A probe circuit is used to probe each signal processing device in response to the trigger signal to generate a corresponding probe result; and A control circuit, coupled to the error event detection circuit and the detection circuit, is used to execute the correction procedure in response to the trigger signal, and in the correction procedure, to adjust the characteristic value of each signal processing device in sequence according to the detection result corresponding to each signal processing device.

2. The interface circuit as described in claim 1, characterized in that, The signal processing circuit is a serializer-deserializer (abbreviated as SerDes).

3. The interface circuit as described in claim 1, characterized in that, These signal processing devices include a voltage regulator circuit and a frequency synthesis circuit. In the calibration procedure, the control circuit first calibrates the voltage regulator circuit and then calibrates the frequency synthesis circuit.

4. A memory controller coupled to a memory device for controlling access operations of the memory device, the memory controller comprising: A host interface for communicating with a host device, the host interface including a signal processing circuit for processing a received signal received from the host device and a transmitted signal transmitted to the host device. The signal processing circuit includes: Multiple signal processing devices, each with different functions; and A calibration device, coupled to these signal processing devices, is used to sequentially correct different characteristic values ​​of each signal processing device in a calibration procedure. The calibration device includes: An error event detection circuit is used to detect whether at least one of a plurality of predetermined error events has occurred in the memory controller, and to generate a trigger signal when at least one of these predetermined error events is detected; A probe circuit is used to probe each signal processing device in response to the trigger signal to generate a corresponding probe result; and A control circuit, coupled to the error event detection circuit and the detection circuit, is used to execute the correction procedure in response to the trigger signal, and in the correction procedure, the characteristic value of each signal processing device is adjusted sequentially according to the detection result corresponding to each signal processing device. In response to the trigger signal, the correction device obtains the detection results of each signal processing device and corrects the corresponding characteristic value based on the detection results of each signal processing device.

5. The memory controller as described in claim 4, characterized in that, The correction procedure is triggered in response to at least one error event of the memory controller.

6. The memory controller as claimed in claim 4, characterized in that, The signal processing circuit is a serializer-deserializer (abbreviated as SerDes).

7. The memory controller as claimed in claim 4, characterized in that, These signal processing devices include: A first signal processing device; and A second signal processing device, wherein the second signal processing device receives a power signal from the first signal processing device. In this calibration procedure, the control circuit first calibrates the first signal processing device, and then calibrates the second signal processing device.

8. A calibration method for calibrating multiple signal processing devices with different functions within an interface circuit, comprising: An error event detection circuit in a calibration device within the interface circuit is used to detect whether a memory controller has experienced at least one of a plurality of predetermined error events, and a trigger signal is generated when at least one of these predetermined error events is detected. The detection circuit in the calibration device responds to the trigger signal to detect each signal processing device to generate a corresponding detection result. as well as In response to the trigger signal, a calibration procedure sequentially corrects the different characteristic values ​​corresponding to each signal processing device based on the detection results corresponding to each signal processing device. The process of correcting the different characteristic values ​​corresponding to each signal processing device in sequence according to the detection results of each signal processing device in response to the trigger signal includes: The calibration device utilizes a control circuit to execute the calibration procedure in response to the trigger signal, and in the calibration procedure, the characteristic values ​​of each signal processing device are adjusted sequentially according to the detection results corresponding to each signal processing device.

9. The correction method as described in claim 8, characterized in that, The interface circuit is configured within the memory controller, and these predetermined error events are error events that occur within the memory controller.

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