A constant frequency adaptive current and conduction time generating circuit

Abstract

The present invention discloses a constant frequency adaptive current and on-time generating circuit, which is composed of an adaptive current generating subcircuit and an adaptive on-time generating subcircuit. The adaptive current generating subcircuit generates an output current that varies with the input voltage and the set frequency by introducing input voltage feedforward and external frequency setting current, and the adaptive on-time generating subcircuit charges the capacitor through the adaptive current and compares it with the output voltage to generate an adaptive on-time signal, the on-time of which is determined by the charging time of the capacitor and is related to the input and output voltages and the external setting frequency, so that the operating frequency of the system can be stabilized.

Description

Technical Field

[0001] The invention relates to the technical field of switching power supplies, and in particular to a constant-frequency adaptive current and on-time generating circuit. Background Art

[0002] With the rise of current consumer electronics and wireless IoT applications, new requirements have been put forward for high efficiency and fast load transient response of power management chips. This has made switching power supplies one of the more important fields at present, among which the most widely used is the switching power supply with constant on-time (COT) working mode. However, since the working frequency of this working mode changes with the input voltage, output voltage and load, it is difficult to centrally deal with EMI problems.

[0003] In a DC / DC circuit in COT working mode, the on-time signal is determined by the time it takes for a current to charge a capacitor, and the current and capacitance are fixed, so the generated on-time signal is a fixed time. A phase-locked loop is generally used to control the on-time current. By giving a reference frequency, the phase-locked loop can stabilize the system operating frequency near the reference frequency. However, this will make the circuit complicated, and the working range of the phase-locked loop is limited. When the system needs to design the operating frequency externally, it is difficult to stabilize the system operating frequency. Summary of the invention

[0004] In view of the above-mentioned deficiencies in the prior art, the present invention provides a constant frequency adaptive current and on-time generating circuit to solve the problems of unstable operating frequency, complex circuit and limited circuit operating range in the existing COT working mode DC / DC circuit.

[0005] In order to achieve the above-mentioned invention object, the technical scheme adopted by the present invention is: a constant frequency adaptive current and conduction time generating circuit, the circuit includes an adaptive current generating subcircuit and an adaptive conduction time generating subcircuit, the adaptive current generating subcircuit includes transistors Q1, Q2, Q3, Q4, Q5, Q6 and Q7, MOS tubes M1, M2, M3, M4, M5, M6, M7 and M8, the emitter of the transistor Q1 is respectively connected to one end of the resistor R1 and the grounding resistor R2, the other end of the resistor R1 is connected to the input voltage SVIN, the collector of the transistor Q1 is respectively connected to the ammeter I b1 The base of transistor Q1 and the base of transistor Q2 are connected, and the ammeter I b1The other end is connected to the power supply, the collector of the transistor Q2 is respectively connected to the gate of the MOS transistor M1, the drain of the MOS transistor M1 and the gate of the MOS transistor M2, the source of the MOS transistor M1 is connected to the power supply, the emitter of the transistor Q2 is connected to the grounding resistor R3, the source of the MOS transistor M2 is connected to the power supply, the drain of the MOS transistor M2 is respectively connected to the drain of the MOS transistor M3, the gate of the MOS transistor M3 and the gate of the MOS transistor M4, the source of the MOS transistor M3 is grounded, the source of the MOS transistor M4 is grounded, the drain of the MOS transistor M4 is respectively connected to the base of the transistor Q3 and the emitter of the transistor Q5, the emitter of the transistor Q3 is grounded, and the collector of the transistor Q3 is respectively connected to the input current I freq and the emitter of transistor Q4, the base of transistor Q4 is respectively connected to the collector of transistor Q4, the base of transistor Q5, and the ammeter I b2 One end of the transistor Q6 is connected to the base of the transistor Q6, the collector of the transistor Q5 is connected to the power supply, and the ammeter I b2 The other end of the transistor Q6 is connected to the power supply, the collector of the transistor Q6 is connected to the power supply, the emitter of the transistor Q6 is connected to the drain of the MOS transistor M6 and the base of the transistor Q7 respectively, the source of the MOS transistor M6 is grounded, and the gate of the MOS transistor M6 is connected to the gate of the MOS transistor M5, the drain of the MOS transistor M5 and the ammeter I respectively. b3 One end of the ammeter I b3 The other end is connected to the power supply, the source of the MOS tube M5 is grounded, the emitter of the triode Q7 is grounded, the collector of the triode Q7 is respectively connected to the drain of the MOS tube M7, the gate of the MOS tube M7 and the gate of the MOS tube M8, the source of the MOS tube M7 is connected to the power supply, the source of the MOS tube M8 is connected to the power supply, and the drain of the MOS tube M8 generates the output current I of the adaptive current generation sub-circuit b .

[0006] The beneficial effect of the above scheme is: through the above technical scheme, the stability of the system operating frequency is ensured, and the problem of unstable operating frequency in the DC / DC circuit of the existing COT working mode is solved. For the design of stable operating frequency, the phase-locked loop design circuit is generally used in the existing circuit, which makes the circuit too complicated and the circuit working range is limited. The present scheme consists of two parts: an adaptive current generating subcircuit and an adaptive conduction time generating subcircuit, and the circuit structure is relatively simple.

[0007] Furthermore, the adaptive conduction time generating sub-circuit includes a MOS tube M9, a MOS tube M 10 、MOS tube M 11 、MOS tube M 12 、MOS tube M 13, operational amplifier AMP and comparator T on CMP, the drain of the MOS tube M9 is respectively connected to the output current I b , the gate of MOS tube M9 and MOS tube M 10 The gate of the MOS tube M9 is connected to the ground. 10 The source of the MOS tube M is grounded. 10 The drain of MOS tube M 11 The drain of MOS tube M 11 The gate and MOS tube M 12 The gate connection of the MOS tube M 11 The source and power supply voltage V DD connection, the MOS tube M 12 The source and power supply voltage V DD connection, the MOS tube M 12 The drain of the MOS tube M is connected to the ground capacitor C and the 13 The drain of the comparator T on The in-phase end of CMP is connected to the MOS tube M 13 The source of the MOS tube M is grounded. 13 The gate of the comparator T is connected to the oscillator clock signal CLK. on The inverting terminal of CMP is connected to the output terminal of the operational amplifier AMP and the inverting terminal of the operational amplifier AMP respectively, and the non-inverting terminal of the operational amplifier AMP is connected to the output voltage V out connection, the comparator T on The output terminal of CMP generates an adaptive on-time signal T on .

[0008] The beneficial effect of the above further solution is that in the adaptive on-time generating subcircuit, the capacitor is charged by the adaptive current and compared with the output voltage to generate an adaptive on-time signal.

[0009] Furthermore, an external frequency setting circuit is introduced into the adaptive current generating sub-circuit, and the external frequency setting circuit includes a MOS tube M 14 、MOS tube M 15 、MOS tube M 16 and unity gain amplifier, the MOS tube M 14 The gate of the MOS tube M is connected to the output end of the unity gain amplifier. 14 The source of T One end is connected to the inverting end of the unity gain amplifier, and the external resistor R T The other end is grounded, and the non-inverting end of the unity gain amplifier is connected to the internal voltage reference V refconnection, the MOS tube M 14 The drain of MOS tube M 15 The drain of MOS tube M 15 The gate and MOS tube M 16 The gate connection of the MOS tube M 15 The source and power supply voltage V DD connection, the MOS tube M 16 The source and power supply voltage V DD connection, the MOS tube M 16 The drain generates an input current I freq .

[0010] The beneficial effect of the above further solution is that in the external frequency setting circuit, the control of the output current by the external resistor is realized through a unit gain amplifier, and the adaptive current generating subcircuit generates the output current that varies with the set frequency.

[0011] Furthermore, the resistors R1 and R2 in the adaptive current generation subcircuit divide the input voltage SVIN, which acts on the resistor R3 and generates a current I1, and the formula is as follows:

[0012] I1=k×SVIN

[0013]

[0014] Among them, k is a resistance-related parameter;

[0015] For transistors Q3, Q5, and Q6, the following formulas are included:

[0016]

[0017]

[0018]

[0019] Among them, V be3 is the base and emitter potential of transistor Q3, V T is the temperature-dependent constant, I b2 is the base current of transistor Q2, I s is the transistor saturation current, V be5 is the base and emitter potential of transistor Q5, V be6 is the base and emitter potential of transistor Q6, I b3 is the base current of transistor Q3;

[0020] Then the base potential of transistor Q5 is V b5 for:

[0021] V b5 =V be3 +V be5

[0022] Then the base and emitter potentials of transistor Q7 are V be7 for:

[0023] V be7 =V b5 -V be6

[0024] The collector current generated by transistor Q7 is the output current I of the adaptive current generation subcircuit. b for:

[0025] I b =(I b2 +I freq )×k×SVIN / I b3 .

[0026] The beneficial effect of the above further solution is that: through the above technical solution, the output current of the adaptive current generating subcircuit is obtained, which is used to charge the capacitor in the adaptive on-time generating subcircuit.

[0027] Furthermore, in the adaptive on-time generation subcircuit, the output current I b The capacitor is charged, and the output voltage V out Compare and generate adaptive on-time signal T on , the formula is as follows:

[0028]

[0029]

[0030] The beneficial effect of the above further scheme is: through the above technical scheme, an adaptive on-time is obtained, and the on-time is determined by the charging time of the capacitor, which is related to the input and output voltages and the externally set frequency, so that the operating frequency of the system can be stabilized. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 Schematic diagram of the adaptive current generation subcircuit.

[0032] Figure 2 Schematic diagram of the subcircuit for adaptive on-time generation.

[0033] Figure 3 Schematic diagram of the circuit for external frequency setting. DETAILED DESCRIPTION

[0034] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments.

[0035] like Figure 1 As shown, a constant frequency adaptive current and on-time generating circuit, the circuit includes an adaptive current generating subcircuit and an adaptive on-time generating subcircuit, the adaptive current generating subcircuit includes transistors Q1, Q2, Q3, Q4, Q5, Q6 and Q7, MOS transistors M1, M2, M3, M4, M5, M6, M7 and M8, the emitter of the transistor Q1 is respectively connected to one end of a resistor R1 and a grounding resistor R2, the other end of the resistor R1 is connected to an input voltage SVIN, the collector of the transistor Q1 is respectively connected to an ammeter I b1 The base of transistor Q1 and the base of transistor Q2 are connected, and the ammeter I b1 The other end is connected to the power supply, the collector of the transistor Q2 is respectively connected to the gate of the MOS transistor M1, the drain of the MOS transistor M1 and the gate of the MOS transistor M2, the source of the MOS transistor M1 is connected to the power supply, the emitter of the transistor Q2 is connected to the grounding resistor R3, the source of the MOS transistor M2 is connected to the power supply, the drain of the MOS transistor M2 is respectively connected to the drain of the MOS transistor M3, the gate of the MOS transistor M3 and the gate of the MOS transistor M4, the source of the MOS transistor M3 is grounded, the source of the MOS transistor M4 is grounded, the drain of the MOS transistor M4 is respectively connected to the base of the transistor Q3 and the emitter of the transistor Q5, the emitter of the transistor Q3 is grounded, and the collector of the transistor Q3 is respectively connected to the input current I freq and the emitter of transistor Q4, the base of transistor Q4 is respectively connected to the collector of transistor Q4, the base of transistor Q5, and the ammeter I b2 One end of the transistor Q6 is connected to the base of the transistor Q6, the collector of the transistor Q5 is connected to the power supply, and the ammeter I b2 The other end of the transistor Q6 is connected to the power supply, the collector of the transistor Q6 is connected to the power supply, the emitter of the transistor Q6 is connected to the drain of the MOS transistor M6 and the base of the transistor Q7 respectively, the source of the MOS transistor M6 is grounded, and the gate of the MOS transistor M6 is connected to the gate of the MOS transistor M5, the drain of the MOS transistor M5 and the ammeter I respectively. b3 One end of the ammeter I b3The other end is connected to the power supply, the source of the MOS tube M5 is grounded, the emitter of the triode Q7 is grounded, the collector of the triode Q7 is respectively connected to the drain of the MOS tube M7, the gate of the MOS tube M7 and the gate of the MOS tube M8, the source of the MOS tube M7 is connected to the power supply, the source of the MOS tube M8 is connected to the power supply, and the drain of the MOS tube M8 generates the output current I of the adaptive current generation sub-circuit b .

[0036] like Figure 2 As shown, the adaptive conduction time generating sub-circuit includes MOS tube M9, MOS tube M 10 、MOS tube M 11 、MOS tube M 12 、MOS tube M 13 , operational amplifier AMP and comparator T on CMP, the drain of the MOS tube M9 is respectively connected to the output current I b , the gate of MOS tube M9 and MOS tube M 10 The gate of the MOS tube M9 is connected to the ground. 10 The source of the MOS tube M is grounded. 10 The drain of MOS tube M 11 The drain of MOS tube M 11 The gate and MOS tube M 12 The gate connection of the MOS tube M 11 The source and power supply voltage V DD connection, the MOS tube M 12 The source and power supply voltage V DD connection, the MOS tube M 12 The drain of the MOS tube M is connected to the ground capacitor C and the 13 The drain of the comparator T on The in-phase end of CMP is connected to the MOS tube M 13 The source of the MOS tube M is grounded. 13 The gate of the comparator T is connected to the oscillator clock signal CLK. on The inverting terminal of CMP is connected to the output terminal of the operational amplifier AMP and the inverting terminal of the operational amplifier AMP respectively, and the non-inverting terminal of the operational amplifier AMP is connected to the output voltage V out connection, the comparator T on The output terminal of CMP generates an adaptive on-time signal T on .

[0037] like Figure 3As shown, an external frequency setting circuit is introduced into the adaptive current generating sub-circuit, and the external frequency setting circuit includes a MOS tube M 14 、MOS tube M 15 、MOS tube M 16 and unity gain amplifier, the MOS tube M 14 The gate of the MOS tube M is connected to the output end of the unity gain amplifier. 14 The source of T One end is connected to the inverting end of the unity gain amplifier, and the external resistor R T The other end is grounded, and the non-inverting end of the unity gain amplifier is connected to the internal voltage reference V ref connection, the MOS tube M 14 The drain of MOS tube M 15 The drain of MOS tube M 15 The gate and MOS tube M 16 The gate connection of the MOS tube M 15 The source and power supply voltage V DD connection, the MOS tube M 16 The source and power supply voltage V DD connection, the MOS tube M 16 The drain generates an input current I freq .

[0038] In the adaptive current generation subcircuit, resistors R1 and R2 divide the input voltage SVIN, which acts on resistor R3 and generates current I1. Figure 1 The circuit shown with I freq The superposition produces the output current, the formula is as follows:

[0039] I1=k×SVIN

[0040]

[0041] Among them, k is a resistance-related parameter;

[0042] For transistors Q3, Q5, and Q6, the following formulas are included:

[0043]

[0044]

[0045]

[0046] Among them, V be3 is the base and emitter potential of transistor Q3, V T is the temperature-dependent constant, I b2is the base current of transistor Q2, I s is the transistor saturation current, V be5 is the base and emitter potential of transistor Q5, V be6 is the base and emitter potential of transistor Q6, I b3 is the base current of transistor Q3;

[0047] Then the base potential of transistor Q5 is V b5 for:

[0048] V b5 =V be3 +V be5

[0049] Then the base and emitter potentials of transistor Q7 are V be7 for:

[0050] V be7 =V b5 -V be6

[0051] The collector current generated by transistor Q7 is the output current I of the adaptive current generation subcircuit. b for:

[0052] I b =(I b2 +I freq )×k×SVIN / I b3

[0053] In the adaptive on-time generation subcircuit, the output current I of the adaptive current generation subcircuit is b The capacitor is charged, and the output voltage V out Compare and generate adaptive on-time signal T on , the formula is as follows:

[0054]

[0055]

[0056] It can be seen from the formula that the on-time is proportional to the output voltage, and inversely proportional to the set frequency and input voltage, so adaptive on-time can be generated.

[0057] In one embodiment of the present invention, the input voltage and external frequency setting current signal are introduced into the adaptive current generation subcircuit to generate a current that varies with the input voltage and the set frequency. In the adaptive on-time generation subcircuit, the capacitor is charged by the adaptive current and compared with the output voltage to generate an adaptive on-time signal. The time for charging the capacitor is the on-time of the power tube per cycle, which is related to the output voltage, the input voltage and the set frequency.

[0058] Aiming at the problem that the fixed on-time of the traditional COT leads to a variable operating frequency, the present invention proposes an adaptive on-time generating circuit, which introduces the output voltage, the input voltage and the external frequency setting signal to generate a corresponding current, and uses the current to charge the capacitor to generate an adaptive on-time signal, thereby ensuring the stability of the system operating frequency and eliminating the influence of the input and output voltages on the system operating frequency.

[0059] Those skilled in the art will appreciate that the embodiments described herein are intended to help readers understand the principles of the present invention, and should be understood that the protection scope of the present invention is not limited to such specific statements and embodiments. Those skilled in the art can make various other specific variations and combinations that do not deviate from the essence of the present invention based on the technical revelations disclosed by the present invention, and these variations and combinations are still within the protection scope of the invention.

Claims

1. A constant frequency adaptive current and on-time generating circuit, characterized in that: The circuit includes an adaptive current generating subcircuit and an adaptive conduction time generating subcircuit, wherein the adaptive current generating subcircuit includes transistors Q1, Q2, Q3, Q4, Q5, Q6 and Q7, MOS transistors M1, M2, M3, M4, M5, M6, M7 and M8, wherein the emitter of the transistor Q1 is respectively connected to one end of a resistor R1 and a grounding resistor R2, the other end of the resistor R1 is connected to an input voltage SVIN, and the collector of the transistor Q1 is respectively connected to a current source I b1 The current source I b1 The other end is connected to the power supply, the collector of the transistor Q2 is respectively connected to the gate of the MOS transistor M1, the drain of the MOS transistor M1 and the gate of the MOS transistor M2, the source of the MOS transistor M1 is connected to the power supply, the emitter of the transistor Q2 is connected to the grounding resistor R3, the source of the MOS transistor M2 is connected to the power supply, the drain of the MOS transistor M2 is respectively connected to the drain of the MOS transistor M3, the gate of the MOS transistor M3 and the gate of the MOS transistor M4, the source of the MOS transistor M3 is grounded, the source of the MOS transistor M4 is grounded, the drain of the MOS transistor M4 is respectively connected to the base of the transistor Q3 and the emitter of the transistor Q5, the emitter of the transistor Q3 is grounded, and the collector of the transistor Q3 is respectively connected to the input current I freq and the emitter of transistor Q4, the base of transistor Q4 is respectively connected to the collector of transistor Q4, the base of transistor Q5, the current source I b2 One end of the transistor Q6 is connected to the base of the transistor Q6, the collector of the transistor Q5 is connected to the power supply, and the current source I b2 The other end of the transistor Q6 is connected to the power supply, the collector of the transistor Q6 is connected to the power supply, the emitter of the transistor Q6 is connected to the drain of the MOS transistor M6 and the base of the transistor Q7 respectively, the source of the MOS transistor M6 is grounded, and the gate of the MOS transistor M6 is connected to the gate of the MOS transistor M5, the drain of the MOS transistor M5 and the current source I b3 One end of the current source I b3 The other end is connected to the power supply, the source of the MOS tube M5 is grounded, the emitter of the triode Q7 is grounded, the collector of the triode Q7 is respectively connected to the drain of the MOS tube M7, the gate of the MOS tube M7 and the gate of the MOS tube M8, the source of the MOS tube M7 is connected to the power supply, the source of the MOS tube M8 is connected to the power supply, and the drain of the MOS tube M8 generates the output current I of the adaptive current generation sub-circuit b An external frequency setting circuit is introduced into the adaptive current generating sub-circuit, and the external frequency setting circuit includes a MOS tube M14, a MOS tube M15, a MOS tube M16 and a unit gain amplifier. The gate of the MOS tube M14 is connected to the output end of the unit gain amplifier, the source of the MOS tube M14 is respectively connected to one end of the external resistor RT and the inverting end of the unit gain amplifier, the other end of the external resistor RT is grounded, the non-inverting end of the unit gain amplifier is connected to the internal voltage reference Vref, the drain of the MOS tube M14 is respectively connected to the drain of the MOS tube M15, the gate of the MOS tube M15 and the gate of the MOS tube M16, the source of the MOS tube M15 is connected to the power supply voltage VDD, the source of the MOS tube M16 is connected to the power supply voltage VDD, and the drain of the MOS tube M16 generates an input current Ifreq.

2. The constant frequency adaptive current and on-time generating circuit according to claim 1, characterized in that: The adaptive conduction time generating sub-circuit comprises a MOS tube M9, a MOS tube M 10 、MOS tube M 11 、MOS tube M 12 、MOS tube M 13 , operational amplifier AMP and comparator T on CMP, the drain of the MOS tube M9 is respectively connected to the output current I b , the gate of MOS tube M9 and MOS tube M 10 The gate of the MOS tube M9 is connected to the ground. 10 The source of the MOS tube M is grounded. 10 The drain of MOS tube M 11 The drain of MOS tube M 11 The gate and MOS tube M 12 The gate connection of the MOS tube M 11 The source and power supply voltage V DD connection, the MOS tube M 12 The source and power supply voltage V DD connection, the MOS tube M 12 The drain of the MOS tube M is connected to the ground capacitor C and the 13 The drain of the comparator T on The in-phase end of CMP is connected to the MOS tube M 13 The source of the MOS tube M is grounded. 13 The gate of the comparator T is connected to the oscillator clock signal CLK. on The inverting terminal of CMP is connected to the output terminal of the operational amplifier AMP and the inverting terminal of the operational amplifier AMP respectively, and the non-inverting terminal of the operational amplifier AMP is connected to the output voltage V out connection, the comparator T on The output terminal of CMP generates an adaptive on-time signal T on .

3. The constant frequency adaptive current and on-time generating circuit according to claim 1, characterized in that: The resistors R1 and R2 in the adaptive current generation subcircuit divide the input voltage SVIN, acting on the resistor R3 and generating a current , the formula is as follows: in, are resistance related parameters; For transistors Q3, Q5, and Q6, the following formulas are included: in, are the base and emitter potentials of transistor Q3, is the temperature-dependent constant, is the base current of transistor Q2, is the transistor saturation current, are the base and emitter potentials of transistor Q5, is the base and emitter potential of transistor Q6, is the base current of transistor Q3; Then the base potential of transistor Q5 is for: Then the base and emitter potentials of transistor Q7 are for: The collector current generated by transistor Q7 is the output current of the adaptive current generation subcircuit for: 。 4. The constant frequency adaptive current and on-time generating circuit according to claim 3, characterized in that: In the adaptive on-time generation subcircuit, the output current of the adaptive current generation subcircuit is generated by The capacitor is charged, and the output voltage Compare and generate adaptive on-time signal , the formula is as follows: 。

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