Power tube control method and controller

Abstract

The application provides a power tube control method and a controller. The power tube control method comprises the following steps: calculating an expected lower limit value and an expected upper limit value based on the parasitic capacitance of the power tube of the upper bridge arm and the lower bridge arm, an input voltage, an output voltage and an output current; setting an expected dead zone value based on at least the expected lower limit value and the expected upper limit value; keeping a dead zone value or setting the expected dead zone value as the dead zone value; and controlling the power tube of the upper bridge arm and the lower bridge arm to be turned off based on the dead zone value. In this way, on the one hand, the dead zone value is continuously adjusted in a real-time calculation manner, thereby improving the adaptive ability of the scheme; on the other hand, the expected dead zone value is calculated based on the expected lower limit value and the expected upper limit value, the dead zone update logic is optimized, and each iteration of the dead zone is more reasonable. The problem that the setting of the dead zone is not flexible and the adaptive ability is not strong in the prior art is solved.

Description

Technical Field

[0001] This invention relates to the field of power module optimization technology, and in particular to a power transistor control method and controller. Background Technology

[0002] High reliability and high efficiency power supply products have always been the relentless pursuit of power supply engineers. Soft-switching technology can effectively reduce the switching losses of power switching devices, thereby improving the efficiency of power supply products, and is therefore widely studied. Among them, phase-shift control technology is widely used in automotive power supply products due to its high reliability and maturity. Furthermore, in order to achieve ZVS (Zero Voltage Switch) turn-on of power switching devices and prevent shoot-through between the upper and lower bridge arms, a dead time needs to be added between the complementary drive signals of the upper and lower bridge arms.

[0003] However, the common fixed dead-time approach has the following disadvantages: 1) If the fixed dead-time is smaller than the actual dead-time required for soft switching, there will be turn-on losses when the power device is turned on; 2) If the fixed dead-time is larger than the actual dead-time required for soft switching, some power will be conducted through the body diode of the power device or the diode connected in parallel, inevitably resulting in diode conduction losses; 3) The differences in power devices cannot guarantee the consistency of power supply product performance. Therefore, the fixed dead-time increases the product's losses, thereby affecting the efficiency of the power supply product and further increasing the thermal design cost of the power device.

[0004] To address the aforementioned issues and improve system reliability, researchers have proposed a segmented dead-time control method. This method sets different dead times based on different input voltages and output loads, effectively resolving dead-time requirements under varying input voltages and output loads. This ensures the zero-voltage switching (ZVS) turn-on of power switching devices under different operating conditions, thereby improving power efficiency and reliability across various power supply scenarios. However, this method requires multiple tests and analyses, increasing design time costs. Furthermore, due to parameter variations in power devices, the set dead time cannot be guaranteed to be applicable to all power supply products, further increasing design complexity.

[0005] Therefore, optimizing the dead zone of power devices in phase-shift control technology while ensuring power supply reliability, so as to achieve ZVS turn-on of power switching devices, is not only of great significance to the overall efficiency of the power supply, but also can save the design time of power supply products and avoid repetitive and tedious testing and verification.

[0006] In summary, existing technologies suffer from problems such as insufficient flexibility in setting dead zones and weak adaptive capabilities. Summary of the Invention

[0007] The purpose of this invention is to provide a power transistor control method and controller to solve the problems of insufficient flexibility in setting the dead time and weak adaptive capability in the prior art.

[0008] To address the aforementioned technical problems, this invention provides a power transistor control method applied to a power supply circuit, the power supply circuit including at least one upper bridge arm and a lower bridge arm. The power transistor control method includes: calculating a lower expected limit and a higher expected limit based on the parasitic capacitance, input voltage, output voltage, and output current of the power transistors in the upper and lower bridge arms; setting an expected dead zone value based at least on the lower expected limit and the higher expected limit; maintaining the dead zone value, or setting the expected dead zone value as the dead zone value; and controlling the switching on and off of the power transistors in the upper and lower bridge arms based on the dead zone value.

[0009] Optionally, the expected lower limit and the expected upper limit are calculated based on zero-voltage switching constraints.

[0010] Optionally, the power supply circuit includes a transformer, an output inductor, and two sets of upper bridge arms and lower bridge arms. In each half-cycle, the upper bridge arm that is turned on first is designated as the first upper bridge arm, and the upper bridge arm that is turned on later is designated as the second upper bridge arm. The lower bridge arm corresponding to the first upper bridge arm is designated as the first lower bridge arm, and the lower bridge arm corresponding to the second upper bridge arm is designated as the second lower bridge arm. The power transistor of the first upper bridge arm is designated as the first upper transistor, the power transistor of the first lower bridge arm is designated as the first lower transistor, the power transistor of the second upper bridge arm is designated as the second upper transistor, and the power transistor of the second lower bridge arm is designated as the second lower transistor.

[0011] The expected lower limit values ​​of the first upper tube and the first lower tube are calculated based on the following formula:

[0012]

[0013] Wherein, Δt1 represents the expected lower limit value of the first upper transistor and the first lower transistor, C1 represents the parasitic capacitance of the first upper transistor, C2 represents the parasitic capacitance of the first lower transistor, Vin represents the input voltage, Nt represents the coil turns ratio of the transformer, Io represents the average current of the output current, Ts represents the duration of one cycle, Vo represents the output voltage, and Lo represents the output inductance.

[0014] The expected lower limit values ​​of the second upper tube and the second lower tube are calculated based on the following formula:

[0015]

[0016] Wherein, Δt2 represents the expected lower limit value of the second upper tube and the second lower tube, C3 represents the parasitic capacitance of the second upper tube, and C4 represents the parasitic capacitance of the second lower tube.

[0017] The expected upper limit value is calculated based on the following formula:

[0018]

[0019] Where Δt3 represents the expected upper limit value, and Lr represents the resonant inductance on the primary side of the transformer.

[0020] Optionally, C1, C2, C3, and C4 can all be set to Cossmax, where Cossmax represents the maximum parameter of the power transistor's device specifications.

[0021] Optionally, the secondary side of the power supply circuit is a full-wave rectified current, a full-bridge rectifier circuit, or a current-doubler rectifier circuit.

[0022] Optionally, the power transistor control method includes: obtaining an initial safe dead zone.

[0023] The step of setting the expected dead zone value based at least on the expected lower limit value and the expected upper limit value specifically involves setting the expected dead zone value based on the initial safe dead zone, the expected lower limit value, and the expected upper limit value.

[0024] Optionally, the power transistor control method includes: obtaining safety design deviations.

[0025] The step of setting the expected dead zone value based on the initial safety dead zone, the expected lower limit value, and the expected upper limit value specifically involves selecting one of the following three values ​​as the expected dead zone value: the initial safety dead zone, the sum of the expected lower limit value and the safety design deviation, and the expected upper limit value.

[0026] Optionally, the step of selecting one of the following three values ​​as the expected dead zone value: the initial safety dead zone, the sum of the expected lower limit and the safety design deviation, and the expected upper limit: specifically includes comparing Tc and Δt. min +ΔT's magnitude, if Δt min +ΔT>Tc, then let dt=Δt min +ΔT, otherwise, let dt = Tc; compare dt with Δt. max The size of dt, if dt < Δt max If dt remains unchanged, then dt remains unchanged; otherwise, let dt = Δt. max ; and dt is taken as the expected dead zone value.

[0027] Where Tc represents the initial safe dead zone, Δt minrepresents the expected lower limit value, ΔT represents the safety design deviation, and Δt max represents the expected upper limit value.

[0028] Optionally, the step of maintaining the dead zone value or setting the expected dead zone value to the dead zone value specifically includes: if |DT - dt| < k, then maintain the dead zone value; otherwise, set the expected dead zone value to the dead zone value, where DT represents the dead zone value, dt represents the expected dead zone value, and k represents the error threshold.

[0029] To solve the above technical problems, the present invention also provides a controller, which is applied to a power supply circuit. The power supply circuit includes at least one set of upper bridge arm and lower bridge arm, and the controller is used to execute the above power transistor control method.

[0030] Compared with the prior art, in the power transistor control method and controller provided by the present invention, the power transistor control method includes: calculating the expected lower limit value and the expected upper limit value based on the parasitic capacitance, input voltage, output voltage, and output current of the power transistors of the upper bridge arm and the lower bridge arm; setting the expected dead zone value based on at least the expected lower limit value and the expected upper limit value; maintaining the dead zone value or setting the expected dead zone value to the dead zone value; and controlling the on and off of the power transistors of the upper bridge arm and the lower bridge arm based on the dead zone value. With such a configuration, on the one hand, the dead zone value is continuously adjusted in a real-time calculation manner, thereby improving the adaptive ability of the solution; on the other hand, the expected dead zone value is calculated based on the expected lower limit value and the expected upper limit value, optimizing the dead zone update logic, making each dead zone iteration more reasonable. It solves the problems of inflexible setting of the dead zone and weak adaptive ability existing in the prior art. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Those of ordinary skill in the art will understand that the provided drawings are used to better understand the present invention and do not constitute any limitation to the scope of the present invention. Among them:

[0032] Figure 1 is a schematic structural diagram of a power supply circuit applied in an embodiment of the present invention;

[0033] Figure 2 is a schematic flowchart of a power transistor control method in an embodiment of the present invention;

[0034] Figure 3 is a waveform diagram of key signals in an embodiment of the present invention;

[0035] Figure 4 is another schematic flowchart of a power transistor control method in an embodiment of the present invention.

[0036] In the drawings:

[0037] 1-First power transistor; 2-Second power transistor; 3-Third power transistor; 4-Fourth power transistor. Detailed Implementation

[0038] To make the objectives, advantages, and features of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to facilitate and clarify the explanation of the embodiments of this invention. Furthermore, the structures shown in the drawings are often part of the actual structures. In particular, different figures may emphasize different aspects and may sometimes use different scales.

[0039] As used in this invention, the singular forms “a,” “an,” and “the” include plural objects; the term “or” is generally used to mean “and / or”; the term “a number” is generally used to mean “at least one”; and the term “at least two” is generally used to mean “two or more”. Furthermore, the terms “first,” “second,” and “third” are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as “first,” “second,” or “third” may explicitly or implicitly include one or at least two of that feature. “One end” and “the other end,” as well as “proximal end” and “distal end,” generally refer to two corresponding parts, including not only endpoints. The terms “installed,” “connected,” and “joined” should be interpreted broadly, for example, as a fixed connection, a detachable connection, or an integral part; a mechanical connection or an electrical connection; a direct connection or an indirect connection through an intermediate medium; or a connection within two elements or an interaction between two elements. Furthermore, as used in this invention, the phrase "one element is disposed on another element" generally only indicates that there is a connection, coupling, cooperation, or transmission relationship between the two elements, and the connection, coupling, cooperation, or transmission between the two elements can be direct or indirect through an intermediate element. It should not be construed as indicating or implying a spatial positional relationship between the two elements, i.e., one element can be located arbitrarily inside, outside, above, below, or to one side of the other element, unless otherwise explicitly stated. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0040] The core idea of ​​this invention is to provide a power transistor control method and controller to solve the problems of insufficient flexibility in setting the dead time and weak adaptive capability in the prior art.

[0041] The following description refers to the accompanying drawings.

[0042] This embodiment provides a method for controlling a power transistor, and the method for controlling the power transistor is applied to a power supply circuit. The power supply circuit includes at least one set of upper and lower bridge arms.

[0043] In one embodiment, the structure of the power supply circuit is as Figure 1 shown, where the power supply circuit includes a transformer T1, the excitation inductor Lm of the transformer, the primary series resonance inductor Lr of the transformer, an output inductor Lo, and two sets of the upper and lower bridge arms, specifically including a first power transistor 1, a second power transistor 2, a third power transistor 3, and a fourth power transistor 4. The output side of the power supply circuit further includes a fifth power transistor S5, a sixth power transistor S6, an output inductor Lo, and an output capacitor Co.

[0044] The method for controlling the power transistor includes the following steps:

[0045] S10 Obtain an initial safety dead zone Tc.

[0046] S20 Obtain a safety design deviation ΔT.

[0047] S30 Based on the parasitic capacitances (such as C1 to C4) of the power transistors of the upper and lower bridge arms, an input voltage Vin, an output voltage Vo, and an output current Io, calculate an expected lower limit value Δt min and an expected upper limit value Δt max .

[0048] S40 Select one of the initial safety dead zone Tc, the sum of the expected lower limit value and the safety design deviation (i.e., Δt min +ΔT), and the expected upper limit value Δt max as the expected dead zone value dt.

[0049] S50 If |DT - dt| < k, then maintain the dead zone value DT; otherwise, set the expected dead zone value dt as the dead zone value DT, where k represents an error threshold.

[0050] And, S60 Control the power transistors of the upper and lower bridge arms to turn on and off based on the dead zone value DT.

[0051] In the above scheme, step S40 can be summarized as: setting an expected dead zone value based at least on the expected lower limit value and the expected upper limit value. Step S50 can be summarized as: maintaining the dead zone value, or setting the expected dead zone value to the actual dead zone value. Therefore, this embodiment can also be summarized as follows: the power transistor control method includes: calculating the expected lower limit value and the expected upper limit value based on the parasitic capacitance, input voltage, output voltage, and output current of the power transistors of the upper and lower bridge arms; setting the expected dead zone value based at least on the expected lower limit value and the expected upper limit value; maintaining the dead zone value, or setting the expected dead zone value to the actual dead zone value; and controlling the switching on and off of the power transistors of the upper and lower bridge arms based on the dead zone value.

[0052] Specifically, the expected lower limit and the expected upper limit are calculated based on zero-voltage switching constraints.

[0053] Please refer to Figure 3 , Figure 3 The diagram shows waveforms of key signals according to an embodiment of the present invention. In this diagram, CS1 represents the control signal for the first power transistor 1, CS2 represents the control signal for the second power transistor 2, CS3 represents the control signal for the third power transistor 3, CS4 represents the control signal for the fourth power transistor 4, CS5 represents the control signal for the fifth power transistor S5, and CS6 represents the control signal for the sixth power transistor S6. ILo represents the current on the output inductor Lo, Io represents the average value of the output current (also ILo), ΔI represents the fluctuation range of ILo, and ILr represents the current on the resonant inductor Lr.

[0054] Figure 3 In this study, the two time periods T1 and T2 are combined and considered as a complete cycle. Within each half-cycle (T1 or T2), the order in which the power transistors are turned on differs, and this order is symmetrical. To ensure consistency in the final conclusions, the following conventions are adopted: In each half-cycle, the upper bridge arm that turns on first is designated as the first upper bridge arm, and the upper bridge arm that turns on later is designated as the second upper bridge arm. The lower bridge arm corresponding to the first upper bridge arm is designated as the first lower bridge arm, and the lower bridge arm corresponding to the second upper bridge arm is designated as the second lower bridge arm. The power transistor of the first upper bridge arm is designated as the first upper transistor S1, the power transistor of the first lower bridge arm is designated as the first lower transistor S2, the power transistor of the second upper bridge arm is designated as the second upper transistor S3, and the power transistor of the second lower bridge arm is designated as the second lower transistor S4.

[0055] In other words, during time period T1, the first power transistor 1 is the first upper transistor S1, the second power transistor 2 is the first lower transistor S2, the third power transistor 3 is the second upper transistor S3, and the fourth power transistor 4 is the second lower transistor S4. During time period T2, the first power transistor 1 is the second upper transistor S3, the second power transistor 2 is the second lower transistor S4, the third power transistor 3 is the first upper transistor S1, and the fourth power transistor 4 is the first lower transistor S2.

[0056] The following description is based solely on the operating logic of time period T1. The operating logic of time period T2 should be understood according to the transformation relationship described above.

[0057] Phase I [t0-t1]: At time t0, S1 and S4 on the primary side are turned on, and S5 on the secondary side is turned on and S6 is turned off. The input voltage Vin provides energy to the output side, causing the current ILo in the output inductor Lo on the secondary side to increase linearly. Similarly, the current ILr in the resonant inductor Lr on the primary side also increases linearly. At time t0, the current in the output inductor Lo satisfies formula (1). Ignoring the magnetizing current of Lm on the primary side of transformer T1, the current ILr in the resonant inductor Lr at time t0 satisfies formula (2), and the duration T from t0 to t1 is... 01 It satisfies formula (3).

[0058]

[0059]

[0060]

[0061] Where Ts represents the duration of one cycle, and Nt is the turns ratio of the transformer T1, Nt = n1:n2. ΔI satisfies formula (4).

[0062]

[0063] Stage II [t1-t2]: At time t1, S1 is turned off, and the current ILr on the resonant inductor Lr remains unchanged in direction. This current resonates with the equivalent capacitance on power devices S1 and S2. At time t2, if the voltage across S1 gradually increases to Vin, the voltage across S2 gradually decreases to 0. Therefore, turning on S2 at time t2 and slightly later will make S2 ​​be in a ZVS on-state. Assuming the time from t1 to t2 is set to Δt1, since Δt1 is very small, ILr(t2)≈ILr(t1). And ignoring the excitation current of Lm on the primary side of transformer T1, the current ILo on the output inductor Lo and the current ILr on the resonant inductor Lr at time t1 satisfy formulas (5) and (6), respectively.

[0064] Furthermore, based on the principle that the capacitor energy remains constant, the duration Δt1 of t2-t1 satisfies the following formula (7).

[0065]

[0066]

[0067]

[0068] Substituting formulas (4) and (6) into formula (7), we can obtain formula (8).

[0069]

[0070] Δt1 represents the minimum dead zone at which power devices S1 and S2 can achieve ZVS. Here, C1 represents the parasitic capacitance of the first upper transistor S1, and C2 represents the parasitic capacitance of the first lower transistor S2.

[0071] Phase III [t2-t3]: At time t2, S2 and S4 are turned on, and the secondary-side output inductor Lo freewheels through S5, so the current ILo decreases linearly. Assume the time from t2 to t3 is set to T. 23 Then, at time t3, the current ILr on the resonant inductor Lr satisfies formula (9), where, for the sake of simplifying the calculation, T 23 T can be approximated as 23 ≈Ts / 2-T 01 .

[0072]

[0073] Stage IIII [t3-t4]: At time t3, S4 is turned off, and the current ILr on the resonant inductor Lr resonates with the equivalent capacitance on the power devices S3 and S4. At time t4, if the voltage across S4 gradually increases to Vin, the voltage across S3 gradually decreases to 0. Therefore, turning on S3 at time t4 and shortly thereafter will put S3 in a ZVS on-state. Assuming the time from t3 to t4 is set to Δt2, similarly, since Δt2 is very small, ILr(t4)≈ILr(t3), and Δt2 satisfies the following formula (10).

[0074]

[0075] Wherein, C3 represents the parasitic capacitance of the second upper transistor S3, and C4 represents the parasitic capacitance of the second lower transistor S4.

[0076] Substituting formula (9) into formula (10), we get formula (11).

[0077]

[0078] Δt2 is the minimum dead zone in which power devices S3 and S4 can achieve ZVS.

[0079] Furthermore, when the current ILr on the resonant inductor Lr gradually crosses zero and becomes negative, if the power device S3 is not turned on at this time, the resonant current ILr charges the equivalent capacitance on the power device S3, thereby gradually increasing the voltage across the power device S3. Therefore, when the drive signal for the power device S3 is turned on when the resonant current ILr crosses zero and becomes negative, S3 loses its ZVS turn-on state. That is, the drive signal for the power device S3 must be turned on before the resonant current ILr crosses zero and becomes negative in order to achieve ZVS turn-on of the power device. This process satisfies formula (12).

[0080]

[0081] Substituting formula (9) into formula (12), we get formula (13).

[0082]

[0083] Δt3 is the maximum dead zone that power devices S3 and S4 can achieve in ZVS.

[0084] In summary, the dead zones of power devices S3 and S4 must simultaneously satisfy the interval (Δt2, Δt3) to ensure their operation in the ZVS on state, thereby effectively improving the efficiency of power supply products.

[0085] The above process analyzes the conditions for the second power transistor 2 and the third power transistor 3 to achieve ZVS turn-on. Similarly, the conditions for the first power transistor 1 and the fourth power transistor 4 to achieve ZVS turn-on in the second half cycle also need to satisfy formulas (8), (11), and (13), which will not be elaborated here.

[0086] Further analysis of formulas (8) and (11) reveals that the minimum dead zone Δt1 required for power devices S1 and S2 to achieve ZVS is less than the minimum dead zone Δt2 required for power devices S3 and S4 to achieve ZVS, i.e., Δt1 < Δt2. Therefore, power devices S1 and S2 are more likely to achieve ZVS turn-on compared to power devices S3 and S4. Thus, to maintain the overall design rationality and consistency of the maximum dead zone, the maximum dead zone of power devices S1 and S2 is also limited to the maximum dead zone Δt3 of power devices S3 and S4, meaning the dead zones of power devices S1 and S2 satisfy the interval (Δt1, Δt2). Furthermore, Δt1 and Δt2 are related to the parasitic capacitances connected in parallel across the power devices.

[0087] The above rules can also be summarized as follows:

[0088] The expected lower limit values ​​of the first upper tube and the first lower tube are calculated based on the following formula:

[0089]

[0090] Wherein, Δt1 represents the expected lower limit value of the first upper transistor and the first lower transistor, C1 represents the parasitic capacitance of the first upper transistor, C2 represents the parasitic capacitance of the first lower transistor, Vin represents the input voltage, Nt represents the coil turns ratio of the transformer, Io represents the average current of the output current, Ts represents the duration of one cycle, Vo represents the output voltage, and Lo represents the output inductance.

[0091] The expected lower limit values ​​of the second upper tube and the second lower tube are calculated based on the following formula:

[0092]

[0093] Wherein, Δt2 represents the expected lower limit value of the second upper tube and the second lower tube, C3 represents the parasitic capacitance of the second upper tube, and C4 represents the parasitic capacitance of the second lower tube.

[0094] The expected upper limit value is calculated based on the following formula:

[0095]

[0096] Where Δt3 represents the expected upper limit value, and Lr represents the resonant inductance on the primary side of the transformer.

[0097] To ensure that all power devices compatible with this model meet the design dead-time requirements, C1, C2, C3, and C4 in formulas (8) and (11) are replaced with the maximum parameters from the power device datasheet. That is, C1, C2, C3, and C4 are all taken as Cossmax, where Cossmax represents the maximum parameter of the power transistor's device specifications.

[0098] Then formulas (8) and (11) can be equivalent to formulas (14) and (15).

[0099]

[0100]

[0101] Further from formulas (13), (14), and (15), it can be seen that the times Δt1, Δt2, and Δt3 are all related to the input Vin, output Vo, and output load Io under different operating conditions. Therefore, the dead time required for power devices S1, S2, S3, and S4 to achieve ZVS turn-on can be designed according to the actual output Vin, output Vo, and output load Io. Moreover, the actual dead time DT1 of power devices S1 and S2 satisfies the interval (Δt1, Δt3), and the actual dead time DT2 of power devices S3 and S4 satisfies the interval (Δt1, Δt3). Therefore, according to the above design, not only can the minimum dead time size actually required under different operating conditions be guaranteed, thus ensuring the rationality of the dead time design of power devices, but the ZVS turn-on of power devices can also be further optimized, reducing unnecessary turn-on losses, thereby improving the efficiency of the power supply and the thermal performance of the power supply products.

[0102] Based on the calculated times Δt1 and Δt2, and considering a safety margin, the actual power supply product adds a safety design deviation ΔT. Therefore, the dead zones of the actual power devices S1 and S2 are Δt1 + ΔT, where Δt1 + ΔT < Δt3; the dead zones of S3 and S4 are Δt2 + ΔT, where Δt1 + ΔT < Δt3. This effectively prevents shoot-through in the upper and lower bridge arms, thereby improving the reliability of the power supply product. Furthermore, these dead zones are compared with the initial safety dead zone Tc to prevent special deviations under special circumstances.

[0103] Therefore, the step of setting the expected dead zone value based at least on the expected lower limit value and the expected upper limit value specifically involves setting the expected dead zone value based on the initial safe dead zone, the expected lower limit value, and the expected upper limit value.

[0104] Step S40, which involves selecting one of the following three values ​​as the expected dead zone value: the initial safety dead zone, the sum of the expected lower limit and the safety design deviation, and the expected upper limit, specifically includes: S41 comparing Tc and Δt. min +ΔT's magnitude, if Δt min +ΔT>Tc, then let dt=Δt min +ΔT, otherwise, let dt = Tc; S42 Compare dt and Δt max The size of dt, if dt < Δt max If dt remains unchanged, then dt remains unchanged; otherwise, let dt = Δt. max S43 uses dt as the expected dead zone value.

[0105] Where Tc represents the initial safe dead zone, Δt min ΔT represents the expected lower limit value, and ΔT represents the safety design deviation. max This represents the expected upper limit value. Δt min That is, Δt1 and Δt2, Δt maxThat is, Δt3.

[0106] Based on the above analysis, one embodiment of the power transistor control method is as follows: Figure 4 The workflow shown is as follows.

[0107] S101 gives the initial dead zone Tc. Step S101 corresponds to step S10.

[0108] S102 gives Cossmax. Step S102 is part of step S30, and in a particular embodiment, Cossmax is used instead of C1, C2, C3 and C4 for calculation.

[0109] S103 collects Vin voltage, output voltage Vo, and output current Io.

[0110] S104 calculates the dead zones Δt1, Δt2, and Δt3. Steps S103 and S104 correspond to step S30.

[0111] S105 Obtain the result Δt1 + ΔT > Tc. S106 If the result of S105 is Y, then let dt1 = Δt1 + ΔT. S107 If the result of S105 is N, then let dt1 = Tc. Here, dt1 is a parameter used to store the calculation process of the expected dead zone value, and is ultimately output as the expected dead zone value. dt1 is the expected dead zone value of the first upper tube S1 and the first lower tube S2.

[0112] S114 Obtain the result Δt2 + ΔT > Tc. S115 If the result of S1114 is Y, then let dt2 = Δt2 + ΔT. S116 If the result of S114 is N, then let dt2 = Tc. Here, dt2 is also a parameter used to store the expected dead zone value calculation process, and is ultimately output as the expected dead zone value. dt2 is the expected dead zone value of the second upper tube S3 and the second lower tube S4.

[0113] Steps S105–S107 and S114–S116 correspond to step S41, dt1 and dt2 correspond to dt in step S41, and Δt1 and Δt2 correspond to Δt in step S41. min .

[0114] S108 Obtain the result that dt1 < Δt3. S109 If the result of S108 is Y, then keep the value of dt1. S110 If the result of S108 is N, then let dt1 = Δt3.

[0115] S117 Obtain the result that dt2 < Δt3. S118 If the result of S117 is Y, then keep the value of dt2. S119 If the result of S117 is N, then let dt2 = Δt3.

[0116] Steps S108 - S110, S117 - S119 correspond to step S42.

[0117] Because in Figure 4 the flowchart, dt1 and dt2 actually serve as the expected dead zone values, so step S43 is implicitly executed.

[0118] S111 obtains the result of |DT1 - dt1| < k. If the result of S111 is Y, then DT1 remains unchanged. If the result of S111 is N, then DT1 becomes the calculated value dt1.

[0119] S120 obtains the result of |DT2 - dt1| < k. If the result of S120 is Y, then DT2 remains unchanged. If the result of S120 is N, then DT2 becomes the calculated value dt2.

[0120] Steps S111 - S113, S120 - S122 correspond to step S50.

[0121] In addition, in this embodiment, the secondary side of the power supply circuit is a full - wave rectifier circuit, but in other embodiments, it can also be a full - bridge rectifier circuit or a current - doubling rectifier circuit.

[0122] This embodiment also provides a controller, which is applied to a power supply circuit. The power supply circuit includes at least one set of upper bridge arm and lower bridge arm. The controller is used to execute the above - mentioned power transistor control method.

[0123] The controller can be a hardware - based or software - based controller. Specifically, it can be a circuit, a chip, an FPGA (Field Programmable Gate Array), an ASIC (Application Specific Integrated Circuit), a CPU (Central Processing Unit), a MCU (Micro Control Unit, micro - controller unit, single - chip microcomputer), a computer, etc.

[0124] In summary, the power transistor control method and controller provided in this embodiment include: calculating a lower and upper expected limit value based on the parasitic capacitance, input voltage, output voltage, and output current of the power transistors in the upper and lower bridge arms; setting an expected dead zone value based at least on the lower and upper expected limit values; maintaining the dead zone value, or setting the expected dead zone value as the dead zone value; and controlling the switching on and off of the power transistors in the upper and lower bridge arms based on the dead zone value. This configuration, on the one hand, continuously adjusts the dead zone value through real-time calculation, thereby improving the adaptive capability of the solution; on the other hand, calculating the expected dead zone value based on the lower and upper expected limit values ​​optimizes the dead zone update logic, making each dead zone iteration more reasonable. This solves the problems of insufficient flexibility in dead zone setting and weak adaptive capability in existing technologies.

[0125] The above description is only a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the present invention.

Claims

1. A power transistor control method, characterized in that, The power transistor control method is applied to a power supply circuit, the power supply circuit including at least one set of upper bridge arms and lower bridge arms, and the power transistor control method includes: Based on the parasitic capacitance, input voltage, output voltage, and output current of the power transistors of the upper and lower bridge arms, calculate the expected lower limit and expected upper limit. The expected dead zone value is set based at least on the expected lower limit value and the expected upper limit value; Set the expected dead zone value to the dead zone value; and, The power transistors of the upper and lower bridge arms are switched on and off based on the dead zone value. The power transistor control method includes: obtaining the initial safe dead zone; obtaining the safe design deviation; The step of setting the expected dead zone value based on the initial safe dead zone, the expected lower limit, and the expected upper limit specifically involves selecting one of the following three values ​​as the expected dead zone value: the initial safe dead zone, the sum of the expected lower limit and the safety design deviation, and the expected upper limit. Specifically, this includes: Compare Tc and Δt min +ΔT's magnitude, if Δt min +ΔT>Tc, then let dt=Δt min +ΔT, otherwise, let dt=Tc; Compare dt and Δt max The size of dt, if dt < Δt max If dt remains unchanged, then dt remains unchanged; otherwise, let dt = Δt. max ;as well as, dt is taken as the expected dead zone value; Where Tc represents the initial safe dead zone, Δt min ΔT represents the expected lower limit value, and ΔT represents the safety design deviation. max This represents the expected upper limit value.

2. The power transistor control method according to claim 1, characterized in that, The expected lower limit and the expected upper limit are calculated based on zero-voltage switching constraints.

3. The power transistor control method according to claim 1, characterized in that, The power supply circuit includes a transformer, an output inductor, and two sets of upper bridge arms and lower bridge arms. In each half-cycle, the upper bridge arm that is turned on first is designated as the first upper bridge arm, and the upper bridge arm that is turned on later is designated as the second upper bridge arm. The lower bridge arm corresponding to the first upper bridge arm is designated as the first lower bridge arm, and the lower bridge arm corresponding to the second upper bridge arm is designated as the second lower bridge arm. The power transistor of the first upper bridge arm is designated as the first upper transistor, the power transistor of the first lower bridge arm is designated as the first lower transistor, the power transistor of the second upper bridge arm is designated as the second upper transistor, and the power transistor of the second lower bridge arm is designated as the second lower transistor. The expected lower limit values ​​of the first upper tube and the first lower tube are calculated based on the following formula: ， Wherein, Δt1 represents the expected lower limit value of the first upper transistor and the first lower transistor, C1 represents the parasitic capacitance of the first upper transistor, C2 represents the parasitic capacitance of the first lower transistor, Vin represents the input voltage, Nt represents the coil turns ratio of the transformer, Io represents the average current of the output current, Ts represents the duration of one cycle, Vo represents the output voltage, and Lo represents the output inductance. The expected lower limit values ​​of the second upper tube and the second lower tube are calculated based on the following formula: ， Wherein, Δt2 represents the expected lower limit value of the second upper tube and the second lower tube, C3 represents the parasitic capacitance of the second upper tube, and C4 represents the parasitic capacitance of the second lower tube; The expected upper limit value is calculated based on the following formula: ， Where Δt3 represents the expected upper limit value, and Lr represents the resonant inductance on the primary side of the transformer.

4. The power transistor control method according to claim 3, characterized in that, C1, C2, C3, and C4 are all set to Cossmax, where Cossmax represents the maximum parameter of the power transistor's device specifications.

5. The power transistor control method according to claim 3, characterized in that, The secondary side of the power supply circuit is a full-wave rectified current, a full-bridge rectifier circuit, or a current-doubler rectifier circuit.

6. The power transistor control method according to claim 1, characterized in that, The step of setting the expected dead zone value to the dead zone value specifically includes: If |DT - dt| < k, then keep the dead zone value; otherwise, set the expected dead zone value to the dead zone value, where DT represents the dead zone value, dt represents the expected dead zone value, and k represents the error threshold.

7. A controller, characterized in that, The controller is applied to a power supply circuit, and the power supply circuit includes at least one set of upper and lower bridge arms. The controller is configured to execute the power transistor control method according to any one of claims 1 to 6.

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