Charge pump circuits and electronic devices

Abstract

A charge pump circuit and electronic device are disclosed. The charge pump circuit includes: a charge pump main circuit; a feedback branch providing a feedback voltage proportional to the output voltage of the main circuit; a dynamic comparator for comparing the feedback voltage and a reference voltage when an enable signal is valid, outputting a comparison result, and outputting a reset signal when the enable signal is invalid, wherein the main circuit receives a signal at its first output terminal as a clock signal; and an enable signal generation circuit for taking the comparator output as an input, and outputting an invalid enable signal in response to receiving the comparison result, and outputting an valid enable signal in response to receiving the reset signal. This invention utilizes the characteristic of the dynamic comparator to compare only during the valid time of the enable signal, and combines it with a delay circuit to achieve mutual triggering of the comparison and reset of the dynamic comparator, thereby directly controlling the operation of the charge pump main part through the output of the dynamic comparator, eliminating the need for an oscillator.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuits, and more particularly to a charge pump voltage regulation and modulation circuit, an on-chip high voltage generation circuit, and an electronic device. Background Technology

[0002] Charge pumps, as on-chip high-voltage generators, are widely used in memories such as DRAM, NAND flash memory, NOR flash memory, and phase-change memory. Structurally, charge pump circuits can be classified into Dickson type, Double type, and four-phase clock type, etc. Depending on the specific requirements, charge pump circuits and their voltage regulation and modulation systems can adopt different connection methods to generate positive or negative high voltages. However, regardless of whether positive or negative high voltage is generated, the traditional charge pump voltage regulation and modulation system can be mainly summarized into the following modules:

[0003] 1. The main body of the charge pump, usually a Dickson type, Double type, or four-phase clock type, etc., functions to transport charge under clock control;

[0004] 2. The load feedback branch, acting as a load of the charge pump, generates a voltage that can be input to the comparator through the voltage divider principle;

[0005] 3. A voltage comparator or error amplifier controls the oscillation of the oscillator by comparing the magnitude of the feedback voltage and the reference voltage;

[0006] 4. Oscillator, which can be a ring oscillator or a voltage-controlled oscillator, is used to generate the clock required for the main body of the charge pump to operate.

[0007] Typically, when the feedback voltage is lower than the reference voltage, the oscillator will continue to operate at the comparator output voltage, thereby providing the clock voltage for the charge pump. However, the circuit combination of the comparator or error amplifier and the oscillator generates significant power consumption and occupies a large area on the chip during charge pump operation.

[0008] Therefore, a new charge pump voltage regulation circuit scheme is needed that can reduce power consumption and save area. Summary of the Invention

[0009] One technical problem this disclosure aims to solve is to provide a novel charge pump circuit. By introducing a dynamic comparator and utilizing its characteristic that comparisons are only performed during the effective time of the enable signal, combined with an enable signal generation circuit that uses the comparator output as input, the comparison and reset of the dynamic comparator are mutually triggered. This allows the operation of the main body of the charge pump to be directly controlled through the output of the dynamic comparator, eliminating the need for an oscillator circuit and significantly saving system power consumption and area.

[0010] According to a first aspect of this disclosure, a charge pump circuit is provided, comprising: a charge pump main circuit; a feedback branch providing a feedback voltage proportional to the output voltage of the charge pump main circuit; a dynamic comparator for comparing the feedback voltage and a reference voltage when an enable signal received at an enable terminal is valid, outputting a comparison result at a first output terminal and a second output terminal, and outputting a reset signal at the first output terminal and the second output terminal when the enable signal is invalid, wherein the charge pump main circuit receives a signal at the first output terminal as a clock signal; and an enable signal generation circuit for connecting the first output terminal and the second output terminal as inputs, wherein in response to receiving the comparison result from the first output terminal and the second output terminal, the enable signal circuit outputs an enable signal having an invalid level, and in response to receiving a reset signal from the first output terminal and the second output terminal, the enable signal circuit outputs an enable signal having an valid level.

[0011] Optionally, the enable signal generation circuit includes a delay circuit for causing the enable signal generation circuit to output a delayed enable signal in response to receiving signals from the first output terminal and the second output terminal.

[0012] Optionally, the delay coefficient of the delay circuit is used to determine the frequency of the enable signal.

[0013] Optionally, the enable signal generation circuit includes an input decision gate, which connects the first output terminal and the second output terminal as inputs, and outputs an enable invalid level when different levels are input to the first output terminal and the second output terminal, and outputs an enable valid level when the same reset level is input to the first output terminal and the second output terminal.

[0014] Optionally, the enable signal generating circuit further includes a gating control terminal, which receives a gating signal and, in response to the gating signal being valid, outputs an enable signal with a valid level.

[0015] Optionally, the enable signal generation circuit further includes a signal control gate, configured to acquire the output of the input decision gate as an input and the strobe signal as another input, and the signal control gate is configured to: output the enable signal with an invalid level in response to the strobe signal being invalid; output the enable signal with an valid level in response to the strobe signal being valid and the input decision gate outputting the enable valid level; and output the enable signal with an invalid level in response to the strobe signal being valid and the input decision gate outputting the enable invalid level.

[0016] Optionally, the dynamic comparator includes a dual differential dynamic comparator, wherein the feedback voltage and the reference voltage serve as symmetrical inputs to a pair of current mirrors, and the enable terminal serves as a symmetrical input to another pair of current mirrors.

[0017] According to a second aspect of this disclosure, an electronic device is provided, comprising: a charge pump circuit as described in the first aspect above.

[0018] Optionally, the electronic device is a memory device.

[0019] Therefore, the charge pump circuit of the present invention utilizes the characteristic of a dynamic comparator that outputs two different comparison results when the enable signal is valid and two identical reset levels when the enable signal is invalid. It directly obtains the output of the dynamic comparator as the enable signal generation circuit, and with the participation of a delay circuit, it can use the output of the dynamic comparator itself to generate the enable signal for controlling the operation of the comparator. Thus, the output of the comparator can be directly used as the clock of the charge pump, thereby avoiding the need for an oscillation circuit in the prior art. Attached Figure Description

[0020] The above and other objects, features and advantages of this disclosure will become more apparent from the more detailed description of exemplary embodiments thereof taken in conjunction with the accompanying drawings, wherein like reference numerals generally denote like parts.

[0021] Figure 1A -B shows an example of a charge pump circuit.

[0022] Figure 2 A schematic diagram of a charge pump circuit according to an embodiment of the present invention is shown.

[0023] Figure 3 It shows Figure 2 The timing diagram of the charge pump voltage regulation and modulation circuit is shown.

[0024] Figure 4 An example of a delay module is shown.

[0025] Figure 5 A schematic diagram of a charge pump circuit according to an embodiment of the present invention is shown.

[0026] Figure 6 It shows Figure 5 The timing diagram of the charge pump voltage regulation and modulation circuit is shown.

[0027] Figure 7 A schematic diagram of a charge pump circuit according to an embodiment of the present invention is shown.

[0028] Figure 8 shows Figure 7 the working timing diagram of the shown charge pump voltage regulation modulation circuit.

[0029] Figure 9 shows the schematic composition diagram of a charge pump circuit according to an embodiment of the present invention.

[0030] Figure 10 shows Figure 9 the working timing diagram of the shown charge pump voltage regulation modulation circuit.

[0031] Figure 11A -B shows different implementations of the dynamic comparator. Detailed implementation manners

[0032] The preferred embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the preferred embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure will be more thorough and complete, and can fully convey the scope of the present disclosure to those skilled in the art.

[0033] A voltage comparator or an error amplifier and an oscillator can be regarded as a voltage regulation modulation system of the charge pump. Figure 1A -B shows an example of a charge pump circuit. The figure includes examples of two common voltage regulation modulation circuits in the charge pump circuit.

[0034] Figure 1A shows the SKIP voltage regulation mode of the charge pump. In addition to the charge pump main circuit 110 and the load feedback branch 120 in the figure, it also includes a voltage comparator 130 and an oscillator 140. Taking the output of positive high voltage as an example, the comparator 130 compares the voltage Vreg obtained by the voltage dividing circuit with the input reference voltage Vref, and outputs a judgment voltage of high level or low level. When Vreg < Vref, the oscillator 140 continuously operates under the action of the output voltage of the comparator, thereby generating a continuously inverted clock voltage to enable the charge pump to continuously carry out charge transfer; when Vreg > Vref, the output voltage of the comparator makes the oscillator stop working, and the charge pump stops charge transfer until the output voltage decreases again to make Vreg < Vref, thereby realizing the voltage regulation of the charge pump output.

[0035] Figure 1B shows the VFM voltage regulation mode of the charge pump. In addition to the charge pump main circuit 110' and the load feedback branch 120' in the figure, it also includes an error amplifier 130' and a voltage-controlled oscillator 140'. Taking the output of positive high voltage as an example. Similar to Figure 1AThe difference lies in the fact that this scheme uses an error amplifier to amplify the difference between the Vreg voltage and the Vref input reference voltage to control the oscillation frequency of the voltage-controlled oscillator, thereby controlling the charge transport speed of the charge pump and achieving voltage regulation of the charge pump output.

[0036] Given that the circuit combination of comparators or error amplifiers and oscillators commonly used in charge pump voltage regulation and modulation systems generates significant power consumption and occupies a large area on the chip during charge pump operation, this invention proposes a novel charge pump voltage regulation and modulation circuit. By introducing a dynamic comparator, which utilizes the characteristic of comparing only during the effective time of the enable signal, and combining it with an enable signal generation circuit that uses the comparator output as input, the dynamic comparator achieves periodic self-comparison and mutual triggering of reset based on the feedback of its own output signal. This allows the operation of the main part of the charge pump to be directly controlled through the output of the dynamic comparator, eliminating the need for an oscillator circuit and greatly saving system power consumption and area.

[0037] Specifically, this invention utilizes a dynamic comparator and an enable signal generation circuit to form a charge pump voltage regulation modulation circuit. The dynamic comparator compares the feedback voltage and the reference voltage when the enable signal received at the enable terminal is valid, outputting the comparison result at a first output terminal and a second output terminal. When the enable signal is invalid, it outputs a reset signal at both the first and second output terminals. Correspondingly, the enable signal generation circuit connects the first and second output terminals as inputs. In response to receiving the comparison result from the first and second output terminals, the enable signal circuit outputs an enable signal with an invalid level. In response to receiving a reset signal from the first and second output terminals, the enable signal circuit outputs an enable signal with an valid level. Thus, by enabling the dynamic comparator to perform periodic comparisons and resets based on feedback from its own output signal through the enable signal generation circuit, the signal at the first output terminal of the dynamic comparator can be used as a clock signal directly received by the main charge pump circuit.

[0038] To control the frequency of the clock signal, the enable signal generation circuit may include a delay circuit, which causes the enable signal generation circuit to output a delayed enable signal in response to receiving signals from the first output terminal and the second output terminal. The delay coefficient of the delay circuit can be used to determine the frequency of the enable signal.

[0039] In order to distinguish the outputs of the comparator, the enable signal generation circuit may include an input decision gate, which connects the first output terminal and the second output terminal as inputs, and outputs an enable invalid level when different levels are input to the first output terminal and the second output terminal, and outputs an enable valid level when the same reset level is input to the first output terminal and the second output terminal.

[0040] Furthermore, an additional gating control (RS) terminal can be added to control the startup of the circuit. For this purpose, the enable signal generation circuit also includes a gating control terminal that receives a gating signal and, in response to the gating signal being valid, the enable signal generation circuit outputs an enable signal with a valid level.

[0041] The strobe signal can be controlled by a signal control gate. Therefore, the enable signal generation circuit further includes a signal control gate, configured to take the output of the input decision gate as one input and the strobe signal as another input, and the signal control gate is configured to: output the enable signal with an invalid level in response to the strobe signal being invalid; output the enable signal with an valid level in response to the strobe signal being valid and the input decision gate outputting the enable valid level; and output the enable signal with an invalid level in response to the strobe signal being valid and the input decision gate outputting the enable invalid level.

[0042] Here, "enable invalid level" can be interpreted as the level of the enable signal that causes the enable signal generation circuit to generate an invalid level; "enable valid level" can be interpreted as the level of the enable signal that causes the enable signal generation circuit to generate a valid level. This is because when using RS signal for gating control, the level of this signal may be opposite to the actual enable level, so it is necessary to distinguish them in terms of terminology.

[0043] The following will combine Figure 2-10 The composition and working principle of the charge pump circuit of the present invention, especially the charge pump modulation voltage regulator circuit, are explained.

[0044] Figure 2 A schematic diagram of a charge pump circuit according to an embodiment of the present invention is shown. For ease of understanding, in addition to the improved charge pump voltage regulation and modulation circuit of the present invention, the charge pump body 210 and the feedback branch 220 for generating the feedback voltage are also shown in the figure.

[0045] Figure 2The charge pump voltage regulation and modulation circuit shown includes a dynamic comparator 230 and an enable signal generation circuit 240. Here, due to the continuous comparison and reset process controlled by the enable signal of the dynamic comparator 230, and because the two output terminals output different levels when generating the comparison result, but output the same reset level during reset, the enable signal generation circuit 230 can obtain the outputs of the two output terminals of the dynamic comparator 230 and utilize logic gate circuits (corresponding to "input decision gates") to... Figure 2 The NAND gate 242 in the dynamic comparator 230 acquires a signal with different levels during comparison and reset (for example, in response to a high level and a low level input to the two inputs during comparison, an enable / invalid level corresponding to the enable signal invalid level is generated; in response to a reset, two reset high levels input to the two inputs are generated, an enable / invalid level corresponding to the enable signal valid level is generated), and delays it using the delay module 241. The delayed signal X is then fed into the enable terminal of the dynamic comparator 230, thereby enabling the dynamic comparator 230 to complete the continuous triggering of comparison and reset with the assistance of the circuit 240. This allows one output of the dynamic comparator to be directly used as the output of the charge pump main circuit 210, thereby avoiding the need for a space-consuming and power-intensive oscillator circuit.

[0046] like Figure 2 As shown, the dynamic comparator 230 includes a first input terminal with a divided voltage Vreg (which can also be considered as the feedback voltage from the feedback branch 120) as input, a second input terminal with a reference voltage Vref as output, an enable terminal for receiving an enable signal EN, and a first output terminal OUTP and a second output terminal OUTN. In the illustrated example, the output of the first output terminal OUTP of the dynamic comparator 230 is used as the clock of the charge pump main circuit 210. The charge pump main circuit 210 typically uses one or more pairs of clocks. A non-overlapping clock generation circuit receives the output signal of the first output terminal OUTP of the dynamic comparator 230 and generates the clock required by the charge pump main circuit 210.

[0047] The enable signal generation circuit 240 directly uses the two outputs OUTP and OUTN of the dynamic comparator as inputs and outputs a signal EN to feed back to the dynamic comparator 230 as the input to the clock control terminal. Here, for distinction, the two input terminals of the enable signal generation circuit 240 can be referred to as the third input terminal and the fourth input terminal, and the output terminal of the enable signal generation circuit 240 can be referred to as the third output terminal.

[0048] It should be understood that the use of "first," "second," "third," and "fourth" here is solely for distinguishing different objects of the same type within the context, and not for implying their importance or order. For example, the "first input" and "second input" of the dynamic comparator 230 can each correspond to Vreg and Vref, or vice versa. Similarly, the "third input" and "fourth input" of the enable signal generation circuit 240 do not refer to the third and fourth inputs of the enable signal generation circuit 240, but rather to the first and second inputs. However, for ease of description and to distinguish them from the inputs of the dynamic comparator 230, they are referred to here as the "third input" and "fourth input." The output of the enable signal generation circuit 240 is called the "third output" for a similar reason.

[0049] Specifically, the first and second input terminals of the dynamic comparator 230 receive the feedback voltage Vreg and the reference voltage Vref, respectively. The first and second output terminals of the dynamic comparator are connected to the third and fourth input terminals of the enable signal generation circuit 230, respectively, i.e., OUTP and OUTN are directly input to the enable signal generation circuit 230 as inputs.

[0050] As mentioned earlier, when the enable signal EN is active, the dynamic comparator 230 performs a comparison. Regardless of whether Vreg > Vref or Vreg < Vref, OUTP and OUTN will inevitably have one high level and the other low level. At this time, the NAND gate 242 outputs a high level (the output will be 1 regardless of whether the input is 01 or 10). After a delay, this high level can be reversed (without considering RS, it can be simply converted into a low-level invalid enable signal EN) through a NOT gate. This invalid enable signal EN resets the dynamic comparator 230. Since the reset voltage of the dynamic comparator 230 is high in this example, OUTP and OUTN will both be high. At this time, the NAND gate 242 outputs a low level (the output is 0 regardless of whether the input is 11). After a delay, this low level can be reversed (without considering RS, it can be simply converted into a high-level active enable signal EN) through a NOT gate. This achieves a cycle where EN being active triggers the comparator to compare, the comparator compares and deactivates EN, deactivating EN resets the comparator, and the comparator resets and then active EN again. Because the comparator's comparison and reset are mutually triggered, the enable signal EN can form a continuous up-and-down clock.

[0051] Here, since the reset level is high, a NAND gate 242 is used as the input decision gate (i.e., the outputs of inputs 01 and 10 must be opposite to the output of input 11). And in the following combination... Figure 5-6 and Figure 9-10 In the example described, since the reset level is low, the input decision gate is a NOR gate (i.e., the output of inputs 01 and 10 is the opposite of the output of input 00).

[0052] Additionally, it should be understood that the delay module can be located in Figure 2 The NAND gate 242 shown can also be located in other positions, for example, two delay modules can be connected to OUTP and OUTN respectively, the delay module can be located after logic gate 243, etc.

[0053] In one embodiment, the enable signal generation circuit 240 further includes a gating control terminal. The RS signal on this gating control terminal can activate the circuit. When the RS signal is valid, the comparator 230 can perform comparisons and reset based on the validity or invalidity of the enable signal. Specifically, the enable signal generation circuit 230 also includes a second gate circuit 243 for enabling the circuit to start under the RS signal. Figure 2 In this example, the NOR gate is 243. This is because the enable invalid level (corresponding to 1 when input is 01) output by the input decision gate 242 is high, and the enable valid level (corresponding to 0 when input is 11) is low. In this example, the enable signal EN is valid when high and invalid when low, and the RS signal is low-level strobe. Therefore, in response to the strobe signal being invalid, the enable signal with an invalid level is output; in response to the strobe signal being valid, and the input decision gate outputs the enable valid level, the enable signal with a valid level is output; and in response to the strobe signal being valid, and the input decision gate outputs the enable invalid level, the enable signal with an invalid level is output, the signal control gate is selected as NOR gate 243.

[0054] Figure 3 It shows Figure 2 The timing diagram of the charge pump voltage regulation and modulation circuit shown is illustrated below. The following will combine... Figure 3 describe Figure 2 The operation of the charge pump voltage regulation and modulation circuit shown is illustrated. It is implemented based on the dynamic comparator 230 circuit (see attached diagram for reference). Figure 11A), which enables the dynamic comparator 230 to perform level comparison when EN is at a high level and reset the dynamic comparator when EN is at a low level. During reset, both the differential output terminals OUTP and OUTN of the dynamic comparator are at a high level. Therefore, when the charge pump circuit needs to start working, make RS go low (i.e., the strobe signal becomes valid). Since the initial value of X is low, the output of the NOR gate 243 becomes high, and EN jumps to a high level. Thus, the dynamic comparator performs level comparison when EN is at a high level. During the level comparison process, when Vreg < Vref, a low level will be generated at the output terminal OUTP of the dynamic comparator, and the OUTN terminal will remain at a high level. Since the dynamic comparator requires a certain time to start up, there is a certain delay between the first rising edge of EN and the first falling edge of the corresponding OUTP as shown in the figure (this delay is not the delay caused by the delay circuit).

[0055] The low level of OUTP generates a high level through the NAND gate 242 (since the OUTN terminal remains at a high level). The above high level is delayed by the delay module 242 to generate a delayed high level X. Since RS remains at a low level, the high level X causes EN to jump to a low level via the NOR gate 243, thereby resetting the dynamic comparator 230. The reset operation of the dynamic comparator 230 pulls OUTP back to a high level and pulls EN back to a high level again through the delay module 241. Thus, it can be seen that the periodic comparison and reset operations of the dynamic comparator 230 will continuously cause EN to jump between high and low levels, and enable the dynamic comparator to continuously perform comparison and reset. As long as Vreg < Vref, the output terminal OUTP of the dynamic comparator can continuously generate a clock signal that can be used for the charge pump main body, thereby avoiding an additional clock generation circuit, i.e., an oscillator, and reducing the power consumption and area of the system. As mentioned above, the charge pump is controlled to start working using the RS terminal. The RS signal is initially at a high level, and when RS jumps to a low level, the low level of X immediately pulls EN to a high level, and the comparator starts working, and the charge pump voltage regulation modulation system enters the normal working state.

[0056] When Vreg < Vref, the transition of signal X is delayed compared to the transition of OUTP ( Figure 3 the "Delay" in). The above delay is caused by the delay module. Compared with the delay between the transition of EN and the transition of OUTP in the figure (caused by the startup of the dynamic comparator), the delay caused by the delay module is controllable. In other words, the frequency of the enable signal is determined by the sum of the startup delay of the dynamic comparator and the delay of the delay module. Since the startup delay of the dynamic comparator is uncontrollable, the delay coefficient of the delay module 241 can be used to determine the frequency of EN, that is, the duration of each high level and low level.

[0057] Figure 4 An example of a delay module is shown in the figure. The delay module can be an RC delay circuit, and the delay coefficient can be determined based on the product of the resistor R and the capacitor C. Its input terminal V in The acquired input can be delayed by RC to obtain a fixed-delay output V. out When implementing on the board, a transmission transistor can be used instead of the resistor R.

[0058] Therefore, combined Figure 2 and Figure 3 As can be seen, the charge pump voltage regulation system of the present invention combines a dynamic comparator with a delayed enable signal generation circuit, so that the comparison and reset of the dynamic comparator are mutually triggered, avoiding the clock input required by the dynamic comparator and reducing the power consumption of the system. Furthermore, since the output of the dynamic comparator can be directly used as the input of the charge pump body, there is no need for an oscillator circuit, thereby further reducing the power consumption and area of ​​the charge pump voltage regulation system.

[0059] Figure 2 and Figure 3 The diagram illustrates an implementation where, when a charge pump circuit generates a positive high voltage VPPI, a dynamic comparator is triggered on the rising edge of the control clock, and when the feedback voltage Vreg is less than the reference voltage Vref, it outputs a continuously toggling clock voltage at the first output terminal OUTP.

[0060] Figure 5 and Figure 6 Another scheme for charge pump voltage regulation modulation for generating positive high voltage VPPI in a charge pump circuit is shown. Figure 5 A schematic diagram of a charge pump circuit according to an embodiment of the present invention is shown. Figure 6 It shows Figure 5 The timing diagram of the charge pump voltage regulation and modulation circuit is shown.

[0061] Figure 5 The charge pump voltage regulation and modulation circuit shown includes a dynamic comparator 530 and an enable signal generation circuit 540. For ease of understanding, Figure 5 Also shown is the charge pump body 510 and the load feedback branch 520 for generating the load voltage. Here, the circuit implementation of the dynamic comparator 530 is described (see attached diagram below). Figure 11B), it enables the dynamic comparator 530 to perform level comparison when EN is at a high level, and reset the dynamic comparator when EN is at a low level. The difference is that when resetting, both the differential output terminals OUTP and OUTN of the dynamic comparator are at a low level. For this reason, since different levels are required for inputs of 01 and 10 and when the input is 00, the input determination gate 542 is a NOR gate. During the level comparison process, when Vreg < Vref, a high level will be generated at the output terminal OUTP of the dynamic comparator, and the OUTN terminal will remain at a low level unchanged (when Vreg > Vref, the outputs of the OUTP and OUTN terminals will be inverted). A high level and a low level pass through the NOR gate 542 to generate a low level, and after being delayed by the delay module 542, a delayed low level is generated. Since RS is effective when it is at a low level and EN is ineffective when it is at a low level, in order to make this delayed low level generate an ineffective enable signal, an additional inverter, that is, the NOT gate 544, is required to invert the delayed signal to obtain the high level X. Since RS remains at a low level, the high level X causes EN to jump to an ineffective low level via the NOR gate 543, thereby resetting the dynamic comparator 230. The reset operation of the dynamic comparator 230 pulls OUTP to a low level again, and EN is pulled to a high level again through the delay module 241. Thus, the comparison and reset operations of the dynamic comparator 230 will also continuously cause EN to jump between high and low levels, and enable the dynamic comparator to continuously perform comparison and reset. Thus, whether Vreg < Vref or Vreg > Vref, the dynamic comparator will alternately perform comparison and reset under the control of EN, and as long as Vreg < Vref, the output terminal OUTP of the dynamic comparator can continuously generate a clock signal that can be used for the charge pump main body.

[0062] Figure 2 and Figure 3 and Figure 5 and Figure 6 Shows two implementations where when the charge pump circuit generates a positive high voltage VPPI, the dynamic comparator compares when the enable signal is at a high level, and when the feedback voltage Vreg is less than the reference voltage Vref, a continuously inverted clock voltage is output on the first output terminal OUTP.

[0063] The charge pump voltage regulation modulation scheme of the present invention is also applicable to the case where the charge pump circuit generates a negative high voltage VNEG. When generating the negative high voltage VNEG, the comparator compares the feedback voltage Vreg with the grounded reference voltage (Vref, which can also be expressed as V GND ), and when Vreg > V GND continuously outputs the clock voltage to the charge pump main circuit.

[0064] Figure 7 and Figure 8 A scheme for charge pump voltage regulation modulation for generating negative high voltage VNEG in a charge pump circuit is shown. Figure 7 A schematic diagram of a charge pump circuit according to an embodiment of the present invention is shown. Figure 8 It shows Figure 7 The timing diagram of the charge pump voltage regulation and modulation circuit is shown.

[0065] Figure 7 The charge pump voltage regulation modulation circuit shown includes a dynamic comparator 730 and an enable signal generation circuit 740. For ease of understanding, Figure 7 The charge pump body 710 and the load feedback branch 720 for generating the load voltage are also shown. Here, according to the circuit implementation of the dynamic comparator 730, the dynamic comparator 730 can perform level comparison when EN is low and reset when EN is high. Upon reset, the differential outputs OUTP and OUTN of the dynamic comparator are both high. Therefore, when RS goes high (i.e., when the strobe signal becomes active), since X is initially high, the output of the NOR gate 743 goes low, EN jumps low, and the dynamic comparator then performs level comparison when EN is low.

[0066] Since the required inputs are 01 and 10, and the output level differs when the input is 11, the input decision gate 742 is a NAND gate. During the level comparison process, when Vreg > V... GND When the dynamic comparator output OUTP is low, the OUTN output remains high (Vreg < V). GND (At this time, the outputs of OUTP and OUTN will be inverted). A high level and a low level are passed through NAND gate 742 to generate a high level. This high level is then delayed by delay module 741 to generate a delayed high level. Since RS is active when it is high and EN is inactive when it is high, in order for this delayed high level to generate an inactive enable signal, an additional inverter is needed, i.e., NOT gate 744 toggles the delayed signal, thus obtaining a low level X. Since RS remains high, the low level X causes EN to jump to high level via NAND gate 743, thereby resetting dynamic comparator 730. The reset operation of dynamic comparator 730 pulls OUTP high again, and then pulls EN low again via delay module 241. Thus, the comparison and reset operations of dynamic comparator 730 will continuously cause EN to switch between high and low levels, enabling the dynamic comparator to continuously compare and reset. Therefore, regardless of Vreg > V GND Or is Vreg < V GND During this time, the dynamic comparator will take turns comparing and resetting under the control of EN, and as long as Vreg > VGND The output terminal OUTP of the dynamic comparator can continuously generate a clock signal that can be used for the charge pump body.

[0067] Figure 9 and Figure 10 A scheme for charge pump voltage regulation modulation for generating negative high voltage VNEG in a charge pump circuit is shown. Figure 9 A schematic diagram of a charge pump circuit according to an embodiment of the present invention is shown. Figure 10 It shows Figure 9 The timing diagram of the charge pump voltage regulation and modulation circuit is shown.

[0068] Figure 9 The charge pump voltage regulation and modulation circuit shown includes a dynamic comparator 930 and an enable signal generation circuit 940. For ease of understanding, Figure 9 The charge pump body 910 and the load feedback branch 920 for generating the load voltage are also shown. Here, according to the circuit implementation of the dynamic comparator 930, the dynamic comparator 930 can perform level comparison when EN is low and reset when EN is high. Unlike the previous scheme, during reset, the differential outputs OUTP and OUTN of the dynamic comparator are both low. Therefore, when RS goes high (i.e., when the strobe signal becomes active), since X is initially high, the output of the NAND gate 243 goes low, EN jumps low, and the dynamic comparator then performs the comparison when EN is low.

[0069] Since the required inputs are 01 and 10, and the output level differs when the input is 00, the input decision gate 942 is a NOR gate. During the level comparison process, when Vreg > V... GND When the dynamic comparator output OUTP is high, the OUTN output remains low (Vreg < V). GND (At this time, the outputs of OUTP and OUTN will be inverted). A high level and a low level are passed through NOR gate 942 to generate a low level. This low level is then delayed by delay module 941 to generate a delayed low level X. Since RS remains high, the low level X causes EN to jump to high level via NAND gate 943, thereby resetting dynamic comparator 930. The reset operation of dynamic comparator 930 pulls OUTP low again, and then pulls EN low again via delay module 241. Thus, the comparison and reset operations of dynamic comparator 930 will continuously cause EN to switch between high and low levels, enabling the dynamic comparator to continuously compare and reset. Therefore, regardless of Vreg > V GND Or is Vreg < V GNDDuring this time, the dynamic comparators will take turns comparing and resetting under the control of EN, as long as Vreg > V GND The output terminal OUTP of the dynamic comparator can continuously generate a clock signal that can be used for the charge pump body.

[0070] thus, Figure 2 and Figure 3 Option 1 and Figure 5 and Figure 6 For the case where the charge pump outputs a positive high voltage, the dynamic comparator uses rising edge triggering. In Scheme 1, the differential outputs of the dynamic comparator in the reset state are all high level, while in Scheme 2, the differential outputs of the dynamic comparator in the reset state are all low level. Figure 7 and Figure 8 Option 3 and Figure 9 and Figure 10 Scheme 4 is designed for the case where the charge pump outputs a negative high voltage. The dynamic comparator is triggered by a falling edge. In Scheme 3, the differential outputs of the dynamic comparator in the reset state are all high level, while in Scheme 4, the differential outputs of the dynamic comparator in the reset state are all low level.

[0071] In one embodiment, the dynamic comparator is a dual differential dynamic comparator, wherein the feedback voltage and the reference voltage serve as symmetrical inputs to a pair of current mirrors, and the clock control terminal serves as a symmetrical input to another pair of current mirrors. Figure 11A -B indicates different implementations of the dynamic comparator. Specifically, Figure 11A Corresponding to Figure 2 A dynamic comparator is used to receive inputs (Vreg and Vref) that are both positive, to compare when EN is positive, and to make OUTP and OUTN both positive upon reset. Figure 11B Corresponding to Figure 7 A dynamic comparator is used to receive inputs that are not positive (the voltage divider Vreg and V of the negative high voltage). GND This is used for comparison when EN is negative, and makes OUTP and OUTN both positive during reset.

[0072] It should be understood that in other embodiments, Vref can be connected to the first input of the dynamic comparator, Vreg to the second output, and OUTN can be used as the clock voltage input for the charge pump body. These transformations can be implemented through different combinations of gate circuits, and all are within the scope of this invention.

[0073] In one embodiment, the invention can also be implemented as an electronic device including the high-voltage generation circuit described above. The electronic device may be a memory device, particularly a NAND or NOR flash memory chip.

[0074] Therefore, this invention ensures the continuous operation of the dynamic comparator by using a dynamic comparator and the mutual triggering of the comparison and reset processes of the dynamic comparator. Compared with non-dynamic comparators or dynamic comparators triggered by an external clock, this further reduces system power consumption. Furthermore, this charge pump voltage regulator system avoids the use of an oscillator, significantly reducing the power consumption and area of ​​the charge pump voltage regulator system.

[0075] The various embodiments of the present invention have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or improvement of the technology in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A charge pump circuit, comprising: Charge pump main circuit; The feedback branch provides a feedback voltage proportional to the output voltage of the charge pump main circuit; A dynamic comparator is used to compare the feedback voltage and the reference voltage when the enable signal received at the enable terminal is valid, and output the comparison result at the first output terminal and the second output terminal. When the enable signal is invalid, a reset signal is output at the first output terminal and the second output terminal. The charge pump main circuit receives the signal at the first output terminal as a clock signal. as well as An enable signal generating circuit is used to connect the first output terminal and the second output terminal as inputs. In response to receiving the comparison result from the first output terminal and the second output terminal, the enable signal circuit outputs the enable signal with an invalid level. In response to receiving a reset signal from the first output terminal and the second output terminal, the enable signal circuit outputs the enable signal with an active level.

2. The charge pump circuit as described in claim 1, wherein, The enable signal generation circuit includes a delay circuit, which is used to enable the signal generation circuit to output a delayed enable signal in response to receiving signals from the first output terminal and the second output terminal.

3. The charge pump circuit as described in claim 2, wherein, The delay coefficient of the delay circuit is used to determine the frequency of the enable signal.

4. The charge pump circuit as described in claim 1, wherein, The enable signal generation circuit includes an input decision gate, which connects the first output terminal and the second output terminal as inputs, and outputs an enable invalid level when different levels are input to the first output terminal and the second output terminal, and outputs an enable valid level when the same reset level is input to the first output terminal and the second output terminal.

5. The charge pump circuit as described in claim 4, wherein, The enable signal generating circuit further includes a gating control terminal, which receives a gating signal and, in response to the gating signal being valid, outputs an enable signal with a valid level.

6. The charge pump circuit as described in claim 5, wherein, The enable signal generation circuit further includes a signal control gate, used to obtain the output of the input decision gate as one input and the gating signal as another input, and the signal control gate is used to: In response to the invalidation of the strobe signal, the enable signal with an invalid level is output; In response to the strobe signal being valid, and the input decision gate outputting the enable valid level, the enable signal with the valid level is output; as well as In response to the strobe signal being valid, and the input decision gate outputting the enable invalid level, the enable signal with the invalid level is output.

7. The charge pump circuit as claimed in claim 1, wherein, The dynamic comparator includes a dual differential dynamic comparator, wherein the feedback voltage and the reference voltage serve as symmetrical inputs to a pair of current mirrors, and the enable terminal serves as a symmetrical input to another pair of current mirrors.

8. An electronic device comprising a charge pump circuit as claimed in any one of claims 1-7.

9. The electronic device as claimed in claim 8, wherein, The electronic device is a memory device.

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