Semiconductor device and method of manufacturing the same
By employing multiple ion implantation and heat treatment processes, the contact plug gap problem was solved, the contact plug density and electrical performance were improved, and the requirements for DRAM performance enhancement were met.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHANGXIN MEMORY TECH INC
- Filing Date
- 2023-02-27
- Publication Date
- 2026-05-12
AI Technical Summary
In existing technologies, gaps exist in the contact plugs during the manufacturing process, leading to a decrease in electrical performance and making it difficult to meet the requirements for improved DRAM performance.
A multi-stage ion implantation process is employed, with the ion beam forming a first preset angle with the perpendicular line to the plane of the semiconductor substrate. After each implantation, the substrate is rotated by a second preset angle, and combined with heat treatment, the gaps in the contact layer are repaired.
It improves the density and electrical properties of the contact plug, eliminates gaps within the contact plug, and enhances the electrical performance of the contact plug.
Smart Images
Figure CN116209256B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for manufacturing the same. Background Technology
[0002] Dynamic Random Access Memory (DRAM) is a common storage device characterized by high integration, fast read / write speeds, and low cost, making it widely used in various consumer electronics products such as computers, mobile phones, and set-top boxes. In DRAM, metal wires, capacitors, and other components are connected to the active areas via contact plugs. With the miniaturization of integrated circuits and the increasing market demands for DRAM performance, contact plugs require superior electrical performance. Therefore, structurally, fewer defects are required within the contact plugs, posing new challenges to existing contact plug manufacturing processes. Summary of the Invention
[0003] According to a first aspect of this disclosure, a method for manufacturing a semiconductor device is provided, comprising:
[0004] Forming contact holes in a semiconductor substrate;
[0005] A first contact material is deposited on the sidewalls and bottom of the contact hole to form a first contact layer;
[0006] An ion implantation process is performed on the first contact layer; wherein the ion implantation process includes multiple ion implantations, in each ion implantation, the ion beam forms a first preset angle with the perpendicular line to the plane where the semiconductor substrate is located, and after each ion implantation, the semiconductor substrate is rotated around the perpendicular line by a second preset angle.
[0007] A second contact material is deposited on the surface of the first contact layer to fill the contact holes, thereby forming a second contact layer;
[0008] The semiconductor substrate is subjected to heat treatment to repair the first contact layer and the second contact layer.
[0009] In some embodiments, the first preset angle is 30° to 60°; the second preset angle is 20°, 30°, 45°, 60°, 90° or 180°.
[0010] In some embodiments, performing an ion implantation process on the first contact layer includes:
[0011] The first contact layer is implanted with ions N times, where N is a positive integer; the second preset angle is γ, and the product of N and γ is 360°.
[0012] In some embodiments, the number of contact holes is multiple; the ion implantation process performed on the first contact layer further includes:
[0013] In each ion implantation, the semiconductor substrate is moved along a preset direction until the first contact layer in all of the plurality of contact holes is implanted with ions, the preset direction being parallel to the plane of the semiconductor substrate.
[0014] In some embodiments, the implanted ions include at least one of germanium, arsenic, and indium.
[0015] In some embodiments, the material of the first contact layer includes silicon or germanium;
[0016] The material of the second contact layer includes doped silicon or doped germanium.
[0017] In some embodiments, in the step of filling the contact hole with a second contact material to form a second contact layer, the formed second contact layer has gaps.
[0018] After the heat treatment step, the gap is filled by the repaired first contact layer and second contact layer.
[0019] In some embodiments, forming a contact hole in the semiconductor substrate includes:
[0020] A substrate is provided; wherein the substrate includes a plurality of active regions that are isolated from each other and arranged in an array, the active regions including source regions and drain regions;
[0021] A dielectric layer and a mask layer are formed sequentially on the substrate;
[0022] The contact hole is formed through the mask layer and the dielectric layer and extends into the source region or drain region.
[0023] In some embodiments, the manufacturing method further includes:
[0024] The repaired first contact layer and second contact layer are etched back until the top surfaces of the repaired first contact layer and second contact layer are flush with the top surface of the dielectric layer.
[0025] Remove the mask layer;
[0026] A bitline material layer is formed covering the dielectric layer, the repaired first contact layer, and the repaired second contact layer;
[0027] The bit line material layer is etched to form a bit line extending along a first direction, and the first contact layer and the second contact layer after etching and repair form a contact plug; wherein, the first direction is parallel to the plane of the semiconductor substrate.
[0028] According to a second aspect of this disclosure, a semiconductor device is provided, comprising:
[0029] Semiconductor substrate;
[0030] A contact plug extends into the semiconductor substrate, the contact plug including a first contact portion and a second contact portion, the first contact portion covering the sidewalls and bottom of the second contact portion, and the second contact portion containing doped ions.
[0031] The semiconductor device manufacturing method provided in this disclosure is used to eliminate gaps existing in existing contact plugs. The manufacturing method includes first ion implanting a first contact layer, followed by forming a second contact layer. This process sequence can increase the distribution depth of implanted ions in the contact hole, making the depth of implanted ions in the contact hole greater than the depth of the gap, thus facilitating the repair of gaps near the bottom of the contact hole. Furthermore, in the ion implantation process of this embodiment, the first contact layer is ion implanted multiple times. In each ion implantation, the ion beam forms a first preset angle with the perpendicular to the plane of the semiconductor substrate, which can increase the contact area between the ion beam and the sidewall of the first contact layer in the contact hole, thereby increasing the implantation area and depth of the ion beam on the sidewall of the first contact layer. After each ion implantation, the semiconductor substrate is rotated around the perpendicular by a second preset angle, which can make the distribution of implanted ions in the first contact layer in the contact hole more uniform. This ion implantation process can improve the uniformity and depth of ion distribution on the sidewalls and bottom of the first contact layer within the contact hole. This allows the ion-implanted area of the first contact layer to recrystallize after heat treatment, thereby repairing and filling the gaps in the ion-implanted area and the adjacent first and second contact layers. This improves the density of the contact plug and thus enhances its electrical performance. Attached Figure Description
[0032] Figures 1a to 1f This is a schematic diagram of the structure of a semiconductor device during the fabrication process, provided by an embodiment of this disclosure;
[0033] Figure 2 The relationship between the range of germanium ions and the energy of the injected ions is shown;
[0034] Figure 3 A schematic flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of this disclosure;
[0035] Figures 4a to 4g This is a schematic diagram of the structure of another semiconductor device provided in the present disclosure during the fabrication process;
[0036] Figure 5 A cross-sectional view of a contact hole along the X direction provided in an embodiment of this disclosure;
[0037] Figure 6 This is a schematic diagram of the structure of an ion implantation device provided in an embodiment of the present disclosure;
[0038] Figure 7 An embodiment of this disclosure provides an example of using... Figure 6 The diagram shows an ion implantation device performing ion implantation on a semiconductor substrate.
[0039] Figure 8 Another method of using the present disclosure embodiments Figure 6 The diagram shows an ion implantation device performing ion implantation on a semiconductor substrate.
[0040] Figure 9 A schematic diagram illustrating a semiconductor substrate placement method provided in an embodiment of this disclosure;
[0041] Figure 10 A schematic diagram of an ion beam implantation process provided in an embodiment of this disclosure;
[0042] Figure 11 A schematic diagram illustrating one rotation method of a semiconductor substrate provided in an embodiment of this disclosure;
[0043] Figures 12a to 12d The diagrams show the distribution of implanted ions in the first contact layer within the pores when the first contact layer is implanted 1, 4, 8, and more than 8 times during the ion implantation process.
[0044] Figure 13 A schematic flowchart of an ion implantation process provided in an embodiment of this disclosure;
[0045] Figure 14a A top view schematic diagram of a semiconductor device provided in an embodiment of this disclosure;
[0046] Figure 14b for Figure 14a The diagram shows a cross-sectional view of the semiconductor device along line BB. Detailed Implementation
[0047] The technical solution of this disclosure will be described in detail below with reference to the accompanying drawings and specific embodiments.
[0048] In the description of this disclosure, it should be understood that the terms “length,” “width,” “depth,” “upper,” “lower,” “outer,” etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this disclosure and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this disclosure.
[0049] Figures 1a to 1f This is a schematic diagram illustrating the fabrication process of a semiconductor device according to an embodiment of the present disclosure. Figure 1a This is a top view of the substrate. Figures 1b to 1e This is a cross-sectional view of the semiconductor device along line AA (i.e., along the Y direction). Figure 1a As shown, the substrate 100 includes a plurality of active regions 110 that are isolated from each other and arranged in an array, with shallow trench isolation structures 120 provided between adjacent active regions 110. The active regions 110 are used to form transistors, and each active region 110 may include one or two transistors. In some embodiments, such as Figure 1a Each active region 110 includes two transistors arranged in parallel. Two word lines 130 extending along the X direction pass through one active region 110 in parallel. The portion of the active region 110 between the two word lines 130 constitutes the drain region 111 (or source region 112) of the two transistors, used for connection to the bit line. The portion of the active region 110 outside each word line 130 constitutes the source region 112 (or drain region 111) of each transistor, used for connection to the capacitor. DRAM can consist of a 1T1C memory cell composed of one transistor and one capacitor. The voltage signal on the word line can control the transistor to turn on or off, thereby reading data from the capacitor through the bit line or writing data to the capacitor through the bit line.
[0050] In DRAM, bit lines can be led out through bit line contact plugs. The bottom of the bit line contact plug is connected to the drain region 111 (or the source region 112), and the top of the bit line contact plug is provided with a bit line extending in the Y direction. Figures 1b to 1f The process of forming a bit line contact plug is shown.
[0051] like Figure 1b As shown, a dielectric layer 200 and a mask layer 400 are sequentially stacked on a substrate 100; wherein, the dielectric layer 200 is used to isolate the bit line from the substrate 100. For example, the dielectric layer 200 includes a first sub-dielectric layer 210 and a second sub-dielectric layer 220 sequentially stacked from bottom to top. The mask layer 400 includes a first sub-mask layer 410 and a second sub-mask layer 420 sequentially stacked from bottom to top. Furthermore, a word line isolation layer 140 is disposed on top of the word line 130, and the word line isolation layer 140 is located between the word line 130 and the dielectric layer 200.
[0052] See also Figure 1b A plurality of contact holes 500 are formed, penetrating the mask layer 400 and the dielectric layer 200 and extending to the drain region 111 (or the source region 112). These contact holes 500 are used to form bit line contact plugs in subsequent processes.
[0053] Next, a first contact material is deposited on the sidewalls and bottom of the contact hole 500 to form a first contact layer 610. It should be understood that the first contact layer 610 also covers the top of the mask layer 400.
[0054] See Figure 1c The second contact material is deposited within the contact hole 500 to form the second contact layer 620.
[0055] See Figure 1d The first contact layer 610 and the second contact layer 620 are etched back until the top of the first contact layer 610 and the second contact layer 620 are flush with the top of the first sub-mask layer 410.
[0056] In some embodiments, when a first contact material and a second contact material are grown in a low-pressure chemical vapor deposition (LPCVD) furnace tube, the second contact material cannot completely fill the remaining space of the contact hole 500, resulting in an abnormality in the second contact layer 620 and / or between the first contact layer 610 and the second contact layer 620. Figure 1c The gap shown is 520. (As shown in the image) Figure 1d As shown, the gap 520 still exists after the re-etching, which reduces the conductivity of the final bit line contact plug.
[0057] One method is as follows Figure 1e and Figure 1f As shown, Figure 1e Ions are implanted into the first contact layer 610 and the second contact layer 620 after the etch is repeated. Figure 1e In the diagram, the arrow above the first contact layer 610 represents an ion beam, and the direction indicated by the arrow represents the direction in which the ion beam is implanted into the semiconductor substrate. Figure 1e In the ion implantation process shown, the ion beam is perpendicular to the plane of the semiconductor substrate.
[0058] like Figure 1f As shown, the device is annealed to repair the gaps.
[0059] Typically, during ion implantation, the ion implantation energy is between 7.5 keV and 8.5 keV, and the dose is 3.5 E15 ions / cm². 2 Up to 4.5E15 ions / cm 2 The range of the implanted ions within the first contact layer 610 and the second contact layer 620 is approximately 10 nm. Range can be understood as the distance the implanted ions travel within the target (i.e., within the first contact layer 610 and the second contact layer 620). Range is related to the energy of the implanted ions. Figure 2 The relationship between the range of germanium ions and the energy of the implanted ions is shown. Generally, the greater the energy of the implanted ions, the greater the range of the ions.
[0060] See also Figure 1e The depth H1 of the bit line contact plug is approximately 30 nm to 35 nm, while the range of the implanted ions within the first contact layer 610 and the second contact layer 620 is approximately 10 nm, which is less than the depth of the bit line contact plug. Therefore, as Figure 1f As shown, ion implantation can only repair gaps 520 within a certain depth on the surface of the bit line contact plug, and cannot repair gaps 520 near the bottom. However, increasing the ion implantation energy or dose will affect the electrical performance of the bit line contact plug. Furthermore, the ion implantation targets the first contact layer 610 of the memory array region, but simultaneously, no barrier layer is installed in the active region of the peripheral region before ion implantation. That is, when ion implantation is performed on the first contact layer 610 of the memory array region, the active region of the peripheral region will also be implanted with ions. Increasing the ion implantation dose will lead to abnormal electrical performance of the transistors formed in the active region of the peripheral region.
[0061] Based on this, the present disclosure provides a method for manufacturing a semiconductor device. Figure 3 This is a schematic flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of this disclosure. Figure 3 As shown, the method for manufacturing this semiconductor device includes:
[0062] S100: Forming contact holes in a semiconductor substrate;
[0063] S200: A first contact material is deposited on the sidewalls and bottom of the contact hole to form a first contact layer;
[0064] S300: Perform an ion implantation process on the first contact material layer; wherein the ion implantation process includes multiple ion implantations, in each ion implantation, the ion beam forms a first preset angle with the perpendicular line to the plane where the semiconductor substrate is located, and after each ion implantation, the semiconductor substrate is rotated around the perpendicular line by a second preset angle.
[0065] S400: A second contact material is deposited on the surface of the first contact layer to fill the contact holes, forming a second contact layer;
[0066] S500: Performs heat treatment on the semiconductor substrate to repair the first and second contact layers.
[0067] Figures 4a to 4g This is a schematic diagram illustrating the fabrication process of another semiconductor device provided in this disclosure. The following will be combined with… Figures 4a to 4g The method for fabricating a semiconductor device provided in the embodiments of this disclosure is described.
[0068] See Figure 4a Step S100 is performed to form a contact hole 500 in the semiconductor substrate.
[0069] For example, the semiconductor substrate is the same Figure 1b The semiconductor substrate shown includes a substrate 100, which includes mutually isolated and arrayed active regions. Word lines 130 extend along the X direction and pass through the active regions. The portions of the active regions located on both sides of each word line 130 are the drain region 111 and the source region, respectively.
[0070] Next, a dielectric layer 200 and a mask layer 400 are formed on the substrate 100, stacked sequentially from bottom to top. For example, the dielectric layer 200 may include multiple layer structures. In this embodiment, the dielectric layer 200 includes a first sub-dielectric layer 210 and a second sub-dielectric layer 220, stacked sequentially from bottom to top. The material of the first sub-dielectric layer may include silicon oxide, and the material of the second sub-dielectric layer may include silicon nitride. For example, the mask layer 400 may include multiple layer structures. In this embodiment, the mask layer 400 includes a first sub-mask layer 410 and a second sub-mask layer 420, stacked sequentially from bottom to top. The material of the first sub-mask layer 410 may include polysilicon, and the material of the second sub-mask layer 420 may include silicon oxide.
[0071] For example, the contact hole 500 penetrates the mask layer 400 and the dielectric layer 200 and extends into the drain region 111 (or source region).
[0072] See Figure 4b Step S200 is performed to deposit a first contact material on the sidewalls and bottom of the contact hole to form a first contact layer 610.
[0073] Since the contact hole penetrates the dielectric layer 200 and extends into the substrate 100, the sidewalls of the contact hole can be made of various materials, such as... Figure 4a The sidewalls of the contact hole 500 contain three materials: silicon (substrate 100), silicon oxide (first sub-dielectric layer 210), and silicon nitride (second sub-dielectric layer 220). If a second contact material (e.g., doped silicon) is directly deposited on the sidewalls of the contact hole, the different growth rates of the second contact material on the surfaces of the three materials will cause areas with faster growth rates to seal prematurely, resulting in larger gaps within the contact plug and degrading electrical performance. Therefore, in some embodiments, the material of the first contact layer 610 includes undoped silicon or undoped germanium, such as undoped polysilicon. Undoped silicon (or undoped germanium) can be deposited more uniformly on the sidewalls and bottom of the contact hole, modifying the sidewalls of the contact hole and facilitating the deposition of the second contact material, thereby reducing gaps within the contact plug.
[0074] In some embodiments, a low-pressure chemical vapor deposition (LPCVD) process can be used to grow the first contact material. For example, silane (SiH4) gas can be supplied into the LCVD furnace tube as a raw material to prepare the first contact material.
[0075] In some embodiments, the thickness of the first contact layer 610 ranges from 5 nm to 6.5 nm. And in the cross-sectional view of the contact hole 500 along the Y direction (e.g.) Figure 4a (As shown) The top width W1 is approximately 30nm to 40nm, and the bottom width W2 is approximately 25nm to 35nm. Figure 5 A cross-sectional view of the contact hole 500 along the X direction is shown. In the cross-sectional view of the contact hole 500 along the X direction, the top width W3 is approximately 45 nm to 55 nm, and the bottom width W4 is approximately 35 nm to 45 nm. It can be seen that after the first contact layer 610 is formed, the contact hole 500 is not completely filled, and there are still pores 510 inside the contact hole 500.
[0076] See Figure 4c Step S300 is executed, in which an ion implantation process is performed on the first contact layer 610 within the pore 510. The ion implantation process includes multiple ion implantations. In each ion implantation, the ion beam forms a first preset angle θ with the perpendicular line L to the plane where the semiconductor substrate is located. After each ion implantation, the semiconductor substrate is rotated around the perpendicular line L by a second preset angle γ.
[0077] here, Figure 4c In the image, the arrow above the first contact layer 610 represents an ion beam, and the direction indicated by the arrow represents the direction in which the ion beam is injected into the semiconductor substrate. Figure 4c The two ion beam directions represent the directions of the ion beams during the two ion implantation processes. After the first ion implantation, the semiconductor substrate was rotated 180° before the second ion implantation.
[0078] Figure 6 This is a schematic diagram of an ion implantation device provided in an embodiment of this disclosure. Figure 6 As shown, the ion implantation apparatus includes an ion source (not shown), an accelerator (not shown), and a scanning system 710. The ion beam 720 generated by the ion source, after gaining sufficient energy through the accelerator, enters the scanning system 710. The scanning system 710 includes two scanning electrodes 711 arranged opposite each other. As the ion beam 720 passes between the two scanning electrodes 711, the deflection angle of the ion beam 720 is continuously changed by continuously adjusting the voltage of the scanning electrodes 710, thereby scanning the surface of the semiconductor substrate 10 along the scanning direction D1 (e.g., the horizontal direction).
[0079] Figure 7 To adopt Figure 6 The diagram shows a schematic of an ion implantation apparatus performing ion implantation. To achieve a first preset angle θ between the ion beam 720 and the perpendicular line L to the plane containing the semiconductor substrate 10, in some embodiments, such as... Figure 7As shown, the semiconductor substrate 10 can be tilted such that its plane deviates from the vertical direction (Z direction) by a first preset angle θ, wherein the angle between the perpendicular line L of the plane containing the semiconductor substrate 10 and the horizontal direction is equal to the first preset angle θ. An ion beam 720 is injected into the semiconductor substrate 10 in a manner parallel to the horizontal direction, thereby achieving a first preset angle θ between the ion beam 720 and the perpendicular line L of the plane containing the semiconductor substrate 10.
[0080] It should be noted here that the first preset angle θ between the ion beam 720 and the perpendicular line L to the plane containing the semiconductor substrate 10 includes two methods, one of which is as follows: Figure 7 As shown, the plane containing the semiconductor substrate 10 deviates clockwise from the vertical direction by a first predetermined angle θ. In other embodiments, such as... Figure 8 As shown, the plane containing the semiconductor substrate 10 can also be deviated from the vertical direction by a first preset angle θ in a counterclockwise direction.
[0081] Here, as Figure 9 As shown, the plane containing the semiconductor substrate 10 can be deviated from the vertical direction clockwise, which is represented by an angle of negative θ (-θ) between the plane containing the semiconductor substrate 10 and the vertical direction. Conversely, the plane containing the semiconductor substrate 10 can be deviated from the vertical direction counterclockwise, which is represented by an angle of positive θ (+θ) between the plane containing the semiconductor substrate 10 and the vertical direction. That is, during ion implantation, the plane containing the semiconductor substrate 10 can deviate from the vertical direction by positive or negative θ, so that the ion beam 720 forms a positive or negative θ angle with the perpendicular L to the plane containing the semiconductor substrate 10.
[0082] Figure 10 This is a schematic diagram of yet another ion beam implantation process provided for an embodiment of this disclosure. In other embodiments, such as Figure 10 As shown, during ion implantation, the semiconductor substrate 10 can be placed with its plane parallel to the vertical direction, and the perpendicular line L of the plane containing the semiconductor substrate 10 is along the horizontal direction. The ion beam 720 is injected into the semiconductor substrate 10 at a first preset angle θ to the horizontal direction, thereby achieving a first preset angle θ between the ion beam 720 and the perpendicular line L of the plane containing the semiconductor substrate 10.
[0083] Compared to injecting an ion beam perpendicular to the plane of the semiconductor substrate into the aperture 510, in this embodiment, ion implantation is performed at a first preset angle θ between the ion beam and the perpendicular line to the plane of the semiconductor substrate. This increases the contact area between the ion beam and the sidewall of the aperture 510, thereby increasing the implantation area and depth of the ion beam within the sidewall of the aperture 510, and improving the uniformity of the implanted ion distribution on the sidewall and bottom of the aperture 510.
[0084] In some embodiments, the first preset angle θ ranges from 30° to 60°, that is, greater than or equal to 30° and less than or equal to 60°. This allows for a more uniform distribution of implanted ions on the sidewalls and bottom of the pore 510.
[0085] In some embodiments, to make the implanted ion distribution in the first contact layer along the circumference of the pores more uniform, step S300 may specifically include:
[0086] The first contact layer is implanted with ions N times, where N is a positive integer; the second preset angle is γ, and the product of N and γ is 360°.
[0087] In some embodiments, N can be 2, 4, 6, 8, 12, 18..., indicating that the ion implantation process may include 2, 4, 6, 8, 12, 18 or more ion implantations, and the rotation angle of the semiconductor substrate after each ion implantation (i.e. the second preset angle γ) is 180°, 90°, 60°, 45°, 30°, 20°... in sequence.
[0088] Taking N=4 as an example, this means that in the ion implantation process, the first contact layer 610 is implanted 4 times. After each implantation, the semiconductor substrate is rotated 90° around the vertical line L. It should be noted that the semiconductor substrate is not rotated during each ion implantation, but only after the ion implantation is completed.
[0089] In some embodiments, the perpendicular line L passes through the center of the semiconductor substrate. For example, the semiconductor substrate is a wafer, and the perpendicular line L passes through the center of the wafer.
[0090] Figure 11 This is a schematic diagram of a semiconductor substrate rotating along a vertical line L. Figures 12a to 12d The diagrams sequentially illustrate the distribution of implanted ions within the first contact layer 610 of the pore 510 under ion implantation processes of 1, 4, 8, and more than 8 implantations of the first contact layer. (See also...) Figure 12a For a given pore, when the ion beam moves along its scanning direction D1 and injects into the pore 510, the injected ion concentration is higher in the sidewall region perpendicular to the scanning direction D1, and lower in the sidewall region parallel to the scanning direction D1. The central region of the pore 510, due to its greater depth, also has a lower injected ion concentration. Furthermore, as... Figure 4c As shown, because the ion beam forms a first preset angle θ with the perpendicular line to the plane of the semiconductor substrate, a shadowing effect is likely to occur, resulting in a high ion concentration in the region of the sidewall of the aperture 510 facing the ion beam, while the ion concentration in the shadowed region is low. Therefore, if only one ion implantation is performed, the ion distribution within the first contact layer along the circumference of the aperture 510 will be uneven.
[0091] See Figure 11and 12b By rotating the semiconductor substrate three times along the vertical line L to perform four ion implantations on the first contact layer, each region of the sidewall of the aperture 510 has the opportunity to face the ion beam and be perpendicular to the scanning direction D1, thus making the distribution of implanted ions within the aperture 510 more uniform than a single implantation. (See also...) Figure 12c and Figure 12d As the number of ion implantation cycles increases, the implanted ions in the first contact layer 610 along the circumferential direction of the pores 510 become more uniformly distributed.
[0092] In this embodiment, during the ion implantation process, the first contact layer 610 within the pore 510 is implanted with ions multiple times. After each ion implantation, the semiconductor substrate is rotated around the vertical line by a second preset angle γ, which makes the distribution of implanted ions within the first contact layer 610 along the circumference of the pore 510 more uniform.
[0093] It should be understood that the product of N and γ can also be a positive integer multiple of 360°, such as 720°.
[0094] In some implementations, a semiconductor substrate (e.g., a wafer) is used to fabricate multiple semiconductor devices, and each region on the semiconductor substrate used to form a semiconductor device may include multiple independent active regions arranged in an array. Correspondingly, the number of contact holes is multiple. To ensure that the first contact layer within each contact hole on the semiconductor substrate is implanted with ions, step S300 may specifically include:
[0095] In each ion implantation, the semiconductor substrate is moved along a preset direction until the first contact layer in multiple contact holes is implanted with ions, and the preset direction is parallel to the plane of the semiconductor substrate.
[0096] For example, the semiconductor substrate 10 can move in a vertical direction parallel to its plane, such as... Figure 6 The movement direction D2 of the semiconductor substrate can be perpendicular to the scanning direction D1 of the ion beam 720.
[0097] In some embodiments, the scanning action of the ion beam along the scanning direction D1 is not performed simultaneously with the movement of the semiconductor substrate along the preset direction D2. That is, after the ion beam completes one scan along the scanning direction D1, the semiconductor substrate moves once along the preset direction D2 until the entire surface of the semiconductor substrate has been scanned, thus completing one ion implantation.
[0098] Figure 13 This is a schematic flowchart illustrating an ion implantation process according to an embodiment of this disclosure. The process of the ion implantation process provided in this embodiment is described in detail below with reference to this flowchart. The ion implantation process shown in this flowchart includes four ion implantations into the first contact layer 610. Figure 13 As shown, step S310 is executed first to perform the first ion implantation on the first contact layer 610 within the aperture 510; wherein, the ion beam 720 forms a first preset angle θ with the perpendicular line L of the plane where the semiconductor substrate is located. The ion beam 720 moves along the scanning direction D1, and the semiconductor substrate moves along the preset direction D2 until the entire surface of the semiconductor substrate has been scanned.
[0099] Next, step S320 is executed, in which the semiconductor substrate is rotated around the vertical line L by a second preset angle γ.
[0100] Next, step S330 is executed to perform a second ion implantation on the first contact layer 610 within the aperture 510; the second ion implantation is the same as the first ion implantation, with the ion beam 720 forming a first preset angle θ with the perpendicular line L to the plane where the semiconductor substrate is located. The ion beam 720 moves along the scanning direction D1, and the semiconductor substrate moves along the preset direction D2, until the entire surface of the semiconductor substrate has been scanned.
[0101] Then, step S340 is executed, in which the semiconductor substrate is rotated around the vertical line L in the same direction of rotation by a second preset angle γ.
[0102] Then, step S350 is executed to perform a third ion implantation on the first contact layer 610 within the pore 510; the third ion implantation is the same as the first ion implantation, so it will not be described in detail.
[0103] Then execute step S360, and rotate the semiconductor substrate around the vertical line L in the same rotation direction by a second preset angle γ.
[0104] Finally, step S370 is executed to perform a fourth ion implantation on the first contact layer 610 within the pore 510; the fourth ion implantation is the same as the first ion implantation, so it will not be described in detail.
[0105] After step S370 is completed, the ion implantation process ends, and the first contact layer 610 within the pore 510 is uniformly implanted with ions. It should be understood that during the ion implantation process, the first contact layer 610 on top of the mask layer 400 is also implanted with ions.
[0106] In some embodiments, the ion implantation energy range is 7.5 to 8.5 keV, and the implantation dose range is 3.8 E15 ions / cm². 2 Up to 4.2E15 ions / cm 2 This ensures that the range and concentration of the injected ions in the first contact layer 610 meet the requirements.
[0107] In some embodiments, the relative atomic mass of the implanted ion is greater than or equal to 70. For example, the implanted ion includes at least one of germanium (Ge), arsenic (As), and indium (In).
[0108] Next, see Figure 4d Step S400 is executed, in which the second contact material is filled into the pores 510 to form the second contact layer 620.
[0109] In some embodiments, the material of the second contact layer 620 includes doped silicon or doped germanium, such as doped polysilicon. The main function of the second contact layer 620 is to conduct bit lines and drain regions (or source regions). The fact that the second contact layer 620 is doped with silicon or doped with germanium ensures that the conductivity of the second contact layer 620 meets the requirements.
[0110] In some embodiments, a low-pressure chemical vapor deposition (LPCVD) process can be used to grow the second contact material. For example, silane (SiH4) gas and a dopant source gas can be supplied into the LCVD furnace tube as raw materials to prepare the second contact material.
[0111] like Figure 4c and Figure 4d As shown, due to the large depth-to-width ratio of the pores 510 and their small openings, the second contact material may prematurely seal the openings of the pores 510 during deposition, resulting in gaps 520 remaining within the contact holes after the formation of the second contact material. These gaps 520 are caused by the second contact material not completely filling the pores 510. Therefore, gaps 520 may be located within the second contact layer 620, between the first contact layer 610 and the second contact layer 620, or partially within the second contact layer 620 and partially between the first and second contact layers 610 and 620.
[0112] Next, see Figure 4e Step S400 is executed to perform heat treatment on the semiconductor substrate to repair the first contact layer and the second contact layer 620, forming the repaired first contact layer 611 and the repaired second contact layer 621.
[0113] Figure 4c In the process of implanting ions into the first contact layer 610, the implanted ions disrupt the original structure of the first contact material. Taking germanium as an example, germanium has a relatively large atomic mass and atomic radius, and its implantation into silicon disrupts the crystal structure of silicon. During heat treatment of the semiconductor substrate, the ion-implanted area on the surface of the first contact layer 610 undergoes recrystallization. This recrystallization process repairs the microstructure of the ion-implanted area and the adjacent first and second contact layers 610 and 620, thereby eliminating the gaps 520 near the implanted ions. Since the surface of the first contact layer 610 within the pores 510 is essentially implanted with ions, after heat treatment, both the gaps 520 near the opening of the contact hole 500 and the gaps 520 near the bottom of the contact hole 500 can be repaired.
[0114] like Figure 4d and Figure 4e As shown, after heat treatment, the repaired first contact layer 611 and second contact layer 621 fill the gap 520, making the gap 520 disappear.
[0115] Figure 4d and Figure 4e In this semiconductor structure, after heat treatment of the semiconductor substrate, the area of the first contact layer 610 that has not recrystallized is the repaired first contact layer 611, and the area of the first contact layer 610 and the second contact layer 620 that has been repaired is the repaired second contact layer 621. The semiconductor structure may also contain a second contact layer 620 that has not recrystallized.
[0116] In some embodiments, the heat treatment includes annealing or rapid thermal processing (RTP). For example, annealing is performed at temperatures ranging from 750°C to 850°C. Rapid thermal processing is performed at temperatures ranging from 750°C to 850°C.
[0117] In this disclosure, the original process sequence of forming the second contact layer first and then ion implantation is modified to first ion implanting the first contact layer within the pore, followed by forming the second contact layer. This process sequence increases the distribution depth of implanted ions in the contact pore, allowing the implanted ions to penetrate deeper than the pore depth, facilitating the repair of pores near the bottom of the contact pore. Furthermore, in this embodiment, the first contact layer is ion implanted multiple times. During each ion implantation, the ion beam forms a first preset angle with the perpendicular to the plane of the semiconductor substrate, increasing the contact area between the ion beam and the pore sidewall, thereby increasing the implantation area and depth on the pore sidewall. After each ion implantation, the semiconductor substrate is rotated around the perpendicular by a second preset angle, resulting in a more uniform distribution of implanted ions within the first contact layer along the circumference of the pore. This ion implantation process improves the uniformity of implanted ion distribution on the pore sidewall and bottom, allowing recrystallization of the ion-implanted area of the first contact layer after heat treatment, repairing the entire pore within the contact plug, and improving the electrical performance of the contact plug.
[0118] In this embodiment of the disclosure, by changing the order and method of ion implantation during the contact plug formation process, gaps in the contact plug layer can be eliminated without changing the ion implantation energy and dose. Furthermore, since the ion implantation energy and dose remain unchanged, the electrical performance of the transistors in the peripheral region is not affected.
[0119] In some embodiments, see Figure 4e , Figure 4f and Figure 4g The manufacturing method also includes:
[0120] The first contact layer 611 and the second contact layer 621 are re-etched and repaired until the top surfaces of the repaired first contact layer 611 and the second contact layer 621 are flush with the top surface of the dielectric layer 200.
[0121] Remove the mask layer 400;
[0122] A bitline material layer 300 is formed to cover the dielectric layer 200, the repaired first contact layer 611, and the second contact layer 621;
[0123] The etched bit line material layer 300 forms bit lines extending along a first direction, and the etched and repaired first contact layer 611 and second contact layer 621 form a contact plug. The remaining repaired first contact layer 611 constitutes the first contact portion of the contact plug, and the remaining repaired second contact layer 621 constitutes the second contact portion of the contact plug.
[0124] The first direction is parallel to the plane containing the semiconductor substrate. For example, the first direction is the Y direction.
[0125] For example, the bit line material layer 300 includes a metal nitride layer and a metal layer stacked sequentially from bottom to top. The material of the metal nitride layer can be titanium nitride, tungsten nitride, etc., and the material of the metal layer can be tungsten, copper, gold, cobalt, etc.
[0126] It should be noted that the manufacturing method provided in this disclosure is applicable not only to bit line contact plugs, but also to the fabrication of other contact plugs with gaps, such as capacitor contact plugs, source contact plugs in the peripheral region, and drain contact plugs. This manufacturing method is applicable not only to DRAM, but also to the fabrication of other semiconductor devices, such as NAND flash memory and SRAM memory.
[0127] This disclosure also provides a semiconductor device. Figure 14a This is a top view schematic diagram of a semiconductor device provided in an embodiment of this disclosure. Figure 14b yes Figure 14a A cross-sectional view along line BB, as shown below. Figure 14a and Figure 14b As shown, the semiconductor device includes:
[0128] Semiconductor substrate;
[0129] The contact plug 810 extends into the semiconductor substrate and includes a first contact portion 811 and a second contact portion 812. The first contact portion 811 covers the sidewalls and bottom of the second contact portion 812, and the second contact portion 812 contains doped ions.
[0130] In some embodiments, the dopant ions include at least one of germanium, arsenic, and indium.
[0131] In some embodiments, there is no gap within the contact plug 810.
[0132] In some embodiments, such as Figure 14a As shown, the semiconductor substrate includes a substrate 100, which includes a plurality of active regions 110 that are isolated from each other and arranged in an array. A word line extending along the X direction passes through the active regions 110, and the portions of the active regions 110 located on both sides of the word line are the source region 112 and the drain region 111, respectively.
[0133] The semiconductor substrate also includes a dielectric layer 200 covering the surface of the substrate 100, a contact plug 810 penetrating the dielectric layer 200 and extending into the drain region 111; a bit line 820 is located on top of the contact plug 810 and the dielectric layer 200, the bit line 820 is connected to the contact plug 810 and extends along the Y direction.
[0134] In the semiconductor device provided in this embodiment, the second contact portion 812 contains doped ions, which are used to recrystallize the second contact portion 812 during the preparation of the contact plug 810, thereby ensuring that there are no gaps in the contact plug 810.
[0135] The above embodiments are merely illustrative of the principles and effects of this disclosure and are not intended to limit this disclosure. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of this disclosure. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this disclosure should still be covered by the claims of this disclosure.
Claims
1. A method for manufacturing a semiconductor device, characterized in that, include: Forming contact holes in a semiconductor substrate; A first contact material is deposited on the sidewalls and bottom of the contact hole to form a first contact layer; An ion implantation process is performed on the first contact layer; wherein the ion implantation process includes multiple ion implantations, in each ion implantation, the ion beam forms a first preset angle with the perpendicular line to the plane where the semiconductor substrate is located, the first preset angle being 30° to 60°, and after each ion implantation, the semiconductor substrate is rotated around the perpendicular line by a second preset angle. A second contact material is deposited on the surface of the first contact layer to fill the contact hole, forming a second contact layer, the second contact layer having gaps; The semiconductor substrate is subjected to heat treatment to repair the first contact layer and the second contact layer, and the gap is filled by the repaired first contact layer and the second contact layer.
2. The method for manufacturing a semiconductor device according to claim 1, characterized in that, The second preset angle is 20°, 30°, 45°, 60°, 90° or 180°.
3. The method for manufacturing a semiconductor device according to claim 1, characterized in that, The ion implantation process performed on the first contact layer includes: The first contact layer is implanted with ions N times, where N is a positive integer; the second preset angle is γ, and the product of N and γ is 360°.
4. The method for manufacturing a semiconductor device according to claim 1, characterized in that, The number of contact holes is multiple; the ion implantation process performed on the first contact layer further includes: In each ion implantation, the semiconductor substrate is moved along a preset direction until the first contact layer in all of the plurality of contact holes is implanted with ions, the preset direction being parallel to the plane of the semiconductor substrate.
5. The method for manufacturing a semiconductor device according to claim 1, characterized in that, The implanted ions include at least one of germanium, arsenic, and indium.
6. The method for manufacturing a semiconductor device according to claim 1, characterized in that, The material of the first contact layer includes silicon or germanium; The material of the second contact layer includes doped silicon or doped germanium.
7. The method for manufacturing a semiconductor device according to claim 1, characterized in that, The process of forming contact holes in a semiconductor substrate includes: A substrate is provided; wherein the substrate includes a plurality of active regions that are isolated from each other and arranged in an array, the active regions including source regions and drain regions; A dielectric layer and a mask layer are formed sequentially on the substrate; The contact hole is formed through the mask layer and the dielectric layer and extends into the drain region or source region.
8. The method for manufacturing a semiconductor device according to claim 7, characterized in that, The manufacturing method further includes: The repaired first contact layer and second contact layer are etched back until the top surfaces of the repaired first contact layer and second contact layer are flush with the top surface of the dielectric layer. Remove the mask layer; A bitline material layer is formed covering the dielectric layer, the repaired first contact layer, and the repaired second contact layer; The bit line material layer is etched to form a bit line extending along a first direction, and the first contact layer and the second contact layer after etching and repair form a contact plug; wherein, the first direction is parallel to the plane of the semiconductor substrate.
9. A semiconductor device formed by the manufacturing method according to any one of claims 1-8, characterized in that, include: Semiconductor substrate; A contact plug extends into the semiconductor substrate, the contact plug including a first contact portion and a second contact portion, the first contact portion covering the sidewalls and bottom of the second contact portion, and the second contact portion containing doped ions.