Metal floating gate memory and method of manufacturing the same

Abstract

The application discloses a metal floating gate memory with a metal floating gate sidewall structure, which comprises a first oxide layer and a second nitride layer self-aligned formed on the side of a first gate groove and superimposed to form a first side spacer, a second groove formed by etching a bottom semiconductor substrate with the second side of the second nitride layer as a self-aligned condition, a third tunneling oxide layer self-aligned formed on the second side of the second nitride layer and the side of the second groove of the bottom and extended to the bottom surface of the second groove, and a metal floating gate self-aligned formed on the second side of the third tunneling oxide layer, with a second side spacer formed on the second side of the metal floating gate, which is superimposed by a fourth oxide layer, a fifth nitride layer, a sixth oxide layer and a seventh nitride layer. The metal floating gate sidewall structure is in an ONO-metal floating gate-ONON structure. The application also provides a manufacturing method of the metal floating gate memory. The application can reduce the oxygen content around the metal floating gate and improve the erasing performance of the device.

Description

TECHNICAL FIELD

[0001] The present application relates to a semiconductor integrated circuit manufacturing method, in particular to a metal floating gate memory. The present application also relates to a manufacturing method of a metal floating gate memory. BACKGROUND

[0002] With the development of microelectronic technology, flash memory also faces a series of challenges, such as lower power consumption, faster speed, higher integration, etc. For the traditional poly floating gate (FG) memory, the thickness of the poly floating gate is reduced synchronously with the reduction of the device feature size, which increases the number of incident electrons with high energy. A large number of high-energy incident electrons cause damage to the blocking oxide layer, generating more traps and defects, affecting the reliability of the device. In order to overcome this problem, a scheme of replacing poly with metal as the floating gate is proposed, so the research and improvement of the performance of metal floating gate memory have received relatively widespread attention.

[0003] The current process uses vertical TiN as the material of the floating gate, horizontal electric field guiding type write operation and tip TiN voltage coupling-free erase operation, which can greatly improve the erase and write efficiency, but using TiN metal material as the floating gate structure, after subsequent high-temperature process steps, the performance of the TiN metal floating gate is easy to change, especially the tip part is easy to be oxidized, and the erase speed is slow

[0004] The prior art has the following problems:

[0005] The TiN of the FG is affected by the surrounding environment and the process, and the TiN metal property of the top region can change and be oxidized, causing the erase voltage to be too high and the speed to be too slow.

[0006] Energy dispersive spectrometer (EDS) line scan analysis of the element content of each region of the FG: it is found that the oxygen content in the top region of the FG, i.e. the erase region, is higher than that in other regions, and the N content in the TiN is almost zero.

[0007] The applicant believes that the top FG of the existing metal floating gate memory is rich in oxygen, and after subsequent processes, N diffusion and vacancy generation, oxygen replaces the N vacancy.

[0008] The existing 38 super flash (SF) is a SF based on a 38 nm node, and TiN is used as the metal floating gate in the existing 38 SF. The following will be described in combination with the drawings:

[0009] As shown in FIG. 1, the existing 38 SF is a 3D NAND flash memory, and the TiN metal floating gate is used as the floating gate of the memory. Figure 1Fig. 1 is a structural schematic diagram of a prior art super flash memory using metal floating gate memory; the prior art super flash memory comprises:

[0010] A gate trench 103 is formed on top of the source region 102, and the bottom surface of the gate trench 103 is lower than the top surface of the semiconductor substrate 101, and the top surface of the gate trench 103 is higher than the top surface of the semiconductor substrate 101.

[0011] Generally, the semiconductor substrate 101 comprises a silicon substrate.

[0012] The source region 102 is formed in the surface area of the semiconductor substrate 101 at the bottom of the gate trench 103.

[0013] Generally, in the cross section perpendicular to the paper surface direction, the source regions 102 of the memory cells of different super flash memories are connected together and form a source line (SL). Figure 1

[0014] The floating gate 105 and the control gate 107 are formed in the gate trench 103.

[0015] Generally, the control gate 107 is usually a tungsten gate. The control gate 107 directly contacts the bottom source region 102.

[0016] An oxide layer 104 is formed between the first side of the floating gate 105 and the side and bottom surface of the gate trench 103. The oxide layer 104 is an HTO oxide layer, which serves as a tunneling oxide layer during writing, i.e. programming.

[0017] An oxide layer 106 is formed between the second side of the floating gate 105 and the side of the control gate 107. The oxide layer 106 is an HTO oxide layer.

[0018] The floating gate 105 is a TiN layer; the top end of the floating gate 105 is higher than the top surface of the control gate 107.

[0019] Two word line gates 108 are symmetrically arranged on the semiconductor substrate 101 on both sides of the gate trench 103, and a first gate dielectric layer (not shown) is arranged between the word line gate 108 and the semiconductor substrate 101.

[0020] A second dielectric layer 109 is arranged between the side of the gate trench 103 and the second side of the word line gate 108, and the first gate dielectric layer is formed by the second dielectric layer 109 and the oxide layer 104, and the second dielectric layer 109 is usually an oxide layer.

[0021] ​An erase gate 113 is formed on the top of the floating gate 105, and the charge stored in the floating gate 105 is discharged to the erase gate 113 through the top tip to achieve erasing. Since two floating gates 105 are symmetrically arranged in the gate trench 103, the erase gate 113 usually covers an area larger than the formed area of the gate trench 103; the erase gate 113 and the bottom first gate interlayer dielectric layer, the floating gate 105 and the oxide layer 106 are isolated by a second gate interlayer dielectric layer 112.

[0022] Generally, the second dielectric layer 109 and the second gate interlayer dielectric layer 112 are both oxide layers, so Figure 1 The corresponding images of the second dielectric layer 109, the second gate interlayer dielectric layer 112, the oxide layer 104 and the oxide layer 106 in the figure are all filled with the same dots.

[0023] A drain region 111 is self-aligned formed in the surface area of the semiconductor substrate 101 on the first side of the word line gate 108. Generally, a side wall (not shown) is also formed on the first side of the word line gate 108, and the drain region 111 and the side wall on the first side of the word line gate 108 are self-aligned. A lightly doped drain region (LDD) 110 is also formed on one side of the drain region 111, and the lightly doped drain region 110 and the first side of the word line gate 108 are self-aligned.

[0024] Generally, the word line gate 108 is a polysilicon gate or a metal gate; the erase gate 113 is a polysilicon gate or a metal gate.

[0025] Figure 1 The existing super flash memory using metal floating gate shown in the figure is the existing metal floating gate memory, which usually uses a metal floating gate sidewall structure, and the structure between the word line gates 108 is formed by a sidewall process. The sidewall structure between the word line gates is described as follows:

[0026] As Figure 2 shown, it is a structure schematic diagram of the existing metal floating gate memory with a metal floating gate sidewall structure; the existing metal floating gate memory with a metal floating gate sidewall structure includes:

[0027] A word line gate 202 formed on a semiconductor substrate 201.

[0028] The word line gate 202 is usually defined by a hard mask layer, and after the word line gate 202 is etched, the interval area of the word line gate 202 serves as a gate trench 203 corresponding to the metal floating gate sidewall structure.

[0029] An oxide layer 204 is formed on the side of the gate trench 203 to form a side wall.

[0030] The semiconductor substrate 201 is etched with the side surfaces of the oxide layer 204 as a self-alignment condition to form a recess, and the interval regions between the side surfaces of the oxide layer 204 and the recess form a second gate trench 205 corresponding to Figure 1 the gate trench 103 in FIG. 1.

[0031] A tunnel oxide layer 206 is formed on the side surfaces and the bottom surface of the second gate trench 205.

[0032] A metal floating gate 207 composed of TiN is formed on the side surfaces of the tunnel oxide layer 206 in self-alignment.

[0033] An oxide layer 208 is formed on the side surfaces of the metal floating gate 207 in self-alignment, and a nitride layer 209 is formed on the side surfaces of the oxide layer 208 in self-alignment.

[0034] The control gate 210 is formed in the interval regions of the nitride layer 209.

[0035] Figure 2 Only the structure related to the metal floating gate sidewall structure is described, and other structures are omitted, please refer to FIG. 2 for details. Figure 1 The source region, the drain region and the erase gate are all omitted.

[0036] Generally, the tunnel oxide layer 206 is an HTO oxide layer formed by an HTO process, and the thickness is, for example, 5-10 nm.

[0037] The oxide layer 208 is generally an ALD oxide layer formed by an ALD process and a superposition layer of the HTO oxide layer, and the thickness of the ALD oxide layer is, for example, 5-10 nm. The thickness of the HTO oxide layer is, for example, 5-10 nm.

[0038] The nitride layer 209 is generally an ALD nitride layer formed by an ALD process, and the thickness is, for example, 5-10 nm.

[0039] ESD analysis shows that, Figure 2 In the metal floating gate sidewall structure shown in FIG. 2, the N content in the top region of the metal floating gate is almost zero, please refer to FIG. 3 for details. Figure 5A As shown in FIG. 3, the N content in the top region of the metal floating gate is almost zero. Figure 5A As shown in FIG. 4, the ESD line scan curves of the metal floating gate of the existing metal floating gate memory at different positions are shown. Figure 2 As shown in FIG. 4, the ESD line scan curves of the metal floating gate of the existing metal floating gate memory at different positions are shown. Figure 5A In FIG. 4, the ESD line scan curves of three regions of the floating gate are shown, which are FG top, FG middle and FG bottom. The curves show that there are four elements, which are O, Si, Ti and N, and the corresponding curves are marked with the elements. Figure 5AThe three groups of curves in the bottom part are zoomed-in views of the corresponding dashed-line boxes in the three groups of curves in the top part. As can be seen from the three groups of curves in the bottom part, the dashed-line circles 501, 502 and 503 are all Ti content peak regions, but the N content in the dashed-line circle 501 is close to zero, i.e. the N content in the top region of the metal floating gate is close to zero. SUMMARY

[0040] The technical problem to be solved by the present application is to provide a metal floating gate memory capable of reducing the oxygen content around the metal floating gate, protecting the material characteristics of the metal floating gate during high-temperature thermal processes and improving the erasing performance of the device while keeping the area and programming performance of the device. To this end, the present application also provides a manufacturing method of a metal floating gate memory.

[0041] To solve the above technical problem, the metal floating gate memory provided by the present application has a metal floating gate sidewall structure.

[0042] The metal floating gate sidewall structure is formed in a first gate trench which opens the surface of a bottom semiconductor substrate.

[0043] The metal floating gate sidewall structure comprises:

[0044] A first oxide layer and a second nitride layer are self-aligned to the side of the first gate trench, and the first oxide layer and the second nitride layer are stacked to form a first side spacer.

[0045] A second recess is formed by etching the bottom semiconductor substrate with the second side of the second nitride layer as a self-alignment condition.

[0046] A third tunneling oxide layer is self-aligned to the second side of the second nitride layer and the side of the second recess in the bottom and extends to the bottom surface of the second recess.

[0047] A metal floating gate is self-aligned to the second side of the third tunneling oxide layer, and the metal floating gate is isolated from the semiconductor substrate by the third tunneling oxide layer.

[0048] A second side spacer is formed on the second side of the metal floating gate, and the second side spacer is stacked by a first layer spacer and a second layer spacer, the first layer spacer is stacked by a fourth oxide layer and a fifth nitride layer, and the second layer spacer is stacked by a sixth oxide layer and a seventh nitride layer.

[0049] The metal floating gate sidewall structure has an ONO-metal floating gate-ONN structure, O represents an oxide layer, and N represents a nitride layer. The nitride layers on both sides of the metal floating gate are used to reduce the oxygen content on both sides of the metal floating gate, thereby protecting the material characteristics of the metal floating gate.

[0050] A further improvement is that the material of the metal floating gate comprises TiN.

[0051] A further improvement is that the metal floating gate memory further comprises word line gates formed on the surface of the semiconductor substrate, the word line gates being superimposed by a first gate dielectric layer and a second gate conductive material layer.

[0052] The first gate trench is composed of the interval between two adjacent second sides of the word line gates.

[0053] A drain region is self-aligned formed in the surface region of the semiconductor substrate outside the first side of the word line gates.

[0054] A further improvement is that one metal floating gate sidewall structure is formed on each side of the first gate trench.

[0055] A control gate is formed in the region between the two metal floating gate sidewall structures within the first gate trench; the top surface of the metal floating gate is higher than the top surface of the control gate.

[0056] A source region is formed in the surface region of the semiconductor substrate at the bottom of the second recess, the bottom of the control gate being in contact with the source region.

[0057] A further improvement is that the first oxide layer adopts an HTO oxide layer formed by an HTO process.

[0058] The second nitride layer adopts an ALD nitride layer formed by an ALD process.

[0059] The third tunneling oxide layer adopts an HTO oxide layer.

[0060] The fourth oxide layer adopts an ALD oxide layer formed by an ALD process.

[0061] The fifth nitride layer adopts an ALD nitride layer.

[0062] The sixth oxide layer adopts an HTO oxide layer.

[0063] The seventh nitride layer adopts an ALD nitride layer.

[0064] A further improvement is that the depth of the second recess is

[0065] A further improvement is that an erase gate is formed on the top surface of the metal floating gate, the metal floating gate and the erase gate being separated by a first gate-to-gate dielectric layer.

[0066] To solve the above technical problems, the application provides a manufacturing method of a metal floating gate memory, wherein the metal floating gate memory has a metal floating gate sidewall structure, and the forming step of the metal floating gate sidewall structure comprises the following steps:

[0067] Step one: forming a first gate trench which opens the bottom semiconductor substrate surface.

[0068] Step two: sequentially forming a first oxide layer and a second nitride layer, the first oxide layer is formed on the side and bottom surface of the first gate trench and the outside surface of the first gate trench, and the second nitride layer is formed on the surface of the first oxide layer.

[0069] Step three: performing overall etching on the second nitride layer, so that the second nitride layer is only reserved on the second side of the first oxide layer at the side of the first gate trench; and the first side spacer wall is formed by the superposition of the first oxide layer and the second nitride layer.

[0070] Step four: etching the exposed semiconductor substrate with the second nitride layer as a self-alignment condition to form a second groove.

[0071] Step five: forming a third tunneling oxide layer on the second side and the inside surface of the second groove of the second groove at the bottom.

[0072] Step six: forming a metal floating gate on the second side of the third tunneling oxide layer in a self-alignment manner, and the metal floating gate is isolated from the semiconductor substrate by the third tunneling oxide layer.

[0073] Step seven: forming a fourth oxide layer which covers the second side of the metal floating gate and the surface of the third tunneling oxide layer exposed in the second groove; sequentially forming a fifth nitride layer, a sixth oxide layer and a seventh nitride layer on the surface of the fourth oxide layer.

[0074] Step eight: performing overall etching on the seventh nitride layer, the sixth oxide layer, the fifth nitride layer, the fourth oxide layer and the third tunneling oxide layer in sequence, and the second side spacer wall is formed by the superposition of the fourth oxide layer, the fifth nitride layer, the sixth oxide layer and the seventh nitride layer reserved on the second side of the metal floating gate after etching, the second side spacer wall is formed by the superposition of a first layer spacer wall and a second layer spacer wall, the first layer spacer wall is formed by the superposition of the fourth oxide layer and the fifth nitride layer, and the second layer spacer wall is formed by the superposition of the sixth oxide layer and the seventh nitride layer.

[0075] The metal floating gate sidewall structure is in an ONO-metal floating gate-ONON structure, O represents an oxide layer, and N represents a nitride layer. The nitride layers on both sides of the metal floating gate are used to reduce the oxygen content on both sides of the metal floating gate, thereby protecting the material properties of the metal floating gate.

[0076] A further improvement is that the material of the metal floating gate comprises TiN.

[0077] A further improvement is that in step one, further comprising forming a word line gate on the surface of the semiconductor substrate, and the sub-steps of forming the word line gate comprise:

[0078] Sequentially forming a first gate dielectric layer and a second gate conductive material layer on the surface of the semiconductor substrate.

[0079] The second gate conductive material layer and the first gate dielectric layer are patterned and etched to form the word line gate superimposed by the etched first gate dielectric layer and the second gate conductive material layer.

[0080] The first gate trench is composed of the interval between the second side surfaces of two adjacent word line gates.

[0081] A further improvement is that a metal floating gate sidewall structure is formed on both sides of the first gate trench; after step eight is completed, further comprising:

[0082] A control gate is formed in the area between the two metal floating gate sidewall structures in the first gate trench; the top surface of the metal floating gate is higher than the top surface of the control gate.

[0083] A further improvement is that the first oxide layer adopts an HTO oxide layer formed by an HTO process.

[0084] The second nitride layer adopts an ALD nitride layer formed by an ALD process.

[0085] The third tunneling oxide layer adopts an HTO oxide layer.

[0086] The fourth oxide layer adopts an ALD oxide layer formed by an ALD process.

[0087] The fifth nitride layer adopts an ALD nitride layer.

[0088] The sixth oxide layer adopts an HTO oxide layer.

[0089] The seventh nitride layer adopts an ALD nitride layer.

[0090] A further improvement is that the depth of the second recess is

[0091] Further improvement is, after the control gate is formed, further comprising:

[0092] Forming a first gate-to-gate dielectric layer.

[0093] Forming an erase gate, the erase gate is on the top surface of the metal floating gate, the metal floating gate and the erase gate are separated by the first gate-to-gate dielectric layer.

[0094] Further improvement is, before the control gate is formed, further comprising: performing source region implantation to form a source region in the surface area of the semiconductor substrate at the bottom of the second recess, the bottom of the control gate is in contact with the source region.

[0095] After the word line gate is formed, further comprising: performing drain region implantation to form a drain region in the surface area of the semiconductor substrate outside the first side surface of the word line gate.

[0096] The metal floating gate sidewall structure is formed with a second nitrided layer in the first side sidewall at the first side surface of the metal floating gate, and a fifth nitrided layer and a seventh nitrided layer in the second side sidewall at the second side surface of the metal floating gate, which makes the metal floating gate sidewall structure present an ONO-metal floating gate-ONON structure, so as to greatly reduce the oxygen content around the metal floating gate, for example, the oxygen content around the metal floating gate is only determined by the third tunneling oxide layer and the fourth oxide layer which are in direct contact with the metal floating gate, and compared with the prior structure, the thickness of the oxide layer which is in direct contact with the metal floating gate on both sides is greatly reduced, so as to greatly reduce the amount of oxidation of the metal floating gate in the high-temperature thermal process, and the top tip portion of the metal floating gate is not easy to be oxidized, so as to protect the material properties of the metal floating gate in the high-temperature thermal process, and thus improve the erasing performance of the device.

[0097] Compared with the prior structure, since the metal floating gate sidewall structure is still adopted in the present application, the size of the first gate trench does not need to be expanded, so the area of the device can be kept, that is, the area of the device can also be minimized in the present application.

[0098] Compared with the prior structure, the second recess of the present application is self-aligned with the second side surface of the second nitrided layer, so the metal floating gate and the semiconductor substrate are separated by the third tunneling oxide layer, the insertion of the second nitrided layer does not affect the thickness of the third tunneling oxide layer, and during programming, the programming carriers enter the metal floating gate by passing through the third tunneling oxide layer, since the second nitrided layer does not affect the thickness of the third tunneling oxide layer, the programming performance of the device can be kept. BRIEF DESCRIPTION OF DRAWINGS

[0099] The application will be described in further detail below with reference to the drawings and specific embodiments.

[0100] Figure 1 is a structural schematic diagram of a prior art 38 super flash memory with a metal floating gate memory;

[0101] Figure 2 is a structural schematic diagram of a prior art metal floating gate memory with a metal floating gate sidewall structure;

[0102] Figure 3 is a structural schematic diagram of a metal floating gate memory according to an embodiment of the application;

[0103] Figures 4A-4G is a structural schematic diagram of a device in each step of a method of manufacturing a metal floating gate memory according to an embodiment of the application;

[0104] Figure 5A is a structural schematic diagram of a device in each step of a method of manufacturing a metal floating gate memory according to an embodiment of the application; Figure 2 is an ESD line scan curve at each position of a metal floating gate of a prior art metal floating gate memory as shown in

[0105] Figure 5B is an ESD line scan curve at each position of a metal floating gate of a metal floating gate memory according to an embodiment of the application. DETAILED DESCRIPTION

[0106] As shown in Figure 3 is a structural schematic diagram of a metal floating gate memory according to an embodiment of the application; the metal floating gate memory according to an embodiment of the application has a metal floating gate sidewall structure.

[0107] The metal floating gate sidewall structure is formed in a first gate trench 303, which opens a surface of a bottom semiconductor substrate 301, i.e. the surface of the semiconductor substrate 301 is exposed and serves as a bottom surface of the first gate trench 303.

[0108] The metal floating gate sidewall structure includes:

[0109] A first oxide layer 304 and a second nitride layer 305 are formed on the side of the first gate trench 303 in a self-aligned manner, and the first oxide layer 304 and the second nitride layer 305 form a first side spacer.

[0110] A second recess 306 is formed by etching the bottom semiconductor substrate 301 with the second side of the second nitride layer 305 as a self-aligned condition.

[0111] In some embodiments, the depth of the second recess 306 is

[0112] The third tunneling oxide layer 307 is self-aligned and formed on the side of the second groove 306 on the second side and bottom of the second nitride layer 305 and extends to the bottom surface of the second groove 306.

[0113] A metal floating gate 308 is self-aligned and formed on the second side of the third tunneling oxide layer 307, and the metal floating gate 308 and the semiconductor substrate 301 are isolated by the third tunneling oxide layer 307.

[0114] A second sidewall is formed on the second side of the metal floating grid 308. The second sidewall is formed by stacking a first sidewall and a second sidewall. The first sidewall is formed by stacking a fourth oxide layer 309 and a fifth nitride layer 310, and the second sidewall is formed by stacking a sixth oxide layer 311 and a seventh nitride layer 312.

[0115] The sidewall structure of the metal floating gate is an ONO-metal floating gate 308-ONON structure, where O represents an oxide layer and N represents a nitriding layer. The nitriding layers on both sides of the metal floating gate 308 are used to reduce the oxygen content on both sides of the metal floating gate 308, thereby protecting the material properties of the metal floating gate 308.

[0116] In this embodiment of the invention, the material of the metal floating gate 308 includes TiN.

[0117] The metal floating gate memory also includes a word line gate 302 formed on the surface of the semiconductor substrate 301, the word line gate 302 being formed by stacking a first gate dielectric layer and a second gate conductive material layer.

[0118] The first gate trench 303 is composed of a spacer region between the second sides of two adjacent word line gates 302.

[0119] Leakage area ( Figure 3 (Not shown) Self-alignment is formed in the surface region of the semiconductor substrate 301 outside the first side of the word line gate 302.

[0120] A metal floating gate sidewall structure is formed on both sides of the first gate trench 303.

[0121] A control gate 313 is formed in the region between the two metal floating gate sidewall structures within the first gate trench 303; the top surface of the metal floating gate 308 is higher than the top surface of the control gate 313.

[0122] Source region ( Figure 3 (Not shown) In the surface region of the semiconductor substrate 301 formed at the bottom of the second groove 306, the bottom of the control gate 313 is in contact with the source region.

[0123] An erase gate 315 is formed on the top surface of the metal floating gate 308, and a first intergate dielectric layer 314 is formed between the metal floating gate 308 and the erase gate 315.

[0124] Figure 3 Only the structure related to the metal floating gate sidewall structure is shown, and the overall structure of the device is shown in the overall structure of the device. Figure 1

[0125] The storage charge of the metal floating gate 308 is written through the third tunneling oxide layer 307, i.e., from the bottom region of the metal floating gate 308.

[0126] The erase operation is performed by applying a voltage to the metal floating gate 308 and the erase gate 315 to erase the storage charge. Figure 3 In the embodiment, the metal floating gate 308 covers two metal floating gates 308 and the region between the metal floating gates 308.

[0127] In the embodiment, the first oxide layer 304 is an HTO oxide layer formed by an HTO process.

[0128] The second nitride layer 305 is an ALD nitride layer formed by an ALD process.

[0129] The third tunneling oxide layer 307 is an HTO oxide layer.

[0130] The fourth oxide layer 309 is an ALD oxide layer formed by an ALD process.

[0131] The fifth nitride layer 310 is an ALD nitride layer.

[0132] The sixth oxide layer 311 is an HTO oxide layer.

[0133] The seventh nitride layer 312 is an ALD nitride layer.

[0134] In some embodiments, the depth of the second recess 306 is 5-20 nm.

[0135] The thickness of the second nitride layer 305 is 5-20 nm.

[0136] The thickness of the third tunneling oxide layer 307 is 5-20 nm.

[0137] The thickness of the metal floating gate 308 is 5-20 nm.

[0138] The thickness of the fourth oxide layer 309 is 5-20 nm. ​

[0139] The thickness of the fifth nitrided layer 310 is

[0140] The thickness of the sixth oxide layer 311 is

[0141] The thickness of the seventh nitrided layer 312 is

[0142] The embodiment of the present application has a metal floating gate sidewall structure, the second nitrided layer 305 is formed in the first side spacer at the first side of the metal floating gate 308, and the fifth nitrided layer 310 and the seventh nitrided layer 312 are formed in the second side spacer at the second side of the metal floating gate 308, which makes the metal floating gate sidewall structure present an ONO-metal floating gate 308-ONON structure, so that the oxygen content around the metal floating gate 308 can be greatly reduced, for example, the oxygen content around the metal floating gate 308 is only determined by the third tunneling oxide layer 307 and the fourth oxide layer 309 which directly contact the metal floating gate 308, and compared with the prior structure, the thickness of the oxide layer which directly contacts the metal floating gate 308 on both sides is greatly reduced, so that the oxygen content around the metal floating gate 308 can be greatly reduced, and after the oxygen content around the metal floating gate 308 is reduced, the amount of the metal floating gate 308 oxidized in the high-temperature thermal process can be greatly reduced, so that the top tip portion of the metal floating gate 308 is not easy to be oxidized, thereby the material properties of the metal floating gate 308 can be protected in the high-temperature thermal process, and the erasing performance of the device can be improved.

[0143] Compared with the prior structure, since the embodiment of the present application still adopts the metal floating gate sidewall structure, the size of the first gate trench 303 does not need to be expanded, so that the area of the device can be maintained by the embodiment of the present application, that is, the area of the device can also be minimized by the embodiment of the present application.

[0144] Compared with the prior structure, the second recess 306 of the embodiment of the present application is self-aligned with the second side of the second nitrided layer 305, so that the metal floating gate 308 and the semiconductor substrate 301 are isolated by the third tunneling oxide layer 307, the insertion of the second nitrided layer 305 does not affect the thickness of the third tunneling oxide layer 307, and during programming, the programming carriers enter the metal floating gate 308 by passing through the third tunneling oxide layer 307, since the second nitrided layer 305 does not affect the thickness of the third tunneling oxide layer 307, so that the programming performance of the device can be maintained.

[0145] As shown in FIG. 6, it is an ESD linescan curve at each position of the metal floating gate of the metal floating gate memory of the embodiment of the present application, Figure 5B Figure 5B Figure 5A ​​In the figure, the ESD line scan curves of the four regions of the floating gate are shown, and the corresponding regions are marked on the photo of the floating gate, including: mark 601a corresponds to the top of the FG, mark 601b corresponds to the top of the FG, mark 601c corresponds to the middle of the FG, and mark 601d corresponds to the bottom of the FG, which corresponds to four graphs, each of which shows that it contains four elements, namely O, Si, Ti and N, and the corresponding curves are marked with elements, and the extension of the Ti element curve is relatively light. In each curve, the Ti content peak area is in the dashed box 601, 602, 603 and 604, and it can be seen that the N content of each region is sufficient; and Figure 5A Compared with the N content at the dashed circle 501 in the figure, the N content in the dashed boxes 601 and 602, which are both FG top regions, is improved, so that the erase rate of the device can be finally improved.

[0146] As shown in Figures 4A to 4G , it is a device structure schematic diagram in each sub-step of forming a floating gate in the manufacturing method of the metal floating gate memory of the embodiment of the application; in the manufacturing method of the metal floating gate memory of the embodiment of the application, the metal floating gate memory has a metal floating gate side wall structure, and the forming step of the metal floating gate side wall structure comprises:

[0147] Step one, as shown in Figure 4A , a first gate trench 303 is formed, which opens the surface of the semiconductor substrate 301 at the bottom.

[0148] In the embodiment method of the application, it also includes forming a word line gate 302 on the surface of the semiconductor substrate 301, and the sub-step of forming the word line gate 302 comprises:

[0149] A first gate dielectric layer and a second gate conductive material layer are sequentially formed on the surface of the semiconductor substrate 301.

[0150] The second gate conductive material layer and the first gate dielectric layer are patterned and etched to form the word line gate 302 which is superimposed by the etched first gate dielectric layer and the second gate conductive material layer.

[0151] In some embodiment methods, a hard mask layer is used in the process of patterned etching, Figure 4A In the figure, the hard mask layer comprises an oxidation layer 401, a nitridation layer 402 and an oxidation layer 403 which are sequentially superimposed.

[0152] The first gate trench 303 is composed of the interval between two adjacent second side surfaces of the word line gate 302.

[0153] Step two, as shown in Figure 4BAs shown, a first oxide layer 304 and a second nitride layer 305 are formed sequentially. The first oxide layer 304 is formed on the side and bottom surfaces of the first gate trench 303 and on the outer surface of the first gate trench 303. The second nitride layer 305 is formed on the surface of the first oxide layer 304.

[0154] Step 3, as follows Figure 4C As shown, the second nitride layer 305 is fully etched so that the second nitride layer 305 is only retained on the second side of the first oxide layer 304 at the side of the first gate trench 303; the first sidewall is formed by the superposition of the first oxide layer 304 and the second nitride layer 305.

[0155] Step 4, as follows Figure 4C As shown, the exposed semiconductor substrate 301 is etched to form a second groove 306 using the second nitride layer 305 as a self-alignment condition.

[0156] Figure 4D for Figure 4C An enlarged view of the region surrounding the first gate trench 303 in the image, which will be shown below. Figure 4D The enlarged view of the area shown is described.

[0157] Step 5, as follows Figure 4E As shown, a third tunneling oxide layer 307 is formed on the inner surface of the second groove 306 on the second side and bottom of the second nitride layer 305.

[0158] Step Six, as Figure 4E As shown, a metal floating gate 308 is formed by self-alignment on the second side of the third tunneling oxide layer 307, and the metal floating gate 308 and the semiconductor substrate 301 are isolated by the third tunneling oxide layer 307.

[0159] In the method of this invention embodiment, the material of the metal floating grid 308 includes TiN.

[0160] The metal floating gate 308 is constructed by depositing a metal layer and then etching the metal layer, and the metal floating gate 308 is composed of the metal layer retained on the second side of the third tunneling oxide layer 307 after etching.

[0161] Step 7, as follows Figure 4F As shown, a fourth oxide layer 309 is formed, which covers the surface of the third tunneling oxide layer 307 exposed in the second side of the metal floating gate 308 and the second groove 306; a fifth nitride layer 310, a sixth oxide layer 311 and a seventh nitride layer 312 are sequentially formed on the surface of the fourth oxide layer 309.

[0162] Step 8, as Figure 4G As shown, the seventh nitride layer 312, the sixth oxide layer 311, the fifth nitride layer 310, the fourth oxide layer 309, and the third tunneling oxide layer 307 are sequentially etched. The fourth oxide layer 309, the fifth nitride layer 310, the sixth oxide layer 311, and the seventh nitride layer 312, which remain on the second side of the metal floating gate 308 after etching, are stacked to form a second sidewall. The second sidewall is formed by stacking a first sidewall and a second sidewall. The first sidewall is formed by stacking the fourth oxide layer 309 and the fifth nitride layer 310, and the second sidewall is formed by stacking the sixth oxide layer 311 and the seventh nitride layer 312.

[0163] The sidewall structure of the metal floating gate is an ONO-metal floating gate 308-ONON structure, where O represents an oxide layer and N represents a nitriding layer. The nitriding layers on both sides of the metal floating gate 308 are used to reduce the oxygen content on both sides of the metal floating gate 308, thereby protecting the material properties of the metal floating gate 308.

[0164] A metal floating gate sidewall structure is formed on both sides of the first gate trench 303.

[0165] like Figure 3 As shown, after step eight is completed, the following also includes:

[0166] A control gate 313 is formed in the region between the two metal floating gate sidewall structures within the first gate trench 303; the top surface of the metal floating gate 308 is higher than the top surface of the control gate 313.

[0167] After the control gate 313 is formed, the following is also included:

[0168] The first inter-gate dielectric layer 314 is formed.

[0169] An eraser gate 315 is formed, which is located above the top surface of the metal floating gate 308, and the first inter-gate dielectric layer 314 is isolated between the metal floating gate 308 and the eraser gate 315.

[0170] Before the control gate 313 is formed, the process further includes: performing source region implantation to form a source region in the surface region of the semiconductor substrate 301 at the bottom of the second recess 306, with the bottom of the control gate 313 contacting the source region. The source region implantation can be performed before the formation of the control gate 313 as needed, for example, after the second recess 306 is formed.

[0171] After the word line gate 302 is formed, further comprising: performing a drain region implant to form a drain region self-aligned in a surface region of the semiconductor substrate 301 outside a first side of the word line gate 302. The drain region implant can be inserted in a step after the word line gate 302 is formed, for example, after the erase gate 315 is formed, to form the drain region with the first side of the word line gate 302 as a self-alignment condition.

[0172] In the embodiment method of the present application, the first oxide layer 304 is formed by HTO process.

[0173] The second nitride layer 305 is formed by ALD process.

[0174] The third tunneling oxide layer 307 is formed by HTO process.

[0175] The fourth oxide layer 309 is formed by ALD process.

[0176] The fifth nitride layer 310 is formed by ALD process.

[0177] The sixth oxide layer 311 is formed by HTO process.

[0178] The seventh nitride layer 312 is formed by ALD process.

[0179] In some embodiment methods, the depth of the second recess 306 is

[0180] The thickness of the second nitride layer 305 is

[0181] The thickness of the third tunneling oxide layer 307 is

[0182] The thickness of the metal floating gate 308 is

[0183] The thickness of the fourth oxide layer 309 is

[0184] The thickness of the fifth nitride layer 310 is

[0185] The thickness of the sixth oxide layer 311 is

[0186] The thickness of the seventh nitride layer 312 is

[0187] The application is described in detail above with specific embodiments, but these do not constitute a limitation on the application. Those skilled in the art can make many modifications and improvements without departing from the principles of the application, and these should also be considered as within the scope of protection of the application.

Claims

1. A metal floating gate memory, characterized by: A metal floating gate sidewall structure is formed in a first gate trench which opens a semiconductor substrate surface at a bottom; The metal floating gate sidewall structure includes: A first oxide layer and a second nitride layer are self-aligned to the side of the first gate trench, the first oxide layer and the second nitride layer are stacked to form a first side spacer; A second recess is formed by etching the semiconductor substrate at a bottom with a second side of the second nitride layer as a self-aligned condition; A third tunneling oxide layer is self-aligned to the second side of the second nitride layer and the side of the second recess at the bottom and extends to the bottom surface of the second recess; A metal floating gate is self-aligned to the second side of the third tunneling oxide layer, the metal floating gate is isolated from the semiconductor substrate by the third tunneling oxide layer; A second side spacer is formed on the second side of the metal floating gate, the second side spacer is stacked by a first layer spacer and a second layer spacer, the first layer spacer is stacked by a fourth oxide layer and a fifth nitride layer, the second layer spacer is stacked by a sixth oxide layer and a seventh nitride layer; The metal floating gate sidewall structure is in an ONO-metal floating gate-ONN structure, O represents an oxide layer, and N represents a nitride layer, the nitride layers on both sides of the metal floating gate are used to reduce the oxygen content on both sides of the metal floating gate, thereby protecting the material properties of the metal floating gate. The material of the metal floating gate includes TiN.

2. The metal floating gate memory of claim 1, wherein: The metal floating gate memory further includes a word line gate formed on the surface of the semiconductor substrate, the word line gate is stacked by a first gate dielectric layer and a second gate conductive material layer; 3. The metal floating gate memory of claim 2, wherein: The first gate trench is composed of an interval between two adjacent second sides of the word line gate; A drain region is self-aligned to the surface region of the semiconductor substrate outside the first side of the word line gate. One metal floating gate sidewall structure is formed on both sides of the first gate trench; 4. The metal floating gate memory of claim 3, wherein: A control gate is formed in the region between the two metal floating gate sidewall structures in the first gate trench; the top surface of the metal floating gate is higher than the top surface of the control gate; A source region is formed in the surface region of the semiconductor substrate at the bottom of the second recess, the bottom of the control gate is in contact with the source region.

5. The metal floating gate memory of claim 2, wherein: The first oxide layer is an HTO oxide layer formed by an HTO process; The second nitride layer is an ALD nitride layer formed by an ALD process; The third tunneling oxide layer is an HTO oxide layer; The fourth oxide layer is an ALD oxide layer formed by an ALD process; The fifth nitride layer is an ALD nitride layer; The sixth oxide layer is an HTO oxide layer; The seventh nitride layer is an ALD nitride layer. An erase gate is formed above the top surface of the metal floating gate, and a first gate dielectric layer is isolated between the metal floating gate and the erase gate.

6. The metal floating gate memory as claimed in claim 2, wherein: a depth of the second groove is 7. The metal floating gate memory as claimed in claim 4, wherein: The metal floating gate memory has a metal floating gate sidewall structure, and the formation steps of the metal floating gate sidewall structure include:

8. A method of fabricating a metal floating gate memory, characterized by: ​ Step one, forming a first gate trench, which opens the bottom semiconductor substrate surface; Step two, sequentially forming a first oxide layer and a second nitride layer, the first oxide layer is formed on the side and bottom surface of the first gate trench and the outside surface of the first gate trench, the second nitride layer is formed on the surface of the first oxide layer; Step three, overall etching the second nitride layer, so that the second nitride layer is only reserved on the second side of the first oxide layer at the side of the first gate trench; the first side spacer is formed by the superposition of the first oxide layer and the second nitride layer; Step four, etching the exposed semiconductor substrate with the second nitride layer as a self-aligned condition to form a second groove; Step five, forming a third tunneling oxide layer, which is formed on the second side and the inside surface of the second groove of the second groove at the bottom; Step six, forming a metal floating gate on the second side of the third tunneling oxide layer in self-alignment, which is isolated from the semiconductor substrate by the third tunneling oxide layer; Step seven, forming a fourth oxide layer, which covers the second side of the metal floating gate and the surface of the third tunneling oxide layer exposed in the second groove; sequentially forming a fifth nitride layer, a sixth oxide layer and a seventh nitride layer on the surface of the fourth oxide layer; Step eight, sequentially overall etching the seventh nitride layer, the sixth oxide layer, the fifth nitride layer, the fourth oxide layer and the third tunneling oxide layer, and forming a second side spacer by the superposition of the fourth oxide layer, the fifth nitride layer, the sixth oxide layer and the seventh nitride layer reserved on the second side of the metal floating gate after etching, the second side spacer is formed by the superposition of a first layer side wall and a second layer side wall, the first layer side wall is formed by the superposition of the fourth oxide layer and the fifth nitride layer, and the second layer side wall is formed by the superposition of the sixth oxide layer and the seventh nitride layer; The metal floating gate side wall structure is in an ONO-metal floating gate-ONN structure, O represents an oxide layer, and N represents a nitride layer, the nitride layers on both sides of the metal floating gate are used to reduce the oxygen content on both sides of the metal floating gate, thereby protecting the material properties of the metal floating gate.

9. The method for manufacturing a metal floating gate memory as described in claim 8, characterized in that: The material of the metal floating gate includes TiN.

10. The method of claim 9, wherein: the metal floating gate is formed by depositing a metal layer on the substrate; and the metal floating gate is formed by etching the metal layer to form the metal floating gate. 5 In step one, it also includes forming a word line gate on the surface of the semiconductor substrate, and the forming steps include: sequentially forming a first gate dielectric layer and a second gate conductive material layer on the surface of the semiconductor substrate; performing patterned etching on the second gate conductive material layer and the first gate dielectric layer to form the word line gate by the superposition of the etched first gate dielectric layer and the second gate conductive material layer; The first gate trench is composed of the interval between the second sides of two adjacent word line gates.

11. The method of claim 10, wherein: the metal floating gate is formed by depositing a metal layer on the substrate; and the metal floating gate is formed by patterning the metal layer. One metal floating gate side wall structure is formed on each side of the first gate trench; after step eight is completed, it also includes: a control gate is formed in a region between two of the metal floating gate sidewall structures within the first gate trench; a top surface of the metal floating gate is higher than a top surface of the control gate.

12. The method of claim 9, wherein: the first oxide layer is an HTO oxide layer formed by an HTO process; the second nitride layer is an ALD nitride layer formed by an ALD process; the third tunneling oxide layer is an HTO oxide layer; the fourth oxide layer is an ALD oxide layer formed by an ALD process; the fifth nitride layer is an ALD nitride layer; the sixth oxide layer is an HTO oxide layer; the seventh nitride layer is an ALD nitride layer.

13. The method for manufacturing a metal floating gate memory as described in claim 9, characterized in that: a depth of the second groove is 14. The method of claim 11, wherein: the metal floating gate is formed by a process selected from the group consisting of: sputtering, evaporation, and electroplating. 5 after the control gate is formed, further comprising: forming a first gate-to-gate dielectric layer; forming an erase gate over a top surface of the metal floating gate, the metal floating gate and the erase gate separated by the first gate-to-gate dielectric layer.

15. The method for manufacturing a metal floating gate memory as described in claim 14, characterized in that: before the control gate is formed, further comprising performing a source region implant to form a source region in a surface region of the semiconductor substrate at a bottom of the second recess, a bottom of the control gate in contact with the source region; after the word line gate is formed, further comprising performing a drain region implant to form a drain region in a surface region of the semiconductor substrate self-aligned to a first side of the word line gate.

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