Method for manufacturing a floating gate split-gate flash memory

Abstract

This application discloses a method for manufacturing a floating-gate split-gate flash memory device, belonging to the field of semiconductor devices and manufacturing. This method eliminates the P-type implantation originally used to increase the threshold voltage of the select transistor. Instead, after forming the select gate dielectric layer, a portion of the select gate polysilicon is first deposited, followed by a P-type self-aligned implantation in the select gate device region. While ensuring that the threshold voltage of the select transistor remains substantially unchanged, the P-type impurity content and depth in the substrate silicon below the select transistor are increased, while the P-type impurity content in the substrate silicon near the LDD junction below the floating gate is reduced, thereby increasing the potential barrier of the substrate silicon below the select transistor while maintaining substantially the same impact ionization intensity in the substrate silicon below the floating gate, effectively improving the reliability of the split-gate floating-gate flash memory device.

Description

Technical Field

[0001] The present application relates to the field of semiconductor devices and manufacturing, and in particular to a method for manufacturing a floating gate split-gate flash memory. Background Art

[0002] Split-gate floating-gate (FG) flash memory technology is widely used in various embedded electronic products such as financial IC cards and automotive electronics. This flash memory can improve storage integration density, save chip area and reduce manufacturing costs.

[0003] like Figures 1 to 7 The existing method for manufacturing a 2-bit / cell (two bits per storage cell) split-gate floating gate flash memory includes the following steps:

[0004] In step 1, a P-type well 101 is formed by implantation on a P-type substrate, a floating gate oxide 102 is grown on the P-type well 101 by thermal oxidation, and a floating gate polysilicon layer 103 and a first silicon nitride layer 502 are deposited. A shallow trench 503 is formed by an STI (Shallow-Trench-Isolation) process. At the same time, the active areas of the flash memory and the peripheral logic area are defined.

[0005] Step 2: Deposit an inter-polysilicon ONO (Oxide-Nitride-Oxide, oxide / nitride / oxide) layer 104, a control gate polysilicon layer 105, and a thick silicon nitride layer 501 in sequence; define the flash memory cell area by photolithography, and etch away the thick silicon nitride layer in the opening area.

[0006] Step three: depositing a silicon oxide layer and forming a first spacer dielectric layer 106 by anisotropic etching. The bottom width of the first spacer dielectric layer defines the length of the control gate.

[0007] Step 4: Using the thick silicon nitride layer 501 and the first spacer dielectric layer 106 as hard masks, anisotropically etch the inter-polysilicon ONO layer 104 and the control gate polysilicon layer 105 to form a self-aligned control gate.

[0008] In step five, an insulating dielectric layer is deposited and anisotropically etched to form a second spacer dielectric layer 108. Using the second spacer dielectric layer 108 and the first spacer dielectric layer 106 as a hard mask, a self-aligned etching is performed to form a floating gate. P-type ion implantation is then performed to increase the select transistor threshold voltage, forming a P-type implant region 116.

[0009] Step 6: Deposit the select gate dielectric layer 109 and the select gate polysilicon layer 110 in sequence, and form a self-aligned select gate by chemical mechanical polishing (CMP).

[0010] In step seven, a protective dielectric layer 111 is formed on the select gate polysilicon layer 110 by thermal oxidation, and the first sidewall dielectric layer 106 and the select gate dielectric layer 109 are used as a hard mask to remove the remaining thick silicon nitride layer 501, the control gate polysilicon layer 105, the inter-polysilicon ONO layer 104, and the floating gate polysilicon layer 103 on both sides. LDD implantation is then performed to form an LDD region 112, and the third sidewall deposition and etching and source and drain implantation are then performed to form a source and drain region 114.

[0011] Split-gate floating-gate flash memory devices manufactured using existing manufacturing processes experience severe MPT (Mass Punch Through) interference during user mode testing in the 01 state, with BL1 = BL2 = 4.5V. This is because at 4.5V, a strong electric field is generated in the substrate silicon near the LDD junction below the floating gate in the 0 state, causing impact ionization and the generation of hot electrons. The high-energy hot electrons cross the potential barrier of the substrate silicon below the select transistor and are injected into the floating gate on the other side, causing strong interference to the bit in the same cell in the 1 state. Therefore, how to improve the reliability of split-gate floating-gate flash memory is an issue that requires further optimization. Summary of the Invention

[0012] The present application provides a method for manufacturing a floating gate split gate flash memory, which can solve the problem of needing to improve the reliability of split gate floating gate flash memories in related technologies.

[0013] The present invention provides a method for manufacturing a floating gate split-gate flash memory, comprising:

[0014] Step 11: implanting a P-type well 101 on the P-type substrate, growing a floating gate oxide 102 on the P-type well 101 by thermal oxidation, depositing a floating gate polysilicon layer 103 and a first silicon nitride layer 502, and performing an STI process to form a shallow trench 503;

[0015] Step 12: depositing the inter-polysilicon ONO layer 104, the control gate polysilicon layer 105, and the thick silicon nitride layer 501 in sequence, and etching away the thick silicon nitride layer in the opening area;

[0016] Step 13: depositing a silicon oxide layer and forming a first spacer dielectric layer 106 by anisotropic etching;

[0017] Step 14: using the thick silicon nitride layer 501 and the first spacer dielectric layer 106 as hard masks, anisotropically etching the inter-polysilicon ONO layer 104 and the control gate polysilicon layer 105 to form a self-aligned control gate;

[0018] Step 15: depositing an insulating dielectric layer and anisotropically etching to form a second spacer dielectric layer 108; using the second spacer dielectric layer 108 and the first spacer dielectric layer 106 as hard masks, self-aligned etching to form a floating gate;

[0019] Step 16: depositing a select gate dielectric layer 109 and a first select gate polysilicon layer 110-1. Using the first select gate polysilicon layer 110-1, the select gate dielectric layer 109, the second spacer dielectric layer 108, the first spacer dielectric layer 106, and the thick silicon nitride layer 501 as a hard mask, a P-type implant region 111 is formed in the select tube region by self-aligned implantation.

[0020] Step 17: depositing a second layer of select gate polysilicon 110 - 2 and forming a self-aligned select gate by CMP;

[0021] Step 18: Thermally oxidize the first select gate polysilicon layer 110-1 and the second select gate polysilicon layer 110-2 to form a protective dielectric layer 112. Using the protective dielectric layer 112, the first spacer dielectric layer 106, and the select gate dielectric layer 109 as a hard mask, the remaining thick silicon nitride layer 501, the control gate polysilicon layer 105, the inter-polysilicon ONO layer 104, and the floating gate polysilicon layer 103 on both sides are removed.

[0022] In step nineteen, lightly doped drain ion implantation is sequentially performed to form the LDD region 113 , the third sidewall spacer 114 is formed, and heavily doped source and drain ion implantation is performed to form the source and drain region 115 .

[0023] Optionally, in step 11, active areas of the flash memory and the peripheral logic area are defined simultaneously.

[0024] Optionally, in the step 12, a flash memory cell area is also defined by photolithography, and the opening area is located at the opening of the flash memory cell area.

[0025] Optionally, the bottom width of the first spacer dielectric layer 106 defines the length of the control gate.

[0026] Optionally, the thickness of the first layer of select gate polysilicon 110 - 1 is 5 to 25 nm.

[0027] Optionally, the P-type injection process at the selection tube area is to pass through the first layer of selection gate polysilicon 110-1 and the selection gate dielectric layer 109 into the P-type substrate, and the lateral distribution range of the P-type injected impurities in the substrate is determined by the thickness of the first layer of selection gate polysilicon 110-1.

[0028] Optionally, the P-type implanted impurity is BF2 with an energy range of 80 to 200 KeV and a dose of 5.0e12 to 5.0e13 cm -2 , the angle is 0°.

[0029] The technical solution of this application has at least the following advantages:

[0030] The present application proposes an improved method for manufacturing a floating-gate split-gate flash memory device. The method eliminates the P-type implantation originally used to increase the threshold voltage of the select transistor. Instead, after forming the select gate dielectric layer, a portion of the select gate polysilicon is first deposited, and then a P-type self-aligned implantation is performed in the select gate device region. The lateral distribution range of the P-type implanted impurities is determined by the deposition thickness of the select gate polysilicon. In this way, while ensuring that the threshold voltage of the select transistor remains substantially unchanged, the P-type impurity content and depth in the substrate silicon below the select transistor are increased, and the P-type impurity content in the substrate silicon near the LDD junction below the floating gate is reduced, thereby increasing the potential barrier of the substrate silicon below the select transistor. At the same time, the impact ionization intensity in the substrate silicon below the floating gate remains substantially unchanged, effectively reducing the MPT interference of the split-gate floating gate, and thereby improving the reliability of the split-gate floating gate flash memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the following is a brief introduction to the drawings required for use in the specific implementation methods or the description of the prior art. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0032] Figures 1 to 7 A diagram showing the process steps of a floating gate split-gate flash memory in the prior art;

[0033] Figures 8 to 11 This is a process step diagram of a floating gate split-gate flash memory provided by an exemplary embodiment of the present application. DETAILED DESCRIPTION

[0034] The following is a clear and complete description of the nine technical solutions in this application, combined with the accompanying drawings. Obviously, the embodiments described are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of this application.

[0035] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely to facilitate the description of this application and simplify the description. They do not indicate or imply that the devices or components referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0036] In the description of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "installed," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; they can refer to internal connections between two components; they can refer to wireless connections or wired connections. Those skilled in the art will understand the specific meanings of the above terms in this application based on the specific circumstances.

[0037] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0038] The manufacturing method of the floating gate type split gate flash memory of the present invention comprises the following steps:

[0039] Step 11 (same as step 1), if Figure 1 As shown, a P-type well 101 is formed by implantation on a P-type substrate, a floating gate oxide 102 is grown on the P-type well 101 by thermal oxidation, a floating gate polysilicon layer 103 and a first silicon nitride layer 502 are deposited, and a shallow trench 503 is formed by an STI process.

[0040] The active areas of the flash memory and the peripheral logic area are defined at the same time.

[0041] Step 12 (same as step 2), if Figure 2 As shown, an inter-polysilicon ONO layer 104, a control gate polysilicon layer 105, and a thick silicon nitride layer 501 are sequentially deposited, and the thick silicon nitride layer in the opening area is etched away.

[0042] The flash memory cell region is also defined by photolithography, and the opening region is located at the opening of the flash memory cell region.

[0043] Step 13 (same as step 3), if Figure 3 As shown, a silicon oxide layer is deposited, and a first spacer dielectric layer 106 is formed by anisotropic etching.

[0044] The bottom width of the first spacer dielectric layer 106 defines the length of the control gate. Figure 4 The remaining portion of the control gate polysilicon layer 105 is removed.

[0045] Step 14 (same as step 4), if Figure 4 As shown, the thick silicon nitride layer 501 and the first spacer dielectric layer 106 are used as hard masks to anisotropically etch the inter-polysilicon ONO layer 104 and the control gate polysilicon layer 105 to form a self-aligned control gate.

[0046] The control gate is specifically Figure 4 The remaining portion of the control gate polysilicon layer 105 is removed.

[0047] Step 15: Figure 8 As shown, an insulating dielectric layer is deposited and anisotropically etched to form a second spacer dielectric layer 108 . The second spacer dielectric layer 108 and the first spacer dielectric layer 106 are used as hard masks to form a floating gate by self-aligned etching.

[0048] The floating gate is Figure 8 The remaining portion of the floating gate polysilicon layer 103.

[0049] Step 16: Figure 9 As shown, a select gate dielectric layer 109 and a first select gate polysilicon layer 110-1 are deposited, and the first select gate polysilicon layer 110-1, the select gate dielectric layer 109, the second spacer dielectric layer 108, the first spacer dielectric layer 106 and the thick silicon nitride layer 501 are used as hard masks to form a P-type implantation region 111 in the select tube region.

[0050] The thickness of the first layer of select gate polysilicon 110-1 is 5 to 25 nm. The P-type implantation process in the select tube region is to penetrate the first layer of select gate polysilicon 110-1 and the select gate dielectric layer 109 into the P-type substrate. The thickness of the first layer of select gate polysilicon 110-1 determines the lateral distribution range of the P-type implanted impurities in the substrate. The P-type implanted impurity is BF2, with an energy range of 80 to 200 KeV and a dose of 5.0e12 to 5.0e13 cm -2 , the angle is 0°.

[0051] Step 17: Figure 10 As shown, a second layer of select gate polysilicon 110 - 2 is deposited, and a self-aligned select gate is formed by CMP.

[0052] Step 18, such as Figure 11As shown, a protective dielectric layer 112 is formed by thermal oxidation on the first layer of select gate polysilicon 110-1 and the second layer of select gate polysilicon 110-2, and the protective dielectric layer 112, the first sidewall dielectric layer 106 and the select gate dielectric layer 109 are used as hard masks to remove the remaining thick silicon nitride layer 501, the control gate polysilicon layer 105, the inter-polysilicon ONO layer 104 and the floating gate polysilicon layer 103 on both sides.

[0053] Step 19, continue as Figure 11 As shown, lightly doped drain ion implantation is performed in sequence to form the LDD region 113 , the third sidewall 114 is formed, and heavily doped source and drain ion implantation is performed to form the source and drain region 115 .

[0054] In summary, the present application proposes an improved method for manufacturing a floating gate split-gate flash memory device, which cancels the P-type implantation originally used to increase the threshold voltage of the select tube. Instead, after forming the select gate dielectric layer, a portion of the select gate polysilicon is first deposited, and then a P-type self-aligned implantation is performed in the select gate device area. The lateral distribution range of the P-type implanted impurities is determined by the deposition thickness of the select gate polysilicon. In this way, while ensuring that the threshold voltage of the select tube remains basically unchanged, the P-type impurity content and depth in the substrate silicon below the select tube are increased, and the P-type impurity content in the substrate silicon near the LDD junction below the floating gate is reduced, thereby achieving an increase in the potential barrier of the substrate silicon below the select tube. At the same time, the impact ionization intensity in the substrate silicon below the floating gate remains basically unchanged, effectively reducing the MPT interference of the split-gate floating gate, thereby improving the reliability of the split-gate floating gate flash memory.

[0055] Obviously, the above embodiments are merely examples for clarity of explanation and are not intended to limit the implementation methods. Those skilled in the art will appreciate that other variations or modifications can be made based on the above description. It is not necessary and impossible to enumerate all implementation methods here. Obvious variations or modifications arising therefrom remain within the scope of protection of this application.

Claims

1. A method for manufacturing a floating gate split-gate flash memory, characterized in that: include: Step 11, implanting a P-type well on the P-type substrate, growing a floating gate oxide by thermal oxidation on the P-type well, depositing a polysilicon layer and a first silicon nitride layer, and performing an STI process to form a shallow trench; Step 12: depositing an inter-polysilicon ONO layer, a control gate polysilicon layer, and a thick silicon nitride layer in sequence, and etching away the thick silicon nitride layer in the opening area; Step 13: depositing a silicon oxide layer and forming a first sidewall dielectric layer by anisotropic etching; Step 14: using the thick silicon nitride layer and the first spacer dielectric layer as a hard mask, anisotropically etching the inter-polysilicon ONO layer and the control gate polysilicon layer to form a self-aligned control gate; Step 15: depositing an insulating dielectric layer, and anisotropically etching to form a second spacer dielectric layer, using the second spacer dielectric layer and the first spacer dielectric layer as a hard mask, and self-aligning etching to form a floating gate; Step 16: depositing a select gate dielectric layer and a first layer of select gate polysilicon, using the first layer of select gate polysilicon, the select gate dielectric layer, the second spacer dielectric layer, the first spacer dielectric layer, and the thick silicon nitride layer as a hard mask to form a P-type implantation region in the select tube region by self-aligned implantation; Step 17: depositing a second layer of select gate polysilicon and forming a self-aligned select gate by CMP; Step 18: Thermally oxidizing the first select gate polysilicon layer and the second select gate polysilicon layer to form a protective dielectric layer, and using the protective dielectric layer, the first sidewall dielectric layer, and the select gate dielectric layer as a hard mask to remove the remaining thick silicon nitride layer, the control gate polysilicon layer, the inter-polysilicon ONO layer, and the floating gate polysilicon layer on both sides; Step 19: performing lightly doped drain ion implantation to form an LDD region, forming a third sidewall, and heavily doped source and drain ion implantation to form a source and drain region in sequence.

2. The method for manufacturing a floating gate split-gate flash memory according to claim 1, wherein: In the step eleven, active areas of the flash memory and the peripheral logic area are defined simultaneously.

3. The method for manufacturing a floating gate split-gate flash memory according to claim 1, wherein: In the step 12, a flash memory cell region is also defined by photolithography, and the opening region is located at the opening of the flash memory cell region.

4. The method for manufacturing a floating gate split-gate flash memory according to claim 1, wherein: The bottom width of the first spacer dielectric layer defines the length of the control gate.

5. The method for manufacturing a floating gate split-gate flash memory according to claim 1, wherein: The thickness of the first layer of select gate polysilicon is 5-25 nm.

6. The method for manufacturing a floating gate split-gate flash memory according to claim 1, wherein: The P-type injection process at the selection tube area is to pass through the first layer of selection gate polysilicon and the selection gate dielectric layer into the P-type substrate, and the lateral distribution range of the P-type injection impurities is determined by the thickness of the first layer of selection gate polysilicon.

7. The method for manufacturing a floating gate split-gate flash memory according to claim 1 or 6, wherein: The P-type implanted impurity is BF2, with an energy range of 80 to 200 KeV and a dose of 5.0e12 to 5.0e13 cm -2 , the angle is 0°.

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