Conveying method and processing system

Abstract

A method for carrying a plurality of substrates to be continuously processed from a carrying section to a processing section in a processing system provided with at least one processing section for performing a desired process on a substrate and the carrying section for carrying the substrate to the processing section, in which method an adjustment value for arbitrarily changing a processing time for each of the plurality of substrates is assigned to the substrate in advance, the method comprising the steps of: acquiring the adjustment value assigned to a first substrate for this time processing; acquiring a reference adjustment value assigned to a reference substrate processed before the first substrate; acquiring an actual processing time, i.e., an actual time, for processing the reference substrate; calculating a predicted processing time for the first substrate by reflecting a difference between the adjustment value assigned to the first substrate and the reference adjustment value into the actual time; and adjusting a carrying timing of a second substrate processed after the first substrate based on the calculated predicted processing time.

Description

Technical Field

[0001] This disclosure relates to a substrate conveying method and processing system. Background Technology

[0002] Patent Document 1 discloses a gas processing apparatus comprising: a chamber for performing desired gas processing on a substrate housed inside the chamber; a conveying mechanism for continuously conveying multiple substrates to the chamber; and a control mechanism for controlling the introduction of the processing gas and the operation of the conveying mechanism to introduce the processing gas into the chamber before the substrate is moved into the chamber, and to move the substrate into the chamber after a predetermined time.

[0003] Existing technical documents

[0004] Patent documents

[0005] Patent Document 1: Japanese Patent Application Publication No. 2008-160000 Summary of the Invention

[0006] The problem the invention aims to solve

[0007] The technology disclosed herein appropriately adjusts the transport timing of multiple substrates to be processed continuously in a substrate processing apparatus in order to efficiently perform substrate processing in the substrate processing apparatus.

[0008] Solution for solving the problem

[0009] One aspect of this disclosure is a method for continuously transporting multiple substrates to be processed from a transport unit to a processing unit in a processing system having at least one processing unit that performs a desired processing on a substrate and a transport unit that transports the substrates to the processing unit. In this method, adjustment values ​​for arbitrarily changing the processing time for each of the multiple substrates are pre-assigned. The method includes the following steps: obtaining the adjustment value assigned to a first substrate being processed; obtaining a reference adjustment value assigned to a reference substrate that was processed before the first substrate; obtaining the actual processing time, i.e., the actual time, performed on the reference substrate; calculating a predicted processing time for the first substrate by reflecting the difference between the adjustment value assigned to the first substrate and the reference adjustment value into the actual time; and adjusting the transport timing of a second substrate being processed after the first substrate based on the calculated predicted processing time.

[0010] The effects of the invention

[0011] According to this disclosure, the transport timing of multiple substrates to be processed continuously in a substrate processing apparatus is appropriately adjusted to efficiently perform substrate processing in the substrate processing apparatus. Attached Figure Description

[0012] Figure 1 This is a top view showing an outline of the structure of the substrate processing apparatus according to this embodiment.

[0013] Figure 2 This is a flowchart illustrating the main steps of the timing control method for wafer transport involved in this embodiment.

[0014] Figure 3 This is an explanatory diagram showing the details of the process information recorded in the process database.

[0015] Figure 4 This is an explanatory diagram schematically illustrating the wafer transport scenario involved in this embodiment. Detailed Implementation

[0016] Previously, a vacuum processing apparatus was known for transporting semiconductor wafers (substrates: hereinafter referred to as "wafers") in a vacuum atmosphere and performing various vacuum treatments on the wafers. In this vacuum processing apparatus, multiple wafers transported into the apparatus are sequentially and continuously transported between various processing modules and subjected to various vacuum treatments.

[0017] Patent Document 1 disclosed a gas processing apparatus that sequentially performs vacuum processing, COR (Chemical Oxide Removal) processing, and PHT (Post Heat Treatment) processing on wafers. According to the gas processing apparatus described in Patent Document 1, wafer transport is controlled by instructions from a process controller to continuously transport multiple wafers to various processing chambers (processing modules).

[0018] In the handling of the wafer and various vacuum processes, it is necessary to control the timing of wafer handling for various processing modules to shorten the wafer processing standby time and suppress the decline in productivity in the vacuum processing unit.

[0019] In the timing control of this wafer transport, the "actual process time" (hereinafter sometimes simply referred to as "actual time") has been conventionally used. This "actual process time" is obtained by storing the measurement time during which a vacuum process (process) was performed on a wafer that was previously processed (hereinafter referred to as "previous wafer") before the wafer to be timed (hereinafter referred to as "current wafer"). Specifically, by using the actual time of the previous wafer that underwent the process, the time required for the current wafer to undergo the same process is predicted, and the transport timing of the current wafer is controlled based on the timing of the process's end, thereby optimizing wafer transport.

[0020] Furthermore, the "actual time" used for timing control during wafer transfer includes, for example, data (hereinafter referred to as "variable data") for adjusting the processing time of the target process for the current wafer based on the processing results of the previous wafer's preceding process and the processing results of the target process of the previous wafer. This variable data is set to be allocated to each of the multiple wafers to be transferred into the vacuum processing unit, for example, through manual input by the operator or automatic input based on the processing results of the preceding process.

[0021] However, the aforementioned conventional wafer handling timing control method does not take into account the variable data allocated to each wafer. If this variable data differs between the previous wafer and the current wafer, productivity may decrease. Specifically, as described above, the wafer handling timing is controlled based on the actual time of the previous wafer. However, this assumes that the variable data for the previous and current wafers are the same, making it impossible to accurately predict the handling timing. This could lead to processing downtime, causing a decrease in productivity. Furthermore, Patent Document 1 does not address this productivity decrease caused by different variable data, leaving room for improvement in this regard.

[0022] The technology disclosed herein was developed in view of the above circumstances, by appropriately adjusting the transport timing of multiple substrates to be processed continuously in a substrate processing apparatus, so as to efficiently perform substrate processing in the substrate processing apparatus. Hereinafter, a vacuum processing apparatus according to one embodiment and a wafer transport method according to this embodiment will be described with reference to the accompanying drawings. Furthermore, in this specification and the accompanying drawings, elements having substantially the same functional structure are labeled with the same reference numerals, thereby omitting repeated descriptions.

[0023] Vacuum Processing Equipment

[0024] First, the structure of a vacuum processing apparatus according to one embodiment will be described. Figure 1 This is a top view schematically showing the outline of the structure of the vacuum processing apparatus 1. In this embodiment, the vacuum processing apparatus 1 is described as an example having a COR module and a PHT module as processing modules. However, the structure of the various processing modules included in the vacuum processing apparatus 1 of this disclosure is not limited to this, and can be arbitrarily selected.

[0025] like Figure 1 As shown, the vacuum processing apparatus 1 has an atmospheric section 10 and a depressurization section 11 connected as a single unit via loading interlock modules 20a and 20b. The atmospheric section 10 includes multiple atmospheric modules for performing desired processing on the wafer W under atmospheric pressure. The depressurization section 11 includes multiple depressurization modules for performing desired processing on the wafer W under depressurized atmosphere.

[0026] The loading interlock module 20a temporarily holds the wafer W to transfer the wafer W from the loading module 30 (described later) in the atmospheric section 10 to the transfer module 60 (described later) in the decompression section 11. The loading interlock module 20a has multiple internal storage sections, such as two (not shown), thereby enabling it to hold two wafers W internally at the same time.

[0027] The loading interlock module 20a is connected to the loading module 30 and the transmission module 60 (described later) via a gate (not shown) equipped with a gate valve (not shown). This gate valve ensures airtightness and connectivity between the loading interlock module 20a, the loading module 30, and the transmission module 60.

[0028] The load interlock module 20a is connected to a gas supply section (not shown) for supplying gas and a gas exhaust section (not shown) for discharging gas, configured such that the interior of the load interlock module 20a can be switched between atmospheric pressure and depressurized atmosphere via the gas supply section and the exhaust section. That is, the load interlock module 20a is configured to allow appropriate transfer of wafer W between the atmospheric pressure section 10 and the depressurized atmosphere section 11.

[0029] Loading interlock module 20b temporarily holds wafer W to transfer wafer W from transfer module 60 to loading module 30. Loading interlock module 20b has the same structure as loading interlock module 20a. That is, it has a gate valve (not shown), a gate (not shown), an air supply section (not shown), and an exhaust section (not shown).

[0030] Furthermore, the number and configuration of the interlocking modules 20a and 20b are not limited to this embodiment and can be set arbitrarily.

[0031] The atmospheric section 10 includes a loading module 30 equipped with a wafer transport mechanism 40 (described later), a loading port 32 for holding a front-opening wafer transport box 31 capable of holding multiple wafers W, a CST module 33 for cooling the wafers W, and a positioning module 34 for adjusting the orientation of the wafers W in the horizontal direction.

[0032] The loading module 30 is composed of a rectangular housing, the interior of which is maintained at atmospheric pressure. Multiple, for example, three loading ports 32 are arranged on one side of the long side of the housing. Loading interlock modules 20a and 20b are arranged on the other side of the long side of the housing. A CST module 33 is arranged on one side of the short side of the housing. A positioning module 34 is arranged on the other side of the short side of the housing.

[0033] Furthermore, the number and configuration of the loading port 32, CST module 33, and positioning module 34 are not limited to this embodiment and can be arbitrarily set. Additionally, the type of atmospheric module provided in the atmospheric section 10 is not limited to this embodiment and can be arbitrarily selected.

[0034] The front-opening wafer transfer box 31 accommodates multiple wafers, for example, a set of 25 wafers W. Furthermore, the interior of the front-opening wafer transfer box 31, located at the loading port 32, is filled and sealed with, for example, atmosphere or nitrogen.

[0035] A wafer transport mechanism 40 for transporting wafers W is provided inside the loading module 30. The wafer transport mechanism 40 includes transport arms 41a and 41b that hold and move the wafer W, a rotary table 42 that rotatably supports the transport arms 41a and 41b, and a rotary mounting stage 43 on which the rotary table 42 is mounted. The wafer transport mechanism 40 is configured to move along its long side inside the housing of the loading module 30.

[0036] The decompression unit 11 includes a transport module 60 for simultaneously transporting two wafers W to various processing modules, a COR module 61 for COR processing of wafers W, and a PHT module 62 for PHT processing of wafers W. The interiors of the transport module 60, COR module 61, and PHT module 62 are maintained in a decompression atmosphere. Furthermore, multiple, for example, three COR modules 61 and three PHT modules 62 are provided for the transport module 60.

[0037] The transfer module 60, serving as the transport unit, is constructed with a rectangular housing. As described above, it is connected to the loading interlock modules 20a and 20b via gate valves (not shown). The transfer module 60 sequentially transports the wafer W, which is being moved into the loading interlock module 20a, to a COR module 61 and a PHT module 62 for COR and PHT processing, respectively. Afterward, the wafer W is moved out to the atmospheric section 10 via the loading interlock module 20b.

[0038] Inside the COR module 61, which serves as the processing unit, are two mounting stages 61a and 61b that hold two wafers W arranged horizontally. The COR module 61 performs COR processing on both wafers W simultaneously by mounting them on the mounting stages 61a and 61b. Furthermore, the COR module 61 is connected to a gas supply section (not shown) for supplying processing gas, purge gas, etc., and an exhaust section (not shown) for discharging gas.

[0039] Inside the PHT module 62, which serves as the processing unit, are two mounting stages 62a and 62b that hold two wafers W arranged horizontally. The PHT module 62 performs PHT processing on both wafers W simultaneously by arranging the wafers W on the mounting stages 62a and 62b. Furthermore, the PHT module 62 is connected to a gas supply section (not shown) for supplying gas and an exhaust section (not shown) for discharging gas.

[0040] In addition, the COR module 61 and PHT module 62 are connected to the transmission module 60 via a gate (not shown) equipped with a gate valve (not shown). This gate valve ensures airtightness between the transmission module 60 and the COR module 61 and PHT module 62, and allows for communication between them.

[0041] Furthermore, the number, configuration, and type of processing modules provided in the transmission module 60 are not limited to this embodiment and can be set arbitrarily.

[0042] A wafer transport mechanism 70 for transporting wafers W is provided inside the transport module 60. The wafer transport mechanism 70 includes transport arms 71a and 71b arranged longitudinally to hold and move two wafers W, a rotary table 72 that rotatably supports the transport arms 71a and 71b, and a rotary mounting stage 73 on which the rotary table 72 is mounted. Additionally, a guide rail 74 extending along the long side of the transport module 60 is provided inside the transport module 60. The rotary mounting stage 73 is mounted on the guide rail 74 and configured to allow the wafer transport mechanism 70 to move along the guide rail 74.

[0043] A control unit 80 is provided in the vacuum processing apparatus 1 described above. The control unit 80 is, for example, a computer equipped with a CPU, memory, etc., and has a program storage unit (not shown). The program storage unit stores programs for controlling the processing of the wafer W in the vacuum processing apparatus 1. Additionally, the program storage unit also stores programs for controlling the operation of the drive systems of the various processing modules, transport mechanisms, etc., described above, to perform timing control of the wafer transport in the vacuum processing apparatus 1, as described later. Specifically, for example, it stores a "wafer transport control task" (described later) for controlling the wafer transport operation, a "process execution control task" (described later) for executing the process in the processing module, and a "process management task" (described later) for managing the process in the processing module, etc. Furthermore, the above programs can be recorded in a computer-readable storage medium H and installed from that storage medium H into the control unit 80.

[0044] <Wafer Transfer Methods>

[0045] The vacuum processing apparatus 1 disclosed herein is configured as described above. Next, wafer processing and wafer transport using the vacuum processing apparatus 1 will be described. Furthermore, in the following description, an example will be given of processing a group (25 wafers) W housed in a front-opening wafer transfer box 31 continuously in pairs. Additionally, regarding the use of "wafers W1 to W" in the following description... 25 “” is a sequence number from 1 to 25 for each wafer W in a group of 25 wafers W, according to the order in which the wafers were processed.

[0046] In addition, in normal wafer processing, multiple COR modules 61 and PHT modules 62 provided in the decompression section 11 are used to process wafers W in parallel. However, in the following description, in order to clarify the timing control of wafer transport, the following description will focus on wafers W1 to W2. 25 The following example illustrates the case where all wafers W are processed using the same COR module 61 and PHT module 62.

[0047] First, a front-opening wafer transfer box 31 containing multiple wafers, in a set (25 wafers), is moved into the loading port 32. When the front-opening wafer transfer box 31 is positioned in the loading port 32, the wafer transport mechanism 40 accesses the front-opening wafer transfer box 31 and removes wafer W1 from it. The positioning module 34 adjusts the horizontal orientation of wafer W1 removed from the front-opening wafer transfer box 31. Then, while adjusting the horizontal orientation of wafer W1, wafer W2 is removed from the front-opening wafer transfer box 31.

[0048] After wafer W1, whose horizontal orientation has been adjusted, is taken out from positioning module 34, wafer W2, which is taken out from front-opening wafer transfer box 31, is moved into positioning module 34 to adjust its horizontal orientation.

[0049] The wafer W1, removed from the positioning module 34, is temporarily held in the storage section (not shown) of the loading interlock module 20a. Similarly, the wafer W2, whose horizontal orientation has been adjusted, is removed from the positioning module 34 and transferred to the storage section (not shown) of the loading interlock module 20a.

[0050] When two wafers W1 and W2 are transferred to the loading interlock module 20a, the internal atmosphere of the loading interlock module 20a is switched from atmospheric pressure to depressurized atmosphere, and then the interior of the loading interlock module 20a is connected to the interior of the transfer module 60. Next, the two wafers W1 and W2 are handed over to the transfer arm 71a of the wafer transfer mechanism 70 and transferred into the transfer module 60.

[0051] The wafer transport mechanism 70, holding two wafers W1 and W2, then moves to the front of a COR module 61. Next, the transport arm 71a enters the interior of the COR module 61 and transfers the two wafers W1 and W2 to the mounting stages 61a and 61b of the COR module 61, respectively. Afterward, the transport arm 71a exits from the COR module 61, and the two wafers W1 and W2 undergo COR processing. Furthermore, in the COR processing according to this embodiment, at least one process is selectively executed from among a plurality of COR processing processes recorded in the process database DB (described later) depending on the purpose.

[0052] When COR processing of two wafers W1 and W2 begins, the next two wafers, W3 and W4, to be processed are taken from the front-opening wafer transfer cassette 31. After being moved into the loading interlock module 20a via the positioning module 34, they are then moved to the front of a COR module 61 via the wafer transfer mechanism 70. The timing control for moving the two wafers W3 and W4 to the COR module 61 is as follows: wafers W3 and W4 arrive at the front of the COR module 61 at the time when the COR processing of the previous wafers, i.e., the two wafers W1 and W2, is completed. That is, the timing control allows for the simultaneous removal of wafers W1 and W2 and the loading of wafers W3 and W4 relative to the COR module 61. Details of the timing control method will be described later.

[0053] Next, when the COR processing for wafers W1 and W2 is completed, the transfer arm 71b of the wafer transfer mechanism 70 enters the COR module 61 and transfers the two wafers W1 and W2 from the mounting stages 61a and 61b to the transfer arm 71b. Then, the transfer arm 71a of the wafer transfer mechanism 70 enters the COR module 61 and transfers the two wafers W3 and W4 from the transfer arm 71b to the mounting stages 61a and 61b. Afterwards, the transfer arm 71a exits the COR module 61, and COR processing is performed on the two wafers W3 and W4.

[0054] Next, the wafer transport mechanism 70, holding two wafers W1 and W2, moves to the front of a PHT module 62. Then, the transport arm 71b enters the PHT module 62, transferring the two wafers W1 and W2 to the mounting stages 62a and 62b of the PHT module 62, respectively. Afterward, the transport arm 71b exits the PHT module 62, and PHT processing is performed on the two wafers W1 and W2. Furthermore, in the PHT processing according to this embodiment, at least one process is selectively executed from a plurality of PHT processing processes recorded in the process database DB (described later) depending on the purpose.

[0055] Next, when the PHT processing for wafers W1 and W2 is completed, the transfer arm 71b of the wafer transfer mechanism 70 enters the interior of the PHT module 62, transferring the two wafers W1 and W2 from the mounting stages 62a and 62b to the transfer arm 71b. At this time, it is preferable to transfer the two wafers W3 and W4, after COR processing, to the mounting stages 62a and 62b of the PHT module 62; that is, it is preferable to simultaneously move wafers W1 and W2 out and wafers W3 and W4 in relative to the PHT module 62. Furthermore, it is more preferable to simultaneously move wafers W3 and W4 out and the two wafers W5 and W6 to be processed next relative to the COR module 61. Moreover, as described above, details of the control method for the transfer timing will be described later.

[0056] When two wafers W1 and W2 are removed from the PHT module 62, the wafer transport mechanism 70, which holds the two wafers W1 and W2, moves to the front of the loading interlock module 20b. Then, the two wafers W1 and W2 are transferred from the transport arm 71b of the wafer transport mechanism 70 to the storage section (not shown).

[0057] When two wafers W1 and W2 are transferred to the loading interlock module 20b, the internal atmosphere of the loading interlock module 20b is switched from depressurized to atmospheric pressure, thus establishing communication between the interior of the loading interlock module 20b and the loading module 30. Next, the two wafers W1 and W2 are transferred to the wafer transport mechanism 40 and then into the loading module 30. Afterward, the loading module 30 stores the two wafers W1 and W2 in the CST module 33 and performs CST processing.

[0058] When the two wafers W1 and W2 transferred to the CST module 33 complete the CST processing for a predetermined time (e.g., 1 minute), the loading module 30 stores the wafers W1 and W2 in the front-opening wafer transfer box 31 mounted on the loading port 32, while the other wafers W3 to W2 are stored in the front-opening wafer transfer box 31 mounted on the loading port 32. 25 Wafers W1 and W2 are in standby mode until the processing is completed.

[0059] In this way, proceed sequentially with all wafers W1 to W2. 25 A series of positioning, COR, PHT, and CST processes are performed. Furthermore, this applies to all wafers W1 to W2. 25 The expected processing is complete, and the final wafer W 25 When the wafer is stored in the front-opening wafer transfer box 31, a series of wafer processing steps in the vacuum processing apparatus 1 are completed.

[0060] The wafer processing and wafer transport in the vacuum processing apparatus 1 according to this embodiment are performed as described above. As mentioned above, it is desirable to control the wafer transport timing so that the previous wafer removal and the current wafer loading are performed simultaneously with respect to a processing module. However, especially when the variable data allocated to each wafer differs between the previous wafer and the current wafer, it may be impossible to accurately predict the end timing of the process in a processing module, thereby making it impossible to properly control the transport timing.

[0061] In this case, if the current wafer is moved to the front of the processing module while the processing of the previous wafer is still in progress, due to an earlier wafer transfer timing, the current wafer will remain idle on the transfer arm 71 of the wafer transfer mechanism 70 until the processing of the previous wafer is completed. Normally, as described above, the vacuum processing apparatus 1 uses multiple processing modules to process multiple wafers W that are moved from multiple front-opening wafer transfer boxes 31 in parallel. Therefore, in the case of the current wafer remaining idle on the transfer arm 71, other wafers W cannot be transferred via the transfer arm 71 during this period. That is, other wafers W cannot be processed during this period, thereby reducing the productivity of the vacuum processing apparatus 1.

[0062] On the other hand, if the wafer transfer timing is delayed and the current wafer is not moved to the front of the processing module even after the previous wafer's process is completed, the previous wafer cannot be removed from the processing module and remains idle inside the processing module. When this idleness occurs, other wafers W cannot be processed by the processing module during this period, resulting in a decrease in productivity. Furthermore, when this idleness occurs inside the processing module, the processing of the previous wafer may over-progress due to the influence of residual gases inside the processing module, potentially leading to unsatisfactory processing results for the previous wafer.

[0063] In such cases, failure to properly control the timing of wafer transport can lead to decreased productivity and poor processing results for previous wafers. Therefore, the timing of wafer transport is preferably within 5 seconds before or after the completion of the process of the previous wafer in the processing module, and more preferably, the current wafer arrives at the front of the processing module approximately at the same time as the completion of the process of the previous wafer.

[0064] Therefore, the details of the control method for the transfer timing of the wafer W in the above-described vacuum processing apparatus 1 will be described. In addition, in the following description, it is assumed that the set time for the COR process in the COR module 61 is t seconds and the set time for the PHT process in the PHT module 62 is T seconds (t < T), that is, the PHT process is longer than the COR process and the processing in the vacuum processing apparatus 1 is speed-limited in the PHT module 62.

[0065] Figure 2 is a flowchart simply showing a series of processes for the timing control of wafer transfer according to the present embodiment. As Figure 2 shown, in the control of the transfer timing according to the present embodiment, the above-described "wafer transfer control task", "process execution control task", and "process management task" are used. In addition, Figure 3 is an explanatory diagram schematically showing the details of the process information recorded in the process database DB.

[0066] First, before the processing of the wafer W in the vacuum processing apparatus 1 starts, according to the wafer transfer control task, a transfer plan ( Figure 2 sequence S1) of the first two wafers W1 and W2 to be processed is constructed.

[0067] When constructing the transfer plan, the variable data V assigned to the two wafers W1 and W is acquired. The variable data V is set for each processing step time of various vacuum processes performed on the wafers W1 and W, and is an adjustment value input for arbitrarily adjusting the execution time of this processing step. By changing this variable data, the execution time of this processing step for any wafer W can be arbitrarily changed.

[0068] In addition, in the present embodiment, it is described by taking the case where the execution time of this processing step for the wafer W is changed by changing the variable data V as an example, but the variable data V can also control other conditions related to the processing of the wafer W, such as the flow rate and temperature of the gas.

[0069] In addition, when constructing the transfer plan, the wafers W1 and W for which the transfer plan is constructed are taken as the current wafers, and the actual process time at the time of the previous wafer transfer for the same process performed on the wafers W1 and W, and the variable data V assigned to the previous wafer are acquired. The actual time and variable data V of the previous wafer are acquired by referring to, for example, the process database DB in which the process management task and the actual time (processing actual measurement time) and variable data V at the previous execution of various processes are paired and recorded.

[0070] When the variable data V of wafers W1 and W2 (this wafer) and the actual time of the previous wafer are obtained, the process processing time required to perform the process on wafers W1 and W2 is then predicted based on the various data obtained in sequence S1. Figure 2 (Sequence S2).

[0071] Specifically, when the variable data V in the previous wafer and the current wafer are different, the process processing time of the previous wafer and the current wafer varies according to the difference in variable data V. That is, for example, if the variable data V of the previous wafer is, for example, 10 seconds and the variable data V of the current wafer is, for example, 20 seconds, it is predicted that the process processing time for the current wafer will be 10 seconds longer than the process processing time of the previous wafer. Therefore, in the timing control of wafer transport according to this embodiment, the process processing time of the current wafer is predicted by the following formula (1).

[0072] The processing time of this wafer [seconds] = the actual time of the previous wafer [seconds] + (the variable data V [seconds] of this wafer - the variable data V [seconds] of the previous wafer) ... (1)

[0073] In this embodiment, the process time of the current wafer is predicted by considering the difference in variable data V between the previous wafer and the current wafer. Then, based on the process time predicted in this way, the transport timing of the current wafer is controlled and adjusted as described later, thereby suppressing the decrease in processing productivity in the vacuum processing apparatus 1 even when the variable data V between wafers W to be processed continuously is different.

[0074] When the process times for wafers W1 and W2 are predicted, the two wafers W1 and W2, for which a transfer plan has been constructed, are started to be moved to various processing modules. Figure 2 The sequence S4), and then perform COR processing and PHT processing in sequence. Figure 2 (Sequence S5). Additionally, during wafer transfer to these various processing modules, the wafer transfer control task provides the process execution control task with variable data V set in the process and various processing data for wafers W1 and W2. Furthermore, wafers W1 and W2 are the first wafers to be processed in the group, therefore no further processing is performed. Figure 2 The timing adjustment of the transport shown in sequence S3.

[0075] When the transfer of two wafers W1 and W2 begins and the processes in various modules commence, a transfer plan is created for the next two wafers W3 and W4 to be processed. Figure 2 The sequence S1) is used to predict the process times of wafers W3 and W4. Figure 2 (Sequence S2).

[0076] The method for constructing the transport plan for wafers W3 and W4 and the prediction of the process processing time are the same as those for wafers W1 and W2. That is, after obtaining the variable data V allocated to wafers W3 and W4, the actual time of the previous wafer recorded in the process database DB, and the variable data V, the process processing time of wafers W3 and W4, which are the current wafers, is predicted based on the above equation (1).

[0077] When the process processing time of wafers W3 and W4 is predicted, the timing of transporting the two wafers W3 and W4 to various processing modules is adjusted based on the constructed transport plan and the transport status (sequence S4) and processing status (sequence S5) of the two previously processed wafers W1 and W2. Figure 2 (Sequence S3).

[0078] The relationship between the transport and processing status (sequences S4 and S5) of two wafers W1 and W2 and the adjustment of the transport timing of two wafers W3 and W4 is explained in detail. Figure 4 This is an explanatory diagram showing the wafer transport process in the vacuum processing apparatus 1 over time.

[0079] When the process times of wafers W1 and W2 are predicted in sequence S3, such as Figure 4 As shown in (a), two wafers W1 and W2, with a pre-constructed transfer plan, are removed from the front-opening wafer transfer box 31 and transferred to a COR module 61 via the loading interlock module 20a, where a COR process is performed for t seconds. Furthermore, this COR process also includes... Figure 3 The process database (DB) shown includes multiple processing steps. The processing time (t seconds) for the aforementioned COR process is as follows: Figure 3 As shown, the process time is represented as the total time for these multiple processing steps.

[0080] When the COR processing for the two wafers W1 and W2 is completed, as follows Figure 4 As shown in (b), two wafers W1 and W2 are moved to the PHT module 62. In this embodiment, the PHT process takes longer than the COR process, and the PHT module 62 imposes a speed limit on the process. Therefore, the two wafers W1 and W2 that have completed the COR process are moved into the PHT module 62 without waiting for the two wafers W3 and W4 that are to be processed next.

[0081] When two wafers W1 and W2 are loaded into the PHT module 62, a PHT process of T seconds begins. The processing time of this PHT process in T seconds is as follows: Figure 3 As shown, the process time is represented as the total time of multiple processing steps.

[0082] When the PHT process for wafers W1 and W2 begins, wafers W3 and W4 are then moved to the front of the PHT module 62 via the load interlock module 10a and the COR module 61. Here, the timing of the arrival of wafers W3 and W4 at the front of the PHT module 62 is preferably within 5 seconds before or after the completion of the PHT process for the previous wafers (wafers W1 and W2), and more preferably approximately simultaneously with the completion of the process for the previous wafers. Therefore, in the timing control of wafer transport in this embodiment, the timing of the start of transport of the current wafers (wafers W3 and W4) from the front-opening wafer transport box 31 is controlled based on the following formula (2).

[0083] X = Remaining time of the process being performed on the previous wafer - Time required to move the current wafer to the front of the processing module that is the object...(2)

[0084] In equation (2), "remaining time of the process being performed on the previous wafer" represents, for example, the remaining time of the PHT processing for the two wafers W1 and W2 in the PHT module 62. In addition, "the time required to move the wafer to the front of the processing module to be processed" represents, for example, the time required to move the wafers W3 and W4 from the front-opening wafer transfer box 31 to the front of the PHT module 62 via the load interlock module 10a and the COR module 61.

[0085] Furthermore, in this embodiment, if the calculation result of Equation (2) is 0 or greater (X≥0), that is, if the remaining time for PHT processing of wafers W1 and W2 is longer than the time required for transporting wafers W3 and W4, the transport of wafers W3 and W4 will not begin. In other words, if there is a possibility that wafers W3 and W4 will have a standby time in front of the PHT module 62, the transport of wafers W3 and W4 will not begin, and wafers W3 and W4 will remain in standby inside the front-opening wafer transfer box 31 until a time when there is no standby time in front of the PHT module 62 will occur. On the other hand, if the calculation result of Equation (2) is other than that (X<0), that is, if the time required for transporting wafers W3 and W4 is longer than the remaining time for PHT processing of wafers W1 and W2, the transport of wafers W3 and W4 will begin immediately. In other words, the transfer of wafers W3 and W4 begins without generating standby time for wafers W3 and W4 on the front side of PHT module 62 or standby time for wafers W1 and W2 inside PHT module 62.

[0086] In this embodiment, by controlling the start timing of the current wafer transfer based on the remaining time of the previous wafer process and the time required for the current wafer transfer, the decrease in productivity in the vacuum processing apparatus 1 can be appropriately suppressed. Furthermore, the remaining process time used in adjusting this transfer timing is based on... Figure 2 The timing of the transfer start is calculated based on the predicted processing time of the previous wafer calculated from the sequence S2. That is, the timing of the transfer start is controlled based on the predicted processing time calculated considering the variable data V assigned to the wafer W. Therefore, even if the variable data V between wafers W to be processed continuously is different, the decrease in processing productivity in the vacuum processing unit 1 can be appropriately suppressed.

[0087] When adjusting the transport timing of two wafers W3 and W4 ( Figure 2 When sequence S3 begins, the transfer and processing of two wafers W3 and W4 to various processing modules starts. Figure 2 Sequences S4 and S5), such as Figure 4 As shown in (c), it is moved to the front of the PHT module 62.

[0088] Then, when the PHT processing for wafers W1 and W2 is completed, as follows: Figure 4 As shown in (d), wafers W1 and W2 are moved out and wafers W3 and W4 are moved in sequentially relative to the PHT module 62.

[0089] Next, wafers W1 and W2, which will be removed from PHT module 62, will be handled as follows: Figure 4 As shown in (e), the wafers are transferred to the CST module 33 via the loading interlock module 20b. Furthermore, they are then transferred to the front-opening wafer transfer box 31 via the wafer transfer mechanism 40, thereby concluding a series of wafer processing steps for wafers W1 and W2.

[0090] When wafer processing for wafers W1 and W2 is completed, the actual time required for various processes of wafers W1 and W2 (actual process time for wafers W1 and W2), and the variable data V allocated to wafers W1 and W2 are saved in [the relevant data]. Figure 2 The process database DB shown Figure 2 (Sequence S6). More specifically, the process database DB related to the process being processed is overwritten and updated using the actual process time and variable data V of wafers W1 and W2. The overwritten and updated actual time and variable data V of the process database DB will be referenced the next time wafer W is processed using the same process.

[0091] On the other hand, when the transfer of two wafers, W3 and W4, begins and the processes in various modules begin ( Figure 2 When the sequences S4 and S5 are given, such as Figure 4As shown in (e), a transfer plan for the two wafers W5 and W6 to be processed next is also constructed. Figure 2 The sequence S1 is used to predict the process time of wafers W5 and W6. Figure 2 (Sequence S2). Furthermore, based on the constructed transport plan, and the transport status (Sequence S4) and processing status (Sequence S5) of the two previously processed wafers W3 and W4, the transport timing for transporting the two wafers W5 and W6 to various processing modules is adjusted. Figure 2 (Sequence S3), then the transfer of two wafers W5 and W6 begins, along with the process in various modules ( Figure 2 (Sequences S4 and S5).

[0092] Moreover, in this embodiment, by means of... Figure 2 and Figure 4 The same method described above is used to transfer and process all wafers W in a set (25 wafers). Then, when all wafers W1 to W2 are transferred... 25 Upon handover to the front-opening wafer transfer box 31, a series of wafer processing steps in the vacuum processing unit 1 are completed. Furthermore, all wafers W1 to W2 are processed... 25 If the same process is used, after this series of wafer processing is completed, the resulting wafer W will have its final processing record recorded in the process database DB. 25 The actual time and the state of the variable data V.

[0093] The timing control of wafer transport in this embodiment is performed as described above. Furthermore, in the above embodiment, for clarity, an example was given of processing multiple wafers W using only one COR module 61 and one PHT module 62. However, it is of course possible to increase the productivity of the vacuum processing apparatus 1 by processing wafers W in parallel using multiple COR modules 61 and PHT modules 62.

[0094] According to the timing control method for wafer transport described in this embodiment, the process time of the wafer W to be processed in the vacuum processing apparatus 1 is calculated by taking into account the variation of the variable data V, which is arbitrarily input adjustment value (variable), using the above formula (1). Therefore, even if the variable data V of the previous wafer differs from that of the current wafer, the processing time of each processing step performed on the wafer W and the total processing time of multiple processing steps can be appropriately calculated, taking into account the difference in the variable data V. In other words, the completion timing of the process for the current wafer can be calculated by taking into account the difference in the variable data V, thereby appropriately determining the transport timing of the wafer W.

[0095] Furthermore, since the wafer W transport timing can be appropriately determined in this way, the standby time of the current wafer on the transport arm and the standby time of the previous wafer inside the processing module can be reduced. Therefore, especially when multiple processing modules are used in parallel, the time during which other wafers cannot be transported by the transport arm due to it being in standby mode while holding a wafer can be reduced, thereby suppressing a decrease in productivity in the vacuum processing apparatus 1. Additionally, it suppresses the decrease in productivity and the excessive processing of previous wafers caused by the standby time of the previous wafer inside the processing module.

[0096] Furthermore, since the wafer W's transport timing can be appropriately determined in this way, the previous wafer removal and the current wafer loading can be performed simultaneously relative to a processing module. As a result, the number of moves the wafer transport mechanism makes toward the front of a processing module can be reduced, and consequently, the decrease in productivity in the vacuum processing apparatus 1 can be more appropriately suppressed.

[0097] Furthermore, according to the above embodiment, the actual process time and variable data V of the current wafer are recorded in the process database DB, which records the actual time and variable data V of the previous wafer used in the timing control of wafer transport, by overwriting. The process processing time for wafer W may sometimes vary, for example, due to changes in the device characteristics of the processing module, but by updating the process database DB by overwriting in this way, the process processing time can always be calculated with reference to the latest data from the previous wafer. That is, it is possible to update changes in device characteristics, etc., over time and calculate the process processing time.

[0098] Furthermore, in the above embodiments, a transport plan for wafer W is sequentially constructed for wafer W before it is removed from the front-opening wafer transfer box 31, but the timing of constructing the transport plan for wafer W is not limited to this. That is, in the above embodiments, the transport of wafer W (removal from the front-opening wafer transfer box 31) begins after a transport plan has been constructed for all a series of wafer processing steps, but a transport plan for wafer W can be constructed separately before transporting wafer W for each processing module. Specifically, for example, a transport plan for COR module 61 can be constructed for wafer W that is idle inside the front-opening wafer transfer box 31, and then a transport plan for PHT module 62 can be constructed again for wafer W that has undergone COR processing.

[0099] Furthermore, in the above embodiments, the example described is that the COR processing in COR module 61 is shorter than the PHT processing in PHT module 62 (due to speed constraints imposed by the PHT processing). However, even when the COR processing is longer than the PHT processing (due to speed constraints imposed by the COR processing) or when the processing times of the COR and PHT processing are the same, the timing control of wafer transport as disclosed in this disclosure is still possible.

[0100] In addition, as in Figure 3 As shown in the process database DB, the COR processing in COR module 61 and the PHT processing in PHT module 62 include multiple processing steps. These processing steps include a "time step" that processes for a predetermined set time and a "stabilization step" that processes until a predetermined processing result (e.g., temperature, pressure, etc.) is reached.

[0101] In this stabilization step, even when the variable data V differs between the previous wafer and the current wafer as described above, the actual time is used until a predetermined processing result is obtained, thus reducing the likelihood of a decrease in productivity due to variations in the variable data V. On the other hand, in the timing step, when the variable data V differs between the previous wafer and the current wafer as described above, the actual process time is used, thus increasing the likelihood of a decrease in productivity due to variations in the variable data V.

[0102] Therefore, in the timing control of wafer transport according to this embodiment, the timing control described above can be performed only in the processing steps related to the "timing step" among the multiple processing steps included in the process performed on wafer W. By reducing the number of processing steps that are subject to timing control in this way, the control of the process in the vacuum processing apparatus 1 can be simplified. However, it is of course also possible to perform the timing control described above in the processing steps related to the "stabilization step".

[0103] Furthermore, in the above embodiments, the example described is the timing control of wafer transport in a vacuum processing apparatus 1 that processes wafer W under reduced pressure. However, any wafer processing apparatus that continuously transports and processes wafer W across multiple processing modules is acceptable, and the structure of the wafer processing apparatus using the technology disclosed herein is not limited. That is, for example, the timing control of wafer transport according to the technology disclosed herein can be performed in an atmospheric processing apparatus that continuously performs multiple processes under atmospheric pressure.

[0104] Furthermore, in the above embodiments, the case of simultaneously transporting and processing two wafers W and performing two-wafer processing was described as an example. However, the timing control of wafer transport involved in this disclosure can be applied even when processing one or more wafers.

[0105] It should be understood that the embodiments disclosed herein are illustrative in all respects and not restrictive. The above embodiments may be omitted, substituted, or modified in various ways without departing from the appended claims and their spirit.

[0106] Explanation of reference numerals in the attached figures

[0107] 1: Vacuum processing device; V: Variable data; W: Wafer.

Claims

1. A conveying method, in a processing system comprising at least one processing unit for performing a desired processing on a substrate and a conveying unit for conveying the substrate to the processing unit, wherein a plurality of substrates to be processed sequentially are conveyed from the conveying unit to the processing unit. In the conveying method, each of the multiple substrates is pre-assigned an adjustment value for arbitrarily changing the processing time for that substrate. The conveying method includes the following steps: Obtain the adjustment value assigned to the first substrate in this process; Obtain the reference adjustment value assigned to the reference substrate that was processed prior to the first substrate; Obtain the actual processing time performed on the reference substrate, i.e., the actual time; The predicted processing time of the first substrate is calculated by reflecting the difference between the adjustment value allocated to the first substrate and the reference adjustment value into the actual time. as well as The transport timing of the second substrate, which is processed after the first substrate, is adjusted based on the calculated predicted processing time.

2. The conveying method according to claim 1, characterized in that, When adjusting the transport timing of the second substrate, the predicted end time of the processing of the first substrate in the processing unit, calculated based on the predicted processing time, is compared with the transport time of transporting the second substrate to the processing unit, thereby adjusting the timing of starting the transport of the second substrate.

3. The conveying method according to claim 2, characterized in that, The timing of the start of the conveying is adjusted so that the second substrate is conveyed to the processing unit within 5 seconds before or after the predicted end time.

4. The conveying method according to claim 2 or 3, characterized in that, The processing system is provided with multiple processing units for performing various processes on the substrate. The processing unit whose timing for starting the conveying is adjusted is one of the multiple processing units that restricts the processing speed of the substrate in the processing system due to the long processing time of the substrate.

5. The conveying method according to any one of claims 1 to 3, characterized in that, It also includes the following steps: after the processing of the first substrate is completed, the reference adjustment value is updated by overwriting the adjustment value assigned to the first substrate.

6. A processing system for continuously processing a plurality of substrates, the processing system comprising: At least one processing unit performs a desired processing on the substrate; The conveying unit conveys the substrate to the processing unit; and The control unit controls the conveying operation of the substrate from the conveying unit to the processing unit. in, Each of the multiple substrates is pre-assigned an adjustment value for arbitrarily changing the processing time for that substrate. The control unit controls the conveying action of the substrate to perform the following processes: Obtain the adjustment value assigned to the first substrate in this process; Obtain the reference adjustment value assigned to the reference substrate that was processed prior to the first substrate; Obtain the actual processing time performed on the reference substrate, i.e., the actual time; The predicted processing time of the first substrate is calculated by reflecting the difference between the adjustment value allocated to the first substrate and the reference adjustment value into the actual time. as well as The transport timing of the second substrate, which is processed after the first substrate, is adjusted based on the calculated predicted processing time.

7. The processing system according to claim 6, characterized in that, When adjusting the transport timing of the second substrate, the control unit compares the predicted end time of the processing of the first substrate in the processing unit, calculated based on the predicted processing time, with the transport time of transporting the second substrate to the processing unit, thereby adjusting the timing of starting the transport of the second substrate.

8. The processing system according to claim 7, characterized in that, The control unit adjusts the timing of the start of the conveying so that the second substrate is conveyed to the processing unit within 5 seconds before or after the predicted end time.

9. The processing system according to claim 7 or 8, characterized in that, A plurality of processing units are arranged adjacent to the conveying unit. The processing unit whose timing for starting the conveying is adjusted is one of the multiple processing units that restricts the processing speed of the substrate in the processing system due to the long processing time of the substrate.

10. The processing system according to any one of claims 6 to 8, characterized in that, After the control unit finishes processing the first substrate, it updates the reference adjustment value by overwriting the adjustment value allocated to the first substrate.

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