Semiconductor structure and method for forming the same

Abstract

A semiconductor structure and a forming method thereof, the forming method comprising: forming separate polysilicon gate layers (200) on a substrate (100) in a first region (100M) and a second region (100L), the polysilicon gate layer (200) in the first region (100M) comprising a bottom gate layer (210) and a top gate layer (220) protruding from the bottom gate layer (210), the top gate layer (220) and the bottom gate layer (210) enclosing a groove (230), a grinding barrier layer (240) being formed on the side wall of the groove (230); forming an interlayer dielectric layer (320) on the substrate (100) at the side of the polysilicon gate layer (200); removing the polysilicon gate layer (200) in the second region (100L) to form a gate opening (330); and forming a metal gate layer (340) in the gate opening (330). The polysilicon gate layer (200) in the first region (100M) has a groove (230), so that the line width dimension, top surface area and spacing between the top gate layer (220) and the adjacent top gate layer (220) are relatively small. Furthermore, the grinding barrier layer (240) is located on the side wall of the groove (230) and can play a grinding barrier role in the flattening process, which is conducive to improving the top surface depression problem of the polysilicon gate layer (200) in the first region (100M) and improving the performance of the semiconductor structure.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] In semiconductor technology, even as device dimensions continue to shrink, it is still desirable to further improve transistor performance and to manufacture integrated circuit semiconductor devices that combine low, medium, and high voltage application ranges.

[0003] For example, an integrated circuit (hereinafter referred to as a driver IC) used to drive image sensors, LCDs, and printed heads, etc., is composed of a drive output unit with a high-voltage MOS transistor with a strong voltage resistance between the drain and the source that operates at a power supply voltage of more than 3.3V, and a logic unit of a control drive output unit with a low-voltage MOS transistor with a poor drain voltage resistance that can be used at a power supply voltage of several volts or less. Such integrated circuits are usually called system-on-chips. Although such integrated circuits include logic transistors that operate with very low voltages (such as 1.8V or 2.5V), other transistors on the same integrated circuit are designed for high voltage applications and therefore operate with high voltages, and often the voltage difference between the drain and the source may be as high as 30V or even 40V. High-voltage transistor elements are capable of carrying more current than logic transistors or peripheral transistors in logic circuits.

[0004] Among them, compared with low voltage (LV) devices, high voltage devices (HV) and medium voltage devices (MV) have higher operating voltages, and the sizes of high voltage devices and medium voltage devices are correspondingly larger. High voltage devices and medium voltage devices still use polysilicon gates (Poly Gate), while low voltage devices use metal gates (Metal Gate). Summary of the invention

[0005] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, so as to improve the performance of the semiconductor structure.

[0006] To solve the above problems, an embodiment of the present invention provides a semiconductor structure, including: a substrate, including a first region for forming a first device and a second region for forming a second device, the channel length of the first device is greater than the channel length of the second device; a polysilicon gate layer, located on the substrate in the first region, the polysilicon gate layer including a bottom gate layer and a top gate layer protruding from the bottom gate layer, the top gate layer and the bottom gate layer forming a groove; a metal gate layer, located on the substrate in the second region; a grinding barrier layer, located on the sidewalls of the groove; and an interlayer dielectric layer, located on the substrate on the sides of the metal gate layer and the polysilicon gate layer.

[0007] Correspondingly, an embodiment of the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate, comprising a first region for forming a first device and a second region for forming a second device, the channel length of the first device being greater than the channel length of the second device; forming discrete polysilicon gate layers on the substrate of the first region and the second region, the polysilicon gate layer in the first region comprising a bottom gate layer and a top gate layer protruding from the bottom gate layer, the top gate layer and the bottom gate layer forming a groove, and a grinding barrier layer being formed on the sidewalls of the groove; forming an interlayer dielectric layer on the substrate on the side of the polysilicon gate layer, the interlayer dielectric layer exposing the top surface of the polysilicon gate layer in the second region; removing the polysilicon gate layer in the second region to form a gate opening in the interlayer dielectric layer; and forming a metal gate layer in the gate opening.

[0008] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages: in the semiconductor structure provided by the embodiment of the present invention, the polysilicon gate layer is located on the substrate of the first region, the polysilicon gate layer includes a bottom gate layer and a top gate layer protruding from the bottom gate layer, the top gate layer and the bottom gate layer form a groove, wherein, by setting the groove in the polysilicon gate layer in the first region, the line width dimension, top surface area and spacing between the top gate layer and the adjacent top gate layer are made smaller, which is conducive to improving the top surface dishing problem of the polysilicon gate layer during the planarization process when forming an interlayer dielectric layer or a metal gate layer; in addition, the semiconductor structure also includes a grinding barrier layer located on the sidewall of the groove, the grinding barrier layer can play a role of grinding barrier during the planarization process, thereby improving the improvement effect of the top surface dishing problem of the polysilicon gate layer in the first region; in summary, the embodiment of the present invention is conducive to improving the performance of the polysilicon gate layer in the first region, thereby improving the performance of the semiconductor structure.

[0009] In the method for forming a semiconductor structure provided by an embodiment of the present invention, the polysilicon gate layer formed in the first region includes a bottom gate layer and a top gate layer protruding from the bottom gate layer, and the top gate layer and the bottom gate layer form a groove; forming an interlayer dielectric layer and forming a metal gate layer both include a planarization step, and by providing the polysilicon gate layer in the first region with the groove, the line width, top surface area and spacing between the top gate layer and the adjacent top gate layer are made smaller, thereby in the process of forming the interlayer dielectric layer and forming the metal gate layer planarization, it is beneficial to improve the top surface dishing problem of the polysilicon gate layer in the first region; in addition, in the embodiment of the present invention, a grinding barrier layer is also formed on the sidewall of the groove, and in the process of forming the interlayer dielectric layer and forming the metal gate layer planarization, the grinding barrier layer can play a role of grinding barrier, thereby improving the improvement effect of the top surface dishing problem of the polysilicon gate layer in the first region; in summary, the embodiment of the present invention is beneficial to improving the performance of the polysilicon gate layer in the first region, thereby improving the performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figures 1 to 3 It is a schematic structural diagram corresponding to each step in a method for forming a semiconductor structure;

[0011] Figures 4 to 19 is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention;

[0012] Figure 20 to Figure 25 It is a schematic structural diagram corresponding to each step in another embodiment of the method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION

[0013] As can be seen from the background technology, the devices currently formed still have the problem of poor performance. The reasons for the poor performance of the devices are now analyzed in combination with a method for forming a semiconductor structure.

[0014] refer to Figures 1 to 3 , showing a structural schematic diagram corresponding to each step in a method for forming a semiconductor structure.

[0015] refer to Figure 1 , providing a substrate 10, including a first region 10M for forming a first device and a second region 10L for forming a second device, wherein a channel length of the first device is greater than a channel length of the second device.

[0016] Continue to refer Figure 1A discrete polysilicon gate structure 31 is formed on the substrate 10 in the first region 10M and the second region 10L, including a gate dielectric layer 32, a metal barrier layer 33 and a polysilicon gate layer 34 stacked in sequence from bottom to top, and the thickness of the gate dielectric layer 32 in the first region 10M is greater than the thickness of the gate dielectric layer 32 in the second region 10L.

[0017] refer to Figure 2 An interlayer dielectric layer 35 is formed on the substrate 10 at the side of the polysilicon gate structure 31 , and the interlayer dielectric layer 35 exposes the top surface of the polysilicon gate layer 34 in the second region 10L.

[0018] Among them, the step of forming the interlayer dielectric layer 35 includes: forming a dielectric material layer (not shown) covering the side walls and top of the polysilicon gate structure 31 on the substrate 10; planarizing the dielectric material layer, removing the dielectric material layer above the top surface of the polysilicon gate layer 34 in the second region 10L, and the remaining dielectric material layer is used as the interlayer dielectric layer 35.

[0019] refer to Figure 3 , remove the polysilicon gate layer 34 of the second region 10L, form a gate opening (not shown) in the interlayer dielectric layer 35 of the second region 10L to expose the metal barrier layer 33; and form a metal gate layer 36 in the gate opening.

[0020] Among them, the step of forming the metal gate layer 36 generally includes: filling the metal gate material (not shown) in the gate opening, and the metal gate material is also located on the interlayer dielectric layer 35; flattening the metal gate material, removing the metal gate material located on the top surface of the interlayer dielectric layer 35, and the remaining metal gate material located in the gate opening is used as the metal gate layer 36.

[0021] Since the channel length of the first device is greater than the channel length of the second device, and the line width of the polysilicon gate layer 34 in the first region 10M is larger than the line width of the polysilicon gate layer 34 in the second region 10L, in the process of planarizing the dielectric material layer and the metal gate material, it is easy to cause over-polishing problem to the polysilicon gate layer 34 in the first region 10M, resulting in serious dishing problem of the top surface of the polysilicon gate layer 34 in the first region 10M, resulting in a reduction in the thickness of the polysilicon gate 34 in the first region 10M, and even exposing the metal barrier layer 33.

[0022] In particular, the channel length of the first device is greater than the channel length of the second device, so that the operating voltage of the first device is greater than the operating voltage of the second device, and the thickness of the gate dielectric layer 32 of the first region 10M is correspondingly greater than the thickness of the gate dielectric layer 32 of the second region 10L, so that the top surface of the polysilicon gate layer 34 of the first region 10M is higher than the top surface of the polysilicon gate layer 34 of the second region 10L. In the process of planarizing the dielectric material layer and planarizing the metal gate material, the probability of a depression problem occurring on the top surface of the polysilicon gate layer 34 of the first region 10M is higher and more serious.

[0023] In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, by making the polysilicon gate layer in the first region have the groove, so that the line width, top surface area and spacing between the top gate layer and the adjacent top gate layer are smaller, thereby helping to improve the top surface dishing problem of the polysilicon gate layer in the first region during the process of forming the interlayer dielectric layer and the planarization of the metal gate layer; in addition, in the embodiment of the present invention, a grinding barrier layer is also formed on the side wall of the groove, and in the process of forming the interlayer dielectric layer and the planarization of the metal gate layer, the grinding barrier layer can play a role of grinding barrier, thereby improving the improvement effect of the top surface dishing problem of the polysilicon gate layer in the first region; in summary, the embodiment of the present invention is conducive to improving the performance of the polysilicon gate layer in the first region, thereby improving the performance of the semiconductor structure.

[0024] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present invention more obvious and understandable, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings. Figures 4 to 19 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention.

[0025] refer to Figure 4 , providing a substrate 100, including a first region 100M for forming a first device and a second region 100L for forming a second device, wherein a channel length of the first device is greater than a channel length of the second device.

[0026] The substrate 100 is used to provide a process platform for subsequent process steps.

[0027] In this embodiment, the substrate 100 is used to form a planar field effect transistor as an example, and the substrate 100 is a planar substrate. In other embodiments, the substrate is used to form a fin field effect transistor (FinFET), and accordingly, the substrate includes a substrate and a fin protruding from the substrate.

[0028] In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the substrate may also be a substrate of other material types.

[0029] A channel length of the first device is greater than a channel length of the second device, so that an operating voltage of the first device is higher than an operating voltage of the second device.

[0030] In this embodiment, the first device includes one or both of a medium voltage device and a high voltage device, and the second device is a low voltage device. The operating voltages of the low voltage device, the medium voltage device, and the high voltage device increase in sequence. As an example, the operating voltage of the low voltage device is less than 1.5V, the operating voltage of the medium voltage device is 1V to 10V, and the operating voltage of the high voltage device is greater than 10V.

[0031] The first device may be an NMOS device or a PMOS device. Similarly, the second device may also be an NMOS device or a PMOS device. As an example, the first region 100M includes a first sub-region 100MN and a second sub-region 100MP, and the first sub-region 100MN and the second sub-region 100MP are used to form a first device of different channel conductivity types. For example, the first device formed in the first sub-region 100MN is an NMOS device, and the first device formed in the second sub-region 100MP is a PMOS device.

[0032] In this embodiment, an isolation structure 101 is also formed in the substrate 100. Specifically, the isolation structure 101 is formed in the substrate 100 at the junction of the first region 100M and the second region 100L. In the first region 100M, the isolation structure 101 is also formed in the substrate 100 at the junction of the first sub-region 100MN and the second sub-region 100MP.

[0033] The isolation structure 101 is used to achieve isolation between adjacent devices. In this embodiment, the isolation structure 101 is a shallow trench isolation (STI) structure, so that the isolation structure 101 has a good isolation effect. In this embodiment, the material of the isolation structure 101 is an insulating material, and the insulating material includes silicon oxide.

[0034] Combined with reference Figures 4 to 9 , a separate polysilicon gate layer 200 (eg, Figure 8 As shown), the polysilicon gate layer 200 in the first region 100M includes a bottom gate layer 210 and a top gate layer 220 protruding from the bottom gate layer 210, the top gate layer 220 and the bottom gate layer 210 form a groove 230, and a grinding barrier layer 240 is formed on the side wall of the groove 230.

[0035] The polysilicon gate layer 200 in the first region 100M is used as a device gate structure of the first device, so as to control the opening or closing of the channel of the first device. The polysilicon gate layer 200 in the second region 100L is used to occupy a space for the subsequent formation of a metal gate layer.

[0036] Wherein, after forming an interlayer dielectric layer on the substrate 100 on the side of the polysilicon gate layer 200, the polysilicon gate layer 200 in the second region 100L is removed to form a gate opening, and then a metal gate layer is formed in the gate opening. The process of forming the metal gate layer generally includes the step of planarizing the metal gate material, and the larger the size of the metal gate layer, the higher the probability of a dishing problem on the top surface of the metal gate layer during the planarization of the metal gate material. Since the first region 100M is used to form a first device, the channel length of the first device is greater than the channel length of the second device, and the gate size of the first device is correspondingly larger. Therefore, by making the first device adopt the polysilicon gate layer 200, the metal gate layer is avoided in the first device, thereby avoiding the dishing problem of the top surface of the metal gate layer caused by the larger gate size in the first region 100M.

[0037] By forming a groove 230 in the polysilicon gate layer 200 of the first region 100M, the line width, top surface area and spacing between the top gate layer 220 and the adjacent top gate layer 220 are made smaller. Therefore, in the process of planarizing the metal gate layer, the probability of over-grinding the polysilicon gate layer 200 in the first region 100M is low, which is beneficial to improving the top surface depression problem of the polysilicon gate layer 200 in the first region 100M, so that the top surface flatness of the polysilicon gate layer 200 in the first region 100M is higher, which correspondingly improves the structural integrity of the polysilicon gate layer 200 in the first region 100M, and further helps to improve the performance of the semiconductor structure.

[0038] In this embodiment, the first region 100M includes a first sub-region 100MN and a second sub-region 100MP. In the first region 100M, the polysilicon gate layer 200 is separated on the first sub-region 100MN and the second sub-region 100MP.

[0039] In this embodiment, the material of the polysilicon gate layer 200 is polysilicon.

[0040] The ratio of the thickness of the bottom gate layer 210 to the total thickness of the polysilicon gate layer 200 should not be too small or too large. If the ratio is too small, it is easy to cause the thickness of the bottom gate layer 210 to be too small. Considering the influence of etching uniformity and load effect, in the process of forming the groove 230, the bottom gate layer 210 exposed by the top gate layer 220 is more likely to be etched through, that is, the groove 230 is easy to penetrate the entire polysilicon gate layer 200, which is easy to affect the performance of the polysilicon gate layer 200 in the first area 100M, and when the conductive ions are injected in the subsequent step, the conductive ions may pass through the bottom gate layer 210 and be injected into the film layer structure (for example: gate oxide layer) below the bottom gate layer 210, which is easy to cause device failure; if the ratio is too large, correspondingly, the thickness of the top gate layer 220 is too small, then in the subsequent planarization process of forming the metal gate layer, it is easy to cause the top gate layer 220 to be completely removed, which is easy to cause over-grinding of the bottom gate layer 210, and thus it is easy to reduce the improvement effect of the top surface depression problem of the polysilicon gate layer 200 in the first area 100M. Therefore, in the present embodiment, the thickness of the bottom gate layer 210 accounts for 1 / 5 to 1 / 3 of the total thickness of the polysilicon gate layer 200 .

[0041] It should also be noted that the line width of the top gate layer 220 and the line width of the groove 230 should not be too small or too large. If the line width of the top gate layer 220 and the line width of the groove 230 are too small, it is easy to increase the process difficulty of the photolithography process used when forming the groove 230, and the spacing between adjacent top gate layers 220 is too small, that is, the line width of the groove 230 is correspondingly too small, which is easy to cause adverse effects on the filling effect of the subsequent interlayer dielectric layer in the groove 230; if the line width of the groove 230 is too large, it is easy to increase the risk of the top surface depression problem of the interlayer dielectric layer located in the groove 230 during the subsequent flattening process of forming the metal gate layer, and if the line width of the top gate layer 220 is too large, when the metal gate layer is subsequently formed, the probability of the top surface depression problem of the top gate layer 220 is high. For this reason, in this embodiment, the line width of the top gate layer 220 is 0.15 microns to 2 microns.

[0042] Similarly, the opening line width of the groove 230 is 0.15 micrometers to 2 micrometers.

[0043] It should be noted that if Figure 8 As shown, the number of the grooves 230 in the polysilicon gate layer 200 in the first region 100M is one. However, the number of the grooves 230 in the polysilicon gate layer 200 in the first region 100M is not limited thereto, and may be other numbers. Fig. 9, schematically shows a top view of the polysilicon gate layer 200 of the first region 100M. When the size of the first device is large, the number of grooves 230 in the polysilicon gate layer 200 of the first region 100M can be multiple, and the multiple grooves 230 can be arranged in parallel and spaced apart.

[0044] For the convenience of illustration and explanation, Fig. 9 Only the top gate layer 220 and the bottom gate layer 210 and the groove 230 are shown.

[0045] In this embodiment, the steps of forming the polysilicon gate layer 200 include: forming a polysilicon gate material layer 110 on the substrate 100; forming the groove 230 in the polysilicon gate material layer 110 in the first area 100M; and patterning the polysilicon gate material layer 110 to form the polysilicon gate layer 200 separated in the first area 100M and the second area 100L.

[0046] In addition, in this embodiment, a grinding barrier layer 240 is also formed on the side wall of the groove 230. In the subsequent process of forming an interlayer dielectric layer and flattening the metal gate layer, the grinding barrier layer 240 can play a role of grinding barrier, thereby improving the improvement effect of the top surface depression problem of the polysilicon gate layer 200 in the first region 100M.

[0047] To this end, the grinding barrier layer 240 is made of a material with high hardness and density, so as to ensure that the grinding barrier layer 240 can play a role of grinding barrier in the process of planarization. Specifically, the material of the grinding barrier layer 240 is selected as follows: the density and hardness of the material of the grinding barrier layer 240 are greater than the hardness and density of the material of the polysilicon gate layer 200, the interlayer dielectric layer and the metal gate layer. At the same time, since the grinding barrier layer 240 of this embodiment is formed at the same time as the gate mask material layer 170 is formed, considering the process compatibility, the grinding barrier layer 240 is made of a material with high process compatibility, thereby reducing process risks and costs.

[0048] In this embodiment, the material of the grinding stop layer 240 includes silicon nitride or silicon oxynitride. As an example, the material of the grinding stop layer 240 is silicon nitride.

[0049] In this embodiment, after the groove 230 is formed in the polysilicon gate material layer 110 in the first region 100M, the grinding stop layer 240 is formed on the sidewall of the groove 230 before the polysilicon gate material layer 110 is patterned.

[0050] In this embodiment, the formation method also includes: in the step of forming the polysilicon gate layer 200, a stacked structure 250 is also formed between the polysilicon gate layer 200 and the substrate 100, the stacked structure 250 includes a gate dielectric layer 260 and a metal barrier layer 270 located on the gate dielectric layer 260; the thickness of the gate dielectric layer 260 in the first region 100M is greater than the thickness of the gate dielectric layer 260 in the second region 100L.

[0051] In this embodiment, the thickness of the gate dielectric layer 260 in the first region 100M is greater than the thickness of the gate dielectric layer 260 in the second region 100L. Therefore, the top surface of the polysilicon gate layer 200 in the first region 100M is higher than the top surface of the polysilicon gate layer 200 in the second region 100L.

[0052] The gate dielectric layer 260 of the first region 100M is used to electrically isolate the polysilicon gate layer 200 from the channel of the first device; the gate dielectric layer 260 of the second region 100L is used to electrically isolate the subsequent metal gate layer from the channel of the second device.

[0053] The thickness of the gate dielectric layer 260 in the first region 100M is greater than the thickness of the gate dielectric layer 260 in the second region 100L, so that the first device can withstand a larger operating voltage.

[0054] In this embodiment, the gate dielectric layer 260 of the first region 100M includes a gate oxide layer 11 and a high-k gate dielectric layer 12 located on the gate oxide layer 11, and the gate dielectric layer 260 of the second region 100L includes an interface buffer layer 13 and a high-k gate dielectric layer 12 located on the interface buffer layer 13. Since the gate oxide layer 11 is thicker than the interface buffer layer 13, the thickness of the gate dielectric layer 260 of the first region 100M is greater. In this embodiment, the material of the gate oxide layer 11 and the interface buffer layer 13 is silicon oxide.

[0055] In this embodiment, the material of the high-k gate dielectric layer 12 is a high-k dielectric material, wherein the high-k dielectric material refers to a dielectric material having a relative dielectric constant greater than the relative dielectric constant of silicon oxide. Specifically, the material of the high-k gate dielectric layer 12 can be selected from HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO or Al2O3. As an example, the material of the high-k gate dielectric layer 12 is HfO2.

[0056] The metal barrier layer 270 is used to isolate the gate dielectric layer 260 from the polysilicon gate layer 200, and to isolate the gate dielectric layer 260 from the subsequently formed metal gate layer, so as to protect the gate dielectric layer 260. Meanwhile, in the subsequent etching process of removing the polysilicon gate layer 200 in the second region 100L, the metal barrier layer 260 serves as an etching stop layer, thereby reducing the probability of damage to the gate dielectric layer 260. Moreover, after the metal gate layer is subsequently formed, the metal barrier layer 270 is also used to block the easily diffusible ions (e.g., aluminum ions) in the metal gate layer from diffusing into the gate dielectric layer 260. Specifically, the metal barrier layer 270 is used to protect the high-k gate dielectric layer 12, reduce the probability of damage to the high-k gate dielectric layer 12, and prevent the easily diffusible ions in the metal gate layer from diffusing into the high-k gate dielectric layer 12. Among them, the metal barrier layer 270 also has a certain influence on the gate work function of the second device.

[0057] The material of the metal barrier layer 270 includes one or both of titanium nitride (TiN) and silicon-doped titanium nitride (TiSiN). In this embodiment, the material of the metal barrier layer 270 is titanium nitride.

[0058] In the actual process, the thickness of the metal barrier layer 270 is reasonably set to ensure that the metal barrier layer 270 can serve as an etching stop layer during the subsequent etching to remove the polysilicon gate layer 200 in the second area 100L. At the same time, the metal barrier layer 270 has a better blocking effect on easily diffusible ions in the metal gate layer.

[0059] The specific steps of forming the polysilicon gate layer 200, the polishing stop layer 240 and the stacked structure 250 according to the present embodiment will be described in detail below with reference to the accompanying drawings.

[0060] like Figure 4 As shown, a gate oxide material layer 120 is formed on the substrate 100 located in the first area 100M, and an interface buffer material layer 130 is formed on the substrate 100 located in the second area 100L; a high-k gate dielectric material layer 140 is formed on the gate oxide material layer 120 and the interface buffer material layer 130, and a metal barrier material layer 150 is located on the gate dielectric material layer 140.

[0061] The gate oxide material layer 120 is used to form a gate oxide layer; the high-k gate dielectric material layer 140 is used to form a high-k gate dielectric layer; the metal barrier material layer 150 is used to form a metal barrier layer; and the interface buffer material layer 130 is used to form an interface buffer layer. The interface buffer layer is used to improve electron mobility, interface stability, and device reliability.

[0062] In this embodiment, the material of the interface buffer material layer 130 is the same as that of the gate oxide material layer 120 , and the interface buffer material layer 130 is relatively thin, with a thickness less than that of the gate oxide material layer 120 .

[0063] like Figure 4 As shown, a polysilicon gate material layer 110 is formed on the substrate 100. Specifically, the polysilicon gate material layer 110 is formed on the metal barrier material layer 150. The polysilicon gate material layer 110 is used to form a polysilicon gate layer.

[0064] like Figure 5 As shown, a groove 230 is formed in the polysilicon gate material layer 110 in the first region 100M.

[0065] In this embodiment, the step of forming the groove 230 in the polysilicon gate material layer 110 in the first area 100M includes: forming a mask layer 160 on the polysilicon gate material layer 110, the mask layer 160 having a mask opening 165 located in the first area 100M; using the mask layer 160 as a mask, etching a partial thickness of the polysilicon gate material layer 110 along the mask opening 165.

[0066] The mask layer 160 is used as a mask for etching the polysilicon gate material layer 110 to form a groove. The mask opening 165 is used to define the position and shape of the groove. In this embodiment, the mask opening 165 is located in the first sub-region 100MN and the second sub-region 100MP respectively.

[0067] In this embodiment, the material of the mask layer 160 includes photoresist. The mask layer 160 is formed by photolithography processes such as exposure and development.

[0068] In this embodiment, an anisotropic dry etching process is used to etch a partial thickness of the polysilicon gate material layer 110. The anisotropic etching process has the characteristics of anisotropic etching, that is, the longitudinal etching rate is much greater than the lateral etching rate, so that a better etching profile can be obtained to improve the morphology quality and dimensional accuracy of the groove 230, and it is conducive to accurately controlling the longitudinal etching amount of the polysilicon gate material layer 110.

[0069] like Figure 6As shown, in this embodiment, the formation method further includes: after forming the groove 230 in the polysilicon gate material layer 110 in the first region 100M and before patterning the polysilicon gate material layer 110, doping the polysilicon gate material layer 110 at the bottom and sidewalls of the groove 230 with conductive ions 235. Specifically, in this embodiment, after forming the groove 230 and before removing the mask layer 160 for defining the position and shape of the groove 230, doping the polysilicon gate material layer 110 at the bottom and sidewalls of the groove 230 with conductive ions 235.

[0070] By doping the polysilicon gate material layer 110 at the bottom and sidewalls of the groove 230 with conductive ions 235, the polysilicon gate layer of the first region 100M is doped with the conductive ions 235, which helps to reduce the resistance of the polysilicon gate layer of the first region 100M, thereby reducing the gate resistance of the first device.

[0071] Moreover, in the present embodiment, the conductive ions 235 are doped before the mask layer 160 is removed, so that the mask layer 160 can continue to be used as a mask for ion doping, so that the mask layer 160 can protect the polysilicon gate material layer 110 of the second region 100L. In addition, in the present embodiment, the process of doping the conductive ions 235 and forming the grooves 230 can share a mask, thereby saving the mask and reducing the manufacturing cost.

[0072] In this embodiment, the step of doping the polysilicon gate material layer 110 at the bottom and sidewalls of the groove 230 with conductive ions 235 includes: using the mask layer 160 as a mask, performing ion implantation on the polysilicon gate material layer 110 exposed by the groove 230, and the ion implantation direction has an acute angle with the normal to the surface of the substrate 100.

[0073] The injection direction of the conductive ions 235 has an acute angle with the normal to the surface of the substrate 100, so that the conductive ions 235 can be injected into the polysilicon gate material layer 110 through the bottom and side walls of the groove 230, increasing the probability of the conductive ions 235 being injected from the side walls of the groove 230 into the top gate layer, and activating the injected ions through subsequent heat treatment, and diffusing the injected ions, thereby reducing the resistance of the polysilicon gate layer in the first region 100M, and correspondingly reducing the gate resistance of the first device.

[0074] In this embodiment, the conductive ions 235 include B ions, Ga ions, In ions, P ions, As ions or Sb ions.

[0075] In this embodiment, ion implantation is used to implant conductive ions 235 into the polysilicon gate material layer 110 exposed in the groove 230. The process of ion implantation is relatively simple.

[0076] The injection energy of the ion implantation should not be too large or too small. If the injection energy is too small, it is difficult to ensure that the conductive ions 235 are injected into the polysilicon gate material layer 110 at the bottom and sidewall of the groove 230, and it is accordingly difficult to ensure that the top gate layer and the bottom gate layer are doped with the conductive ions 235, and it is easy to reduce the uniformity of the doping concentration of the conductive ions 235 in the polysilicon gate layer, and accordingly, it is not conducive to reducing the resistance of the polysilicon gate layer in the first region 100M; if the injection energy is too large, the conductive ions 235 are easily injected into the film layer structure (for example: high-k gate dielectric material layer 140, gate oxide material layer 120 or substrate 100) below the polysilicon gate material layer 110 through the bottom of the groove 230, which is easy to have an adverse effect on the performance of the device. For this reason, in this embodiment, the injection energy of the ion implantation is 1KeV to 10KeV.

[0077] It should be noted that in the actual process, the injection angle of the ion implantation is flexibly adjusted according to the actual opening size of the groove 230 and the mask opening 165 to ensure that the conductive ions 235 can be injected into the polysilicon gate material layer 110 at the side wall and bottom of the groove 230, thereby improving the uniformity of the doping distribution of the conductive ions 235 in the polysilicon gate layer.

[0078] As an example, when the opening line width of the groove 230 is 150 nm, the angle between the implantation direction of the ion implantation and the surface normal of the substrate 100 is 5° to 30°.

[0079] In this embodiment, after doping the conductive ions 235 into the polysilicon gate material layer 110 at the bottom and sidewalls of the groove 230, the formation method further includes: removing the mask layer 160 to facilitate subsequent processes. Specifically, the mask layer 160 is removed by using one or both of an ashing process and a wet stripping process.

[0080] like Figure 7 As shown, a grinding stop layer 240 is formed on the sidewall of the groove 230 .

[0081] Specifically, in this embodiment, the step of forming the grinding barrier layer 240 includes: after forming the groove 230 and before patterning the polysilicon gate material layer 110, forming a gate mask material layer 170 on the polysilicon gate material layer 110 and the bottom and side walls of the groove 230, and the gate mask material layer 170 located on the side walls of the groove 230 is used as the grinding barrier layer 240.

[0082] The gate mask material layer 170 is also used to form a gate mask layer, and the gate mask layer is used as a mask for patterning the polysilicon gate material layer 110 .

[0083] Therefore, in this embodiment, after forming the groove 230 and before patterning the polysilicon gate material layer 110, a gate mask material layer 170 is formed, and the gate mask material layer 170 located on the side wall of the groove 230 is used as the grinding barrier layer 240, so that the steps of forming the grinding barrier layer 240, forming the gate mask layer and subsequently patterning the polysilicon gate material layer 110 can be integrated, and there is no need for an additional process step of forming the grinding barrier layer 240, thereby improving process compatibility and process integration, and thus helping to reduce process risks and costs.

[0084] In addition, the gate mask layer is usually made of a material with high density and hardness to serve as a mask for patterning the polysilicon gate material layer 110. At the same time, by using the gate mask material layer 170 located on the side wall of the groove 230 as a grinding barrier layer 240, the requirement that the grinding barrier layer 240 play a grinding barrier role can be met.

[0085] In this embodiment, a deposition process is used to form the gate mask material layer 170. The deposition process includes a chemical vapor deposition process or an atomic layer deposition process.

[0086] As an example, the gate mask material layer 170 is formed by an atomic layer deposition process, which is beneficial to improving the step coverage capability, thickness consistency and film quality (for example, density, fewer impurity defects) of the gate mask material layer 170, and correspondingly beneficial to improving the coverage capability of the grinding barrier layer 240 on the side wall of the groove 230, as well as the density and hardness of the grinding barrier layer 240.

[0087] like Figure 8 As shown, the polysilicon gate material layer 110 is patterned to form the polysilicon gate layer 200 separated in the first region 100M and the second region 100L.

[0088] In this embodiment, the step of patterning the polysilicon gate material layer 110 includes: patterning the gate mask material layer 170, retaining the gate mask material layer 170 located at the bottom and side walls of the groove 230, and extending at the top of the polysilicon gate material layer 110, and the gate mask material layer 170 located at the top of the polysilicon gate material layer 110 in the second area 100L, for use as a gate mask layer 175; using the gate mask layer 175 as a mask, patterning the polysilicon gate material layer 110 to form a polysilicon gate layer 200.

[0089] In this embodiment, in the step of patterning the polysilicon gate material layer 110, the gate mask layer 175 is also used as a mask to pattern the metal barrier material layer 150, the high-k gate dielectric material layer 140, the gate oxide material layer 120 and the interface buffer material layer 130 to form a metal barrier layer 270, a high-k gate dielectric layer 12, a gate oxide layer 11 and an interface buffer layer 13.

[0090] The gate dielectric layer 260 of the first region 100M is composed of a gate oxide layer 11 and a high-k gate dielectric layer 12, and the gate dielectric layer 260 of the second region 100L is composed of a high-k gate dielectric layer 12 and an interface buffer layer 13. The gate dielectric layer 260 and the metal barrier layer 270 located on the gate dielectric layer 260 form a stacked structure 250.

[0091] refer to Fig.10 After forming the polysilicon gate layer 200 and the grinding barrier layer 240 and before forming the interlayer dielectric layer, the method for forming the semiconductor structure further includes: forming a sidewall 280 on the sidewall of the polysilicon gate layer 200 and the grinding barrier layer 240 on the sidewall of the groove 230.

[0092] The sidewall 280 is used to protect the sidewall of the polysilicon gate layer 200 and is also used to define the position of the subsequent source and drain doping regions. Moreover, the sidewall 280 is also formed on the sidewall of the groove 230, which is beneficial to further reduce the probability of over-grinding the top surface of the polysilicon gate layer 200 in the first region 100M during the subsequent planarization process, thereby further improving the top surface depression problem of the polysilicon gate layer 200.

[0093] In this embodiment, the material of the sidewall 280 includes silicon nitride. Silicon nitride has high hardness and density, and the polishing rate of the sidewall 280 during the planarization process is low, thereby further improving the top surface depression problem of the polysilicon gate layer 200 in the first region 100M.

[0094] The sidewall spacer 280 may be a stacked structure or a single-layer structure. As an example, the sidewall spacer 280 is a stacked structure, and the sidewall spacer 280 includes a first silicon oxide layer covering the sidewalls of the polysilicon gate layer 200 and the groove 230, a silicon nitride layer covering the sidewalls of the first silicon oxide layer, and a second silicon oxide layer located on the silicon nitride layer.

[0095] refer to Fig.11 and Fig.12The formation method further includes: after forming the polysilicon gate layer 200 and the grinding barrier layer 240 and before forming the interlayer dielectric layer, forming source-drain doped regions 300 in the substrate 100 on both sides of the polysilicon gate layer 200. Specifically, in this embodiment, after forming the sidewalls 280 and before forming the interlayer dielectric layer, the source-drain doped regions 300 are formed.

[0096] The source-drain doped region 300 serves as a source region or a drain region of the formed device.

[0097] When the formed device is an NMOS device, the doped ions in the source / drain doping region 300 are N-type ions, which include P ions, As ions or Sb ions. When the formed device is a PMOS device, the doped ions in the source / drain doping region 300 are P-type ions, which include B ions, Ga ions or In ions.

[0098] In this embodiment, the steps of forming the source-drain doped region 300 include: forming a blocking layer 290 on the substrate 100, the blocking layer 290 also covering the polysilicon gate layer 200 of the first area 100M and the second area 100L, and doping openings 295 are formed in the blocking layer 290 on both sides of the polysilicon gate layer 200; using the blocking layer 290 as a mask, ion doping is performed on the substrate 100 exposed by the doping openings 295 to form the source-drain doped region 300; and removing the blocking layer 290.

[0099] Specifically, source-drain doping treatment is performed on the first region 100M and the second region 100L respectively to form source-drain doping regions 300 .

[0100] In the present embodiment, taking the formation of a source-drain doped region 300 in the substrate 100 of the first sub-region 100MN as an example, the source-drain doping process includes: forming a shielding layer 290 on the substrate 100, the shielding layer 290 also covering the polysilicon gate layer 200 of the first region 100M and the second region 100L, and in the first sub-region 100MN, a doping opening 295 penetrating the shielding layer 290 is formed in the shielding layer 290 on both sides of the polysilicon gate layer 200; doping the substrate 100 exposed by the doping opening 295 to form the source-drain doping region 300.

[0101] In this embodiment, an ion implantation process is used to dope the substrate 100 exposed by the doping opening 295 to form the source-drain doping region 300 .

[0102] In this embodiment, after the source-drain doping region 300 is formed, the source-drain doping process further includes: removing the shielding layer 290 .

[0103] Accordingly, reference Fig.12, the second sub-region 100MP and the second region 100L are subjected to source-drain doping treatment respectively, so as to form source-drain doped regions 300 in the substrate 100 on both sides of the polysilicon gate layer 200 of the first sub-region 100MN and in the substrate 100 on both sides of the polysilicon gate layer 200 of the second region 100L. The specific steps can refer to the description of forming the source-drain doped region 300 in the substrate 100 of the first sub-region 100MN, which will not be repeated here.

[0104] It should be noted that when forming the source-drain doping region 300, since the injection energy of the ion implantation process is relatively large, the blocking layer 290 is made to cover the bottom of the groove 230, thereby reducing the probability of ions being injected into the gate dielectric layer 260 and the substrate 100 below the polysilicon gate layer 200 through the bottom of the groove 230.

[0105] refer to Fig.13 , a source-drain silicide layer 310 is formed on the top surface of the source-drain doped region 300 .

[0106] Subsequently, source-drain contact plugs are formed on the top of the source-drain doped region 300, and the contact resistance between the source-drain doped region 300 and the source-drain contact plugs is reduced by forming the source-drain silicide layer 310. In this embodiment, the material of the source-drain silicide layer 310 can be nickel-silicon compound, cobalt-silicon compound or titanium-silicon compound.

[0107] It should be noted that, in the present embodiment, a gate mask layer 175 is formed on the top of the top gate layer 220 and on the bottom of the groove 230, and a grinding barrier layer 240 is formed on the sidewalls of the groove 230. Therefore, in the process of forming the source / drain silicide layer 310, the surface of the polysilicon gate layer 200 is covered, thereby avoiding the formation of a gate silicide layer on the top surface of the polysilicon gate layer 200. Therefore, in the subsequent planarization process of forming a metal gate layer, the gate silicide layer will not be ground, thereby avoiding metal contamination of the grinding machine.

[0108] It should also be noted that after forming the source-drain doped regions 300 and before forming the source-drain silicide layer 310, a step of forming a salicide block (SAB) layer is also included. By forming the silicide block layer, the region for forming the source-drain silicide layer 310 is exposed, and the region where the silicide layer is not desired to be formed is protected.

[0109] In the actual process, a silicide blocking layer 315 (eg, Fig.14 Specifically, the silicide blocking layer 315 may be located on the top of the gate mask layer 175 on the top gate layer 220 .

[0110] Therefore, a gate mask layer 175 and the silicide blocking layer 315 are formed on the top of the top gate layer 220. The film layer on the top gate layer 220 is thicker, which is beneficial to improving the polishing blocking effect in the subsequent planarization process, and correspondingly improving the improvement effect of the top surface depression problem of the polysilicon gate layer 200. The material of the silicide blocking layer 315 includes silicon nitride. The silicon nitride material has a large density and hardness, thereby improving the blocking effect in the subsequent planarization process.

[0111] refer to Fig.15 An interlayer dielectric layer 320 is formed on the substrate 100 at the side of the polysilicon gate layer 200 , and the interlayer dielectric layer 320 exposes the top surface of the polysilicon gate layer 200 in the second region 100L.

[0112] The interlayer dielectric layer 320 is used to isolate adjacent devices. Moreover, the interlayer dielectric layer 320 exposes the top of the polysilicon gate layer 200 in the second region 100L, so as to facilitate the removal of the polysilicon gate layer 200 in the second region 100L.

[0113] The material of the interlayer dielectric layer 320 is an insulating material, and the material includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon carbon oxynitride. In this embodiment, the material of the interlayer dielectric layer 320 is silicon oxide.

[0114] In this embodiment, the steps of forming the interlayer dielectric layer 320 include: forming a dielectric material layer (not shown) on the substrate 100 to cover the side walls and top of the polysilicon gate layer 200; and planarizing the dielectric material layer to retain the remaining dielectric material layer on the substrate 100 on the side of the polysilicon gate layer 200 for use as the interlayer dielectric layer 320.

[0115] In the present embodiment, during the process of planarizing the dielectric material layer, since the line width, top surface area and spacing between the top gate layer 220 and the adjacent top gate layer 220 are relatively small, it is beneficial to improve the top surface dipping problem of the polysilicon gate layer 200 in the first region 100M; moreover, a grinding barrier layer 240 and a side wall 280 are formed on the side wall of the groove 230, and the grinding barrier layer 240 and the side wall 280 can also play a grinding barrier role in the planarization process, thereby improving the improvement effect of the top surface dipping problem of the polysilicon gate layer 200 in the first region 100M.

[0116] In this embodiment, a deposition process is used to form the dielectric material layer. The deposition process includes a chemical vapor deposition process. In this embodiment, the planarization process includes a chemical mechanical planarization (CMP) process.

[0117] In this embodiment, during the process of forming the interlayer dielectric layer 320, the gate mask layer 175, the side wall 280 and the grinding barrier layer 240 are also planarized. Therefore, during the process of forming the interlayer dielectric layer 320, the gate mask layer 175 located on the top of the polysilicon gate layer 200, and the side wall 280 and the grinding barrier layer 240 higher than the top of the polysilicon gate layer 200 are also removed.

[0118] In this embodiment, the thickness of the gate dielectric layer 260 of the first region 100M is greater than the thickness of the gate dielectric layer 260 of the second region 100L. Therefore, the top surface of the polysilicon gate layer 200 of the first region 100M is higher than the top surface of the polysilicon gate layer 200 of the second region 100L. Therefore, accordingly, in order to expose the top surface of the polysilicon gate layer 200 of the second region 100L, after the interlayer dielectric layer 320 is formed, the top surface of the polysilicon gate layer 200 of the first region 100M is usually also exposed.

[0119] As an example, the interlayer dielectric layer 320 is filled in the groove 230 .

[0120] refer to Fig.16 , the polysilicon gate layer 200 in the second region 100L is removed, and a gate opening 330 is formed in the interlayer dielectric layer 320 . The gate opening 330 exposes the metal barrier layer 270 .

[0121] The gate opening 330 is used to provide a space for forming a metal gate layer.

[0122] In this embodiment, the metal barrier layer 270 of the second region 100L is used as an etching stop layer to remove the polysilicon gate layer 200 of the second region 100L. In this embodiment, one or both of a dry etching process and a wet etching process are used to remove the polysilicon gate layer 200 of the second region 100L.

[0123] refer to Fig.17 , a metal gate layer 340 is formed in the gate opening 330 .

[0124] The high-k gate dielectric layer 12, the metal barrier layer 270 and the metal gate layer 340 in the second region 100L are used to form a metal gate structure. Since the channel length of the second device is small, the operating voltage of the second device is small. As the critical dimensions of the device continue to shrink, the metal gate structure is used to improve the short channel effect.

[0125] When the device is working, the metal gate layer 340 is used to control the opening and closing of the conductive channel of the second device, and the high-k dielectric layer 12 is used to isolate the metal gate layer 340 from the conductive channel.

[0126] The material of the metal gate layer 340 is Al, Cu, Ag, Au, Pt, Ni, Ti or W. In this embodiment, the material of the metal gate layer 340 is Al.

[0127] In this embodiment, the step of forming the metal gate layer 340 includes: filling a metal gate material layer (not shown) in the gate opening 330, and the metal gate material layer is also formed on the top of the interlayer dielectric layer 320; planarizing the metal gate material layer, and retaining the remaining metal gate material layer located in the gate opening 330 for use as the metal gate layer 340.

[0128] In this embodiment, the process of forming the metal gate material layer includes one or more of an atomic layer deposition process, a physical vapor deposition process and an electrochemical plating process. In this embodiment, the planarization process includes a chemical mechanical planarization process.

[0129] During the planarization process of the metal gate material layer, since the line width, top surface area and spacing between the top gate layer 220 and the adjacent top gate layer 220 are relatively small, and the grinding barrier layer 240 located on the side wall of the groove 230 can act as a grinding barrier, the probability of a depression problem occurring on the top surface of the polysilicon gate layer 200 in the first area 100M is low.

[0130] refer to Fig.18 In this embodiment, the formation method further includes: after forming the metal gate layer 340 , forming a gate silicide layer 350 on the top surface of the top gate layer 220 .

[0131] Subsequent steps also include: forming a gate contact plug on the top surface of the top gate layer 220 , and the gate silicide layer 350 is used to reduce the contact resistance between the gate contact plug and the polysilicon gate layer 200 .

[0132] In this embodiment, the material of the gate silicide layer 350 may be a nickel silicon compound, a cobalt silicon compound or a titanium silicon compound.

[0133] In this embodiment, the step of forming the gate silicide layer 350 includes: forming a protection layer 360 covering the metal gate layer 200 , wherein the protection layer 360 exposes the first region 100M; and forming the gate silicide layer 350 on the polysilicon gate layer 200 exposed by the protection layer 360 .

[0134] The protection layer 360 is used to protect the metal gate layer 340. The protection layer 360 is a dielectric material, such as silicon oxide.

[0135] Combined with reference Fig.19, showing a top view of the first region 100M, subsequent steps also include: forming a first gate contact plug 370 in contact with the top gate layer 220, a second gate contact plug in contact with the metal gate layer 340, and a source-drain contact plug 380 in contact with the source-drain doped region 300.

[0136] For the convenience of illustration and explanation, Fig.19 Only the polysilicon gate layer 200, the groove 230, the first gate contact plug 370, the source-drain doped region 300 and the source-drain contact plug 380 are illustrated, and other related structures are not illustrated.

[0137] Figure 20 to Figure 25 1 is a schematic diagram of another embodiment of the method for forming a semiconductor structure of the present invention. The similarities between the embodiment of the present invention and the aforementioned embodiment are not repeated here. The difference between the embodiment of the present invention and the aforementioned embodiment is that after forming the polysilicon gate layer and before forming the interlayer dielectric layer, a gate silicide layer is formed on the top surface of the bottom gate layer at the bottom of the groove.

[0138] The steps of the method for forming the semiconductor structure of this embodiment are described in detail below with reference to the accompanying drawings.

[0139] refer to Fig. 20 and Fig.21 A discrete polysilicon gate layer 400 is formed on the substrate 401 of the first region 400M and the second region 400L, the polysilicon gate layer 400 of the first region 400M includes a bottom gate layer 410 and a top gate layer 420 protruding from the bottom gate layer 410, the top gate layer 420 and the bottom gate layer 410 form a groove 430, and a grinding barrier layer 440 is formed on the sidewall of the groove 430.

[0140] in, Fig.21 FIG. 4 is a top view of the polysilicon gate layer 400 in the first region 400M.

[0141] The channel direction of the device is the first direction (such as Fig.21 The direction perpendicular to the first direction is the second direction (e.g. Fig.21 The polysilicon gate layer 400 extends along the second direction.

[0142] As an example, there are multiple grooves 430 in each of the polysilicon gate layers 400 , and the multiple grooves 430 extend along the second direction and are arranged in parallel and at intervals along the first direction.

[0143] In this embodiment, the groove 430 also extends along the first direction at the end of the polysilicon gate layer 400, and a gate silicide layer will be formed on the top surface of the bottom gate layer 410 at the bottom of the groove 430 later, and the first gate contact plug in contact with the bottom gate layer 410 is connected through the gate silicide layer at the bottom of the groove 430. Specifically, the groove 430 located at the end of the polysilicon gate layer 400 and extending along the first direction is located above the isolation structure 405, so that the first gate contact plug can contact the gate silicide layer located above the isolation structure 405 later.

[0144] In this embodiment, in the step of forming the polysilicon gate layer 400 and the grinding barrier layer 440, a gate mask layer 450 is also formed on the bottom of the groove 430 and the top of the top gate layer 420. The gate mask layer 450 is used as an etching mask for patterning the polysilicon gate material layer to form the polysilicon gate layer 400.

[0145] refer to Fig. 22 The method for forming the semiconductor structure further includes: after forming the polysilicon gate layer 400 and the grinding barrier layer 440 and before forming the source and drain doping regions, removing the gate mask layer 450 at the bottom of the groove 430 to expose the bottom gate layer 410 at the bottom of the groove 430.

[0146] The bottom gate layer 410 at the bottom of the groove 430 is exposed, so that a gate silicide layer can be subsequently formed on the top surface of the bottom gate layer 410 at the bottom of the groove 430 .

[0147] Specifically, in this embodiment, the mask used when forming the groove 430 can be used to form a masking layer (not shown) on the substrate 401 and the polysilicon gate layer 400, and a masking opening (not shown) is formed in the masking layer above the groove 430. Then, the masking layer is used as a mask to etch the gate mask layer 450 at the bottom of the groove 430 along the masking opening.

[0148] Therefore, in this embodiment, the step of removing the gate mask layer 450 located at the bottom of the groove 430 can share a mask with the step of forming the groove 430, which is beneficial to saving a photomask and reducing costs.

[0149] In this embodiment, an anisotropic dry etching process is used to remove the gate mask layer 450 at the bottom of the groove 430. The longitudinal etching rate of the anisotropic dry etching process is much greater than the lateral etching rate, which is beneficial to reduce the probability of damaging the grinding barrier layer 440 located on the side wall of the groove 430 while removing the gate mask layer 450 at the bottom of the groove 430, thereby ensuring the grinding barrier effect of the grinding barrier layer 440 in the subsequent planarization process.

[0150] refer to Fig.23 After forming the polysilicon gate layer 400 and the grinding stop layer 440 , a gate silicide layer 480 is formed on the top surface of the bottom gate layer 410 at the bottom of the groove 430 .

[0151] By forming a gate silicide layer 480 on the bottom surface of the groove 430 , current can flow through the gate silicide layer 480 when the first device is working, thereby reducing the gate resistance.

[0152] A first gate contact plug in contact with the polysilicon gate layer 400 is subsequently formed, and the gate silicide layer 480 can reduce the contact resistance between the first gate contact plug and the polysilicon gate layer 400 .

[0153] In this embodiment, after forming the polysilicon gate layer 400 and the grinding barrier layer 440, the forming method further includes: forming source-drain doping regions 460 in the substrate 401 on both sides of the polysilicon gate layer 400; forming a source-drain silicide layer 470 (such as Fig.23 shown).

[0154] In this embodiment, in the step of forming the source / drain silicide layer 470 , a gate silicide layer 480 is formed on the top surface of the bottom gate layer 410 at the bottom of the groove 430 .

[0155] At the same time, source-drain contact plugs are formed on the top of the source-drain doped region 460 , and the contact resistance between the source-drain doped region 460 and the source-drain contact plugs is reduced by forming the source-drain silicide layer 470 .

[0156] It should be noted that a gate mask layer 450 is formed on the top of the top gate layer 420. Therefore, in the process of forming the gate silicide layer 480, the gate mask layer 450 is used as a protective layer to avoid forming the gate silicide layer 480 on the top surface of the polysilicon gate layer 400. Therefore, in the subsequent planarization process of forming the metal gate layer, the gate silicide layer 480 will not be ground, thereby avoiding metal contamination of the grinding machine. Moreover, in the present embodiment, the source and drain silicide layer 470 and the gate silicide layer 480 are formed in the same step, thereby simplifying the process steps and improving the process compatibility.

[0157] Specifically, a metal layer is formed on the surface of the source / drain doped region 460 and the bottom of the groove 430, and an annealing treatment is performed to allow the metal layer to react with the materials of the source / drain doped region 460 and the bottom gate layer 410, thereby converting the metal layer located on the surface of the source / drain doped region 460 into a source / drain silicide layer 470, and converting the metal layer located on the bottom of the groove 430 into a gate silicide layer 480. After the source / drain silicide layer 470 and the gate silicide layer 480 are formed, the remaining unreacted metal layer is removed.

[0158] refer to Fig.24 , an interlayer dielectric layer 495 is formed on the substrate 401 on the side of the polysilicon gate layer 400, and the interlayer dielectric layer 495 exposes the top surface of the polysilicon gate layer 400 in the second region 400L; the polysilicon gate layer 400 in the second region 400L is removed, and a gate opening (not shown) is formed in the interlayer dielectric layer 495; and a metal gate layer 490 is formed in the gate opening.

[0159] Combined with reference Fig.25 , showing a top view of the first region 400M. After forming the interlayer dielectric layer 495 and the metal gate layer 490, subsequent steps also include: forming a first gate contact plug 475 in contact with the bottom gate layer 410, a second gate contact plug (not shown) in contact with the metal gate layer 490, and a source-drain contact plug 485 in contact with the source-drain doped region 460.

[0160] For the convenience of illustration and explanation, Fig.25 Only the polysilicon gate layer 400, the first gate contact plug 475, the source-drain doped region 460 and the source-drain contact plug 485 are illustrated, and other related structures are not illustrated.

[0161] For the specific description of the method for forming the semiconductor structure described in this embodiment, reference may be made to the corresponding description in the aforementioned embodiments, and this embodiment will not be repeated here.

[0162] Accordingly, the present invention also provides a semiconductor structure. Fig.18 and Fig.19 , showing a schematic structural diagram of an embodiment of a semiconductor structure of the present invention.

[0163] The semiconductor structure includes: a substrate 100, including a first area 100M for forming a first device and a second area 100L for forming a second device, wherein the channel length of the first device is greater than the channel length of the second device; a polysilicon gate layer 200, located on the substrate 100 in the first area 100M, wherein the polysilicon gate layer 200 includes a bottom gate layer 210 and a top gate layer 220 protruding from the bottom gate layer 210, wherein the top gate layer 220 and the bottom gate layer 210 form a groove 230; a metal gate layer 340, located on the substrate 100 in the second area 100L; a grinding barrier layer 240, located on the side wall of the groove 230; and an interlayer dielectric layer 320, located on the substrate 100 at the side of the metal gate layer 340 and the polysilicon gate layer 200.

[0164] In the semiconductor structure, a polysilicon gate layer 200 is located on a substrate 100 in a first region 100M, and the polysilicon gate layer 200 includes a bottom gate layer 210 and a top gate layer 220 protruding from the bottom gate layer 210, and the top gate layer 220 and the bottom gate layer 210 form a groove 230, wherein the top gate layer 220 makes the line width dimension, top surface area, and spacing between the top gate layer 220 and the adjacent top gate layer 220 of the first region 100M smaller through the top gate layer 220, which is beneficial to improve the polysilicon gate layer 200 when forming an interlayer dielectric layer 320 or a metal gate layer 340. The top surface dishing problem of the polysilicon gate layer 200 is generated; in addition, the semiconductor structure also includes a grinding barrier layer 240, which is located on the side wall of the groove 230. In the process of planarizing the interlayer dielectric layer 320 or the metal gate layer 340, the grinding barrier layer 240 can play a grinding barrier role, thereby improving the improvement effect of the top surface dishing problem of the polysilicon gate layer 200 in the first area 100M; in summary, this embodiment is conducive to improving the performance of the polysilicon gate layer 200 in the first area 100M, thereby improving the performance of the semiconductor structure.

[0165] In this embodiment, the substrate 100 is used to form a planar field effect transistor as an example, and the substrate 100 is a planar substrate. In other embodiments, the substrate is used to form a fin field effect transistor (FinFET), and accordingly, the substrate includes a substrate and a fin protruding from the substrate.

[0166] In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the substrate may also be a substrate of other material types.

[0167] A channel length of the first device is greater than a channel length of the second device, so that an operating voltage of the first device is higher than an operating voltage of the second device.

[0168] In this embodiment, the first device includes one or both of a medium voltage device and a high voltage device, and the second device is a low voltage device. The operating voltages of the low voltage device, the medium voltage device, and the high voltage device increase in sequence. As an example, the operating voltage of the low voltage device is less than 1.5V, the operating voltage of the medium voltage device is 1V to 10V, and the operating voltage of the high voltage device is greater than 10V.

[0169] The first device may be an NMOS device or a PMOS device. Similarly, the second device may also be an NMOS device or a PMOS device. As an example, the first region 100M includes a first sub-region 100MN and a second sub-region 100MP, and the first sub-region 100MN and the second sub-region 100MP are used to form first devices of different channel conductivity types. For example, the first device located in the first sub-region 100MN is an NMOS device, and the first device located in the second sub-region 100MP is a PMOS device.

[0170] In this embodiment, an isolation structure 101 is also formed in the substrate 100. Specifically, the isolation structure 101 is located in the substrate 100 at the junction of the first region 100M and the second region 100L. In the first region 100M, the isolation structure 101 is also located in the substrate 100 at the junction of the first sub-region 100MN and the second sub-region 100MP.

[0171] The isolation structure 101 is used to isolate adjacent devices. In this embodiment, the isolation structure 101 is made of an insulating material, and the insulating material includes silicon oxide.

[0172] The polysilicon gate layer 200 is used as a device gate structure of the first device, so as to control the opening or closing of the channel of the first device.

[0173] The step of forming the metal gate layer 340 includes a process of planarizing the metal gate material layer. The larger the size of the metal gate layer 340 is, the higher the probability of a dishing problem on the top surface of the metal gate layer 340 during the planarization of the metal gate material. Since the first region 100M is used to form a first device, the operating voltage of the first device is relatively high, and the gate size of the first device is correspondingly relatively large. Therefore, by making the first device use the polysilicon gate layer 200, the metal gate layer is avoided in the first device, thereby avoiding the dishing problem of the top surface of the metal gate layer caused by the large gate size in the first region 100M.

[0174] By forming a groove 230 in the polysilicon gate layer 200 of the first region 100M, the line width, top surface area and spacing between the top gate layer 220 and the adjacent top gate layer 220 are made smaller. Therefore, in the process of planarizing the metal gate layer 340, the probability of over-grinding the polysilicon gate layer 200 in the first region 100M is low, which is beneficial to improving the top surface depression problem of the polysilicon gate layer 200 in the first region 100M, so that the top surface flatness of the polysilicon gate layer 200 in the first region 100M is higher, thereby correspondingly improving the structural integrity of the polysilicon gate layer 200 in the first region 100M.

[0175] In this embodiment, the first region 100M includes a first sub-region 100MN and a second sub-region 100MP, and the polysilicon gate layer 200 is separated on the first sub-region 100MN and the second sub-region 100MP.

[0176] In this embodiment, the material of the polysilicon gate layer 200 is polysilicon.

[0177] It should be noted that the ratio of the thickness of the bottom gate layer 210 to the total thickness of the polysilicon gate layer 200 should not be too small or too large. If the ratio is too small, it is easy to cause the thickness of the bottom gate layer 210 to be too small. Considering the influence of etching uniformity and load effect, in the process of forming the groove 230, the bottom gate layer 210 exposed by the top gate layer 220 is more likely to be etched through, that is, the groove 230 is easy to penetrate the entire polysilicon gate layer 200, thereby affecting the performance of the polysilicon gate layer 200 in the first region 100M, and when the conductive ions are injected into the bottom and sidewalls of the groove 230, they may pass through the bottom gate layer 210 and be injected into the film layer structure (for example: gate oxide layer) below the bottom gate layer 210, resulting in device failure; if the ratio is too large, correspondingly, the thickness of the top gate layer 220 is too small, then in the process of planarization of the metal gate layer 340, it is easy to cause the top gate layer 220 to be completely removed, thereby easily causing over-grinding of the bottom gate layer 210, and then easily reducing the improvement effect of the top surface depression problem of the polysilicon gate layer 200 in the first region 100M. To this end, in this embodiment, the thickness of the bottom gate layer 210 accounts for 1 / 5 to 1 / 3 of the total thickness of the polysilicon gate layer 200 .

[0178] It should also be noted that the line width of the top gate layer 220 and the line width of the groove 230 should not be too small or too large. If the line width of the top gate layer 220 and the line width of the groove 230 are too small, it is easy to increase the process difficulty of the photolithography process used when forming the groove 230, and the spacing between adjacent top gate layers 220 is too small, that is, the line width of the groove 230 is correspondingly too small, which is easy to cause adverse effects on the filling effect of the interlayer dielectric layer 320 in the groove 230; if the line width of the groove 230 is too large, it is easy to increase the risk of the top surface depression problem of the interlayer dielectric layer 320 located in the groove 230 during the planarization process of forming the metal gate layer 340, and if the line width of the top gate layer 220 is too large, when the metal gate layer 340 is formed, the probability of the top surface depression problem of the top gate layer 220 is high. For this reason, in this embodiment, the line width of the top gate layer 220 is 0.15 microns to 2 microns.

[0179] Similarly, the opening line width of the groove 230 is 0.15 micrometers to 2 micrometers.

[0180] It should be noted that if Fig.18 As shown, the number of the grooves 230 in the polysilicon gate layer 200 in the first region 100M is one. However, the number of the grooves 230 in the polysilicon gate layer 200 in the first region 100M is not limited thereto, and may be other numbers. Fig.19 , schematically shows a top view of the polysilicon gate layer 200 of the first region 100M. When the size of the first device is large, the number of grooves 230 in the polysilicon gate layer 200 of the first region 100M can be multiple, and the multiple grooves 230 can be arranged in parallel and spaced apart.

[0181] During the planarization process of forming the interlayer dielectric layer 320 and the metal gate layer 340 , the polishing barrier layer 240 can function as a polishing barrier, thereby improving the effect of improving the top surface depression problem of the polysilicon gate layer 200 in the first region 100M.

[0182] To this end, the grinding barrier layer 240 is made of a material with high hardness and density, so as to ensure that the grinding barrier layer 240 can play the role of a grinding barrier during the planarization process. Specifically, the material of the grinding barrier layer 240 is selected as follows: the density and hardness of the material of the grinding barrier layer 240 are greater than the hardness and density of the material of the polysilicon gate layer 200, the interlayer dielectric layer 320 and the metal gate layer 340. At the same time, considering the process compatibility, the grinding barrier layer 240 is made of a material with high process compatibility, so as to reduce process risks and costs.

[0183] In this embodiment, the material of the grinding stop layer 240 includes silicon nitride or silicon oxynitride. As an example, the material of the grinding stop layer 240 is silicon nitride.

[0184] In this embodiment, the semiconductor structure further includes: a gate mask layer 175 located at the bottom of the groove 230 , and the gate mask layer 175 and the polishing stop layer 240 are an integrated structure.

[0185] The gate mask layer 175 is used as a mask for patterning the polysilicon gate material layer to form a polysilicon gate layer 200 .

[0186] The gate mask layer 175 and the grinding barrier layer 240 are an integrated structure. In the step of forming the gate mask layer 175, the gate mask layer 175 located on the side wall of the groove 230 is used as the grinding barrier layer 240, thereby integrating the process of forming the gate mask layer 175, the process of forming the polysilicon gate layer 200, and the process of forming the grinding barrier layer 240, which is beneficial to improving process integration and process compatibility.

[0187] Therefore, the material of the gate mask layer 175 is the same as the material of the polishing stop layer 240 .

[0188] In this embodiment, the polysilicon gate layer 200 at the sidewall and bottom of the groove 230 is doped with conductive ions 235. The conductive ions 235 are used to reduce the resistance of the polysilicon gate layer 200 in the first region 100M, thereby reducing the gate resistance of the first device.

[0189] In this embodiment, the conductive ions 235 include B ions, Ga ions, In ions, P ions, As ions or Sb ions.

[0190] In this embodiment, the semiconductor structure also includes: a stacked structure 250, located between the polysilicon gate layer 200 and the substrate 100 of the first region 100M, and between the metal gate layer 340 and the substrate 100 of the second region 100L, the stacked structure 250 includes a gate dielectric layer 260 and a metal barrier layer 270 located on the gate dielectric layer 260; the thickness of the gate dielectric layer 260 of the first region 100M is greater than the thickness of the gate dielectric layer 260 of the second region 100L.

[0191] The gate dielectric layer 260 of the first region 100M is used to electrically isolate the polysilicon gate layer 200 from the channel of the first device; the gate dielectric layer 260 of the second region 100M is used to electrically isolate the metal gate layer 340 from the channel of the second device.

[0192] The thickness of the gate dielectric layer 260 in the first region 100M is greater than the thickness of the gate dielectric layer 260 in the second region 100L, so that the first device can withstand a larger operating voltage.

[0193] In this embodiment, the gate dielectric layer 260 of the first region 100M includes a gate oxide layer 11 and a high-k gate dielectric layer 12 located on the gate oxide layer 11, and the gate dielectric layer 260 of the second region 100L includes an interface buffer layer 13 and a high-k gate dielectric layer 12 located on the interface buffer layer 13. Since the gate oxide layer 11 is thicker than the interface buffer layer 13, the thickness of the gate dielectric layer 260 of the first region 100M is greater.

[0194] The interface buffer layer 13 is used to improve electron mobility, interface stability and device reliability. In this embodiment, the gate oxide layer 11 and the interface buffer layer 13 are made of silicon oxide.

[0195] In this embodiment, the material of the high-k gate dielectric layer 12 is a high-k dielectric material. Specifically, the material of the high-k gate dielectric layer 12 can be selected from HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO or Al2O3, etc. As an example, the material of the high-k gate dielectric layer 12 is HfO2.

[0196] The metal barrier layer 270 is used to isolate the gate dielectric layer 260 from the polysilicon gate layer 200, and to isolate the gate dielectric layer 260 from the metal gate layer 340, so as to protect the gate dielectric layer 260. Moreover, the metal barrier layer 270 is also used to prevent the easily diffusible ions (e.g., aluminum ions) in the metal gate layer 340 from diffusing into the gate dielectric layer 260. Specifically, the metal barrier layer 270 is used to protect the high-k gate dielectric layer 12, reduce the probability of damage to the high-k gate dielectric layer 12, and prevent the easily diffusible ions in the metal gate layer 340 from diffusing into the high-k gate dielectric layer 12. Among them, the metal barrier layer 270 also has a certain influence on the gate work function of the second device.

[0197] The material of the metal barrier layer 270 includes one or both of titanium nitride (TiN) and silicon-doped titanium nitride (TiSiN). In this embodiment, the material of the metal barrier layer 270 is titanium nitride.

[0198] In the actual process, the thickness of the metal barrier layer 270 is reasonably set to ensure that the metal barrier layer 270 can serve as an etching stop layer during the subsequent etching to remove the polysilicon gate layer 200 in the second area 100L. At the same time, the metal barrier layer 270 has a better blocking effect on easily diffusible ions in the metal gate layer.

[0199] The high-k gate dielectric layer 12, the metal barrier layer 270 and the metal gate layer 340 in the second region 100L are used to form a metal gate structure. Since the channel length of the second device is small, the operating voltage of the second device is small. As the critical dimensions of the device continue to shrink, the metal gate structure is used to improve the short channel effect.

[0200] When the device is working, the metal gate structure is used to control the opening and closing of the conductive channel of the second device.

[0201] The metal gate layer 340 is used to electrically lead out the metal gate structure. The material of the metal gate layer 340 is Al, Cu, Ag, Au, Pt, Ni, Ti or W. In this embodiment, the material of the metal gate layer 340 is Al.

[0202] In this embodiment, the semiconductor structure further includes: a sidewall spacer 280 located on the sidewalls of the polysilicon gate layer 200 and the metal gate layer 340 , and the sidewalls of the groove 230 .

[0203] The sidewall 280 is used to protect the sidewalls of the polysilicon gate layer 200 and the metal gate layer 340, and is also used to define the position of the source-drain doped region 300. Moreover, the sidewall 280 is also formed on the sidewall of the groove 230, which is beneficial to further reduce the probability of over-grinding the top surface of the polysilicon gate layer 200 in the first region 100M during the planarization process of forming the interlayer dielectric layer 320 and the metal gate layer 340, thereby further improving the top surface depression problem of the polysilicon gate layer 200.

[0204] In this embodiment, the material of the sidewall 280 includes silicon nitride. Silicon nitride has high hardness and density, and the polishing rate of the sidewall 280 during the planarization process is low, which further improves the top surface depression problem of the polysilicon gate layer 200 in the first region 100M.

[0205] The sidewall spacer 280 may be a stacked structure or a single-layer structure. As an example, the sidewall spacer 280 is a stacked structure, and the sidewall spacer 280 includes a first silicon oxide layer covering the sidewalls of the polysilicon gate layer 200 and the groove 230, a silicon nitride layer covering the sidewalls of the first silicon oxide layer, and a second silicon oxide layer located on the silicon nitride layer.

[0206] The semiconductor structure also includes: source-drain doped regions 300, located in the substrate 100 in the first region 100M on both sides of the polysilicon gate layer 200, and in the substrate 100 in the second region 100L on both sides of the metal gate layer 340; and a source-drain silicide layer 310, located between the top surface of the source-drain doped regions 300 and the interlayer dielectric layer 320.

[0207] The source-drain doped region 300 serves as a source region or a drain region of the formed device.

[0208] When the device is an NMOS device, the doped ions in the source and drain doping regions 300 are N-type ions, including P ions, As ions or Sb ions. When the device is a PMOS device, the doped ions in the source and drain doping regions 300 are P-type ions, including B ions, Ga ions or In ions.

[0209] The semiconductor structure generally further includes a source-drain contact plug located on the top of the source-drain doped region 300 and in contact with the source-drain doped region 300, and the source-drain silicide layer 310 is used to reduce the contact resistance between the source-drain doped region 300 and the source-drain contact plug. In this embodiment, the material of the source-drain silicide layer 310 can be a nickel-silicon compound, a cobalt-silicon compound, or a titanium-silicon compound.

[0210] The interlayer dielectric layer 320 is used to isolate adjacent devices. The material of the interlayer dielectric layer 320 is an insulating material, and the material includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon carbon nitride oxide. In this embodiment, the material of the interlayer dielectric layer 320 is silicon oxide.

[0211] In this embodiment, the top surface of the polysilicon gate layer 200 in the first region 100M is higher than the top surface of the polysilicon gate layer 200 in the second region 100L. Accordingly, the top surface of the interlayer dielectric layer 320 in the second region 100L is lower than the top surface of the interlayer dielectric layer 320 in the first region 100M. The interlayer dielectric layer 320 also exposes the top surface of the polysilicon gate layer 200 in the first region 100M. As an example, the interlayer dielectric layer 320 is filled in the groove 230.

[0212] In this embodiment, the semiconductor structure further includes: a gate silicide layer 350, which is located on the top surface of the top gate layer 220. The semiconductor structure generally also includes: a gate contact plug located on the top surface of the top gate layer 220 and in contact with the top gate layer 220, and the gate silicide layer 350 is used to reduce the contact resistance between the first gate contact plug and the polysilicon gate layer 200.

[0213] In this embodiment, the material of the gate silicide layer 350 may be a nickel silicon compound, a cobalt silicon compound or a titanium silicon compound.

[0214] Combined with reference Fig.19 , showing a top view of the first region 100M, the semiconductor structure also includes: a first gate contact plug 370 in contact with the top gate layer 220, a second gate contact plug (not shown) in contact with the metal gate layer 340, and a source-drain contact plug 380 in contact with the source-drain doped region 300.

[0215] For the convenience of illustration and explanation, Fig.19 Only the polysilicon gate layer 200 , the first gate contact plug 370 , the source-drain doped region 300 , and the source-drain contact plug 380 are illustrated, and other related structures are not illustrated.

[0216] The semiconductor structure can be formed by the formation method described in the above embodiment, or by other formation methods. For the specific description of the semiconductor structure described in this embodiment, reference can be made to the corresponding description in the above embodiment, and this embodiment will not be repeated here.

[0217] Fig.24 and Fig.25 1 is a schematic diagram of another embodiment of the semiconductor structure of the present invention. The similarities between the embodiment of the present invention and the above embodiment are not repeated here. The difference between the embodiment of the present invention and the above embodiment is that the gate silicide layer 480 is located on the top surface of the bottom gate layer 410 at the bottom of the groove (not shown).

[0218] By disposing a gate silicide layer 480 on the bottom surface of the groove 430, when the first device is working, current can flow through the gate silicide layer 480, thereby reducing the gate resistance. The gate silicide layer 480 is used to reduce the contact resistance between the first gate contact plug and the polysilicon gate layer 400.

[0219] The channel direction of the device is the first direction (such as Fig.25 The direction perpendicular to the first direction is the second direction (e.g. Fig.25 The polysilicon gate layer 400 extends along the second direction.

[0220] like Fig.25 As shown, as an example, there are multiple grooves 430 in each polysilicon gate layer 400, and the multiple grooves 430 extend along the second direction and are arranged in parallel and at intervals along the first direction.

[0221] In this embodiment, the groove 430 further extends along the first direction at the end of the polysilicon gate layer 400 , so that the groove 430 is connected, and the gate silicide layer 480 located at the bottom of the groove 430 is connected.

[0222] The semiconductor structure also includes: source and drain doped regions 460, located in the substrate 401 of the first region 400M on both sides of the polysilicon gate layer 200, and in the substrate 401 of the second region 400L on both sides of the metal gate layer 490; a source and drain silicide layer 470, located between the top surface of the source and drain doped regions 460 and the interlayer dielectric layer 495; the source and drain silicide layer 470 and the gate silicide layer 480 are made of the same material.

[0223] The source-drain silicide layer 470 is used to reduce the contact resistance between the source-drain doped region 460 and the source-drain contact plugs.

[0224] The source / drain silicide layer 470 and the gate silicide layer 480 are made of the same material because the source / drain silicide layer 470 and the gate silicide layer 480 are formed in the same step in this embodiment, thereby simplifying the process steps and improving process compatibility.

[0225] Combined with reference Fig.25 , showing a top view of the first area 400M, the semiconductor structure generally also includes: a first gate contact plug 475 located on the top of the top gate layer 420 and in contact with the top gate layer 420; a second gate contact plug (not shown) located on the top of the metal gate layer 490 and in contact with the metal gate layer 490; and a source-drain contact plug 485 located on the top of the source-drain doped region 460 and in contact with the source-drain doped region 460.

[0226] For the convenience of illustration and explanation, Fig.25 Only the polysilicon gate layer 400, the first gate contact plug 475, the source-drain doped region 460 and the source-drain contact plug 485 are illustrated, and other related structures are not illustrated.

[0227] The semiconductor structure can be formed by the formation method described in the above embodiment, or by other formation methods. For the specific description of the semiconductor structure described in this embodiment, reference can be made to the corresponding description in the above embodiment, and this embodiment will not be repeated here.

[0228] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, It is characterized in that include: A substrate, comprising a first region for forming a first device and a second region for forming a second device, wherein a channel length of the first device is greater than a channel length of the second device; A polysilicon gate layer, located on the substrate of the first region, the polysilicon gate layer comprising a bottom gate layer and a top gate layer protruding from the bottom gate layer, the top gate layer and the bottom gate layer forming a groove; a metal gate layer, located on the substrate in the second region; A grinding barrier layer is located on the sidewall of the groove; The interlayer dielectric layer is located on the substrate at the side of the metal gate layer and the polysilicon gate layer.

2. The semiconductor structure according to claim 1, It is characterized in that The polysilicon gate layer on the sidewall and bottom of the groove is doped with conductive ions.

3. The semiconductor structure according to claim 1, It is characterized in that The material of the polishing stop layer includes silicon nitride or silicon nitride oxide.

4. The semiconductor structure according to claim 1, It is characterized in that The thickness of the bottom gate layer accounts for one fifth to one third of the total thickness of the polysilicon gate layer.

5. The semiconductor structure according to claim 1, It is characterized in that The semiconductor structure further includes: a gate silicide layer located on the top surface of the top gate layer, or the gate silicide layer is located on the top surface of the bottom gate layer at the bottom of the groove.

6. The semiconductor structure according to claim 5, It is characterized in that The gate silicide layer is located on the top surface of the top gate layer; The semiconductor structure further includes: a gate mask layer located at the bottom of the groove, and the gate mask layer and the polishing barrier layer are an integrated structure.

7. The semiconductor structure according to claim 5, It is characterized in that The gate silicide layer is located on the top surface of the bottom gate layer at the bottom of the groove; The semiconductor structure further includes: source-drain doped regions located in the substrate in the first region on both sides of the polysilicon gate layer and in the substrate in the second region on both sides of the metal gate layer; A source-drain silicide layer, located between the top surface of the source-drain doped region and the interlayer dielectric layer; The source / drain silicide layer and the gate silicide layer are made of the same material.

8. The semiconductor structure according to claim 1, It is characterized in that The semiconductor structure further includes sidewalls located on the sidewalls of the polysilicon gate layer and the metal gate layer, and the sidewalls of the groove.

9. The semiconductor structure according to claim 1, It is characterized in that The opening line width of the groove is 0.15 μm to 2 μm.

10. The semiconductor structure according to claim 1, It is characterized in that The semiconductor structure also includes: a stacked structure located between the polysilicon gate layer and the substrate of the first region, and between the metal gate layer and the substrate of the second region, the stacked structure including a gate dielectric layer and a metal barrier layer located on the gate dielectric layer; the thickness of the gate dielectric layer in the first region is greater than the thickness of the gate dielectric layer in the second region.

11. A method for forming a semiconductor structure, It is characterized in that include: Providing a substrate, comprising a first region for forming a first device and a second region for forming a second device, wherein a channel length of the first device is greater than a channel length of the second device; forming separate polysilicon gate layers on the substrates of the first region and the second region, wherein the polysilicon gate layer of the first region comprises a bottom gate layer and a top gate layer protruding from the bottom gate layer, wherein the top gate layer and the bottom gate layer form a groove, and a grinding barrier layer is formed on the sidewall of the groove; forming an interlayer dielectric layer on the substrate at the side of the polysilicon gate layer, wherein the interlayer dielectric layer exposes the top surface of the polysilicon gate layer in the second region; removing the polysilicon gate layer in the second region and forming a gate opening in the interlayer dielectric layer; A metal gate layer is formed in the gate opening.

12. The method for forming a semiconductor structure according to claim 11, It is characterized in that The steps of forming the polysilicon gate layer include: forming a polysilicon gate material layer on the substrate; forming the groove in the polysilicon gate material layer in the first region; and patterning the polysilicon gate material layer to form the polysilicon gate layer separated in the first region and the second region.

13. The method for forming a semiconductor structure according to claim 12, It is characterized in that After forming the groove and before patterning the polysilicon gate material layer, the grinding stop layer is formed on the sidewall of the groove.

14. The method for forming a semiconductor structure according to claim 13, It is characterized in that The step of forming the grinding barrier layer comprises: after forming the groove and before patterning the polysilicon gate material layer, forming a gate mask material layer on the polysilicon gate material layer and the bottom and sidewall of the groove, wherein the gate mask material layer located on the sidewall of the groove is used as the grinding barrier layer; The step of patterning the polysilicon gate material layer includes: patterning the gate mask material layer, retaining the gate mask material layer located at the bottom and sidewalls of the groove, and extending at the top of the polysilicon gate material layer portion, and the top of the polysilicon gate material layer portion located in the second area, for use as a gate mask layer; using the gate mask layer as a mask, patterning the polysilicon gate material layer to form the polysilicon gate layer.

15. The method for forming a semiconductor structure according to claim 12, It is characterized in that The method for forming the semiconductor structure further comprises: after forming the groove and before patterning the polysilicon gate material layer, doping conductive ions into the polysilicon gate material layer at the bottom and sidewalls of the groove.

16. The method for forming a semiconductor structure according to claim 15, It is characterized in that The step of forming the groove comprises: forming a mask layer on the polysilicon gate material layer, the mask layer having a mask opening located in the first area; using the mask layer as a mask, etching a portion of the polysilicon gate material layer along the mask opening; The step of doping the polysilicon gate material layer at the bottom and sidewall of the groove with conductive ions comprises: using the mask layer as a mask, performing ion implantation on the polysilicon gate material layer exposed by the groove, wherein the ion implantation direction has an acute angle with the normal line of the substrate surface; After doping the polysilicon gate material layer at the bottom and sidewalls of the groove with conductive ions, the method for forming the semiconductor structure further includes: removing the mask layer.

17. The method for forming a semiconductor structure according to claim 16, It is characterized in that The implantation energy of the ion implantation is 1 KeV to 10 KeV.

18. The method for forming a semiconductor structure according to claim 11, It is characterized in that After forming the polysilicon gate layer and the grinding barrier layer and before forming the interlayer dielectric layer, the method for forming the semiconductor structure further includes: forming sidewalls on the sidewalls of the polysilicon gate layer and the grinding barrier layer on the sidewalls of the groove.

19. The method for forming a semiconductor structure according to claim 11, It is characterized in that The method for forming a semiconductor structure further includes: after forming the metal gate layer, forming a gate silicide layer on a top surface of the top gate layer; Alternatively, after forming the polysilicon gate layer and before forming the interlayer dielectric layer, a gate silicide layer is formed on the top surface of the bottom gate layer at the bottom of the groove.

20. The method for forming a semiconductor structure according to claim 19, It is characterized in that After forming the metal gate layer, forming a gate silicide layer on a top surface of the top gate layer; The step of forming the gate silicide layer includes: forming a protection layer covering the metal gate layer, wherein the protection layer exposes the first region; The gate silicide layer is formed on the polysilicon gate layer exposed by the protection layer.

21. The method for forming a semiconductor structure according to claim 19, It is characterized in that The method for forming the semiconductor structure further comprises: after forming the polysilicon gate layer and the grinding barrier layer and before forming the interlayer dielectric layer, forming source and drain doping regions in the substrate on both sides of the polysilicon gate layer; forming a source-drain silicide layer on the top surface of the source-drain doped region; Wherein, in the step of forming the source-drain silicide layer, a gate silicide layer is formed on the top surface of the bottom gate layer at the bottom of the groove.

22. The method for forming a semiconductor structure according to claim 21, It is characterized in that In the step of forming the polysilicon gate layer and the grinding barrier layer, a gate mask layer is also formed on the bottom of the groove and the top of the top gate layer; The method for forming the semiconductor structure further includes: after forming the polysilicon gate layer and the grinding barrier layer and before forming the source and drain doping regions, removing the gate mask layer at the bottom of the groove to expose the bottom gate layer at the bottom of the groove.

23. The method for forming a semiconductor structure according to claim 21, It is characterized in that The method for forming a semiconductor structure further includes: forming a silicide blocking layer on top of the top gate layer after forming the source and drain doping regions and before forming the source and drain silicide layer.

24. The method for forming a semiconductor structure according to claim 21, It is characterized in that The steps of forming the source-drain doped regions include: forming a shielding layer on the substrate, the shielding layer also covering the polysilicon gate layer of the first region, and forming doped openings in the shielding layer on both sides of the polysilicon gate layer; using the shielding layer as a mask, ion doping the substrate exposed by the doped openings to form the source-drain doped regions; and removing the shielding layer.

25. The method for forming a semiconductor structure according to claim 11, It is characterized in that The material of the polishing stop layer includes silicon nitride or silicon nitride oxide.

26. The method for forming a semiconductor structure according to claim 11, It is characterized in that The thickness of the bottom gate layer accounts for one fifth to one third of the total thickness of the polysilicon gate layer.

27. The method for forming a semiconductor structure according to claim 11, It is characterized in that The opening line width of the groove is 0.15 μm to 2 μm.

28. The method for forming a semiconductor structure according to claim 11, It is characterized in that The method for forming the semiconductor structure also includes: in the step of forming the polysilicon gate layer, forming a stacked structure located between the polysilicon gate layer and the substrate, the stacked structure including a gate dielectric layer and a metal barrier layer located on the gate dielectric layer; the thickness of the gate dielectric layer in the first region is greater than the thickness of the gate dielectric layer in the second region.

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