Processor-oriented on-chip high-speed high-precision voltage glitch monitoring circuit

Abstract

The application discloses a high-speed high-precision voltage sudden change monitoring circuit on a chip for a processor, and particularly relates to a monitoring technology for a processor power supply network, and belongs to the technical field of electronic circuits.The voltage monitoring circuit provided by the application uses a digital standard unit to build a monitoring circuit comprising a time-digital conversion module, a bubble suppression and decoding module, an adjustable delay module and an H-shaped clock tree module, has a small circuit cost, is easy to deploy, supports monitoring of voltage sag and voltage surge at the same time, and realizes real-time accurate grid monitoring of the on-chip power supply voltage.The application improves monitoring accuracy and robustness through a mirror sampling clock unit, further improves monitoring accuracy through the bubble suppression and decoding module, and improves the monitoring range of the voltage through a multi-stage delay adjustable unit, thereby solving the technical problem that a conventional voltage monitoring circuit is difficult to simultaneously ensure speed, accuracy and a monitoring range.

Description

Technical Field

[0001] This invention belongs to the field of electronic circuit technology, and in particular relates to an on-chip high-speed, high-precision voltage surge monitoring circuit for processors. Background Technology

[0002] With the widespread use of electronic devices and the rapid development of the Internet, integrated circuit technology is constantly innovating, bringing more complex and varied tasks to processors. These tasks often change drastically, requiring not only rapid processor response but also constant monitoring of the power supply network's stability. Since changes in processor tasks directly affect changes in supply current, this can lead to sudden voltage fluctuations.

[0003] Voltage surges include voltage drops and voltage spikes. A voltage drop occurs when the power supply network cannot provide sufficient power in time when the processor load increases, causing a sudden drop in voltage in the circuit. This phenomenon frequently occurs in large processors. Voltage drops may lead to insufficient timing margins, or even failure to meet minimum requirements, resulting in calculation errors. Such calculation errors can seriously affect the normal operation of electronic devices and the accuracy of data. Voltage spikes generally occur when the processor load decreases, caused by a momentary overcharging of the power supply network, resulting in a sudden increase in the supply voltage. Voltage spikes may cause excessive circuit breakdown and reduced lifespan, thereby shortening the lifespan of electronic devices.

[0004] To improve processor efficiency and robustness, it is essential to monitor the supply voltage quickly and accurately. Currently, voltage monitoring circuits often struggle to simultaneously guarantee speed, accuracy, and monitoring range; therefore, we require a high-speed, high-precision voltage monitoring circuit. Summary of the Invention

[0005] The purpose of this invention is to provide an on-chip high-speed, high-precision voltage surge monitoring circuit for processors. It utilizes digital standard units to construct a monitoring circuit including a time-to-digital conversion module, a bubble suppression and decoding module, an adjustable delay module, and an H-type clock tree module. The circuit is low-cost, easy to deploy, and supports monitoring of both voltage drops and surges, achieving real-time, accurate, and gridded monitoring of the on-chip power supply voltage. This invention improves monitoring accuracy and robustness through a mirrored sampling clock unit, further enhances monitoring accuracy through a bubble suppression and decoding module, and expands the voltage monitoring range through a multi-level adjustable delay unit, thus solving the technical problem that conventional voltage monitoring circuits struggle to simultaneously guarantee speed, accuracy, and monitoring range.

[0006] To solve the above-mentioned technical problems, the specific technical solution of the present invention is as follows:

[0007] A high-speed, high-precision on-chip voltage surge monitoring circuit for processors includes a time-to-digital conversion module, a bubble suppression and decoding module, an adjustable delay module, and an H-type clock tree module.

[0008] The time-to-digital converter module encodes the chip's power supply voltage to form a digital code value. The module includes a measurement unit and a sampling unit. The measurement unit receives the input measurement signal, which consists of an inverter chain composed of several inverters. The input measurement signal flips sequentially in the inverter chain. By observing the effect of voltage on inverter delay, the voltage change is mapped to the change in inverter chain delay. Therefore, the current power supply voltage of the chip can be reflected by the number of inverters that successfully transmit the signal within one clock cycle. The sampling unit counts the number of inverters that successfully transmit the signal by sampling the outputs of all inverters in the measurement unit at the rising edge of the clock, forming a set of digital code values.

[0009] The bubble suppression and decoding module is used to eliminate the bubble problem caused by metastable sampling of the trigger and form a decoded value. The bubble suppression and decoding module includes a bubble suppression unit and a decoding unit. The bubble suppression unit receives the digital code value from the time-to-digital converter module and eliminates the bubble problem caused by metastable sampling of the trigger by shifting the bubble backward, forming a set of bubble-suppressed code values. The decoding unit receives the output code value from the bubble suppression unit and decodes the code value using a preamble detector to form a decoded value, which is the number of inverters that successfully transmitted the input signal.

[0010] The adjustable delay module supports multi-level adjustment and is used to adjust the phase of the input signal to form the input measurement signal of the time-to-digital converter module. It is also used to compensate for the impact of voltage surges on the H-type clock tree module, thereby reducing the impact of voltage surges on the synchronization between the measurement unit and the sampling unit. The adjustable delay module includes a mirror sampling clock unit and a multi-level adjustable delay unit. The mirror sampling clock unit is used to compensate for the impact of voltage surges on the H-type clock tree module, thereby reducing the impact of voltage surges on the synchronization between the measurement unit and the sampling unit. The multi-level adjustable delay unit includes a coarse delay circuit and a fine delay circuit. Before silicon processing, the coarse delay circuit is used to adjust the range of the time-to-digital converter module. After silicon processing, the fine delay circuit is adjusted according to the process and temperature to ensure that the time-to-digital converter module covers the range of the voltage to be measured.

[0011] The H-type clock tree module is used to reduce clock skew and form the input clock signal for the time-to-digital converter module.

[0012] Preferably, the H-type clock tree module includes several clock buffers, and the input clock of the sampling unit is formed by using one clock buffer to drive four clock buffers.

[0013] Preferably, the sampling unit includes: several rising edge triggered flip-flops and several inverters; the flip-flops sample the output of the inverter chain in the measurement unit at the rising edge of each clock cycle, and the output of the flip-flops is connected to the inverter every other clock cycle, thereby converting the output code value into a thermometer code, which represents the number of inverters in the measurement unit that successfully transmit the input measurement signal within one clock cycle.

[0014] Preferably, the method for handling the bubble problem caused by metastable sampling of triggers includes the following steps:

[0015] Step 101: Read the output code value of the sampling module and scan from left to right to see if there is a '01' code value. If it exists, proceed to step 102; otherwise, proceed to step 103.

[0016] Step 102: Replace the '01' code value with the '10' code value, then proceed to step 101;

[0017] Step 103: Use a leading detector to find the position where the first '1' of the code value appears from right to left. This position represents the number of inverters in the measurement unit where the input measurement signal has been successfully transmitted.

[0018] Preferably, the mirror sampling clock unit includes: a mirror H-type clock tree circuit and a mirror sampling circuit; wherein the mirror H-type clock tree circuit is consistent with the circuit of the H-type clock tree module, and the mirror sampling circuit is consistent with the circuit of the sampling unit; the first output signal at the end of the mirror H-type clock tree circuit, i.e., the clock of the first flip-flop of the mirror sampling circuit, is used as the input signal of the multi-level delay adjustable unit.

[0019] Preferably, the delay fine-tuning circuit includes: several 4-to-1 multiplexers and several inverters; first, the output signal of the mirror sampling clock unit passes through 2×3=6 inverters; the first input of the first 4-to-1 multiplexer is directly connected to the output signal of the mirror sampling clock unit, the second input is connected to the output signal after passing through 2 inverters, the third input is connected to the output signal after passing through 4 inverters, and the fourth input is connected to the output signal after passing through 6 inverters; then, the output signal of the first 4-to-1 multiplexer passes through 4×2×3=24 inverters; the first input of the second 4-to-1 multiplexer is directly connected to the output signal of the first 4-to-1 multiplexer, the second input is connected to the output signal after passing through 8 inverters, the third input is connected to the output signal after passing through 16 inverters, and the fourth input is connected to the output signal after passing through 24 inverters; then, the output signal of the second 4-to-1 multiplexer passes through 4... 2×2×3=96 inverters; the first input of the third 4-to-1 multiplexer is directly connected to the output signal of the second 4-to-1 multiplexer, the second input is connected to the output signal after passing through 32 inverters, the third input is connected to the output signal after passing through 64 inverters, the fourth input is connected to the output signal after passing through 96 inverters; and so on, that is, the output signal of the nth 4-to-1 multiplexer is then connected to 4... n ×2×3 inverters; adjust the number of cascaded 4-to-1 multiplexers according to the required adjustment accuracy.

[0020] Preferably, the delay coarse adjustment circuit includes several inverters. The number of inverters is adjusted during the pre-silicon circuit design stage so that the delay fine adjustment circuit is in the middle position, that is, when the last stage 4-to-1 multiplexer selects the signal of the second input terminal and the other 4-to-1 multiplexers select the signal of the fourth input terminal, the code value output by the bubble suppression and decoding module is half the number of inverters in the measurement unit.

[0021] The on-chip high-speed, high-precision voltage surge monitoring circuit for processors of the present invention has the following advantages:

[0022] (1) This invention compensates for the impact of voltage fluctuations on the H-type clock tree module by mirroring the sampling clock unit, thereby reducing the impact of voltage fluctuations on the synchronization between the measurement unit and the sampling unit, improving the detection circuit's ability to resist deviations such as process, voltage, temperature, and aging (PVTA), thereby improving monitoring accuracy and robustness.

[0023] (2) The bubble problem caused by metastable sampling of the trigger is eliminated by the bubble suppression and decoding module, thereby improving the monitoring accuracy.

[0024] (3) The multi-level delay adjustable unit composed of delay coarse adjustment circuit and delay fine adjustment circuit improves the monitoring range and flexibility, and can support more diverse working scenarios. Attached Figure Description

[0025] Figure 1 This is a schematic diagram of the on-chip high-speed, high-precision voltage surge monitoring circuit for processors according to the present invention;

[0026] Figure 2 This is a schematic diagram of the H-type clock tree module of the present invention;

[0027] Figure 3 This is a schematic diagram of the adjustable delay module of the present invention;

[0028] Figure 4 This is a schematic diagram of the multi-level delay adjustable unit of the present invention. Detailed Implementation

[0029] To better understand the purpose, structure, and function of this invention, the following detailed description of an on-chip high-speed, high-precision voltage surge monitoring circuit for processors, in conjunction with the accompanying drawings, is provided.

[0030] like Figure 1 As shown, the on-chip high-speed, high-precision voltage surge monitoring circuit for the processor includes: a time-to-digital conversion module, a bubble suppression and decoding module, an adjustable delay module, and an H-type clock tree module.

[0031] The system clock is the chip's input clock and serves three purposes: as the input signal for the adjustable delay module, as the input clock for the H-type clock tree module, and as the clock signal for the bubble suppression and decoding module.

[0032] The time-to-digital converter module encodes the chip's supply voltage into a digital code value. This module includes a measurement unit and a sampling unit. The measurement unit comprises a chain of 64 inverters. The input measurement signal is flipped sequentially through the inverter chain, and the voltage change is mapped to the change in inverter chain delay by observing the effect of voltage on inverter delay. The sampling unit includes 64 rising-edge triggered flip-flops and several inverters. The flip-flops sample the output of the inverter chain in the measurement unit at the rising edge of each clock cycle. The outputs of the flip-flops are connected to inverters at intervals of one, thus converting the output code value into a thermometer code. This code value represents the number of inverters in the measurement unit where the input measurement signal was successfully transmitted within one clock cycle.

[0033] Ideally, the output of the sampling unit should be the thermometer code value, assuming it is 64'b 111110000…00; however, at the sampling moment, the measuring unit is very likely to be in a flip-flop state, i.e., metastable sampling occurs, which may result in the bubble phenomenon shown below:

[0034] Ideal case: 64'b 111110000…00

[0035] One bubble case: 64'b 111101000…00

[0036] Two bubble configurations: 64'b 111101010…00

[0037] …

[0038] The bubble suppression and decoding module is used to eliminate bubbles in the digital code values, forming decoded values. This module includes a bubble suppression unit and a decoding unit. The bubble suppression unit receives the digital code values ​​from the time-to-digital converter and eliminates bubbles caused by metastable sampling of the triggers by shifting the bubbles backward, forming a set of bubble-suppressed code values. The decoding unit receives the output code values ​​from the bubble suppression unit and decodes them using a preamble detector to form the decoded value, which represents the number of inverters that successfully transmitted the input signal. The specific steps are as follows:

[0039] Step 101: Read the output code value of the sampling module and scan from left to right to see if there is a '01' code value. If it exists, proceed to step 102; otherwise, proceed to step 103.

[0040] Step 102: Replace the '01' code value with the '10' code value, then proceed to step 101;

[0041] Step 103: Use a leading detector to find the position where the first '1' of the code value appears from right to left. This position represents the number of inverters in the measurement unit where the input measurement signal has been successfully transmitted.

[0042] The code value after removing bubbles is as follows:

[0043] Ideal case: 64'b 111110000…00

[0044] One bubble configuration: 64'b 111101000…00 → 64'b 111110000…00

[0045] Two bubble configurations: 64'b 111101010…00 → 64'b 111111000…00

[0046] …

[0047] The H-type clock tree module is used to reduce the clock skew of the trigger sampling, such as Figure 2 As shown, the module includes 85 clock buffers, and uses one clock buffer to drive four clock buffers to form the input clock of the sampling unit.

[0048] The adjustable delay module is used to adjust the phase of the input signal, providing an initial delay. It can also actively adjust the delay length based on PVTA changes, ultimately forming the input measurement signal for the time-to-digital converter. For example... Figure 3 As shown, the module includes a mirror sampling clock unit and a multi-level adjustable delay unit.

[0049] When a voltage surge occurs, the voltage on the H-type clock tree module may change faster than that of the sampling unit, leading to a decrease in sampling accuracy. The mirrored sampling clock unit can compensate for the impact of voltage surges on the H-type clock tree module, thereby reducing the impact of voltage surges on the synchronization between the measurement and sampling units. This unit includes a mirrored H-type clock tree circuit and a mirrored sampling circuit. The mirrored H-type clock tree circuit is identical to the circuitry of the H-type clock tree module, and the mirrored sampling circuit is identical to the circuitry of the sampling unit. The first output signal at the end of the mirrored H-type clock tree circuit (i.e., the clock of the first flip-flop in the mirrored sampling circuit) is used as the input signal for the multi-stage delay adjustable unit.

[0050] like Figure 4 As shown, the multi-level adjustable delay unit includes a coarse delay adjustment circuit and a fine delay adjustment circuit. Before siliconization, the coarse delay adjustment circuit is used to adjust the range of the time-to-digital converter module. After siliconization, the fine delay adjustment circuit is adjusted according to the process and temperature to make the time-to-digital converter module cover the range of the voltage to be measured.

[0051] The delay fine-tuning circuit includes three 4-to-1 multiplexers and 126 inverters. First, the output signal of the mirror sampling clock unit passes through six inverters. The first input of the first 4-to-1 multiplexer is directly connected to the output signal of the mirror sampling clock unit; the second input is connected to the output signal after passing through two inverters; the third input is connected to the output signal after passing through four inverters; and the fourth input is connected to the output signal after passing through six inverters. Next, the output signal of the first 4-to-1 multiplexer passes through 24 inverters. The first input of the second 4-to-1 multiplexer is directly connected to the output signal of the first 4-to-1 multiplexer; the second input is connected to the output signal after passing through eight inverters; the third input is connected to the output signal after passing through sixteen inverters; and the fourth input is connected to the output signal after passing through twenty-four inverters. Finally, the output signal of the second 4-to-1 multiplexer passes through 96 inverters. The first input of the third 4-to-1 multiplexer is directly connected to the output signal of the second 4-to-1 multiplexer. The second input is connected to the output signal after passing through 32 inverters. The third input is connected to the output signal after passing through 64 inverters, and the fourth input is connected to the output signal after passing through 96 inverters. MUX_SEL is a 6-bit selection signal with 64 positions. MUX_SEL is adjusted according to the required adjustment precision.

[0052] The coarse-tuning delay circuit includes 43 inverters. To achieve higher voltage resolution and ensure the initial code value is in the middle of the measurement range, the number of inverters is adjusted during the pre-silicon circuit design stage. This ensures that when the fine-tuning delay circuit is in the middle range (i.e., MUX_SEL = 6'b 011111), the code value output by the bubble suppression and decoding module is half the number of inverters in the measurement unit (i.e., 32). During the post-silicon calibration stage, under fixed voltage and temperature conditions, by adjusting MUX_SEL of the fine-tuning delay circuit, it is ensured that the code value output by the bubble suppression and decoding module is equal to 32 under process deviations. This means that the input signal under test is transmitted through 32 of the 64 inverters. This ensures the measurement range for both voltage spikes and drops, thus widening the voltage monitoring range.

[0053] It is understood that the present invention has been described through some embodiments, and those skilled in the art will recognize that various changes or equivalent substitutions can be made to these features and embodiments without departing from the spirit and scope of the invention. Furthermore, under the teachings of the present invention, these features and embodiments can be modified to adapt to specific situations and materials without departing from the spirit and scope of the invention. Therefore, the present invention is not limited to the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of this application are within the protection scope of the present invention.

Claims

1. A high-speed, high-precision on-chip voltage surge monitoring circuit for processors, characterized in that, Includes a time-to-digital conversion module, a bubble suppression and decoding module, an adjustable delay module, and an H-type clock tree module; The time-to-digital converter module is used to encode the chip's power supply voltage to form a digital code value. The time-to-digital converter module includes a measurement unit and a sampling unit. The measurement unit is used to receive the input measurement signal, which includes an inverter chain composed of several inverters. The input measurement signal will be flipped one by one in the inverter chain. By the effect of voltage on the inverter delay, the voltage change is mapped to the change in inverter chain delay. Thus, the current power supply voltage of the chip can be reflected by the number of inverters that successfully transmit the signal in one clock cycle. The sampling unit is used to count the number of inverters that have been successfully transmitted. It samples the output of all inverters in the measurement unit at the rising edge of the clock to form a set of digital code values. The bubble suppression and decoding module is used to eliminate the bubble problem caused by metastable sampling of the trigger and form a decoded value. The bubble suppression and decoding module includes a bubble suppression unit and a decoding unit. The bubble suppression unit is used to receive the digital code value from the time-to-digital conversion module and eliminate the bubble problem caused by metastable sampling of the trigger by shifting the bubble backward, forming a set of bubble-suppressed code values. The decoding unit is used to receive the output code value from the bubble suppression unit and decode the code value using a preamble detector to form a decoded value, i.e., the number of inverters that successfully transmitted the input signal. The adjustable delay module supports multi-level adjustment and is used to adjust the phase of the input signal to form the input measurement signal of the time-to-digital converter module. It also compensates for the impact of voltage surges on the H-type clock tree module, thereby reducing the impact of voltage surges on the synchronization between the measurement unit and the sampling unit. The adjustable delay module includes a mirror sampling clock unit and a multi-level adjustable delay unit. The mirror sampling clock unit compensates for the impact of voltage surges on the H-type clock tree module, thereby reducing the impact of voltage surges on the synchronization between the measurement unit and the sampling unit. The multi-level adjustable delay unit includes a coarse delay circuit and a fine delay circuit. Before silicon processing, the coarse delay circuit is used to adjust the range of the time-to-digital converter module. After silicon processing, the fine delay circuit is adjusted according to the process and temperature to ensure that the time-to-digital converter module covers the range of the voltage to be measured. The H-type clock tree module is used to reduce clock skew and form the input clock signal for the time-to-digital converter module.

2. The on-chip high-speed, high-precision voltage surge monitoring circuit for processors according to claim 1, characterized in that, The H-type clock tree module includes several clock buffers, and one clock buffer drives four clock buffers to form the input clock of the sampling unit.

3. The on-chip high-speed, high-precision voltage surge monitoring circuit for processors according to claim 1, characterized in that, The sampling unit includes: several rising edge triggered flip-flops and several inverters; the flip-flops sample the output of the inverter chain in the measurement unit at the rising edge of each clock cycle, and the output of the flip-flops is connected to the inverter every other clock cycle, thereby converting the output code value into a thermometer code, which represents the number of inverters in the measurement unit that successfully transmit the input measurement signal within one clock cycle.

4. The on-chip high-speed, high-precision voltage surge monitoring circuit for processors according to claim 1, characterized in that, The method for handling the bubble problem caused by metastable sampling of triggers includes the following steps: Step 101: Read the output code value of the sampling module and scan from left to right to see if there is a '01' code value. If it exists, proceed to step 102; otherwise, proceed to step 103. Step 102: Replace the '01' code value with the '10' code value, then proceed to step 101; Step 103: Use a leading detector to find the position where the first '1' of the code value appears from right to left. This position represents the number of inverters in the measurement unit where the input measurement signal has been successfully transmitted.

5. The on-chip high-speed, high-precision voltage surge monitoring circuit for processors according to claim 1, characterized in that, The mirror sampling clock unit includes: a mirror H-type clock tree circuit and a mirror sampling circuit; wherein the mirror H-type clock tree circuit is consistent with the circuit of the H-type clock tree module, and the mirror sampling circuit is consistent with the circuit of the sampling unit; the first output signal at the end of the mirror H-type clock tree circuit, i.e. the clock of the first flip-flop of the mirror sampling circuit, is used as the input signal of the multi-level delay adjustable unit.

6. The on-chip high-speed, high-precision voltage surge monitoring circuit for processors according to claim 1, characterized in that, The delay fine-tuning circuit includes several 4-to-1 multiplexers and several inverters. First, the output signal of the mirror sampling clock unit passes through 2 × 3 = 6 inverters. The first input of the first 4-to-1 multiplexer is directly connected to the output signal of the mirror sampling clock unit, the second input is connected to the output signal after passing through 2 inverters, the third input is connected to the output signal after passing through 4 inverters, and the fourth input is connected to the output signal after passing through 6 inverters. Next, the output signal of the first 4-to-1 multiplexer passes through 4 × 2 × 3 = 24 inverters. The first input of the second 4-to-1 multiplexer is directly connected to the output signal of the first 4-to-1 multiplexer, the second input is connected to the output signal after passing through 8 inverters, the third input is connected to the output signal after passing through 16 inverters, and the fourth input is connected to the output signal after passing through 24 inverters. Finally, the output signal of the second 4-to-1 multiplexer passes through 4 × 2 × 3 = 24 inverters. 2 ×2×3=96 inverters; the first input of the third 4-to-1 multiplexer is directly connected to the output signal of the second 4-to-1 multiplexer, the second input is connected to the output signal after passing through 32 inverters, the third input is connected to the output signal after passing through 64 inverters, the fourth input is connected to the output signal after passing through 96 inverters; and so on, that is, the output signal of the nth 4-to-1 multiplexer is then connected to 4... n ×2×3 inverters; adjust the number of cascaded 4-to-1 multiplexers according to the required adjustment accuracy.

7. The on-chip high-speed, high-precision voltage surge monitoring circuit for processors according to claim 1, characterized in that, The delay coarse adjustment circuit includes several inverters. The number of inverters is adjusted during the pre-silicon circuit design stage so that the delay fine adjustment circuit is in the middle position, that is, when the last stage 4-to-1 multiplexer selects the signal of the second input terminal and the other 4-to-1 multiplexers select the signal of the fourth input terminal, the code value output by the bubble suppression and decoding module is half the number of inverters in the measurement unit.

Images