Overlay error compensation method and system, and computer-readable storage medium

Abstract

The embodiments of the present application disclose an overlay error compensation method, system, and storage medium. The overlay error compensation method includes providing N wafer groups, each of the N wafer groups includes M wafers, and each of the M wafers includes a current layer and a previous layer; wherein N and M are both positive integers greater than or equal to 2; determining a first overlay error of each wafer based on the device structure of the current layer and the previous layer, and calculating a photolithography compensation value for each wafer based on the first overlay error; calculating a first average compensation value for each wafer group based on the photolithography compensation value; calculating a second average compensation value for the N wafer groups based on the first average compensation value; and if the second average compensation value is within a preset range, feeding the second average compensation value back to a batch control system to compensate for the N+1th wafer group.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of semiconductor technology, and more specifically, to an overlay error compensation method and system, and a computer-readable storage medium. Background Art

[0002] A key parameter characterizing integrated circuit manufacturing technology is the minimum feature size, namely the critical dimension (CD). As the critical dimension shrinks, even to the nanometer level, it becomes possible to have millions of devices on each chip.

[0003] In the preparation process of semiconductor devices, it is usually necessary to form a layered structure with upper and lower layers stacked together, and form various components in the corresponding layers. In the layered structure with upper and lower layers stacked together, the current layer and the previous layer need to be aligned so that a component formed in the current layer corresponds to or is connected to a component in the previous layer up and down, etc. Therefore, the overlay between the upper and lower layers becomes an important factor affecting the performance of the device.

[0004] However, the overlay compensation method in the related art cannot effectively improve the overlay accuracy, thereby affecting the product yield. Summary of the Invention

[0005] Embodiments of the present application provide an overlay error compensation method and system, and a computer-readable storage medium capable of improving overlay accuracy.

[0006] The overlay error compensation method of the embodiment of the present application includes:

[0007] Providing N wafer groups, each of the N wafer groups includes M wafers, and each of the M wafers includes a current layer and a previous layer; wherein N and M are both positive integers greater than or equal to 2;

[0008] determining a first overlay error of each wafer according to the device structures of the current layer and the previous layer, and calculating a lithography compensation value of each wafer according to the first overlay error;

[0009] Calculating a first average compensation value of each wafer group according to the photolithography compensation value;

[0010] Calculating a second average compensation value of the N wafer groups according to the first average compensation value;

[0011] If the second average compensation value is within a preset range, the second average compensation value is fed back to the batch control system to compensate the N+1th wafer group.

[0012] According to some embodiments of the present application, the device structure includes a transistor and / or a bit line and / or a word line and / or a contact structure.

[0013] According to some embodiments of the present application, determining the first overlay error of each wafer according to the device structures of the current layer and the previous layer includes:

[0014] Obtaining the first overlay error using a light diffraction method specifically includes: obtaining a first overlay error between the device structure of the current layer and the device structure of the previous layer in the X direction and the Y direction based on the diffraction beam intensity distribution formed by the device structure of the current layer and the device structure of the previous layer.

[0015] According to some embodiments of the present application, determining the first overlay error of each wafer according to the device structures of the current layer and the previous layer includes:

[0016] Obtaining the first overlay error using a scanning electron microscope specifically includes: obtaining first overlay errors in the X and Y directions between the device structure of the current layer and the device structure of the previous layer based on scanned images of the device structure of the current layer and the device structure of the previous layer.

[0017] According to some embodiments of the present application, the method further comprises:

[0018] A second overlay error of each wafer is determined according to the overlay marks of the current layer and the previous layer, and a machine compensation value of each wafer is calculated according to the second overlay error.

[0019] According to some embodiments of the present application, determining the second overlay error of each wafer according to the overlay marks of the current layer and the previous layer includes:

[0020] The second overlay error is obtained by using a light wave reflection method, specifically comprising: obtaining the second overlay error between the overlay mark of the current layer and the overlay mark of the previous layer in the X direction and the Y direction based on the image formed by the reflection of the overlay mark of the current layer and the overlay mark of the previous layer.

[0021] According to some embodiments of the present application, calculating the lithography compensation value of each wafer according to the first overlay error includes: determining the lithography compensation value by non-zero compensation and / or independent compensation;

[0022] Calculating the tool compensation value of each wafer according to the second overlay error includes: determining the tool compensation value by non-zero compensation and / or independent compensation.

[0023] According to some embodiments of the present application, each of the lithography compensation value, the tool compensation value, the first average compensation value, and the second average compensation value includes one or more of the following parameters:

[0024] X-direction translation, Y-direction translation, wafer rotation parameters, wafer non-orthogonality parameters, wafer X-direction extension, wafer Y-direction extension, exposure area rotation parameters, exposure area magnification, exposure area asymmetry rotation parameters, exposure area asymmetry magnification.

[0025] According to some embodiments of the present application, the method further comprises:

[0026] According to the second overlay error, compensation values ​​for different machine models are obtained, and each wafer group is compensated according to the machine model corresponding to each wafer group. According to some embodiments of the present application, the method further includes:

[0027] Compensation is performed on the next wafer group of the current wafer group according to the first average compensation value.

[0028] The overlay error compensation system of the embodiment of the present application includes:

[0029] N wafer groups, each of the N wafer groups includes M wafers, and each of the M wafers includes a current layer and a previous layer; wherein N and M are positive integers greater than or equal to 2;

[0030] a first measurement unit, configured to determine a first overlay error of each wafer according to the device structures of the current layer and the previous layer;

[0031] a first calculation unit, configured to calculate a lithography compensation value for each wafer according to the first overlay error, calculate a first average compensation value for each wafer group according to the lithography compensation value, and calculate a second average compensation value for the N wafer groups according to the first average compensation value;

[0032] The batch control system is configured to compensate the N+1th wafer group when the second average compensation value is within a preset range.

[0033] According to some embodiments of the present application, the first measurement unit obtains the first overlay error using a light diffraction method.

[0034] According to some embodiments of the present application, the first measurement unit obtains the first overlay error using a scanning electron microscope.

[0035] According to some embodiments of the present application, further comprising a second measuring unit and a second calculating unit;

[0036] The second measurement unit is used to determine a second overlay error of each wafer according to the overlay marks of the current layer and the previous layer; and the second calculation unit is used to calculate a machine compensation value of each wafer according to the second overlay error.

[0037] According to some embodiments of the present application, the second measurement unit obtains the second overlay error using a light wave reflection method.

[0038] According to some embodiments of the present application, the first calculation unit determines the lithography compensation value through non-zero compensation and / or independent compensation; the second calculation unit determines the tool compensation value through non-zero compensation and / or independent compensation.

[0039] According to some embodiments of the present application, each of the lithography compensation value, the tool compensation value, the first average compensation value, and the second average compensation value includes one or more of the following parameters:

[0040] X-direction translation, Y-direction translation, wafer rotation parameters, wafer non-orthogonality parameters, wafer X-direction extension, wafer Y-direction extension, exposure area rotation parameters, exposure area magnification, exposure area asymmetry rotation parameters, exposure area asymmetry magnification.

[0041] According to some embodiments of the present application, the batch control system obtains compensation values ​​for machines of different models according to the second overlay error, and compensates each wafer group according to the machine model corresponding to each wafer group.

[0042] The computer-readable storage medium of the embodiment of the present application stores a computer program thereon, and when the computer program is executed by a processor, the steps of any one of the methods described above are implemented.

[0043] The overlay error compensation method and system of the embodiment of the present application determines the overlay error of the actual device structure of the current layer and the previous layer of the wafer, calculates the compensation value based on the overlay error, and then compensates for the next layer of the wafer. Compared with the measurement of the overlay mark used in the related art, the compensation method of the embodiment of the present application is more accurate and the overlay accuracy is significantly improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figures 1A to 1D Shown is a schematic diagram of the overlay error on the wafer

[0045] Figure 2 FIG. 1 is a flow chart of an overlay error compensation method according to an embodiment of the present application.

[0046] Figure 3 FIG. 1 shows a flow chart of an overlay error compensation method according to another embodiment of the present application.

[0047] Figure 4 Shown is a schematic diagram of an overlay error compensation system according to an embodiment of the present application. DETAILED DESCRIPTION

[0048] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art. Like reference numerals in the figures represent like or similar structures, and thus their detailed description will be omitted.

[0049] During the operation of an overlay device (such as a photolithography machine), all fields on a semiconductor material (such as a silicon wafer) are exposed one by one, and then the semiconductor material is replaced until all the semiconductor materials are exposed. After the semiconductor material is processed, the mask is replaced, and then a second layer of patterns is exposed on the semiconductor material, which is a repeated exposure. The pattern exposed by the second mask layer must accurately overlap with the pattern exposed by the first mask layer, which is called overlay. In theory, the two layers of patterns should completely overlap, but in reality, due to the existence of high-order distortion, the positions of the two layers of patterns deviate, which is an overlay deviation value.

[0050] like Figures 1A to 1D Schematic diagram of the overlay error on the wafer.

[0051] refer to Figure 1A , Figure 1A This is a schematic diagram of overlay error. The box represents the fixed area of ​​the wafer, point A represents the position of the overlay mark of the previous layer, and point A' represents the position of the overlay mark of the current layer. a and b are the deviations of point A' relative to point A on the X and Y axes of the coordinate system, respectively. The overlay error of point A' relative to point A is represented by (a, b), and can be represented on the wafer by a vector pointing from point A to point A'.

[0052] refer to Figure 1B , Figure 1B This is a schematic diagram of the overlay error detection result display interface. In order to more accurately detect the process deviation of different positions of the wafer, multiple overlay marks are usually set in each layer of the wafer, so that the overlay errors of different positions of the wafer can be obtained in one test, that is, Figure 1B Generally speaking, a standard length is set for the overlay error of a layer (different standard lengths are set for the overlay errors of different layers), so that when the length of an overlay error is less than (or less than or equal to) the standard length of the layer where it is located, it is determined that the overlay error is within a normal range.

[0053] Figure 1C This is a schematic diagram of the wafer inspection interface where the overlay error is mostly within the normal range. The vectors representing the overlay error are all short, indicating that the overlay error is small.

[0054] Figure 1DThis is a schematic diagram of the wafer inspection interface where the overlay error is mostly abnormal. The longer the vector representing the overlay error, the larger the overlay error.

[0055] As described in the background, to improve overlay accuracy, related technologies employ overlay compensation methods to minimize overlay deviation to zero. However, using existing compensation methods and performing etching processes can cause pattern shifts on the wafer, failing to achieve the desired results.

[0056] The inventors of this application discovered during their research that in the related art, the overlay deviation value is determined by the overlay mark formed in the photoresist layer on the surface of the wafer and the overlay mark of the previous layer. Since the overlay mark in the photoresist layer can only be used to simulate the graphics and cannot represent the actual position of the real graphics, the pattern in the related art will be offset, resulting in low overlay accuracy, which affects the product yield.

[0057] like Figure 2 As shown, Figure 2 The flowchart of the overlay error compensation method according to an embodiment of the present application is shown. The overlay compensation method according to an embodiment of the present application includes:

[0058] Step S110, providing N wafer groups, each of the N wafer groups including M wafers, each of the M wafers including a current layer and a previous layer; wherein N and M are both positive integers greater than or equal to 2;

[0059] Step S120, determining a first overlay error of each wafer according to the device structures of the current layer and the previous layer, and calculating a lithography compensation value of each wafer according to the first overlay error;

[0060] Step S130 , calculating a first average compensation value for each wafer group according to the photolithography compensation value;

[0061] Step S140, calculating a second average compensation value of the N wafer groups according to the first average compensation value;

[0062] In step S150 , if the second average compensation value is within the preset range, the second average compensation value is fed back to the batch control system to compensate the N+1th wafer group.

[0063] The overlay compensation method of the embodiment of the present application determines the overlay error of the actual device structure of the current layer and the previous layer of the wafer, and calculates the compensation value based on the overlay error, and then compensates for the next layer of the wafer. Compared with the measurement of overlay marks used in related technologies, the compensation method of the embodiment of the present application measures the actual graphics of the current layer and the previous layer, which can more realistically reflect the position between the device structure of the current layer and the previous layer, and finally derives the prepared compensation value, thereby significantly improving the overlay accuracy.

[0064] Step S110 , providing N wafer groups, each of the N wafer groups including M wafers, each of the M wafers including a current layer and a previous layer; wherein N and M are both positive integers greater than or equal to 2.

[0065] In this step, N wafer groups may represent N batches of wafers. In one embodiment, N may be another positive integer such as 2, 3, or 4. Each batch of wafer groups includes M wafers, and M may be, for example, greater than or equal to 10 and less than or equal to 50, but is not limited thereto.

[0066] Each of the M wafers includes a current layer and a previous layer, each of which includes a device structure. Of course, the current layer and the previous layer may also include overlay marks. It is understood that by measuring the offset of the current layer pattern relative to the previous layer pattern, the quality of the photolithography process can be verified, that is, whether the overlay error meets a preset value can be determined.

[0067] In a specific implementation, the layer may be adjacent to or not adjacent to the previous layer. For example, when the layer is not adjacent to the previous layer, another dielectric film layer, conductive metal layer, etc. may be deposited between the layer and the previous layer.

[0068] Step S120 , determining a first overlay error of each wafer according to the device structures of the current layer and the previous layer, and calculating a lithography compensation value of each wafer according to the first overlay error.

[0069] In this step, the first overlay error for each wafer is determined by obtaining the position between the device structures in the previous layer and the device structures in the current layer corresponding to the device structures in the previous layer. Because this step obtains the position between the actual device structures in the current layer and the previous layer, the value of the first overlay error more accurately reflects the positional deviation between the actual patterns in the current layer and the previous layer of the wafer, thereby making the determined lithography compensation value more accurate.

[0070] It is worth mentioning that the term "lithography compensation value" can be understood as compensation for the lithography / etching process of the wafer. Specifically, the "lithography compensation value" can be determined by the control accuracy of the mask itself, the movement synchronization accuracy of the mask stage and the silicon wafer stage, the lens magnification and aberration control.

[0071] The device structure of the wafer may include one or more of transistors, bit lines, word lines, and contact structures. For example, the device structure may include only one of transistors, bit lines, word lines, and contact structures. Of course, it may also be any combination of transistors, bit lines, word lines, and contact structures.

[0072] The first overlay error of the embodiment of the present application can be determined by measuring using an image-based overlay (IBO) measurement technology, a scanning electron microscope (SEM), and a novel diffraction measurement technology (IDM, In Device Metrology, also known as In Die Measurement).

[0073] In one embodiment, determining a first overlay error of each wafer based on device structures of a current layer and a previous layer includes:

[0074] Obtaining the first overlay error using the light diffraction method specifically includes: obtaining the first overlay error in the X direction and the Y direction between the device structure of the current layer and the device structure of the previous layer according to the diffraction beam intensity distribution formed by the device structure of the current layer and the device structure of the previous layer.

[0075] Specifically, after the device structures are formed in the front layer and the current layer of the wafer respectively, the optical diffraction method is used for measurement, and the first overlay error of the device structure of the current layer and the device structure of the front layer in the X direction and the Y direction is obtained based on the diffraction beam intensity distribution formed by the device structure of the current layer and the device structure of the front layer.

[0076] Based on the principle of optical diffraction, the principle of overlay error measurement using the above-mentioned overlay mark is as follows:

[0077] As+d=K*(OV+d);

[0078] As-d = K*(OV-d);

[0079] OV=d*[(As +d +As -d ) / (As +d -As -d )];

[0080] Wherein, OV represents the unknown first overlay error, As+d represents the intensity of the diffracted light obtained by measuring the device structure of the current layer and the device structure of the previous layer, As-d represents the intensity of the diffracted light obtained by measuring the device structure of the next layer of the current layer and the device structure of the previous layer, K represents the coefficient related to the thickness, and d represents the offset value.

[0081] In some embodiments, the first overlay error can also be obtained using a scanning electron microscope, specifically including: obtaining the first overlay error between the device structure of the current layer and the device structure of the previous layer in the X direction and the Y direction based on the scanned images of the device structure of the current layer and the device structure of the previous layer, that is, directly obtaining the overlay error between the device structure of the current layer and the device structure of the previous layer in the X direction and the Y direction by measuring the scanned images.

[0082] Step S130 , calculating a first average compensation value for each wafer group according to the photolithography compensation value;

[0083] Step S140 , calculating a second average compensation value of the N wafer groups according to the first average compensation value.

[0084] In step S130 and step S140 , a first average compensation value of each wafer group is calculated based on the photolithography compensation value, and then second average compensation values ​​of the N wafer groups are calculated based on the first average compensation value.

[0085] Specifically, each wafer in each wafer group has a corresponding lithography compensation value. Therefore, the first average compensation value = (lithography compensation value of the first wafer + lithography compensation value of the second wafer + lithography compensation value of the Mth wafer) / M. Similarly, each of the N wafer groups has a first average compensation value. Therefore, the second average compensation value = (first average compensation value of the first wafer group + first average compensation value of the second wafer group + first average compensation value of the Nth wafer group) / N.

[0086] By obtaining an averaged compensation value, the influence of extreme values ​​is avoided, so that the wafer can be optimally compensated, thereby ensuring that the overlay accuracy meets the requirements.

[0087] In step S150 , if the second average compensation value is within the preset range, the second average compensation value is fed back to the batch control system to compensate the N+1th wafer group.

[0088] In this step, if the second average compensation value is within a preset range, the batch control system can compensate the lithography / etching processes of the N+1 wafer groups based on this second average compensation value, achieving early compensation. Furthermore, by determining whether the second average compensation value exceeds the preset range, the impact of extreme values ​​can be avoided, improving compensation accuracy.

[0089] Specifically, as mentioned above, the second average compensation value = (the first average compensation value of the first wafer group + the first average compensation value of the second wafer group + ... the first average compensation value of the Nth wafer group) / N. Therefore, the lithography compensation value of each wafer in each wafer group will affect the final second average compensation value. If the second average compensation value is not considered to be within the preset range and the wafer processing is directly compensated according to the second average compensation value, it may be that the second average compensation value is larger or smaller due to one or more abnormal wafers, resulting in the second average compensation value not being the compensation value required by the majority of wafers, and ultimately leading to a decrease in compensation accuracy.

[0090] like Figure 3 As shown, Figure 3FIG. 1 shows a flow chart of an overlay error compensation method according to another embodiment of the present application.

[0091] In an embodiment of the present application, the overlay error compensation method further includes: step S260, determining the second overlay error of each wafer according to the overlay marks of the current layer and the previous layer, and calculating the machine compensation value of each wafer according to the second overlay error.

[0092] In step S260, the second overlay error is determined by the overlay marks of the current layer and the previous layer to obtain a tool compensation value for each wafer. Based on the tool compensation value, the lithography machine can be compensated to improve the overlay accuracy of the wafer.

[0093] It can be understood that steps S210 to S250 may be the same as steps S110 to S150 of the above embodiment, and will not be described in detail here.

[0094] It should be noted that the obtained machine compensation value is used to compensate for the error of the machine itself. After the machine is compensated once or twice based on the machine compensation value, the error of the machine itself has been corrected, and there is no need to continue to obtain a second set of engraving errors.

[0095] In one embodiment, determining a second overlay error of each wafer based on overlay marks of a current layer and a previous layer includes:

[0096] The second overlay error is obtained by using a light wave reflection method, specifically including: obtaining the second overlay error between the overlay mark of the current layer and the overlay mark of the previous layer in the X direction and the Y direction according to the image formed by the reflection of the overlay mark of the current layer and the overlay mark of the previous layer.

[0097] It is understood that overlay marks can include AIM (advanced imaging metrology) structures composed of periodic materials, bar-in-bar structures composed of single line structures, box-in-box structures, frame-in-frame structures, or any other structure that can accurately identify edge features and calculate interlayer overlay based on optical methods. Considering the currently most commonly used minimum resolution requirements of visible light or near-infrared optics, the size of the overlay mark is not limited to the existing fixed period and size. The minimum line period can be reduced to 1 micron, the minimum line width can be reduced to 500 nanometers, and the size of the entire overlay mark area can be 10 microns or larger.

[0098] In an example embodiment, a lithography compensation value for each wafer is calculated based on a first overlay error, including: determining the lithography compensation value through non-zero compensation (None Zero Offset, NZO) and / or independent compensation (Correction Per Exposure, CPE); and a tool compensation value for each wafer is calculated based on a second overlay error, including: determining the lithography compensation value, the tool compensation value, the first average compensation value, and the second average compensation value through non-zero compensation and / or independent compensation.

[0099] It is understood that non-zero compensation refers to compensation for the entire wafer, while independent compensation refers to compensation for a partial area of ​​the wafer.

[0100] It should be noted that each of the lithography compensation value, the tool compensation value, the first average compensation value, and the second average compensation value in the embodiment of the present application includes one or more of the following:

[0101] X-direction translation, Y-direction translation, wafer rotation parameters, wafer non-orthogonality parameters, wafer X-direction extension, wafer Y-direction extension, exposure area rotation parameters, exposure area magnification, exposure area asymmetry rotation parameters, exposure area asymmetry magnification.

[0102] Specifically, the compensation values ​​include grid parameters: X / Y translation (Tx, Ty), X / Y wafer rotation (Rx, Ry), and X / Y grid magnification (Mx, My). Exposure area parameters include X / Y reticle rotation (R'x, R'y) and X / Y reticle magnification (M'x, M'y).

[0103] The following description will be made by taking an example where the compensation value includes the grid parameter translation (Tx, Ty) in the X / Y direction.

[0104] The position of an overlay mark can be represented by the coordinates of the overlay mark on a two-dimensional horizontal plane. Correspondingly, the first overlay error between the current layer and the previous layer can be represented by a vector on the two-dimensional horizontal plane. For example, assuming that the position of an overlay mark on the current layer is (x1, y1) and the corresponding overlay mark on the previous layer is (x2, y2), then the first overlay deviation of the current layer at position (x1, y1) relative to the previous layer at the corresponding position is (x1-x2, y1-y2).

[0105] Similarly, the second overlay error can also be expressed using the above-mentioned X / Y direction translation (Tx, Ty) parameters, which will not be described in detail here.

[0106] The overlay error compensation method of the embodiment of the present application further includes: the batch control system obtains compensation values ​​for different machine models based on the second overlay error, and compensates each wafer group based on the machine model corresponding to each wafer group.

[0107] Typically, a wafer or a group of wafers needs to be processed by multiple tools of different models. In this embodiment, the compensation values ​​for different tool models are obtained based on the second overlay error. This allows the batch control system to perform corresponding compensation based on the tool model corresponding to the wafer group. In other words, the compensation values ​​for different tool models can be combined to compensate the wafers.

[0108] Specifically, the different machine compensation values ​​corresponding to multiple different models of machines A, B, C and D are A1, B1, C1 and D1 respectively. If a wafer needs to be processed by machines A, B, C, then A1, B1, C1 are directly called. If a wafer needs to be processed by machines B, C and D, then B1, C1 and D1 are directly called.

[0109] It is understandable that different models of machines include but are not limited to I-line lithography machines, KrF lithography machines, ArF lithography machines, EUV lithography machines and electron beam lithography machines.

[0110] The overlay error compensation method of the embodiment of the present application further includes compensating the next wafer group of the current wafer group according to the first average compensation value.

[0111] Specifically, as mentioned above, the first average compensation value = (lithography compensation value of the first wafer + lithography compensation value of the second wafer + ... lithography compensation value of the Mth wafer) / M, then the first average compensation value is the compensation value of one of the N wafer groups, and the next wafer group of one of the wafer groups can be compensated according to the first average compensation value.

[0112] like Figure 4 As shown, Figure 4 Shown is a schematic diagram of an overlay error compensation system of an embodiment of the present application. On the other hand, an overlay error compensation system is further provided in the embodiment of the present application. The system 10 includes: N wafer groups 11, a first measurement unit 12, a first calculation unit 13 and a batch control system 14. Each wafer group in the N wafer groups includes M wafers, and each wafer in the M wafers includes a current layer and a previous layer; wherein N and M are both positive integers greater than or equal to 2; the first measurement unit 12 is used to determine the first overlay error of each wafer according to the device structure of the current layer and the previous layer; the first calculation unit 13 is used to calculate the lithography compensation value of each wafer according to the first overlay error, and calculate the first average compensation value of each wafer group according to the lithography compensation value, and calculate the second average compensation value of the N wafer groups according to the first average compensation value; the batch control system 14 is used to compensate the N+1th wafer group when the second average compensation value is within a preset range.

[0113] In one embodiment, the first measurement unit 12 obtains the first overlay error using a light diffraction method.

[0114] In one embodiment, the first measurement unit 12 obtains the first overlay error using a scanning electron microscope.

[0115] The overlay error compensation system of the embodiment of the present application further includes a second measuring unit 15 and a second calculating unit 16.

[0116] The second measurement unit 15 is used to determine a second overlay error of each wafer according to the overlay marks of the current layer and the previous layer; the second calculation unit 16 is used to calculate a machine compensation value of each wafer according to the second overlay error.

[0117] In one embodiment, the second measurement unit 15 obtains the second overlay error using a light wave reflection method.

[0118] In one embodiment, the first calculation unit 12 determines the lithography compensation value through non-zero compensation and / or independent compensation; the second calculation unit 15 determines the tool compensation value through non-zero compensation and / or independent compensation.

[0119] In one embodiment, the batch control system 14 determines the tool compensation values ​​corresponding to different models of tools based on the information of each wafer group.

[0120] In another aspect of the present application, a computer scale storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps of any one of the above methods are implemented.

[0121] The computer-readable storage medium of an embodiment of the present application stores a program product capable of implementing the above-mentioned method of this specification. In some possible implementations, various aspects of the present application may also be implemented in the form of a program product, which includes program code. When the program product is executed on a terminal device, the program code is used to cause the terminal device to execute the steps described in the above-mentioned method section of this specification according to various exemplary embodiments of the present application.

[0122] The program product of the present application may be a portable compact disc read-only memory (CD-ROM) and include program code, and may be run on a terminal device, such as a personal computer. However, the program product of the present application is not limited thereto. In this application document, a readable storage medium may be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device.

[0123] The program product may employ any combination of one or more readable media. The readable medium may be a readable signal medium or a readable storage medium. The readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or component, or any combination thereof. More specific examples (a non-exhaustive list) of readable storage media include: an electrical connection with one or more wires, a portable disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof.

[0124] A computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, which carries readable program code. Such propagated data signals may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A readable signal medium may also be any readable medium other than a readable storage medium that can transmit, propagate, or transfer a program for use by or in conjunction with an instruction execution system, apparatus, or device.

[0125] The program code embodied on the readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.

[0126] The program code for performing the operations of the present application can be written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Java, C++, and the like, as well as conventional procedural programming languages ​​such as "C" or similar programming languages. The program code can be executed entirely on the user computing device, partially on the user device, as a stand-alone software package, partially on the user computing device and partially on a remote computing device, or entirely on a remote computing device or server. In cases involving a remote computing device, the remote computing device can be connected to the user computing device through any type of network, including a local area network (LAN) or a wide area network (WAN), or can be connected to an external computing device (e.g., via the Internet using an Internet service provider).

[0127] It should be noted that, although several modules or units of the device for action execution are mentioned in the above detailed description, this division is not mandatory. In fact, according to the embodiment of the application, the features and functions of two or more modules or units described above can be concretized in one module or unit. On the contrary, the features and functions of one module or unit described above can be further divided into multiple modules or units to be concretized.

[0128] Furthermore, although the steps of the method of the present application are described in a particular order in the accompanying drawings, this does not require or imply that the steps must be performed in this particular order, or that all steps shown must be performed to achieve the desired results. Additionally or alternatively, some steps may be omitted, multiple steps may be combined into one step, and / or one step may be decomposed into multiple steps.

[0129] Through the description of the above embodiments, it is easy for those skilled in the art to understand that the example embodiments described herein can be implemented by software or by combining software with necessary hardware. Therefore, the technical solution according to the embodiments of the present application can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (which can be a CD-ROM, a USB flash drive, a mobile hard disk, etc.) or on a network, and includes several instructions to enable a computing device (which can be a personal computer, a server, a mobile terminal, or a network device, etc.) to execute the method according to the embodiments of the present application.

[0130] In the application examples, the terms "first", "second", and "third" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance; the term "plurality" refers to two or more, unless otherwise expressly defined. Terms such as "installed", "connected", "connected", and "fixed" should be understood in a broad sense. For example, "connected" can mean a fixed connection, a detachable connection, or an integral connection; "connected" can mean a direct connection or an indirect connection through an intermediate medium. For those skilled in the art, the specific meanings of the above terms in the application examples can be understood according to the specific circumstances.

[0131] In the description of the application embodiments, it should be understood that the terms "up", "down", "left", "right", "front", "back", etc., indicating directions or positional relationships, are based on the directions or positional relationships shown in the accompanying drawings. They are only for the convenience of describing the application embodiments and simplifying the description, and do not indicate or imply that the device or unit referred to must have a specific direction, be constructed and operated in a specific direction. Therefore, they cannot be understood as limitations on the application embodiments.

[0132] Throughout this specification, terms such as "one embodiment," "some embodiments," and "specific embodiments" mean that the specific features, structures, materials, or characteristics described in conjunction with that embodiment or example are included in at least one embodiment or example of the claimed invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

[0133] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Those skilled in the art will readily appreciate that various modifications and variations of the present invention are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention shall be included within the scope of protection of the present invention.

Claims

1. A method for compensating overlay error, characterized in that: include: Providing N wafer groups, each of the N wafer groups includes M wafers, and each of the M wafers includes a current layer and a previous layer; wherein N and M are both positive integers greater than or equal to 2; determining a first overlay error of each wafer according to the device structures of the current layer and the previous layer, and calculating a lithography compensation value of each wafer according to the first overlay error; Calculating a first average compensation value of each wafer group according to the photolithography compensation value; Calculating a second average compensation value of the N wafer groups according to the first average compensation value; If the second average compensation value is within a preset range, the second average compensation value is fed back to the batch control system to compensate the N+1th wafer group.

2. The overlay error compensation method according to claim 1, wherein: The device structure includes at least one or more of a transistor, a bit line, a word line and a contact structure.

3. The overlay error compensation method according to claim 1, wherein: Determining a first overlay error of each wafer according to the device structures of the current layer and the previous layer includes: Obtaining the first overlay error using a light diffraction method specifically includes: obtaining a first overlay error between the device structure of the current layer and the device structure of the previous layer in the X direction and the Y direction based on the diffraction beam intensity distribution formed by the device structure of the current layer and the device structure of the previous layer.

4. The overlay error compensation method according to claim 1, wherein: Determining a first overlay error of each wafer according to the device structures of the current layer and the previous layer includes: Obtaining the first overlay error using a scanning electron microscope specifically includes: obtaining first overlay errors in the X and Y directions between the device structure of the current layer and the device structure of the previous layer based on scanned images of the device structure of the current layer and the device structure of the previous layer.

5. The overlay error compensation method according to any one of claims 1 to 4, characterized in that: The method further comprises: A second overlay error of each wafer is determined according to the overlay marks of the current layer and the previous layer, and a machine compensation value of each wafer is calculated according to the second overlay error.

6. The overlay error compensation method according to claim 5, characterized in that: Determining a second overlay error of each wafer according to the overlay marks of the current layer and the previous layer includes: The second overlay error is obtained by using a light wave reflection method, specifically comprising: obtaining the second overlay error between the overlay mark of the current layer and the overlay mark of the previous layer in the X direction and the Y direction based on the image formed by the reflection of the overlay mark of the current layer and the overlay mark of the previous layer.

7. The overlay error compensation method according to claim 6, wherein: Calculating the lithography compensation value of each wafer according to the first overlay error includes: determining the lithography compensation value by non-zero compensation and / or independent compensation; Calculating the tool compensation value of each wafer according to the second overlay error includes: determining the tool compensation value by non-zero compensation and / or independent compensation.

8. The overlay error compensation method according to claim 7, wherein: Each of the lithography compensation value, the tool compensation value, the first average compensation value, and the second average compensation value includes one or more of the following parameters: X-direction translation, Y-direction translation, wafer rotation parameters, wafer non-orthogonality parameters, wafer X-direction extension, wafer Y-direction extension, exposure area rotation parameters, exposure area magnification, exposure area asymmetry rotation parameters, exposure area asymmetry magnification.

9. The overlay error compensation method according to claim 5, wherein: The method further comprises: Compensation values ​​for machines of different models are obtained according to the second overlay error, and compensation is performed on each wafer group according to the machine model corresponding to each wafer group.

10. The overlay error compensation method according to claim 1, wherein: The method further comprises: Compensation is performed on the next wafer group of the current wafer group according to the first average compensation value.

11. An overlay error compensation system, characterized in that: include: N wafer groups, each of the N wafer groups includes M wafers, and each of the M wafers includes a current layer and a previous layer; wherein N and M are positive integers greater than or equal to 2; a first measurement unit, configured to determine a first overlay error of each wafer according to the device structures of the current layer and the previous layer; a first calculation unit, configured to calculate a lithography compensation value for each wafer according to the first overlay error, calculate a first average compensation value for each wafer group according to the lithography compensation value, and calculate a second average compensation value for the N wafer groups according to the first average compensation value; The batch control system is configured to compensate the N+1th wafer group when the second average compensation value is within a preset range.

12. The overlay error compensation system according to claim 11, wherein: The first measurement unit obtains the first overlay error by using a light diffraction method.

13. The overlay error compensation system according to claim 11, wherein: The first measurement unit obtains the first overlay error by using a scanning electron microscope.

14. The overlay error compensation system according to claim 11, wherein: Also includes a second measuring unit and a second calculating unit; The second measurement unit is used to determine a second overlay error of each wafer according to the overlay marks of the current layer and the previous layer; and the second calculation unit is used to calculate a machine compensation value of each wafer according to the second overlay error.

15. The overlay error compensation system according to claim 14, wherein: The second measurement unit obtains the second overlay error by using a light wave reflection method.

16. The overlay error compensation system according to claim 15, wherein: The first calculation unit determines the lithography compensation value through non-zero compensation and / or independent compensation; the second calculation unit determines the tool compensation value through non-zero compensation and / or independent compensation.

17. The overlay error compensation system according to claim 16, wherein: Each of the lithography compensation value, the tool compensation value, the first average compensation value, and the second average compensation value includes one or more of the following parameters: X-direction translation, Y-direction translation, wafer rotation parameters, wafer non-orthogonality parameters, wafer X-direction extension, wafer Y-direction extension, exposure area rotation parameters, exposure area magnification, exposure area asymmetry rotation parameters, exposure area asymmetry magnification.

18. The overlay error compensation system according to claim 14, wherein: The batch control system obtains compensation values ​​of machines of different models according to the second overlay error, and compensates each wafer group according to the machine model corresponding to each wafer group.

19. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 10 are implemented.

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