A hardware structure for data fragmentation processing

Abstract

The application discloses a hardware structure for data fragmentation processing. The application comprises a core processor, an interface arbitration module, a shared memory and application blocks, each of which comprises an application module and an independent memory. The core processor, the application module, the interface arbitration module and the independent memory are connected with a system bus through a master interface, a slave interface and a slave interface; the application module is connected with the independent memory, and the interface arbitration module is connected with the shared memory. The core processor can directly access the application module and the interface arbitration module; the application module can directly access the interface arbitration module; the core processor and the application module can indirectly access the shared memory; and a reserved data channel is arranged between the core processor and the independent memory. When the reserved data channel is opened, the core processor directly accesses the independent memory; otherwise, the core processor indirectly accesses the independent memory. The application can improve the operation efficiency of the application module and reduce the waiting time for the response of the shared memory.

Description

Technical Field

[0001] This invention belongs to the field of chip architecture technology and relates to a hardware structure for data fragmentation processing. Background Technology

[0002] In chip systems, the efficiency and reliability of data transmission are closely related to the chip architecture. Shared memory is a common form of chip architecture. While shared memory architectures are relatively simple and easy to implement, data access by multiple modules requires arbitration to grant access to the shared memory, and data transmission efficiency is affected by data requests from other modules. Prioritization among multiple modules is also a common problem. If a high-priority module requests a large amount of data frequently, lower-priority modules will be suspended for extended periods, severely impacting their data transmission. For modules with high data response speed requirements, chip architectures based on shared memory are significantly limited in terms of performance and efficiency. Summary of the Invention

[0003] The purpose of this invention is to provide a hardware structure for data fragmentation processing.

[0004] It includes a core processor, an interface arbitration module, a shared memory, and one or more application blocks, each application block including an application module and an independent memory.

[0005] The core processor is used to control system operation, schedule transactions, and execute software instructions;

[0006] The interface arbitration module is used to arbitrate the main interface of the core processor and the main interface of the application module, and then select the interface with higher priority to access the shared storage memory to ensure data consistency.

[0007] The application module is controlled by the core processor and is used to implement specific application operations. The core processor configures the application module and can start, pause and terminate the application module.

[0008] The independent storage memory is used for data reading and writing through the application module. The independent storage memory is used to store data information closely related to the application module, or some fixed data information, and can also store data and instructions related to the core processor.

[0009] The shared storage memory stores system running data and instructions, and stores general information. The core processor and application modules need to perform interface arbitration to access the shared storage memory.

[0010] The main interface of the core processor, the main and slave interfaces of the application modules, the slave interface of the interface arbitration module, and the slave interface of the independent storage memory are connected to the system bus; the application modules are connected to the independent storage memory, and the interface arbitration module is connected to the shared storage memory.

[0011] The core processor accesses the application module through the core processor main interface, system bus, and application module; the core processor accesses the interface arbitration module through the core processor main interface, system bus, and interface arbitration module; the application module accesses the interface arbitration module through the application module main interface, system bus, and interface arbitration module; the core processor accesses the independent storage memory through the core processor main interface, system bus, and independent storage memory, and this access line is a reserved data channel.

[0012] If the application module is open, the reserved data channel is closed; if the application module is closed, the reserved data channel can be opened.

[0013] With the reserved data channel closed, the core processor can directly access the application module and the interface arbitration module, indirectly access the independent storage memory through the application module, and indirectly access the shared storage memory through the interface arbitration module; the application module can directly access the independent storage memory and the interface arbitration module, and indirectly share the storage memory through the interface arbitration module.

[0014] With the reserved data channel open, the application module is closed, and the core processor can directly access the independent storage memory.

[0015] This invention proposes a hardware architecture for data fragmentation processing. In addition to shared memory, an independent memory module is added for each application module. This independent memory is accessed through the application module. When an application module is enabled but not running, the core processor can indirectly access the independent memory through the application module to store system data and instructions. When an application module is running, the independent memory stores data closely related to that module. The core processor and application modules need to arbitrate their interface before accessing the shared memory. This architecture improves the operating efficiency of application modules and reduces waiting time due to arbitration and other modules occupying shared memory. Furthermore, for data requiring core processor processing, the application module can move it from the shared memory without copying it to the independent memory, saving data transfer time and improving system and application operating efficiency. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the hardware structure of the present invention;

[0017] Figure 2 This is a schematic diagram of an embodiment of the present invention. Detailed Implementation

[0018] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0019] like Figure 1 As shown, a hardware architecture for data fragmentation processing includes a core processor, an interface arbitration module, a shared memory, and one or more application blocks. Each application block (the dashed box in the figure) includes an application module and an independent memory.

[0020] The core processor is used to control system operation, schedule transactions, and execute software instructions.

[0021] The interface arbitration module is used to arbitrate the main interface of the core processor and the main interface of the application module, and then select the interface with higher priority to access the shared storage memory, so as to ensure data consistency.

[0022] Application modules, controlled by the core processor, are used to implement specific application operations. The core processor can configure application modules and can start, pause, and terminate application modules.

[0023] Independent storage memory is used for data reading and writing through application modules. This independent storage memory can store data closely related to the application module, fixed data, or data and instructions related to the core processor. When the application module is open but not yet started, it can store data and instructions related to the core processor. When the application module is open and started, it stores information including but not limited to control information, basic information, encryption / decryption information, time information, and operation status information. Independent storage memory includes, but is not limited to, SRAM, DRAM, SDRAM, FLASH, EFUSE, ROM, and PSRAM.

[0024] Shared storage memory stores system data and instructions, and contains general information. The core processor and application modules need to perform bus arbitration to access the shared storage memory. Shared storage memory includes, but is not limited to, SRAM, DRAM, SDRAM, FLASH, EFUSE, ROM, and PSRAM.

[0025] The main interface of the core processor, the main and slave interfaces of the application modules, the slave interface of the interface arbitration module, and the slave interface of the independent storage memory are connected to the system bus; the application modules are connected to the independent storage memory, and the interface arbitration module is connected to the shared storage memory.

[0026] The core processor accesses the application module via the core processor main interface, system bus, and application module; the core processor accesses the interface arbitration module via the core processor main interface, system bus, and interface arbitration module; and the application module accesses the interface arbitration module via the application module main interface, system bus, and interface arbitration module. The core processor accesses independent storage memory via the core processor main interface, system bus, and independent storage memory; this access line is a reserved data channel. The connection channel between the core processor and independent storage memory is a reserved data channel, allowing the core processor to directly access the independent storage memory space without needing the application module as a stepping stone. When using the reserved data channel, the application module is shut down to maintain data consistency in the independent storage memory.

[0027] According to the hardware architecture, the core processor is connected to the application module, and the application module is connected to the independent storage memory. When the application module is open but not yet started, the core processor can indirectly access the independent storage memory and store data and instructions unrelated to the application module. When the application module is open and started, the independent storage memory stores information closely related to the application module.

[0028] If the application module is open, the reserved data channel will necessarily be closed; if the application module is closed, the reserved data channel can be opened.

[0029] With the reserved data channel closed, the core processor can directly access the application module and the interface arbitration module, indirectly access the independent storage memory through the application module, and indirectly access the shared storage memory through the interface arbitration module; the application module can directly access the independent storage memory and the interface arbitration module, and indirectly share the storage memory through the interface arbitration module.

[0030] With the reserved data channel open, the application module is closed. The core processor can directly access the independent storage memory, while access to the shared storage memory requires interface arbitration to ensure the uniqueness of access.

[0031] Another implementation example Figure 2 As shown, the hardware architecture includes a core processor, an interface arbitration module, a shared memory, two application blocks, and one independent application module. The independent application module's master interface and slave interface are connected to the system bus. The core processor accesses the independent application module through its master interface, the system bus, and the independent application module's slave interface. The independent application module accesses the interface arbitration module through its master interface, the system bus, and the interface arbitration module.

[0032] Independent application modules are the same as application modules, controlled by the core processor, and used to implement specific application operations. The core processor can configure independent application modules, and can start, pause, and terminate independent application modules.

[0033] With the reserved data channel closed, the core processor can directly access application module A, application module B, independent application modules, and shared storage memory, and can indirectly access independent storage memory A and independent storage memory B; application module A can directly access independent storage memory A and shared storage memory, application module B can directly access independent storage memory B and shared storage memory, and independent application modules can directly access shared storage memory.

[0034] If the reserved data channel A is open, then application module A is in a closed state, and the core processor can directly access independent storage memory A.

[0035] If the reserved data channel B is open, the application module B is in a closed state, and the core processor can directly access the independent storage memory B.

[0036] Shared storage memory requires interface arbitration to access, ensuring the uniqueness of access.

[0037] The architecture of this invention will be explained below using Bluetooth communication as an example.

[0038] Bluetooth communication operates on a frame-by-frame basis. Constructing a frame requires specific control information such as the Bluetooth address, Bluetooth clock, encryption / decryption key, frequency hopping data, and target Bluetooth address. However, the data transmitted or received via Bluetooth is not fixed in length and requires segmentation and packetization by higher layers. Therefore, transmitted or received data must be processed by the core processor before it can be used in subsequent processes.

[0039] In Bluetooth wireless communication applications, the core processor is the SOC control system, the application module is the Bluetooth baseband, the independent storage memory is the SRAM storage space dedicated to the Bluetooth baseband, and the shared storage memory is the SOC's SRAM space, used to store system data and instructions.

[0040] Independent storage memory stores control information for each link, including but not limited to Bluetooth address, Bluetooth clock, encryption / decryption keys, frequency hopping data, target Bluetooth address, data packet type, data length, Bluetooth mode, response information, and RF configuration information. This facilitates quick access to control information by the Bluetooth baseband module, reduces waiting time due to arbitration and other modules sharing storage memory, and improves application efficiency and performance.

[0041] The shared storage memory stores the SOC's operating data, operating instructions, data information from other modules, and data transmitted or received by the Bluetooth baseband. Since Bluetooth data transmitted or received must be processed by the core processor before it can be used in subsequent processes, storing the data in the shared storage memory facilitates data processing by the core processor and reduces data movement. The Bluetooth baseband module can read and write data through an interface connected to the shared storage memory. This eliminates the need to copy data to a separate storage memory, saving time and improving efficiency. Because both the SOC control system and the Bluetooth baseband module can access the shared storage memory, interface arbitration is required before accessing it to ensure data consistency.

[0042] With the Bluetooth baseband function enabled but not activated, the SOC control system can indirectly access the independent storage memory through the Bluetooth baseband module, storing data and commands unrelated to the Bluetooth baseband module. In this case, the independent storage memory is not wasted, effectively utilizing all fragmented memory space. Alternatively, the SOC control system can directly access the independent storage memory via reserved data, but in this case, the Bluetooth baseband module is disabled to ensure data consistency.

Claims

1. A hardware structure for data fragmentation processing, characterized by: It comprises a core processor, an interface arbitration module, a common storage memory and one or more application blocks, each of which comprises an application module and an independent storage memory; The core processor is used for controlling system operation, transaction arrangement and execution of software instructions; The interface arbitration module is used for arbitrating the core processor main interface and the application module main interface, then selecting the interface with high priority to access the common storage memory, and ensuring data consistency; The application module is controlled by the core processor and is used for realizing specific application operation, the core processor can configure the application module, and the core processor can start, pause and terminate the application module; The independent storage memory is used for storing data information closely connected with the application module or some fixed data information, and can also store data and instructions related to the core processor; The common storage memory stores data and instructions of system operation and stores general information, and the core processor and the application module need to perform interface arbitration to access the common storage memory; The core processor main interface, the application module main interface and slave interface, the interface arbitration module slave interface and the independent storage memory slave interface are connected with the system bus; The application module is connected with the independent storage memory, and the interface arbitration module is connected with the common storage memory; The core processor accesses the application module through the core processor main interface, the system bus and the application module slave interface; The core processor accesses the interface arbitration module through the core processor main interface, the system bus and the interface arbitration module slave interface; The application module accesses the interface arbitration module through the application module main interface, the system bus and the interface arbitration module slave interface; The core processor accesses the independent storage memory through the core processor main interface, the system bus and the independent storage memory slave interface, and the access line is a reserved data channel; When the application module is opened, the reserved data channel is closed, and when the application module is closed, the reserved data channel can be opened; In the closed state of the reserved data channel, the core processor can directly access the application module and the interface arbitration module, indirectly access the independent storage memory through the application module and indirectly access the common storage memory through the interface arbitration module; The application module can directly access the independent storage memory and the interface arbitration module and indirectly access the common storage memory through the interface arbitration module; In the opened state of the reserved data channel, the application module is closed, and the core processor can directly access the independent storage memory.

2. The hardware structure of data fragmentation processing as claimed in claim 1, wherein: The hardware structure further comprises one or more independent application modules; The independent application module is controlled by the core processor and is used for realizing specific application operation, the core processor can configure the independent application module, and the core processor can start, pause and terminate the independent application module; The independent application module main interface and slave interface are connected with the system bus, the core processor accesses the independent application module through the core processor main interface, the system bus and the independent application module slave interface, and the independent application module accesses the interface arbitration module through the independent application module main interface, the system bus and the interface arbitration module slave interface.

3. The hardware structure of data fragmentation process as claimed in claim 1 wherein: The connection channel of the core processor and the independent storage memory is a reserved data channel, allowing the core processor to directly access the independent storage memory space without needing to use the application module as a stepping stone.

4. The hardware structure of data fragmentation processing as claimed in claim 1, wherein: When the application module is in an open but not started state, the core processor can indirectly access the independent storage memory and store data and instructions unrelated to the application module; when the application module is in an open and started state, the independent storage memory stores information closely related to the application module, and the stored information includes control information, basic information, encryption and decryption information, time information and operation state information.

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