A data decoding structure

Abstract

This application belongs to the field of data processing technology and discloses a data decoding structure. The data decoding structure includes: a write control module, which receives decoded data, message header indication information, and valid detection information, and writes the valid decoded data and message header indication information from the decoded data into a first storage unit; a first storage unit, which stores the valid decoded data and message header indication information written by the write control module, and modifies the address of the write pointer of the first storage unit according to the bit width of the valid decoded data, and modifies the address of the read pointer of the first storage unit according to the bit width of the read valid decoded data when the valid decoded data is read out; and a read control module, which reads out valid decoded data with a read bit width when the bit width of the valid decoded data stored in the first storage unit is greater than the read bit width of the first storage unit. The data decoding structure provided by this application supports the decoding of SKP data blocks of arbitrary bit width, effectively expanding the application of data decoding structures.

Description

Technical Field

[0001] This application belongs to the field of data processing technology and relates to a data decoding structure. Background Technology

[0002] 128-bit / 130-bit encoding / decoding is a common function related to the PCIe (Peripheral Component Interconnect Express) protocol. When the serdes IP (SERializer / DESerializer) performs 128-bit / 130-bit encoding / decoding on transmitted data, the SKP block used for frequency offset compensation in the transmitted data may have its bit width uncertain during data transmission in serdes because the SKP block may have been added or removed during the transmission from the serdes transmitter to the receiver for decoding. This uncertainty in the SKP block bit width complicates the decoding process at the receiver.

[0003] One existing technical solution for decoding SKP data blocks is to limit the bit width of the SKP data blocks, supporting only SKP data block bit widths of 64 / 128 / 192 bits during decoding. However, the PCIe protocol specifies that the bit width of the SKP data block can be 64 / 96 / 128 / 160 / 192 bits. When the bit width of the SKP data block is 64 bits or an integer multiple of 64 bits, the 64-bit data output in the SERDES can be made to belong to the same data block in any cycle, ensuring that SKP data blocks with bit widths of 64 / 128 / 192 bits always belong to the same data block in the output. However, although the existing technical solution solves the technical problem of the data decoding process becoming complicated due to the uncertainty of the SKP data block bit width, it is obvious that the existing technical solution does not support SKP data blocks with bit widths that are not integer multiples of 64 bits, such as 96 bits or 160 bits, which greatly limits the application scenarios of the data decoding structure. Summary of the Invention

[0004] The purpose of this application is to provide a data decoding structure to solve the technical problem that existing data decoding structures can only support decoding of SKP data blocks with a bit width of 64 bits and multiples of 64 bits.

[0005] To solve the above-mentioned technical problems, the technical solution of this application is as follows:

[0006] This application provides a data decoding structure, including a write control module, a first storage unit, and a read control module;

[0007] The write control module is used to receive decoded data, message header indication information and validity detection information, and write the valid decoded data and message header indication information from the decoded data into the first storage unit. The message header indication information is used to indicate whether the valid decoded data includes a message header, and the validity detection information is used to detect the valid decoded data in the decoded data.

[0008] The first storage unit is used to store the valid decoded data and the message header indication information written by the write control module, and to modify the address of the write pointer of the first storage unit according to the bit width of the valid decoded data; and,

[0009] Used to modify the address of the read pointer of the first storage unit according to the bit width of the read valid decoded data when the valid decoded data is read out;

[0010] The read control module is configured to read out the valid decoded data with a read bit width equal to the read bit width when the bit width of the valid decoded data stored in the first storage unit is greater than the read bit width of the first storage unit.

[0011] In some embodiments, the write control module is configured to receive decoded data, packet header indication information, and valid detection information, and write the valid decoded data and the packet header indication information from the decoded data into the first storage unit, including:

[0012] When all the decoded data is valid decoded data, the valid decoded data is written into the first storage unit;

[0013] When the decoded data portion is the valid decoded data, the valid decoded data and the padding data are written into the first storage unit. The padding data is used to make the bit width of the data written into the first storage unit the same as the bit width of the decoded data.

[0014] In some embodiments, the read control module is configured to read out the valid decoded data with a read bit width equal to the read bit width when the bit width of the valid decoded data stored in the first storage unit is greater than the read bit width of the first storage unit, including:

[0015] Obtain the address of the read pointer and the address of the write pointer of the first storage unit, and determine the bit width of the valid decoded data stored in the first storage unit;

[0016] Obtain the message header indication information written to the first storage unit, and determine whether the valid decoded data to be read includes the message header;

[0017] If the valid decoded data to be read includes the message header, then when the bit width of the valid decoded data stored in the first storage unit is greater than the first readout bit width, the valid decoded data with the first readout bit width is read out.

[0018] If the valid decoded data to be read does not include the message header, then when the bit width of the valid decoded data stored in the first storage unit is greater than the second readout bit width, the valid decoded data with the second readout bit width is read out.

[0019] In some embodiments, the data decoding structure further includes:

[0020] The second storage unit is used to store SKP data indication information, which is used to indicate whether the valid decoded data written into the first storage unit is SKP data.

[0021] In some embodiments, the write control module further includes:

[0022] Receive the SKP data indication information and write the SKP data indication information into the second storage unit.

[0023] In some embodiments, the write control module further includes:

[0024] Generate decoding start indication information and write the decoding start indication information into the first storage unit and the second storage unit. The decoding start indication information is used to indicate the start of decoding when the write control module receives the decoding data for the first time.

[0025] In some embodiments, the first storage unit further includes:

[0026] Upon receiving the decoding start indication information, when the decoding start indication information indicates that decoding has started, the address of the read pointer and the address of the write pointer of the first storage unit are initialized.

[0027] In some embodiments, the read control module further includes:

[0028] Generate decoding end indication information, and read the valid decoded data stored in the first storage unit when the decoding ends, and make the address of the read pointer of the first storage unit coincide with the address of the write pointer of the first storage unit.

[0029] In some embodiments, the data decoding structure further includes:

[0030] The SKP data control module is used to read the SKP data indication information written to the second storage unit when the valid decoded data read by the read control module includes the message header;

[0031] The SKP data processing module is used to acquire the valid decoded data read by the read control module and the SKP data indication information read by the SKP data control module. When the SKP data exists in the valid decoded data, it determines whether there is any erroneous data in the SKP data in the valid decoded data.

[0032] If the SKP data in the valid decoded data contains the bit error data, then the SKP data indication information is modified according to the bit error data;

[0033] If the erroneous data is not present in the valid decoded data, the SKP data indication information is stored.

[0034] In some embodiments, the read control module further includes:

[0035] A pre-read indication is generated and output to the SKP data control module. The pre-read indication is used to indicate whether the read control module will perform a read operation next time, and when it is determined that the read control module will perform a read operation next time, it indicates whether the valid decoded data read next time includes the message header.

[0036] Compared to existing technologies, the advantages of this application are as follows:

[0037] The data decoding structure provided in this application supports the decoding of SKP data blocks of arbitrary width conforming to the PCIE protocol, solves the limitation of existing data decoding structures on the frequency difference compensation function related to SKP data blocks, and effectively expands the application scenarios of data decoding structures. Attached Figure Description

[0038] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0039] Figure 1 This is a block diagram of a data decoding structure provided in an embodiment of this application.

[0040] Figure 2 Another block diagram of the data decoding structure provided in the embodiments of this application.

[0041] Figure 3This is a schematic diagram illustrating an application of the data decoding structure provided in an embodiment of this application. Detailed Implementation

[0042] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the described embodiments are merely some embodiments of this application, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0043] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such use of data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0044] The data decoding structure provided in this application supports decoding operations on SKP data blocks of arbitrary width conforming to the PCIE protocol. The supported SKP data block widths include at least 64bit / 96bit / 128bit / 160bit / 192bit. The data decoding structure provided in this application will be described below with reference to the accompanying drawings.

[0045] Figure 1 A block diagram of a data decoding structure provided in an embodiment of this application, such as Figure 1 As shown, the data decoding structure provided in this application embodiment includes a write control module, a first storage unit, and a read control module.

[0046] The write control module is used to receive decoded data, message header indication information and validity detection information, and write the valid decoded data and message header indication information in the decoded data into the first storage unit. The message header indication information is used to indicate whether the valid decoded data includes a message header, and the validity detection information is used to detect the valid decoded data in the decoded data.

[0047] In some embodiments, the write control module is configured to receive decoded data, message header indication information, and validity detection information, and write the valid decoded data and message header indication information from the decoded data into the first storage unit, including:

[0048] When all the decoded data is valid, write the valid decoded data into the first storage unit;

[0049] When the decoded data is valid decoded data, the valid decoded data and the padding data are written into the first storage unit. The padding data is used to make the bit width of the data written into the first storage unit the same as the bit width of the decoded data.

[0050] Figure 3 This is an application diagram illustrating the data decoding structure provided in the embodiments of this application, such as... Figure 3 As shown, the write control module receives decoded data (dec_din), message header indication information (dec_headervld_in, dec_headeraddr_in), and validity detection information (dec_align_in). When write enable (wr_en) is valid (i.e., high level), it writes the valid decoded data in the decoded data (dec_din) into the first storage unit and writes the message header indication information (dec_headervld_in, dec_headeraddr_in) into the first storage unit.

[0051] The valid detection information (dec_align_in) is used to detect valid decoded data in the decoded data (dec_din). For example, the method for detecting valid decoded data in the decoded data (dec_din) is as follows: when the valid detection information (dec_align_in) is high, it indicates that the data in the decoded data (dec_din) corresponding to the high level of the valid detection information (dec_align_in) is valid decoded data. When only a portion of the decoded data detected by the valid detection information (dec_align_in) is valid, in order to ensure that the bit width of the data written to the first storage unit is the same as the bit width of the decoded data (dec_din) received by the write control module, the write... The data (wr_data) written by the control module to the first storage unit includes valid decoded data and padding data. Typically, it can also be configured to jointly confirm the valid data in the decoded data based on valid detection information (dec_align_in) received at different times before and after. Among them, the padding data is meaningless and is only used to make the bit width of the data written to the first storage unit the same as the bit width of the decoded data. In fact, in most application scenarios, when the data decoding structure provided in this application performs data decoding, the write control module only includes part of the valid decoded data in the first decoded data received at the beginning of decoding and the last decoded data received at the end of decoding, while all the decoded data received during the decoding process is valid decoded data.

[0052] The header indication information (dec_headervld_in) is used to indicate whether the valid decoded data includes a header. For example, if the header indication information (dec_headervld_in) is high, it indicates that the valid decoded data includes a header; if... Figure 3As shown, in order to further detect the message header, the message header indication information received by the write control module includes the dec_headervld_in signal and the dec_headeraddr_in signal. The dec_headeraddr_in signal is used to indicate the specific position of the message header in the decoded data when the dec_headervld_in signal is high. At this time, the write control module receives the message header indication information (dec_headervld_in, dec_headeraddr_in) and writes the message header indication information (dec_headervld_in, dec_headeraddr_in) into the first storage unit in the form of an indication signal (wr_header_vld). It should be noted that in this embodiment, the message header indication information (dec_headervld_in, dec_headeraddr_in) is renamed to (wr_header_vld) after being output from the write control module only to simplify the number of signal names.

[0053] It should be made clear that, such as Figure 3 The signal transmission of the write control module shown is merely one signal setting method for the write control module of the data decoding structure provided in this application embodiment, and does not imply that the write control module of the data decoding structure provided in this application embodiment can only use such methods. Figure 3 The setup method shown is, in fact, only as long as the signals designed by the designer can achieve the corresponding functions, the data decoding structure provided in this application embodiment can be used. For example, in order to further indicate the data written to the first storage unit, the write control module may also include outputting a wr_length signal to the first storage unit to indicate the bit width of the data written to the first storage unit; and the message header indication information (dec_headervld_in, dec_headeraddr_in) can be set as two signals, or it can be set as one signal to indicate whether the valid data includes a message header and the specific position of the message header in the valid data.

[0054] The first storage unit is used to store the valid decoded data and message header indication information written by the write control module, and to modify the address of the write pointer of the first storage unit according to the bit width of the valid decoded data; and to modify the address of the read pointer of the first storage unit according to the bit width of the read valid decoded data when the valid decoded data is read out; wherein, the bit width of the valid decoded data and the bit width of the message header indication information that the first storage unit can store are determined according to the bit depth of the first storage unit. For example, when the first storage unit includes two storage modules with a bit depth of 131 bits, which are used to store the valid decoded data and the message header indication information respectively, it means that the first storage unit can store 132 bits of valid decoded data and 132 bits of message header indication information. When the data written by the write control module at one time is set to 64 bits, the bit of the valid decoded data written by the write control module for the third time [5] will begin to overwrite the valid decoded data previously stored in the first storage unit.

[0055] like Figure 3 As shown, the first storage unit includes two storage modules (Mem_data and Mem_header_vld), which are used to store the data (wr_data) and message header indication information (wr_header_vld) written by the write control module, respectively. When the first storage unit receives the data (wr_data) and message header indication information (wr_header_vld) written by the write control module, the write pointer of the first storage unit moves according to the bit width of the valid decoded data. For example, if the address of the write pointer is bit[0] before the data is written, when the first storage unit receives 64 bits of valid decoded data, the write pointer moves 64 bits. Specifically, the write pointer moves 64 bits. The pointer is moved to the address of bit

[64] ; or the address of the write pointer is bit[0] before the data is written. When 32 bits of valid decoded data and 32 bits of padding data are received, the write pointer moves 32 bits according to the width of the valid decoded data, specifically to the address of bit

[32] . Similarly, when the valid decoded data stored in the first storage unit is read out, the read pointer is moved according to the width of the read valid decoded data. For example, if the address of the read pointer is bit[0] before the data is read out, when 66 bits of valid decoded data are read out of the first storage unit, the read pointer is moved 66 bits, specifically to the address of bit

[66] .

[0056] The read control module is used to read out valid decoded data with a readout bit width when the bit width of the valid decoded data stored in the first storage unit is greater than the readout bit width of the first storage unit.

[0057] In some embodiments, the read control module is configured to read out valid decoded data with a readout bit width equal to the readout bit width when the bit width of the valid decoded data stored in the first storage unit is greater than the readout bit width of the first storage unit, including:

[0058] The address of the read pointer and the address of the write pointer of the first storage unit are obtained to determine the bit width of the effective decoded data stored in the first storage unit. For the data decoding structure provided in this application embodiment, the first storage unit always writes data first and then reads data. Therefore, except at the beginning and end of decoding when the read pointer and the write pointer are at the same address, the read pointer will always lag behind the write pointer during the decoding process. That is, the bit width difference between the read pointer and the write pointer during the decoding process is the bit width of the effective decoded data stored in the first storage unit.

[0059] Obtain the message header indication information written to the first storage unit, and determine whether the valid decoded data to be read includes the message header;

[0060] If the valid decoded data to be read includes a message header, then when the bit width of the valid decoded data stored in the first storage unit is greater than the first read bit width, the valid decoded data with the first read bit width is read out.

[0061] If the valid decoded data to be read does not include the message header, then when the bit width of the valid decoded data stored in the first storage unit is greater than the second read bit width, the valid decoded data with the second read bit width is read out.

[0062] like Figure 3 As shown, the read control module obtains the address of the read pointer (wptr), the address of the write pointer (rptr), and the data stored in the storage module (Mem_header_vld) from the first storage unit. The data stored in the storage module (Mem_header_vld) includes at least the message header indication information and other indication information written to the first storage unit by the write control module (all information other than the valid decoded data written). The bit width of the valid decoded data stored in the storage module (Mem_data) of the first storage unit is the bit width difference between the read pointer and the write pointer. It should be clear that the bit depth of the storage module (Mem_data) is 131 bits, that is, the distance that the read pointer and the write pointer can move, 131 bits, is regarded as one cycle. When calculating the bit width difference between the read pointer and the write pointer, the cycle difference between the read pointer and the write pointer should be included. When the bit width difference between the read pointer and the write pointer is included, this bit width difference will always be less than the cycle value of 131; otherwise, data loss in the first storage unit may occur. Figure 3The data decoding structure shown is set to a 64-bit width. For a 128-bit / 130-bit data decoding structure, the effective data width that the read control module can read should be 64 bits (excluding the header) / 66 bits (including the header). Specifically, when the effective decoded data corresponding to the address where the read pointer is located is detected as header data through the header indication information, or when the effective decoded data corresponding to the address 32 bits after the address where the read pointer is located contains header data, it indicates that the effective decoded data to be read includes header data, and the read width of the first storage unit is the first read width of 66 bits. Otherwise, it indicates that the read width of the first storage unit is the second read width of 64 bits, and the read control module outputs read enable (rd_en). When the read enable (rd_en) is high, the corresponding width of effective decoded data (rd_data) is read and output.

[0063] To further indicate the valid decoded data to be read, such as Figure 3 As shown, the read control unit may further include an rd_length signal output to the first storage unit to indicate the bit width of the valid decoded data to be read; wherein, when the read control module outputs data, it will output the message header data and valid data in the valid decoded data (rd_data) separately, that is, the data output by the read control module includes message header data (rx_header) and valid data (dec_dout). When the valid decoded data (rd_data) read by the read control module does not include the message header data, the valid data (dec_dout) is the same as the valid decoded data (rd_data).

[0064] To further instruct the read control module to output data, such as Figure 3 As shown, the output of the read control module may also include: the align_out signal, which indicates whether there is valid data in the output of the read control module; the rx_data_vld signal, which indicates whether the valid data (rd_data) is valid; and the rx_header_vld signal, which indicates whether the message header data (rx_header) is valid.

[0065] It should be made clear that, such as Figure 3 The signal transmission of the read control module shown is merely one signal setting method for the write control module of the data decoding structure provided in this application embodiment, and does not imply that the read control module of the data decoding structure provided in this application embodiment only includes such... Figure 3 The signal setting method shown is, in fact, only necessary as long as the signal designed by the designer meets the corresponding function.

[0066] Figure 2 Another block diagram of the data decoding structure provided in the embodiments of this application is shown below. Figure 2 As shown, in some embodiments, the data decoding structure provided in this application further includes:

[0067] The second storage unit is used to store SKP data indication information, which is used to indicate whether the valid decoded data written to the first storage unit is SKP data; wherein, the write control module receives the SKP data indication information and writes the SKP data indication information into the second storage unit.

[0068] The SKP data control module is used to read and write SKP data indication information to the second storage unit when the valid decoded data read by the read control module includes the message header.

[0069] The SKP data processing module is used to acquire the valid decoded data read by the read control module and the SKP data indication information read by the SKP data control module. When SKP data exists in the valid decoded data, it determines whether there is erroneous data in the SKP data in the valid decoded data. For example, one design for determining the presence of SKP data in the valid decoded data based on the SKP data indication information is as follows: the SKP data indication information received by the SKP data processing module contains 2-bit indication signals, which are used to indicate whether the high 32 bits and low 32 bits of the output 64-bit valid decoded data are SKP data.

[0070] If there are erroneous data in the SKP data of the valid decoded data, the SKP data indication information is modified according to the erroneous data. For example, one design for modifying the SKP data indication information according to the erroneous data is as follows: when it is determined that the SKP data at the current moment contains an error that does not conform to the SKP characteristics (i.e., erroneous data), the SKP indication corresponding to the SKP data is kept at a low level starting from the rising edge of the next clock, until all the data in the data block where the SKP data is located is output.

[0071] If there are no erroneous data in the valid decoded data, store the SKP data indication information without modifying it.

[0072] In some embodiments, to further indicate the start and end of data decoding, such as Figure 2 As shown, the write control module also includes:

[0073] Generate decoding start indication information and write the decoding start indication information into the first storage unit and the second storage unit. The decoding start indication information is used to indicate the start of decoding when the write control module receives the decoding data for the first time.

[0074] The first storage unit receives the decoding start indication information. When the decoding start indication information indicates that decoding has started, the address of the read pointer and the address of the write pointer of the first storage unit are initialized. That is, the read pointer and the write pointer are both located at the same address when decoding starts. Usually, the read pointer and the write pointer are reset to the address of bit[0]. It should be clear that the address where the read pointer and the write pointer are reset refers to the bit depth address of the first storage unit.

[0075] The read control module also includes:

[0076] Generate decoding end indication information. When the decoding end indication information indicates that decoding has ended, read out the valid decoded data stored in the first storage unit and make the address of the read pointer of the first storage unit coincide with the address of the write pointer of the first storage unit.

[0077] The pre-read indication information is generated and output to the SKP data control module. The pre-read indication information is used to indicate whether the read control module will perform a read operation next time, and when it is determined that the read control module will perform a read operation next time, it indicates whether the valid decoded data read next time includes the message header.

[0078] like Figure 3 As shown, the write control module includes a first storage unit control area (For Mem) and a second storage unit control area (For Mem_header_related), which are used to process the information of the first storage unit and the information of the second storage unit, respectively. The write control module receives SKP data indication information (dec_skp_in) and outputs SKP data indication information (dec_skp_in) to the second storage unit according to the write enable (wr_en).

[0079] To indicate the start of data decoding, the write control module generates a decoding start indication message (din_new_start) upon receiving the decoded data for the first time, and outputs it to both the first and second storage units. The second storage unit receives the SKP data indication message (dec_skp_in) and the decoding start indication message (din_new_start), processes them, and merges them into a single signal, (rd_seqstart_skp). This signal indicates the SKP data and the start of the decoding loop. A decoding loop represents one decoding cycle. For example, if a decoding cycle includes 32 data blocks, writing data to the first storage unit 32 times represents one decoding cycle.

[0080] To indicate the end of data decoding, the write control module / read control module performs logical processing on the align signal (dec_align_in / align_out) and the message header indication information to generate decoding end indication information (din_last_end). The write control module determines the end of decoding based on the decoding end indication information (din_last_end) and sets the write enable to a low level, preventing the write pointer of the first storage unit from being updated. The read control module determines the end of decoding based on the decoding end indication information (din_last_end), and the read control unit outputs the next_last_vld_dout signal to the first storage unit to indicate that the upcoming read operation is the last read operation. After the last valid decoded data stored in the first storage unit is read, the read enable is set to a low level, and the read pointer and write pointer are aligned. The read control module also includes outputting the next_last_vld_dout signal to the SKP data control module.

[0081] To further instruct the read control module on the data read, it can also determine whether to perform a read operation next time and whether the data read next time includes a message header based on the read pointer, write pointer, and message header indication information. For the data decoding process, the bit width of the valid decoded data written to the first storage unit remains unchanged. For example, if the valid decoded data written to the first storage unit during the data decoding process is set to 64 bits, the read control module can estimate the address of the write pointer when the first storage unit is next written with valid decoded data as the current address plus 64 bits. Furthermore, it can determine the bit width difference between the current read pointer address and the next write pointer address, thus obtaining the bit width of the valid decoded data stored after the first storage unit is next written with valid decoded data, and thereby determining whether to perform a read operation next time. Whether the data read next time includes a message header is determined based on the message header indication information.

[0082] The SKP data control module receives the rx_data_vld and rx_header_vld signals from the read control module. Based on the rx_data_vld and rx_header_vld signals, it determines whether the valid decoded data read by the read control module includes a message header. If the valid decoded data includes a message header, it reads the SKP data indication information stored in the second storage unit according to the read enable (rd_en_seqstart_skp).

[0083] To further instruct the SKP data control module to read the data stored in the second storage unit, the SKP data control module receives the next_rx_data_vld signal and the next_rx_header_vld signal from the read control module. These signals are used to indicate whether the read control module should perform a read operation next time, and whether the data read by the read control module next time includes the message header data.

[0084] The SKP data processing module receives valid data (dec_dout) and header data (rx_header_vld) from the read control module, and receives the rd_seqstart_skp signal output by the SKP data control module. It uses the SKP data indication information in the rd_seqstart_skp signal to determine whether SKP data exists in the valid decoded data composed of valid data (dec_dout) and header data (rx_header_vld). If SKP data exists in the valid decoded data, it further determines whether there is any erroneous data within the SKP data.

[0085] If the bit error data exists, modify the SKP data indication information in the rd_seqstart_skp signal according to the bit error data, and indicate the bit error data and the valid decoded data with a higher bit value than the bit error data as non-SKP data;

[0086] If there is no erroneous data, the SKP data processing module will not modify the SKP data indication information in the rd_seqstart_skp signal.

[0087] In some embodiments, such as Figure 3As shown, to facilitate the application of SKP data by external circuits, the write control module is also used to receive SKP type indication information (dec_skp_endctrl), process the SKP type indication information (dec_skp_endctrl) and SKP data indication information (dec_skp_in) and merge them into an output signal (wr_header_related) and write it into the second storage unit. The second storage unit includes two storage modules (Mem_skp_enctrl and Mem_seqstart_skp) to store the SKP type indication information (dec_skp_endctrl) and the rd_seqstart_skp signal (including SKP data indication information and decoding start indication information), respectively. The SKP type indication information (dec_skp_endctrl) is used to indicate that the type of SKP data is "standard" or "control". The SKP data control module reads the SKP type indication information (rd_skp_endctrl) according to the read enable (rd_en_skp_endctrl) and outputs the SKP type indication information (rd_skp_endctrl) to the SKP data processing module.

[0088] Furthermore, it should be made clear that, such as Figure 3 The data decoding structure shown in the figure uses clock signals (clk), reset signals (rst_n), and clock enable signals (clk_en) received by the first and second storage units. These are common signals used to configure storage units, so they will not be further described in this embodiment.

[0089] It should be made clear that, such as Figure 3 The signal transmission of the SKP data control module and SKP data processing module shown is merely one signal setting method for the write control module of the data decoding structure provided in this application embodiment, and does not imply that the read control module of the data decoding structure provided in this application embodiment only includes the following: Figure 3 The signal setting method shown is, in fact, only necessary as long as the signal designed by the designer meets the corresponding function.

[0090] The above description, in conjunction with specific embodiments, provides a further detailed explanation of this application and should not be construed as limiting the specific implementation of this application to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of this application, and all such modifications and substitutions should be considered within the scope of protection of this application.

Claims

1. A data decoding structure, characterized in that, It includes a write control module, a first storage unit, and a read control module; The write control module is used to receive decoded data, message header indication information and validity detection information, and write the valid decoded data and message header indication information from the decoded data into the first storage unit. The message header indication information is used to indicate whether the valid decoded data includes a message header, and the validity detection information is used to detect the valid decoded data in the decoded data. The first storage unit is used to store the valid decoded data and the message header indication information written by the write control module, and to modify the address of the write pointer of the first storage unit according to the bit width of the valid decoded data; as well as, Used to modify the address of the read pointer of the first storage unit according to the bit width of the read valid decoded data when the valid decoded data is read out; The read control module is configured to read out the valid decoded data with a read bit width equal to the read bit width when the bit width of the valid decoded data stored in the first storage unit is greater than the read bit width of the first storage unit.

2. The data decoding structure as described in claim 1, characterized in that, The write control module is used to receive decoded data, message header indication information, and valid detection information, and to write the valid decoded data and message header indication information from the decoded data into the first storage unit, including: When all the decoded data is valid decoded data, the valid decoded data is written into the first storage unit; When the decoded data portion is the valid decoded data, the valid decoded data and the padding data are written into the first storage unit. The padding data is used to make the bit width of the data written into the first storage unit by the write control module the same as the bit width of the decoded data.

3. The data decoding structure as described in claim 1, characterized in that, The read control module is configured to read out valid decoded data with a read bit width equal to the read bit width when the bit width of the valid decoded data stored in the first storage unit is greater than the read bit width of the first storage unit, including: Obtain the address of the read pointer and the address of the write pointer of the first storage unit, and determine the bit width of the valid decoded data stored in the first storage unit; Obtain the message header indication information written to the first storage unit, and determine whether the valid decoded data to be read includes the message header; If the valid decoded data to be read includes the message header, then when the bit width of the valid decoded data stored in the first storage unit is greater than the first readout bit width, the valid decoded data with the first readout bit width is read out. If the valid decoded data to be read does not include the message header, then when the bit width of the valid decoded data stored in the first storage unit is greater than the second readout bit width, the valid decoded data with the second readout bit width is read out.

4. The data decoding structure as described in claim 1, characterized in that, Also includes: The second storage unit is used to store SKP data indication information, which is used to indicate whether the valid decoded data written into the first storage unit is SKP data.

5. The data decoding structure as described in claim 4, characterized in that, The write control module further includes: Receive the SKP data indication information and write the SKP data indication information into the second storage unit.

6. The data decoding structure as described in claim 4, characterized in that, The write control module further includes: Generate decoding start indication information and write the decoding start indication information into the first storage unit and the second storage unit. The decoding start indication information is used to indicate the start of decoding when the write control module receives the decoding data for the first time.

7. The data decoding structure as described in claim 6, characterized in that, The first storage unit further includes: Upon receiving the decoding start indication information, when the decoding start indication information indicates that decoding has started, the address of the read pointer and the address of the write pointer of the first storage unit are initialized.

8. The data decoding structure as described in claim 6, characterized in that, The read control module also includes: Generate decoding end indication information, and read the valid decoded data stored in the first storage unit when the decoding ends, and make the address of the read pointer of the first storage unit coincide with the address of the write pointer of the first storage unit.

9. The data decoding structure as described in claim 4, characterized in that, Also includes: The SKP data control module is used to read the SKP data indication information written to the second storage unit when the valid decoded data read by the read control module includes the message header; The SKP data processing module is used to acquire the valid decoded data read by the read control module and the SKP data indication information read by the SKP data control module. When the SKP data exists in the valid decoded data, it determines whether there is any erroneous data in the SKP data in the valid decoded data. If the SKP data in the valid decoded data contains the bit error data, then the SKP data indication information is modified according to the bit error data; If the erroneous data is not present in the valid decoded data, the SKP data indication information is stored.

10. The data decoding structure as described in claim 9, characterized in that, The read control module also includes: A pre-read indication is generated and output to the SKP data control module. The pre-read indication is used to indicate whether the read control module will perform a read operation next time, and when it is determined that the read control module will perform a read operation next time, it indicates whether the valid decoded data read next time includes the message header.

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