Read control system for DDR memory

Abstract

This application discloses a read control system for DDR memory, comprising an MCU, an external cache, and a DDR interface controller. The read control system is configured to read DDR memory. The DDR memory is used to store pixel data. The DDR interface controller is connected to the external DDR memory of the MCU read control system and is used to read pixel data from the DDR memory according to a first preset operating mode. The external cache has multiple cache lines. The external cache reads pixel data through the DDR interface controller and temporarily stores the read pixel data in the corresponding cache line. When the read pixel data fills all cache lines, it is determined that pixel data covered by a detection window has been obtained. Each cache line is connected to the MCU so that the MCU can read the pixel data in each cache line simultaneously or read the pixel data in the corresponding cache line sequentially. The MCU reads the pixel data in each cache line according to a second preset operating mode.

Description

Technical Field

[0001] This invention relates to the technical field of memory control design, and more specifically to a read control system for DDR memory. Background Technology

[0002] Traditional domestically produced robot main control MCUs integrate CPU, ROM, RAM, various I / O interfaces, and basic functional units (timers / counters, etc.) on a single chip. However, with the rapid development of integrated circuits and map annotation information, traditional MCUs can no longer meet the storage requirements of semantically rich image information and are not conducive to the efficient transmission of pixel data. Compared with traditional single-data-rate memory, Double Data Rate (DDR) memory technology enables two read / write operations within one clock cycle, that is, one read / write operation is performed on the rising edge and one falling edge of the clock. The speed advantage of DDR memory can meet this requirement for efficient transmission.

[0003] However, in the existing storage technology field, traditional MCU single-core architecture does not have a dedicated DDR interface. The MCU core needs to embed a DDR controller to access its external DDR memory, which will increase the MCU area and chip cost, and will also make it difficult for the MCU to quickly traverse the image pixel information covered within the detection window using DDR memory. Summary of the Invention

[0004] This application discloses a read control system for DDR memory, and the specific technical solution is as follows:

[0005] A read control system for DDR memory includes an MCU, an external cache, and a DDR interface controller. The read control system is configured to read from the DDR memory, which stores pixel data. The DDR interface controller is connected to the external DDR memory of the MCU read control system and reads pixel data from the DDR memory according to a first preset operating mode. The external cache has multiple cache lines. The external cache reads pixel data through the DDR interface controller and temporarily stores the read pixel data into the corresponding cache line. When multiple lines of read pixel data fill all cache lines, the cache continues reading until all cache lines are filled. The system determines the pixel data covered by a detection window; a cache line contains a row of pixel data defined by the detection window within a frame of an image; the detection window is a sliding box configured to traverse pixel data on a frame of an image, and its size is related to the number of cache lines; each cache line is connected to the MCU so that the MCU can read the pixel data in each cache line simultaneously, or read the pixel data in a corresponding cache line sequentially; the MCU reads the pixel data in each cache line according to a second preset operation mode; the MCU, off-chip cache, and DDR memory are not manufactured on the same silicon chip.

[0006] Furthermore, the off-chip cache also includes a multiplexing unit, which is connected to the DDR interface controller. The DDR interface controller establishes communication between the data signal and the DDR memory, converting the address signal into an address value corresponding to a cache line, and then transmitting the converted address value to the multiplexing unit. The DDR interface controller also transmits data signals to the multiplexing unit in units of window lines. Here, a window line represents a row of pixel data defined by the detection window within the surface of a frame image. When the detection window defines a new area on the surface of a frame image, the DDR interface controller transmits new data signals to the multiplexing unit in units of window lines. The multiplexing unit is used to select the cache line that needs to be cached based on the address value converted by the DDR interface controller, and then transmit the data signal to the cache line that needs to be cached, so as to establish a data channel between the cache line that needs to be cached and the DDR memory, and enable the MCU to start reading the pixel data in the cache line that needs to be cached.

[0007] Furthermore, the size of the detection window is measured in pixels within a frame of an image; the size of the detection window in the column direction of a frame of an image is equal to the number of rows of the image it covers, and the size of the detection window in the column direction of a frame of an image is equal to the number of cache lines provided in the off-chip cache.

[0008] Furthermore, the DDR interface controller includes a DDR interface data control module and a DDR interface address control module. The DDR interface address control module is constructed using an address decoder, which maps the address signal to the address value of the storage unit corresponding to a cache line and an addressing control signal to achieve the conversion purpose. The addressing control signal is used to control the multiplexing unit to select the data channel between the corresponding cache line and the DDR interface data control module. The DDR interface data control module includes a cache register group, which is used to cache the data signal according to a first preset operation mode, so as to store the data signal in units of the window lines. The data signal includes pixel data of corresponding rows and columns read sequentially in a frame of image, and is located within the range covered by the detection window.

[0009] Furthermore, the DDR memory includes a read control register, a read address register, a read data register, and a read status register. In addition to storing pixel data, the DDR memory determines the first preset operation mode through the read control register, stores various working status information indicating the current reading result through the read status register, temporarily stores the data signal to be read through the read data register, and temporarily stores the address signal to be decoded through the read address register, so as to realize the read operation control of the DDR memory by the off-chip cache under the target system bus protocol.

[0010] Furthermore, the MCU includes an MCU core and MCU interface control logic; the MCU interface control logic is designed based on the MCU core's access bus requirements. Both the MCU core and the off-chip cache are processed according to the target system bus protocol to determine the number of cache lines, the address information of each cache line, the capacity of each cache line, and the cache line that needs to be accessed before performing an access operation, thereby enabling the MCU core to control the read operation of the off-chip cache.

[0011] Furthermore, the read operations specified by the target system bus protocol include burst read operations and single read operations; the MCU core performs single read operations or burst read operations on each cache line of the external cache by using the MCU interface control logic; the external cache performs burst read operations on the DDR memory through the DDR interface data control module.

[0012] Furthermore, each time the MCU core receives the signal corresponding to the target address value mapped by the address decoder, the MCU core traverses each cache line through the MCU interface control logic. If the target address value exists in the currently traversed cache line, the pixel data stored in the target address is read from the currently traversed cache line. If the target address value does not exist in any cache line in the off-chip cache, the off-chip cache is triggered to read pixel data and its address value of one unit access length from the DDR memory at once through the DDR interface controller and store it in the corresponding cache line. One unit access length is equal to the burst length reached under one burst read operation. The first preset operation mode is a burst read operation.

[0013] Furthermore, the DDR interface controller also includes an interrupt register. When the off-chip cache reads pixel data of a unit access length from the DDR memory in a single operation through the DDR interface controller, the DDR interface controller configures the first cache address of the pixel data of a unit access length in the off-chip cache as the starting address of the earliest cache line read by the MCU. Simultaneously, the interrupt register transmits an interrupt signal to the MCU core to determine the starting address of the earliest cache line currently read by the MCU core. The first cache address of the pixel data of a unit access length in the off-chip cache is inserted into the interrupt vector table of the MCU core, and the read operation priority of each cache line is configured for the MCU core.

[0014] Furthermore, the number of consecutive address units in each cache line is equal, and the data bit width of each address unit is equal, so that the off-chip cache is composed of multi-row, multi-column data blocks, wherein the address unit is the storage unit; the number of consecutive address units in each cache line is greater than or equal to the unit access length; the data stored in each address unit is pixel data with a preset data bit width; wherein the data storage capacity of each address unit is equal.

[0015] Furthermore, within one clock cycle of the read control system's counting, the number of pixel data read by the MCU performing a burst read operation on the external cache is greater than the number of pixel data read by the MCU performing a single read operation on the external cache; when the MCU accesses the external memory in the same operating mode, the MCU retrieves data from the external cache faster than the MCU core retrieves data from the DDR memory; the rate at which the MCU retrieves data from the DDR memory in the second preset operating mode is equal to the rate at which the external cache retrieves data from the DDR memory in the second preset operating mode; wherein, the second preset operating mode is either a burst read operation or a single read operation.

[0016] Compared with existing technologies, this application does not integrate DDR memory, cache, and MCU core into the same on-chip system. Instead, it sets the DDR memory, off-chip cache, and DDR interface controller as external devices of the MCU. This leverages the flexibility of the MCU in developing applications using externally mounted DDR memory. The DDR interface controller acts as the communication interface between the DDR memory and the off-chip cache. Based on a bus protocol, it accelerates the off-chip cache's row-by-row and column-by-column traversal of the pixel data within the frame of a single-frame image. Then, based on the corresponding bus protocol, it transmits the traversal results to the MCU. Therefore, when designing access to external image memory, the MCU does not need to design a dedicated on-chip interface control module. Instead, it completes the search work in the matching window pixel environment through an externally connected interface control device with appropriate logic. This reduces costs and ensures that pixel data is quickly acquired by the bus within a reasonable range. The lack of a memory interface control unit does not significantly limit the development of window image processing and computing applications for the MCU.

[0017] By combining the address decoder inside the DDR interface controller to map the address signals issued by the DDR memory and the cache unit inside the DDR interface controller to temporarily store the data signals, each cache line in the external cache can be selected sequentially to form a data channel between the MCU, the external cache, the DDR interface controller, and the DDR memory. This allows the MCU core to traverse each row of pixel data covered by the detection window in a single frame image with fewer on-chip interfaces and less on-chip cache. Since the internal logic of the DDR interface controller works with the multiplexing unit inside the external cache to select the data channel to be accessed, the read control system uses data signals and address signals to interact and selectively read one or more rows of pixel data that can be framed by the detection window, adapting to the traversal scenarios of image detection algorithms; and reducing the design and application complexity of reading and writing the external DDR memory of the MCU. Attached Figure Description

[0018] Figure 1 This is a schematic block diagram of a read control system for a DDR memory, as one embodiment is disclosed.

[0019] Figure 2 A schematic block diagram illustrating the connection relationship between a DDR interface controller and a DDR memory is disclosed as one embodiment. Detailed Implementation

[0020] The following descriptions of the embodiments are with reference to the accompanying drawings, illustrating specific embodiments in which this application can be implemented. Directional terms used in this application, such as "up," "down," "front," "back," "left," "right," "inner," "outer," and "side," are merely for reference to the accompanying drawings. Therefore, the directional terms used are for illustrative and understanding purposes only, and not for limiting the scope of this application.

[0021] The terms "first," "second," "third," etc. (if present) in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the objects described in this way can be used interchangeably where appropriate. Furthermore, the terms "comprising" and "having," and their variations, are intended to cover non-exclusive inclusion.

[0022] The terminology used in this application specification is only used to describe specific embodiments and is not intended to represent the concepts of this application. Unless the context clearly distinguishes them, expressions used in the singular encompass expressions used in the plural. In this application specification, it should be understood that terms such as “comprising,” “having,” and “containing” are intended to describe the possibility of the presence of the features, numbers, steps, actions, or combinations thereof disclosed in this application specification, and are not intended to exclude the possibility of the presence or addition of one or more other features, numbers, steps, actions, or combinations thereof. The same reference numerals in the drawings refer to the same parts. The drawings and descriptions are considered illustrative in nature and not restrictive. In the drawings, structurally similar units are indicated by the same reference numerals. Furthermore, for understanding and ease of description, the dimensions and thicknesses of each component shown in the drawings are arbitrarily shown, but this application is not limited thereto. To further illustrate the technical means and effects adopted by this application to achieve the intended inventive purpose, the following detailed description, in conjunction with the accompanying drawings and specific embodiments, describes in detail the specific implementation, structure, features, and effects of the read control system for DDR memory proposed according to this application.

[0023] As one embodiment, a read control system for DDR memory is disclosed, such as Figure 1As shown, the read control system includes an MCU, an external cache, and a DDR interface controller. The read control system is configured to read DDR memory, which stores pixel data. The read control system can interact with the DDR memory via a bus connected to its internal interface, allowing the MCU to acquire pixel data from the image with less need for dedicated embedded interfaces. The DDR interface controller is connected to the external DDR memory of the read control system. The DDR interface controller reads pixel data from the DDR memory according to a first preset operating mode. This first preset operating mode is set by the instruction fetch interface of the DDR interface controller or the MCU. It can be implemented with a one-to-one bus connection between the DDR interface controller and the DDR memory, or with a one-to-one bus connection between the external cache and the MCU. The external cache has multiple cache lines, ensuring that each cache line caches at least one row of pixel data framed by the detection window in one frame of the image. The off-chip cache reads pixel data through the DDR interface controller and temporarily stores the read pixel data in the corresponding cache line. In order to meet the needs of image traversal and make full use of a cache line, the currently read cache line needs to be filled with pixel data and the stored pixel data is sent to the MCU in a timely manner. When multiple lines of read pixel data fill all cache lines, it is determined that the pixel data covered by a detection window has been obtained. The pixel data cached in a cache line is a row of pixel data framed by the detection window within the surface of a frame image. The detection window is a sliding box configured to traverse pixel data on the surface of a frame image. The size of the detection window is related to the number of cache lines and specifically to the unit of measurement of the size of the detection window. Each cache line is connected to the MCU, allowing the MCU to simultaneously read pixel data from each cache line. This achieves the effect of parallel transmission of pixel data covered within a detection window, or sequential reading of pixel data from a given cache line to achieve pixel-by-pixel traversal. Each cache line is configured with a starting address value for external device operation and can be mapped to a corresponding address signal, enabling the MCU to perform read operations line by line based on the mapped address signal. The MCU reads pixel data from each cache line according to a second preset operating mode. This second preset operating mode is configured by a dedicated register and is related to the bus connected to the MCU and DDR memory, configuring the timing functions of the data channel between the MCU, external cache, and DDR memory.

[0024] The MCU can establish communication with each cache line through a target system bus (e.g., SPI bus, I2C bus, DDR bus, etc.) to perform parallel or serial transmission of pixel data across multiple window lines, meeting the needs of image processing algorithms under various timing conditions. The MCU interacts with its external cache lines for pixel data exchange. Generally, to meet certain image processing requirements (at least matrix multiplication and convolution operations can be performed on the pixel data within the detection window), the MCU's internal logic resources mainly include logic control blocks, clock networks, digital signal processing resources (DSP cores), and MCU interface control logic. The logic control blocks include display lookup tables, adders, registers, etc., but do not include SRAM storage units to reduce wafer area. In the read control system disclosed in this embodiment, an external cache is used instead to utilize the data caching function between the MCU and the external DDR memory. Furthermore, the external cache can be flexibly configured to adapt to the range of pixel data traversed in a single pass through the detection window via the logic control resources within the DDR interface controller.

[0025] It should be noted that the MCU, off-chip cache, and DDR memory are not manufactured on the same silicon chip, so that the MCU, off-chip cache, and DDR memory do not constitute the same on-chip system; preferably, the DDR interface controller, MCU, off-chip cache, and DDR memory are not integrated into the same on-chip system; or, the DDR interface controller and off-chip cache are integrated into the same on-chip system.

[0026] Compared with existing technologies, this embodiment does not integrate the DDR memory, cache, and MCU core into the same on-chip system. Instead, it sets the DDR memory, off-chip cache, and DDR interface controller as external devices of the MCU. This leverages the flexibility of the MCU in developing applications using externally mounted DDR memory. The DDR interface controller acts as the communication interface between the DDR memory and the off-chip cache. Based on a bus protocol, it accelerates the off-chip cache's row-by-row and column-by-column traversal of the pixel data within the frame of a single-frame image. Then, based on the corresponding bus protocol, it transmits the traversal results to the MCU. Therefore, when designing access to external image memory, the MCU does not need to design a dedicated on-chip interface control module. Instead, it completes the search work in the matching window pixel environment through an externally connected interface control device with appropriate logic. This reduces costs and ensures that pixel data is quickly acquired by the bus within a reasonable range. The lack of a memory interface control unit does not significantly limit the development of window image processing and computing applications for the MCU.

[0027] As one example, such as Figure 1As shown, the off-chip cache also includes a multiplexing unit, which is connected to the DDR interface controller. The DDR interface controller establishes communication between the DDR memory and the data signal and the address signal. The DDR interface controller is used to convert the address signal into the address value corresponding to a cache line, and then transmits the converted address value to the multiplexing unit. The DDR interface controller also transmits the data signal to the multiplexing unit in units of window lines. In this embodiment, the DDR interface controller plays the role of parsing and converting the data signal and the address signal, and conforms to the target system bus protocol so that the off-chip cache can perform a first preset operation mode on the DDR memory. The window line represents a row of pixel data framed by the detection window within the surface of a frame image. It is a part of a row in a frame image that is framed in real time. The number of pixels in a row of a frame image and the number of pixel data contained in the window line are pre-configured. When the detection window frames a new area on the surface of a frame image, the DDR interface controller transmits new data signals to the multiplexing unit in units of window lines. The data and address signals originate from the external DDR bus (belonging to the target system bus) of the DDR memory, forming the interaction channel between the off-chip cache and the DDR memory. The DDR interface controller can be an interface, including address bus, data bus, control signal lines, etc., which can connect control registers, status registers and read data registers. From the perspective of the terminal device, it can be equivalent to a connector, connecting different devices to access the corresponding data registers.

[0028] The multiplexing unit is used to select the cache line that needs to be cached based on the address value converted by the DDR interface controller, and then transmit the data signal to the cache line that needs to be cached to establish a data channel between the cache line that needs to be cached and the DDR memory, thereby forming a data channel between the MCU, the off-chip cache and the DDR memory, which enables the MCU to start reading pixel data in the cache line that needs to be cached. Figure 1As shown, the off-chip cache has four cache lines internally, named cacheline1, cacheline2, cacheline3, and cacheline4 from top to bottom. A multiplexing unit is connected to cacheline1, cacheline2, cacheline3, and cacheline4 respectively. The converted address value output by the DDR interface controller to the multiplexing unit can be the address range or starting address value of cacheline1, cacheline2, cacheline3, and cacheline4 that currently needs to be cached, establishing a data channel between the off-chip cache and the DDR memory. Each data channel established in the multiplexing unit is a channel for reading and writing data between the DDR memory and each cache line. When the multiplexing unit uses a multiplexer, the converted address value is used to control the relevant input / output ports to switch and select one data channel, enabling the off-chip cache to read, write, and control the DDR memory through the DDR interface controller on that data channel.

[0029] like Figure 1 As shown, each cache line in the off-chip cache has four storage units. In each cache line, the leftmost storage unit is the first storage unit where the data signal is input in that cache line, and the rightmost storage unit is the first storage unit where the data signal is read by the MCU in that cache line. The off-chip cache is a register group arranged in a matrix (each register is equivalent to a storage unit), forming a complete and reusable control logic with good structure, reusability, and scalability. This type of register group can provide the data source under the detection window condition for the MCU to implement various complex image processing control logics, and can perform mathematical matrix operations, convolution function operations, etc.

[0030] Specifically, the size of the detection window is measured in pixels within a frame of an image; the size of the detection window in the column direction of a frame of an image is equal to the number of rows of the image it covers, and the size of the detection window in the column direction of a frame of an image is equal to the number of cache lines in the off-chip cache. For example... Figure 1 As shown, the off-chip cache has 4 cache lines. Therefore, the size of the detection window in the column direction of a frame image is equal to 4 pixels, i.e., 4 pixel data. In a frame image, pixel coordinates can be used to represent pixel points or pixel data. One storage unit of a cache line is used to store one pixel point or one pixel data. Figure 1The off-chip cache shown can be filled with 16 pixels at once, which is the pixel data framed by the 4x4 detection window of the MCU. Based on this, multiply-accumulators can be used within the MCU to perform rotation matrix and translation vector operations on the pixel data framed by the 4x4 detection window. Since the off-chip cache can be refreshed by external pixel data, the MCU can iteratively adjust the pixel data framed by the 4x4 detection window to obtain a more accurate calculation result.

[0031] As one example, such as Figure 1 As shown, the DDR interface controller includes a DDR interface data control module and a DDR interface address control module. These two modules are electrically connected, including but not limited to sharing the same clock source. This allows the DDR interface data control module to output data signals to the multiplexer units in the external cache, while the DDR interface address control module simultaneously outputs address signals to the multiplexer units in the external cache. The DDR interface data control module includes a cache register group, which is used to cache the data signals according to a first preset operating mode, storing the data signals in units of window rows. In this embodiment, the data signals include pixel data from corresponding rows and columns read sequentially within a frame of an image, located within the area covered by the detection window. This data can originate from pixel data collected by a visual sensor and be stored in the DDR memory in real time. Figure 2It is known that the DDR interface address control module is composed of an address decoder. The address decoder is used to map the address signal into the address value of the memory cell in the corresponding cache line and the address control signal to achieve the conversion purpose. The address control signal is used to control the multiplexing unit to select the data channel between the corresponding cache line and the DDR interface data control module. The address decoder decodes the address signal into the address value of a cache line to be cached. For easier MCU access, it can also be configured to decode the address value of the space occupied by the MCU in the off-chip cache, i.e., decode the address range and pixel data capacity of the corresponding cache line, as well as the address control signal used to index different cache lines. Then, the multiplexing unit can transmit the pixel data and its address value stored in the cache register group to the storage unit of the corresponding cache line. The address decoder can also load the decoding result of the address signal into the target system bus for transmission to the MCU, enabling the MCU to read, write, and control cacheline1, cacheline2, cacheline3, and cacheline4 without affecting the MCU's operation or occupying the MCU's on-chip bus, thus improving read / write speed. Therefore, in this embodiment, the DDR interface controller and the off-chip cache act as read / write caches for the DDR memory and the MCU, respectively. Combined with the matching design of various bus protocols, the overall read / write speed will be improved several times.

[0032] Furthermore, the address decoder is also used to dynamically configure the number of selected cache lines in the off-chip cache. To achieve address segmentation and mapping, a top-level index table can be used to map each cache line; then, a secondary address table is used to map each part of the storage unit of each cache line to a specific address value; finally, according to the addressing control signal, the off-chip cache and the MCU query the corresponding address value in the secondary address table, thereby realizing the segmentation and mapping of the cache lines.

[0033] As one example, combined with Figure 2As can be seen, the DDR memory includes a read control register, a read address register, a read data register, and a read status register. Besides storing pixel data acquired by an external vision sensor (camera), the DDR memory determines the first preset operation mode through the read control register and stores various working status information indicating the current read result through the read status register. This working status information is the state machine state information that cyclically appears under the first or second preset operation mode. The DDR memory also temporarily stores the data signal to be read through the read data register for transmission to the cache register group, and temporarily stores the address signal to be decoded through the read address register for transmission to the address decoder, thereby enabling the off-chip cache to control the read operation of the DDR memory under the target system bus protocol. This, combined with the characteristics of the DDR memory and the off-chip cache, ensures improved, balanced, and stable read / write performance of the DDR interface controller.

[0034] In summary, the external cache, combined with the address decoder inside the DDR interface controller mapping the address signals from the DDR memory and the cache unit inside the DDR interface controller temporarily storing the data signals, can sequentially select each cache line in the external cache to form a data channel between the MCU, the external cache, the DDR interface controller, and the DDR memory. This allows the MCU core to traverse each row of pixel data covered by the detection window in a single frame image with fewer on-chip interfaces and less on-chip cache. Furthermore, since the internal logic of the DDR interface controller works with the multiplexing unit inside the external cache to select the data channel to be accessed, the read control system uses data signals and address signals to interact and selectively read one or more rows of pixel data that can be framed by the detection window, adapting to the traversal scenarios of image detection algorithms; and reducing the design and application complexity of reading and writing DDR memory outside the MCU.

[0035] As one example, such as Figure 1As shown, the MCU includes an MCU core and MCU interface control logic. The MCU interface control logic is designed based on the MCU core's bus access requirements. The bus that the MCU core needs to access is an on-chip system bus (e.g., AHB bus or AXI bus) inside the MCU, and a target system bus (e.g., DDR bus) outside the MCU. Both the MCU core and the off-chip cache are processed according to the target system bus protocol to determine the number of cache lines, the address information of each cache line, the capacity of each cache line, and the cache line to be accessed before performing an access operation. The characteristics of these cache lines are specifically obtained by the MCU interface control logic from the target system bus, realizing the MCU core's read operation control of the off-chip cache, including triggering the MCU core to simultaneously read the pixel data in each cache line through the MCU interface control logic, effectively improving the speed at which the MCU uses DDR memory to traverse the image information covered within the detection window.

[0036] It should be noted that, in this embodiment, the MCU can be composed of dedicated control logic; the MCU can be a single-core or multi-core processing architecture. The MCU's read request instructions are controlled by the MCU interface control logic and follow the timing characteristics of the access bus protocol supported by the MCU to ensure that the MCU core can normally access the off-chip cache. The MCU typically accesses external memory through a single transfer operation.

[0037] Preferably, the read operations specified by the target system bus protocol include burst read operations and single read operations; the MCU core performs single read operations or burst read operations on each cache line of the off-chip cache by using the MCU interface control logic to realize a second preset operation mode; the off-chip cache performs burst read operations on the DDR memory through the DDR interface data control module to realize a first preset operation mode.

[0038] It's important to note that a burst read operation is a type of memory access where the host can continuously read / write multiple words. It leverages the linear relationship between memory locations by providing the initial address at the start of the burst read operation and then transferring n-1 addresses during the read process, thus reducing the number of cycles required for access. Here, n is the burst length, i.e., the burst length achieved in a single burst read operation. Burst read operations improve access speed and enhance the performance of the read control system. A single read operation, on the other hand, is a data transfer method that reads only a single word from memory. It only requires providing one address, and the single-word length achieved in a single read operation is less than the burst length achieved in a burst read operation. Single read operations are most commonly used to retrieve random data from external or internal memory. This operation can speed up the processing time of specific pixel data, thereby improving system performance.

[0039] It should be noted that DDR SDRAM (DDR for short) is a double data rate synchronous dynamic random access memory. DDR memory can establish an electrical connection with the off-chip cache through the DDR interface to configure the memory access space (each cache line) outside the MCU as a double data rate memory system. The DDR interface of DDR memory can significantly improve the data transfer rate without changing the maximum signal frequency of the system; even if the maximum frequency of the data signal is doubled, the DDR signal allows external access devices to double the throughput while maintaining the current maximum feasible clock frequency.

[0040] In this embodiment, the cache memory, or simply cache, is used to cache the data that the MCU needs to read from the DDR memory, as well as the data that the MCU needs to write to the DDR memory. The MCU can then indirectly access the DDR memory through the cache memory (acting as a data cache instead of the target on-chip memory). Each time, it can directly read a portion of the data to be accessed from the cache memory (equivalent to several instructions from an instruction set originally stored in the DDR memory, which are pre-read into the cache memory). Of course, the MCU can also write a small portion of the instructions into the cache memory for data backup. It is worth noting that the input rate supported by the cache memory interface should ideally be the same as its output rate. This eliminates the need for a data buffer in the device accessing the cache memory to balance this difference, reducing the complexity of the access control logic.

[0041] As one embodiment, each time the MCU core receives the signal corresponding to the target address value mapped by the address decoder, the MCU core... Figure 1The MCU interface control logic traverses each cache line, specifically by checking the address values ​​stored in each memory cell within the cache line to determine if the required pixel data has been successfully accessed. In this embodiment, when the MCU core accesses data using the signal corresponding to the target address value mapped by the address decoder, the MCU core first searches for the target address value in the corresponding cache line in the off-chip cache. Only when the target address value required by the MCU is not found in the off-chip cache does the off-chip cache access the DDR memory through the DDR interface controller, thereby accelerating the access speed of the MCU core. Here, the target address value can be an address value within the DDR memory, which can be further mapped to the address value of a memory cell in the corresponding cache line in the off-chip cache.

[0042] Before each read of the target address value from the off-chip cache, the MCU core sequentially checks... Figure 1 The cache lines shown (cacheline1, cacheline2, cacheline3, and cacheline4) are indexed for address data, including in ascending order of index number (e.g., ...). Figure 1 The cache lines are indexed sequentially from top to bottom (from cacheline1 to cacheline4). Within each cache line, the memory locations are indexed in ascending order of address value, for example, traversing the small boxes from right to left within the same cache line. Then, a newline is started to index the memory locations in the next cache line, which is the cache line with the larger index number. For example, after traversing all the memory locations in cacheline1, the process switches to start traversing cacheline2.

[0043] If the target address value exists in a currently traversed cache line, the pixel data stored at the target address is read from that cache line. To facilitate the MCU kernel's addressing of various memory units in the off-chip cache, the address bus (which can be defined by an on-chip bus such as the AHB bus) mounted on the MCU interface control logic can be used to specify the address of each memory unit, and then the data bus (which can be defined by an on-chip bus such as the AHB bus) can be used to transmit the data to be written or read. It should be noted that the MCU kernel can store index data and addresses within it; furthermore, the MCU interface control logic can also use index registers and address registers to store the corresponding data, and can communicate with the MCU kernel using the on-chip bus to control the index data and addressing. Additionally, the MCU interface control logic can use a set of control signal lines to indicate the current operating mode (e.g., burst write or single read), and the address of the current register and memory unit.

[0044] If the target address value does not exist in any cache line of the off-chip cache, the off-chip cache is triggered to read a unit access length of pixel data and its address value (from the address value of the DDR memory) from the DDR memory in one go through the DDR interface controller, and store it in the corresponding cache line to update the existing pixel data and its address value. Since a unit access length is equal to the burst length reached under a burst read operation, the first preset operation mode is a burst read operation. Therefore, the off-chip cache is configured by the DDR interface controller to read a unit access length of pixel data from the DDR memory through a burst read operation to refresh the pixel data in the corresponding cache line of the off-chip cache. After updating the data in the corresponding cache line, the MCU kernel is notified to read the updated data in the cache line (which can also be considered as the data in a cache line of the current index). It then determines whether the address value in the cache line of the current index contains the required pixel data. If so, the address matches and the indexing is complete, but it doesn't necessarily traverse the entire cache line. Otherwise, a cache loss is determined, and the off-chip cache needs to be triggered to further read a new unit of access length of pixel data and its address value from the DDR memory. This update and indexing process is repeated until the MCU reads the required target address value from a cache line of the current index and obtains the corresponding pixel data. The MCU kernel then determines that it has obtained valid data and a matching address. In this embodiment, the entire indexing process can be considered as being controlled by the MCU interface control logic issuing corresponding access commands to complete the process.

[0045] It should be noted that the unit access length is equal to the burst length, which is preferably 64, 32, 16, 8, or 4. The burst length represents the number of consecutive address units transferred in a single burst read operation. The burst read operation is configured with a dedicated register within the DDR interface controller. The external cache's access to the DDR memory is designed based on the AHB or AXI protocol to ensure that the external cache's read operation to the DDR memory is a burst read operation; similarly, the MCU's access to the external cache is designed based on the AHB or AXI protocol to ensure that the MCU's read operation to the external cache is either a burst read operation or a single read operation.

[0046] Based on the aforementioned embodiments, the DDR interface controller further includes an interrupt register, located outside the off-chip cache, which needs to maintain address signal interaction with the off-chip cache. When the off-chip cache reads pixel data of a unit access length from the DDR memory at once through the DDR interface controller, it also actually reads the target address value. In this case, the DDR interface controller configures the first cache address of the pixel data of a unit access length in the off-chip cache as the starting address of the first cache line read by the MCU. Figure 1 The address of the rightmost storage unit of a cache line (cacheline1) within the off-chip cache can be represented as the starting address value. Simultaneously, the interrupt register transmits an interrupt signal to the MCU core to determine the starting address of the earliest cache line currently being read by the MCU core. The first cache address of the pixel data of a unit access length within the off-chip cache is inserted into the interrupt vector table of the MCU core, and the read operation priority of each cache line is configured for the MCU core. The interrupt register within the DDR interface controller primarily connects to the output terminals of some combinational logic circuits to configure and send interrupt signals. The combinational logic circuits are characterized in that their output at any given time depends solely on the input at that moment, regardless of the circuit's previous state. The interrupt register is used to transmit the interrupt signals of each cache line (corresponding to the control signal corresponding to the first cache address of each cache line, specifically originating from...) Figure 2The read control register and read status register shown (which can be output in an orderly manner under the processing of combinational logic) are mapped to the interrupt vector table of the MCU core according to a specified priority. Therefore, when the MCU core reads multiple cache lines in parallel through the MCU interface control logic, it can pre-determine the multiple address spaces of the MCU's external devices and map them into multiple data signal buses by the MCU interface control logic. Then, the interrupt register decides the priority to read one or more cache lines, and can preferentially read one or more memory units of a cache line, thereby realizing the MCU core's control over the priority of each cache line.

[0047] In one embodiment of cache lines, each cache line consists of multiple storage units. Within a cache line, one or more idle storage units are grouped into a queue. When a storage unit in use is queued by the multiplexing unit, it is placed at the end of the queue (in the cache line). Figure 1 The leftmost storage unit), when the MCU needs to read the storage unit, will use the first storage unit of the queue (the cache line in the leftmost storage unit). Figure 1 The rightmost memory cell (used as the first cache address) is retrieved and used to form the read operation priority. Reducing the occupation of the MCU's internal bus helps to improve read and write speeds, thereby speeding up the time required for specific pixel data processing programs and improving system performance.

[0048] In some embodiments, the number of consecutive address units in each cache line is equal, and the data width of each address unit is equal, so that the off-chip cache consists of multi-row, multi-column data blocks. A data block in a certain row and column is equivalent to an address unit in the corresponding column of a cache line at that row, where the address unit is the storage unit. The number of consecutive address units in each cache line is greater than or equal to the unit access length, and the number of consecutive address units in each cache line is marked as the cache line length. The cache line length is used here as a standard for dividing an address line. When accessing, reading, or storing data externally, this division is a prerequisite. The data capacity of the divided address can be determined by the width of the data transmitted per clock cycle. The data stored in each address unit is pixel data with a preset data width. Preferably, the preset data width is 64 bits, 32 bits, or 16 bits, which can be used as the smallest unit for the MCU to access the off-chip cache. Since each address unit stores the same amount of data, the capacity of the off-chip cache is equal to the product of the total number of cache lines, the cache line length, and the preset data width. The number of consecutive addresses indicated in each cache line is equal and fixed. Each address unit stores pixel data of a preset data width, which can be set to 32 bits. When the cache line length is set to 16, one cache line stores 16 32-bit pixel data entries. Furthermore, when the off-chip cache has 32 cache lines, its capacity for pixel data is 32. 16 32-bit.

[0049] The number of consecutive address units in each cache line is greater than or equal to the unit access length (i.e., the burst length). Specifically, the unit access length is equal to the product of the first preset parameter and the cache line length.

[0050] When the first preset parameter equals 1, the pixel data read from the DDR memory using a burst read operation in the off-chip cache updates the pixel data in the earliest cache line read by the MCU, enabling the MCU to access data in units of one cache line, and refreshing cached data with a granularity of one cache line length. This implementation can occur when the MCU detects that the target address value does not exist in any cache line of the off-chip cache, or it can occur before the MCU begins accessing the off-chip cache.

[0051] When the first preset parameter is less than 1 and greater than 0, the data read from the DDR memory by the off-chip cache in a burst read operation updates a portion of the data in the earliest cache line read by the MCU. The ratio of the number of address units occupied by this portion of data to the total number of address units in a cache line is the first preset parameter. If the amount of data read from the DDR memory by the off-chip cache in a burst read operation is less than the length of the cache line, then only a portion of the data in a cache line can be replaced. This implementation can occur when the MCU detects that the target address value does not exist in any cache line in the off-chip cache, or it can occur before the MCU starts accessing the off-chip cache.

[0052] In the embodiments provided in this application, it should be understood that the disclosed systems and chips can be implemented in other ways. For example, the system embodiments described above are merely illustrative. For instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the shown or discussed mutual couplings, direct couplings, or communication connections may be indirect couplings or communication connections through some interfaces, devices, or units, and may be electrical, mechanical, or other forms. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

Claims

1. A read control system for DDR memory, characterized in that, The read control system includes an MCU, an off-chip cache, and a DDR interface controller; the read control system is configured to read from the DDR memory; the DDR memory is used to store pixel data. The DDR interface controller is connected to the external DDR memory of the MCU read control system. The DDR interface controller is used to read pixel data from the DDR memory according to the first preset operation mode. Multiple cache lines are set up in the off-chip cache; The off-chip cache reads pixel data through the DDR interface controller and temporarily stores the read pixel data in the corresponding cache line. When the read pixel data fills all cache lines, it is determined that the pixel data covered by a detection window has been obtained. A cached row of pixel data is a row of pixel data that the detection window defines within the surface of a frame of image; The detection window is a sliding box configured to traverse pixel data on the surface of an image frame. The size of the detection window is related to the number of cache lines. The size of the detection window in the column direction of an image frame is equal to the number of cache lines in the off-chip cache. Each cache line is connected to the MCU, so that the MCU can read the pixel data in each cache line simultaneously, or read the pixel data in a corresponding cache line sequentially; wherein, the MCU reads the pixel data in each cache line according to the second preset operation mode; The MCU, off-chip cache, and DDR memory are not manufactured on the same silicon chip.

2. The read control system according to claim 1, characterized in that, The off-chip cache also includes a multiplexing unit, which is connected to the DDR interface controller; The DDR interface controller establishes communication between the DDR memory and the DDR memory for data and address signals. The DDR interface controller converts the address signals into address values ​​corresponding to a cache line and then transmits the converted address values ​​to the multiplexing unit. The DDR interface controller also transmits data signals to the multiplexing unit in units of window rows. Here, a window row represents a row of pixel data defined by the detection window within the surface of a frame image. When the detection window defines a new area on the surface of a frame image, the DDR interface controller transmits new data signals to the multiplexing unit in units of window rows. The multiplexing unit is used to select the cache line that needs to be cached based on the address value converted by the DDR interface controller, and then transmit the data signal to the cache line that needs to be cached to establish a data channel between the cache line that needs to be cached and the DDR memory, and enable the MCU to start reading the pixel data in the cache line that needs to be cached.

3. The read control system according to claim 2, characterized in that, The size of the detection window is measured in pixels within a frame of an image; the size of the detection window in the column direction of a frame of an image is equal to the number of rows of the image it covers.

4. The read control system according to claim 2, characterized in that, The DDR interface controller includes a DDR interface data control module and a DDR interface address control module; The DDR interface address control module is composed of an address decoder. The address decoder is used to map the address signal into the address value of the memory cell in the corresponding cache line and the address control signal to achieve the conversion purpose. The address control signal is used to control the multiplexing unit to select the data channel between the corresponding cache line and the DDR interface data control module. The DDR interface data control module includes a cache register group, which is used to cache the data signal according to a first preset operation mode, so as to store the data signal in units of the window rows. The data signal includes pixel data of corresponding rows and columns read sequentially in a frame of image, and is located within the range covered by the detection window.

5. The read control system according to claim 4, characterized in that, The DDR memory includes a read control register, a read address register, a read data register, and a read status register; In addition to storing pixel data, the DDR memory determines the first preset operation mode through a read control register, stores various working status information indicating the current reading result through a read status register, temporarily stores the data signal to be read through a read data register, and temporarily stores the address signal to be decoded through a read address register, so as to realize the read operation control of the DDR memory by the off-chip cache under the target system bus protocol.

6. The read control system according to claim 4, characterized in that, The MCU includes an MCU core and MCU interface control logic. The MCU interface control logic is designed based on the MCU core's access to the bus requirements. Both the MCU core and the off-chip cache are processed according to the target system bus protocol to determine the number of cache lines, the address information of each cache line, the capacity of each cache line, and the cache line that needs to be accessed before performing an access operation, thereby enabling the MCU core to control the read operation of the off-chip cache.

7. The read control system according to claim 6, characterized in that, The target system bus protocol specifies that the read operations include burst read operations and single read operations; The MCU core performs single read operations or burst read operations on each cache line in the off-chip cache using the MCU interface control logic; the off-chip cache performs burst read operations on the DDR memory through the DDR interface data control module.

8. The read control system according to claim 7, characterized in that, Each time the MCU kernel receives the signal corresponding to the target address value mapped by the address decoder, the MCU kernel traverses each cache line through the MCU interface control logic. If the target address value exists in a cache line currently being traversed, then the pixel data stored in the target address is read from the cache line currently being traversed. If the target address value does not exist in any cache line of the off-chip cache, the off-chip cache is triggered to read pixel data and its address value of one unit access length from the DDR memory at once through the DDR interface controller and store it in the corresponding cache line. A unit access length is equal to the burst length achieved in a single burst read operation; wherein, the first preset operation mode is a burst read operation.

9. The read control system according to claim 8, characterized in that, The DDR interface controller also includes an interrupt register; When the off-chip cache reads a unit access length of pixel data from the DDR memory at one time through the DDR interface controller, the DDR interface controller configures the first cache address of the unit access length of pixel data in the off-chip cache as the starting address of the first cache line read by the MCU. At the same time, the interrupt register transmits an interrupt signal to the MCU core to determine the starting address of the first cache line currently read by the MCU core. Specifically, the pixel data of a unit access length is inserted into the interrupt vector table of the MCU kernel at the first cache address in the off-chip cache, and the read operation priority of each cache line is configured for the MCU kernel.

10. The read control system according to claim 8, characterized in that, The number of consecutive address units in each cache line is equal, and the data bit width set for each address unit is equal, so that the off-chip cache is composed of multi-row, multi-column data blocks, wherein the address unit is the storage unit; The number of consecutive address units in each cache line is greater than or equal to the unit access length; Each address unit stores pixel data with a preset data bit width; Each address unit stores the same amount of data.

11. The read control system according to claim 1, characterized in that, Within one clock cycle of the read control system's counting, the number of pixel data read by the MCU performing a burst read operation on the off-chip cache is greater than the number of pixel data read by the MCU performing a single read operation on the off-chip cache; When the MCU accesses the off-chip memory in the same operating mode, the MCU retrieves data from the off-chip cache faster than the MCU core retrieves data from the DDR memory. The rate at which the MCU acquires data from the DDR memory in the second preset operation mode is equal to the rate at which the off-chip cache acquires data from the DDR memory in the second preset operation mode; wherein, the second preset operation mode is either a burst read operation or a single read operation.

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