Quantum chip and method of fabrication, and quantum computer

Abstract

The application discloses a quantum chip and a preparation method thereof, and a quantum computer. The quantum chip comprises a first chip, a second chip, a rigid support and a connecting body between the first chip and the second chip. The rigid support supports between the first chip and the second chip, and the connecting body forms an electrical connection between the first chip and the second chip. The application solves the technical problem of low yield of the prepared flip chip in the related art.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of quantum, in particular to a quantum chip and a preparation method, and a quantum computer. BACKGROUND

[0002] Flip-chip technology is a necessary technology to realize a scalable multi-qubit quantum processor. The current mainstream Flip-chip technology is based on indium (In) pillars, that is, after a thick In plating layer is prepared into a columnar structure on a quantum chip, the In pillars are bonded to another quantum chip through compression to form a Flip-chip structure. In this mainstream method, the In pillars simultaneously play the roles of mechanical support and electrical conduction. However, In is soft in texture and prone to compression tilting, resulting in a low yield.

[0003] Therefore, in the related art, the prepared Flip-chip has the problem of low yield.

[0004] In view of the above problems, no effective solution has been proposed so far. SUMMARY

[0005] Embodiments of the present application provide a quantum chip and a preparation method, and a quantum computer, to at least solve the technical problem of low yield of the prepared Flip-chip in the related art.

[0006] According to an aspect of an embodiment of the present application, a quantum chip is provided, comprising: a first chip, a second chip, and a rigid support and a connecting body between the first chip and the second chip, wherein the rigid support supports between the first chip and the second chip, the connecting body forms an electrical connection between the first chip and the second chip, a plurality of qubits are arranged on the first chip, a read resonant cavity and a qubit controller are arranged on the second chip, and the first chip and the second chip are connected in a flip-chip manner, wherein the electrical connection formed by the connecting body includes a first electrical connection and a second electrical connection, the read resonant cavity is configured to read the states of the plurality of qubits based on the first electrical connection, and the qubit controller is configured to adjust a magnetic communication signal input to the plurality of qubits based on the second electrical connection to control the plurality of qubits.

[0007] Optionally, the control of the plurality of qubits by the qubit controller includes driving the plurality of qubits to transition between different energy levels and adjusting the frequencies of the plurality of qubits.

[0008] Optionally, the second electrical connection transmits the magnetic communication signal in the form of a coplanar waveguide.

[0009] Optionally, the rigid support is a rigid column, the rigid column is arranged on the first chip, a first superconducting thin film is arranged on an outer surface of the rigid column, and the connecting body forms the electrical connection between the first chip and the second chip in a manner comprising: a crimping manner and a welding manner.

[0010] Optionally, in the case where the electrical connection manner is the crimping manner, a second superconducting thin film is arranged on the first superconducting thin film at a position corresponding to a top end of the rigid column, and the first chip is crimped to the second chip in a flip-chip manner.

[0011] Optionally, the welding manner comprises at least one of the following: the first chip is welded to the second chip in a flip-chip manner at a position of the first superconducting thin film corresponding to a top end of the rigid column; a second superconducting thin film is arranged on the first superconducting thin film at a position corresponding to the top end of the rigid column, and the first chip is welded to the second chip in a flip-chip manner at the second superconducting thin film; a third superconducting thin film is arranged on the second chip at a position corresponding to the top end of the rigid column after the first chip is flipped, and the first chip is connected to the second chip by welding the third superconducting thin film to the first superconducting thin film.

[0012] Optionally, the welding manner is a manner of applying pressure to the connecting body in combination with ultrasonic vibration.

[0013] According to an aspect of some embodiments of the present application, there is provided a quantum chip, comprising: a first chip, a second chip, and a rigid support and a connecting body between the first chip and the second chip, wherein the rigid support supports between the first chip and the second chip, and the connecting body forms an electrical connection between the first chip and the second chip.

[0014] Optionally, the rigid support comprises a rigid column.

[0015] Optionally, a material of the rigid column is at least one of the following: metal, non-metal, alloy, and compound.

[0016] Optionally, the connecting body comprises a welding portion, and the welding portion forms the electrical connection between the first chip and the second chip in a welding manner.

[0017] Optionally, the welding portion is a superconducting thin film.

[0018] Optionally, the superconducting thin film is at least one of the following: aluminum, tantalum, tin, titanium, zirconium, nitride, carbide, and oxide.

[0019] Optionally, the first chip, the rigid support and the connecting body are connected to the second chip as a whole.

[0020] Optionally, the rigid support has a first part of the connecting body thereon, the second chip has a second part of the connecting body thereon, the first chip, the rigid support and the first part are connected as a whole, the second chip and the second part are connected as another whole, and the whole and the another whole are connected.

[0021] Optionally, the first chip is welded to the second chip by applying pressure to the connecting body in combination with ultrasonic vibration.

[0022] According to another aspect of the present application, there is provided a quantum device, comprising: a first chip, a rigid support and a connecting body, wherein the first chip is connected to one end of the rigid support, and the other end of the rigid support is connected to the connecting body, the rigid support is used to support between the first chip and a second chip of another quantum device, and the connecting body is used to form an electrical connection between the first chip and the second chip.

[0023] Optionally, the connecting body comprises a welding portion, and the first chip is welded to the second chip by applying pressure to the welding portion in combination with ultrasonic vibration.

[0024] According to still another aspect of the present application, there is provided a method for manufacturing a quantum chip, comprising: manufacturing a rigid support on a first chip; manufacturing a connecting body; and connecting the first chip to a second chip through the rigid support and the connecting body, wherein the rigid support supports between the first chip and the second chip, and the connecting body forms an electrical connection between the first chip and the second chip.

[0025] Optionally, the rigid support comprises a rigid column, the connecting body comprises a first superconducting thin film covering an outer surface of the rigid column and a welding portion, and the first chip is welded to the second chip by applying pressure to the welding portion in combination with ultrasonic vibration.

[0026] Optionally, the manufacturing of the connecting body comprises: manufacturing the first superconducting thin film on the rigid column on the first chip, and forming the first superconducting thin film at a position corresponding to a contact point with the second chip as the welding portion, wherein the connecting body comprises the first superconducting thin film and the welding portion; and the connecting of the first chip to the second chip through the rigid support and the connecting body comprises welding the first chip to the second chip through the welding portion.

[0027] Optionally, the preparing the connector comprises: preparing the first superconducting thin film on the rigid column on the first chip, and preparing a second superconducting thin film on the first superconducting thin film at a position corresponding to the contact point of the second chip, and taking the second superconducting thin film as the welding part, wherein the connector comprises the first superconducting thin film and the welding part; and the connecting the first chip to the second chip by the rigid support and the connector comprises: welding the first chip to the second chip by the welding part.

[0028] Optionally, the preparing the connector comprises: preparing a third superconducting thin film on the contact point of the second chip, and taking the third superconducting thin film as the welding part, and preparing a first superconducting thin film on the rigid column on the first chip, wherein the connector comprises the first superconducting thin film and the welding part; and the connecting the first chip to the second chip by the rigid support and the connector comprises: connecting the first chip to the second chip by combining the welding part with the first superconducting thin film.

[0029] According to still another aspect of the present application, there is provided a quantum computer comprising the quantum chip according to any one of the above.

[0030] In the embodiments of the present application, the rigid support and the connector are used to connect the first chip and the second chip, and the rigid support and the connector form mechanical connection and electrical connection between the first chip and the second chip. Since the rigid support has high hardness and good mechanical properties, the distance between the first chip and the second chip can be stably maintained, and the problem of inclination between the first chip and the second chip can be avoided, so that the mechanical connection is more stable and accurate on the basis of ensuring electrical connection, and the yield of the quantum chip prepared based on the flip-chip process is improved. BRIEF DESCRIPTION OF DRAWINGS

[0031] The accompanying drawings, which are included to provide a further understanding of the present application and constitute a part of this application, illustrate embodiments of the present application and together with the description serve to explain the present application. In the drawings:

[0032] Figure 1 is a structural schematic diagram of a quantum chip according to an embodiment of the present application;

[0033] Figure 2 is an exploded view of components included in a quantum chip according to an embodiment of the present application;

[0034] Figure 3 is another exploded view of components included in a quantum chip according to an embodiment of the present application;

[0035] Figure 4 is another exploded view of components included in a quantum chip according to an embodiment of the present application;

[0036] Figure 5 is a structural schematic diagram of a quantum device according to an embodiment of the present application;

[0037] Figure 6 is a flowchart of a method for manufacturing a quantum chip according to an embodiment of the present application;

[0038] Figure 7 is a structural schematic diagram of a quantum computer according to an embodiment of the present application;

[0039] Figure 8 is a schematic diagram of a first chip according to a first chip in the present alternative embodiment;

[0040] Figure 9 is a schematic diagram of manufacturing a rigid medium layer when manufacturing a rigid support on the first chip in the present alternative embodiment;

[0041] Figure 10 is a schematic diagram of manufacturing the rigid medium layer into a rigid column structure in the present alternative embodiment;

[0042] Figure 11 is a schematic diagram of manufacturing a superconducting thin film on the rigid column structure in the present alternative embodiment;

[0043] Figure 12 is a schematic diagram of flip-chipping the first chip with the manufactured rigid support and superconducting thin film onto a second chip in the present alternative embodiment;

[0044] Figure 13 is a schematic diagram of a complete quantum chip finally obtained in the present alternative embodiment;

[0045] Figure 14 is a schematic diagram of a quantum chip according to another alternative embodiment of the present application. DETAILED DESCRIPTION

[0046] In order to enable persons skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by persons skilled in the art without creative labor should fall within the scope of protection of the present application.

[0047] It is to be understood that the terms "first", "second", and the like, used in the description and the claims of the application and the above description of the drawings merely serve the purpose of differentiating between similar objects and do not necessarily imply a sequence or order of precedence. It is to be understood that the data so distinguished can be interchanged under appropriate circumstances, so that the embodiments of the application described herein can be carried out in other sequences than the one illustrated or described herein. Furthermore, the terms "comprising", "including", "containing", and any variations thereof, are intended to cover a non-exclusive inclusion such that a process, method, system, product, or apparatus that comprises, includes, or contains an item or list of items who have the enclosed quantity of those items does not include only those items or items respectively, but can include other items not expressly listed or inherent to such process, method, system, product, or apparatus.

[0048] First, some of the nouns or terms appearing in the description of the embodiments of the application are applicable to the following explanations:

[0049] Flip Chip Technology: also known as "flip-chip packaging method", is a chip packaging technology. Unlike the past chip packaging technology which directly places the chip on the substrate, and then uses wire bonding technology to connect the chip and the pad (refers to the input / output part of the chip) on the substrate, flip-chip packaging technology refers to growing bumps at the chip connection points, then turning the chip upside down, with the front facing down, and directly connecting with the packaging shell or wiring substrate (substrate). The technology has been widely used in the field of chip processing. The chip processed by flip-chip technology is called flip chip. Simply put, it is a process of integrating two layers of chips into one, with corresponding structures providing mechanical support and electrical connection between the two layers of chips.

[0050] In: indium, a metal material that exhibits superconducting properties at low temperatures. Its soft and low melting point characteristics are often used as a material for preparing quantum chips using flip-chip technology.

[0051] In column: a columnar structure formed of metal indium.

[0052] Rigid column: a columnar structure formed of a rigid medium. The rigid medium forming the rigid column can be various, that is, mainly strong in hardness.

[0053] PVD: Physical Vapor Deposition (PVD), refers to a thin film preparation technology that makes materials deposited on the plated workpiece under vacuum conditions by using physical methods. PVD technology is divided into three categories, namely vacuum evaporation coating, vacuum sputtering coating and vacuum ion coating. The principle of PVD coating technology is that under vacuum conditions, through high-current arc discharge technology, gas discharge is used to evaporate the target material and ionize the evaporated material, and under the action of the electric field, the evaporated material or its reaction product is deposited on the workpiece. The bonding force of the PVD film layer to the surface of the workpiece is greater, the hardness of the film layer is higher, the wear resistance and corrosion resistance are better, and the performance of the film layer is more stable.

[0054] CVD: Chemical Vapor Deposition (CVD), is to introduce gaseous reactants containing thin film elements into the reaction chamber, and chemical reactions occur on the wafer surface to generate the required solid thin film and deposit on the surface. In the chip manufacturing process, most of the required thin film materials, whether conductors, semiconductors, or dielectric materials, can be prepared by chemical vapor deposition, such as silicon dioxide film, silicon nitride film, polysilicon film, etc. It has the advantages of low deposition temperature, easy control of film composition and thickness, proportional relationship between film thickness and deposition time, good uniformity and repeatability, good step coverage, easy operation, etc. Among them, low deposition temperature and good step coverage are very beneficial to the manufacture of ultra-large scale integrated circuits. Therefore, it is an important thin film deposition method in the production process of integrated circuits. Commonly used are atmospheric pressure chemical vapor deposition, low pressure chemical vapor deposition, and plasma enhanced chemical vapor deposition, etc.

[0055] As described above, the flip chip technology applied in the quantum technology field is based on indium pillars to achieve the process, and after the thick In plating layer on a quantum chip is prepared into a columnar structure, it is bonded to another quantum chip by pressure bonding to form a flip chip. Therefore, when the flip chip process is used in the quantum field, the quantum field needs to meet the quantum low-temperature superconducting characteristics, and indium is one of the few materials that can meet the above characteristics, so the use of indium pillars between chips is the mainstream, that is, the currently used process in the existing public technology is indium pillars, and it is difficult to think of alternative solutions.

[0056] But the indium column also has its own defects, for example, the indium is relatively soft, the indium column structure is prone to deformation, such as, after preparing the indium column between the two chips, it is easy to cause the whole structure to tilt. To solve the above problems, the embodiment of the application improves the flip chip in the existing quantum chip field, and exceeds the limitation of the quantum characteristics under the premise of meeting the quantum low-temperature superconducting characteristics, and proposes a stable structure between the two chips of the flip chip, so as to solve the problems caused by the mainstream indium column in the existing scheme.

[0057] According to the embodiment of the application, a quantum chip is provided, Figure 1 is a structure diagram of the quantum chip provided by the embodiment of the application, as Figure 1 shown, the quantum chip 10 includes: a first chip 20, a second chip 30, and a rigid support 40 and a connecting body 50 between the first chip 20 and the second chip 30, wherein the rigid support 40 is supported between the first chip 20 and the second chip 30, and the connecting body 50 forms an electrical connection between the first chip 20 and the second chip 30.

[0058] By using the above embodiment, the rigid support 40 and the connecting body 50 are connected between the first chip 20 and the second chip 30, and the rigid support 40 and the connecting body 50 form a mechanical connection and an electrical connection between the first chip 20 and the second chip 30. Since the rigidity of the rigid support 40 is high, it has good mechanical properties and can stabilize the distance between the first chip 20 and the second chip 30, avoiding the tilt problem between the first chip 20 and the second chip 30, realizing more stable, accurate mechanical connection on the basis of ensuring electrical connection, and improving the yield of the quantum chip prepared based on the flip process.

[0059] As an optional embodiment, since the rigid support 40 and the connecting body 50 are used, the structure can replace the indium column structure used in the related art. Since indium is not used, there is no performance reduction of the quantum chip caused by the introduction of the indium surface oxide layer. By using the above structure, since there is no oxide layer, the problem of performance reduction of the quantum chip caused by the introduction of the oxide layer can be effectively avoided. By using the above structure, compared with the flip technology of the quantum chip in the related art, there are few alternative materials, and indium is the mainstream choice, which effectively breaks through this technical problem and provides a way to replace the indium column structure.

[0060] As an optional embodiment, the first chip 20 and the second chip 30 can be of the same type or different types. For example, the first chip 20 and the second chip 30 can both be quantum chips, or one of the first chip 20 and the second chip 30 can be a quantum chip and the other can be a traditional computer chip. The first chip 20 is stacked on the second chip 30 in a manner that the first chip 20 is flipped on the second chip 30 to obtain the quantum chip.

[0061] As an optional embodiment, in the quantum chip 10, the first chip 20 and the second chip 30 can be two chips of the same status. Therefore, the rigid support 40 and the connecting body 50 between the first chip 20 and the second chip 30 can be connected in the following manners. One is that the rigid support 40 is arranged on the first chip 20 and supports between the first chip 20 and the second chip 30, and the connecting body 50 is electrically connected to the first chip 20 and the second chip 30. The other is that the rigid support 40 is arranged on the second chip 30 and supports between the first chip 20 and the second chip 30, and the connecting body 50 is electrically connected to the first chip 20 and the second chip 30.

[0062] As an optional embodiment, for the rigid support 40 and the connecting body 50 between the first chip 20 and the second chip 30, the rigid support 40 mainly plays a role of mechanical fixation between the first chip 20 and the second chip 30. Since it is rigid, the structure is stable. The connecting body 50 is used to realize the electrical connection between the first chip 20 and the second chip 30, and the electrical connection can be superconducting connection. Therefore, the rigid support 40 and the connecting body 50 between the first chip 20 and the second chip 30 realize the mechanical connection and the electrical connection between the first chip 20 and the second chip 30. It should be noted that between the first chip 20 and the second chip 30, most of the structure is the rigid support 40, and the connecting body 50 can be a superconducting film. Therefore, the height of the rigid support 40 can be the spacing between the first chip 20 and the second chip 30 to a certain extent.

[0063] It should be noted that the rigid support 50 supports between the first chip 20 and the second chip 30 to form a gap space between the first chip 20 and the second chip 30. The gap space can isolate the interference between the first chip 20 and the second chip 30, so that the quantum devices on the first chip 20 and the quantum devices on the second chip 30 are arranged separately. On the one hand, the arrangement of the quantum devices can be more regular, and the utilization rate of the chip space can be improved. On the other hand, since the interference between the devices can be effectively avoided, the quantum coherence of the quantum devices can also be better maintained.

[0064] In addition, it should be noted that the connection body 50 can be in contact or non-contact with the first chip 20 and the second chip 30, and the connection mode can be determined according to the design requirements of the circuit.

[0065] The connection body 50 can be in contact or non-contact with the first chip 20 and the second chip 30, and the connection mode can be determined according to the design requirements of the circuit.

[0066] As an optional embodiment, the connection between the first chip 20 and the second chip 30 through the rigid support body 40 and the connection body 50 is to stack the first chip 20 on the second chip 30, that is, to form a flip chip to a certain extent, to obtain a quantum chip formed by two chips based on the flip chip process, and to realize the expansion of the chip function. Therefore, the first chip 20 and the second chip 30 can be quantum elements that can respectively realize corresponding predetermined functions to a certain extent, and based on the quantum elements that can respectively realize corresponding predetermined functions, a quantum chip with overall function is formed.

[0067] As an optional embodiment, the material of the rigid support body 40 can be in various forms, for example, it can be a material with high hardness, such as metal, non-metal, alloy and compound, etc. For example, the material forming the rigid support body 40 can be metal: gold, iron, aluminum, etc., non-metal: silicon, carbon, carbon silicon, etc., alloy: metal alloy, non-metal alloy, metal and non-metal alloy, etc., and compound: silicon nitride, nitride, carbon silicon, etc. Alternatively, the rigid support body 40 can be of various types, for example, it can be a rigid column with indefinite quantity. The shape of the rigid column can also be various, for example, it can be a circular column, a trapezoidal column, a cubic column, a rectangular column, etc. The rigid column with high hardness can effectively realize a stable mechanical structure.

[0068] As an optional embodiment, when the first chip 20 and the second chip 30 are connected through the rigid support 40 and the connecting body 50, the connection between the connecting body 50 and the chip can be achieved in various ways in the above-mentioned example. For example, the connecting body 50 can be connected to the second chip 30 by crimping. In this case, the connecting body 50 can be made of a soft material, such as indium, which is crimped to the second chip 30. For example, to achieve a more secure electrical connection between the first chip 20 and the second chip 30, a more reliable connection can be achieved by welding the connecting body 50 to the second chip 30, so that the connection between the first chip 20 and the second chip 30 is more secure. In this case, the connecting body 50 can include a welding portion, and the welding portion can be used to achieve the electrical connection between the first chip 20 and the second chip 30. The welding portion can be a weldable superconducting material. Therefore, when the connecting body 50 includes a welding portion that is connected by welding, the connection between the first chip 20 and the second chip 30 can not only ensure the stability of the mechanical connection, but also ensure the reliability of the electrical connection, thereby achieving a double guarantee of mechanical connection and electrical connection.

[0069] As an optional embodiment, the connecting body 50 can include a conductive portion as the main body of the electrical connection, which can be combined with the welding portion or directly formed as one body with the connecting body 50. In this case, the conductive portion can be a superconducting film, which can be a single type or multiple types.

[0070] As an optional embodiment, the welding portion can also be a superconducting film, which can be welded to the second chip 30. In this case, the superconducting film can be made of various materials, such as at least one of aluminum, tantalum, tin, titanium, zirconium, nitride, carbide, and oxide. For example, the superconducting film can be a single material film, such as a tantalum film, an aluminum film, a nickel film, or the like. It can also be a nitride film, such as a titanium nitride film (TiN), a zirconium nitride film (ZrN), a chromium nitride film (CrN), an aluminum titanium nitride film (TiAlN), or the like. For example, the carbide film can be a titanium carbide film (TiC), a titanium carbon nitride film (TiCN), or the like. For example, the oxide film can be a titanium oxide film (TiO), or the like.

[0071] As an optional embodiment, when the first chip 20 and the second chip 30 are connected through the rigid support 40 and the connecting body 50, the connection relationship between the first chip 20, the second chip 30, the rigid support 40 and the connecting body 50 can be various. For example, based on the different positions of the connecting body 50, the following connection modes can be adopted.

[0072] One connection mode is that the first chip 20, the rigid support 40 and the connecting body 50 are connected with the second chip 30 as a whole. In this connection mode, the rigid support 40 and the connecting body 50 can be regarded as a part of the first chip 20 and connected with the second chip 30. In this connection mode, the connecting body 50 is on the first chip 20. In the case that the connecting body 50 is on the first chip 20, various combination modes can also be adopted. Hereinafter, the connection between the connecting body 50 and the second chip 30 is taken as a welding mode as an example for illustration.

[0073] For example, one combination mode can be that the connecting body 50 can be a type of superconducting thin film (first superconducting thin film). Figure 2 is an exploded view of components included in a quantum chip according to an embodiment of the present application, as shown in Figure 2 A layer of the first superconducting thin film 501 is deposited on the outer surface of the rigid support 40, and a welding portion (the black part 502 in the figure only represents the welding portion) of the first superconducting thin film 502 at the position corresponding to the contact point of the second chip 30 is formed, and the first chip 20 is welded to the second chip 30 through the welding portion. In this combination mode, the first superconducting thin film and the welding portion form the connecting body 50. The first superconducting thin film 501 and the welding portion are actually a superconducting material, or the welding portion is a part of the first superconducting thin film 501, and only pressure and ultrasonic vibration are applied at the position corresponding to the contact point of the second chip 30, so as to form the welding portion. It should be noted that the welding portion of the first superconducting thin film at the position corresponding to the contact point of the second chip 30 is formed, and the first chip 20 is welded to the second chip 30 through the welding portion, which can be completed in one step, that is, the welding portion is formed by applying pressure and ultrasonic vibration to the first superconducting thin film at the position corresponding to the contact point of the second chip 30, and the first chip 20 is welded to the second chip 30.

[0074] Another combination mode is that the connecting body 50 can include various types of superconducting thin films. Figure 3 is another exploded view of components included in a quantum chip according to an embodiment of the present application, as shown in Figure 3As shown, a first type of superconducting thin film (first superconducting thin film 501) can be deposited on the outer surface of the rigid support 40, and a second type of superconducting thin film (second superconducting thin film 503, different from the first type of superconducting thin film) can be deposited on the first type of superconducting thin film, corresponding to the contact position of the second chip 30, and the second superconducting thin film 503 serves as a soldering portion. The first chip 20 is soldered to the second chip 30 through the soldering portion. In this combination, the first superconducting thin film 501 and the second superconducting thin film 503 as the soldering portion form the connecting body 50. In this combination, the first superconducting thin film 501 can serve as the main electrical connection part of the first chip 20 and the second chip 30, and the second superconducting thin film 503 as the soldering portion becomes the contact position of the first chip 20 and the second chip 30. Therefore, in this combination, the first chip 20, the rigid support 40 and the connecting body 50 are integrated, that is, the first chip 20, the rigid support 40 and the first superconducting thin film 501 and the second superconducting thin film 503 are integrated. In this combination, the connecting body 50 combined with both the first superconducting thin film 501 and the second superconducting thin film 503 is on the first chip 20. In this combination, the second type of superconducting thin film serves as the soldering portion to solder the first chip 20 to the second chip 30.

[0075] Another connection mode is that the connecting body 50 is partially on the second chip 30. Figure 4 is another exploded view of components included in a quantum chip according to an embodiment of the present application, as shown in Figure 4As shown, the rigid support body 40 has a first part (i.e. the first superconducting thin film 501) of the connecting body 50, the second chip 30 has a second part 504 of the connecting body 50, the first chip 20, the rigid support body 40 and the first part are integrated as one, the second chip 30 and the second part 504 are integrated as another, and the one and the another are connected. That is, the first chip 20, the rigid support body 40 and the first part are integrated as one, the second chip 30 and the second part 504 (i.e. the soldering part) are integrated as another, and the one and the another are connected, so that the first chip 20 and the second chip 30 are connected. Still taking the soldering as an example to illustrate the connecting mode of the connecting body 50. In this connecting mode, the main conductive part (the first part on the rigid support body 40) and the soldering part (the part on the second chip 30) included in the connecting body 50 are separated. The soldering part is soldered on the second chip 30, and a layer of superconducting thin film (the first superconducting thin film 501) is deposited on the rigid support body 40 of the first chip 20, i.e. the first part of the connecting body 50, and the first superconducting thin film 501 and the soldering part form the connecting body 50. Through the combination of the first superconducting thin film and the soldering part (wherein the combination mode can also be soldering, etc.), the first chip 20 is soldered on the second chip 30. Through the above connecting mode, the connecting body 50 is connected between the first chip 20 and the second chip 30, and the connecting body 50 is prepared separately, so that the flexibility of the chip structure connection can be improved simultaneously or without being limited by the preparation conditions.

[0076] As an optional embodiment, when the first chip 20 and the second chip 30 are connected through the rigid support body 40 and the connecting body 50, the first chip 20 can be soldered on the second chip 30 by applying pressure and ultrasonic vibration to the connecting body 50. In this connecting mode, the rigid support body 40 can bring mechanical stability to the connection between the first chip 20 and the second chip 30, and the first chip 20 is soldered on the second chip 30 by applying pressure and ultrasonic vibration to the connecting body 50, which significantly improves the stability of the connection compared with the pressure connection of the flexible material in the related art, and effectively realizes the stable and reliable electrical connection between the first chip 20 and the second chip 30. Based on the above connecting mode, the mechanical connection between the first chip 20 and the second chip 30 is stable, and the electrical connection is stable, so that the dual reliability of the mechanical connection and the electrical connection is improved.

[0077] As an optional embodiment, when the first chip 20 is soldered on the second chip 30 by applying pressure and ultrasonic vibration to the connecting body 50, and when the rigid support body 40 is in the form of a column, i.e. a rigid column, the connecting body 50 can correspond to the rigid column, for example, the number of rigid columns can correspond to the number of connecting bodies 50, i.e. when there are multiple rigid columns, there are multiple connecting bodies 50 corresponding to the rigid columns.

[0078] According to embodiments of the present invention, a quantum device is also provided. Figure 5 This is a schematic diagram of the structure of a quantum device provided according to an embodiment of the present invention, such as... Figure 5 As shown, the quantum device 60 includes: a first chip 20, a rigid support 40, and a connector 50, wherein the first chip 20 is connected to one end of the rigid support 40, and the other end of the rigid support 40 is connected to the connector 50. The rigid support 40 is used to support the first chip 20 of the quantum device 60 and the second chip 30 of another quantum device, and the connector 50 is used to form an electrical connection between the first chip 20 and the second chip 30.

[0079] As an optional embodiment, the rigid support 40 described above can be a rigid support, i.e., sufficiently strong to support the mechanical structure between the first chip 20 and the second chip 30 of other quantum devices. The connector 50 is a weldable superconductor.

[0080] As an optional embodiment, the quantum device 60 can be considered to some extent as part of the quantum chip formed using the flip-chip technique described above. It should be noted that the quantum device 60 is a partial structure of the aforementioned quantum chip, and similar aspects of the structure also apply here, without further explanation.

[0081] According to embodiments of the present invention, a method for fabricating a quantum chip is also provided. Figure 6 This is a flowchart of a method for fabricating a quantum chip according to an embodiment of the present invention, such as... Figure 6 As shown, the process includes the following steps:

[0082] S602, a rigid support 40 is fabricated on the first chip 20;

[0083] S604, prepare connector 50;

[0084] S606, the first chip 20 is connected to the second chip 30 by a rigid support 40 and a connector 50, wherein the rigid support 40 supports the first chip 20 and the second chip 30, and the connector 50 forms an electrical connection between the first chip 20 and the second chip 30.

[0085] Through the above steps, the first chip 20 and the second chip 30 are connected through the rigid support body 40 and the connecting body 50, and the rigid support body 40 and the connecting body 50 form mechanical connection and electrical connection between the first chip 20 and the second chip 30. Since the rigid support body 40 has high hardness and good mechanical properties, it can stabilize the spacing between the first chip 20 and the second chip 30 and avoid the problem of inclination between the first chip 20 and the second chip 30, thereby realizing more stable mechanical connection, improving the yield of the quantum chip prepared based on the flip-chip process, and ensuring electrical connection.

[0086] As an optional embodiment, the rigid support body 40 includes a rigid column, and the connecting body 50 includes a first superconducting film covering the outer surface of the rigid column and a welding portion. The first chip 20 is welded to the second chip 30 by applying pressure to the welding portion in combination with ultrasonic vibration. That is, when the first chip 20 and the second chip 30 are connected through the rigid support body 40 and the connecting body 50, the first chip 20 can be welded to the second chip 30 by applying pressure to the connecting body 50 in combination with ultrasonic vibration. By using such a connection method, the rigid support body 40 can provide mechanical stability for the connection between the first chip 20 and the second chip 30. By applying pressure to the connecting body 50 while applying ultrasonic vibration, the first chip 20 is welded to the second chip 30, thereby realizing stable and reliable electrical connection between the first chip 20 and the second chip 30. Based on the above connection method, the mechanical connection between the first chip 20 and the second chip 30 is effectively stable, and the electrical connection is stable, thereby achieving double reliability of mechanical connection and electrical connection.

[0087] As an optional embodiment, when the rigid support body 40 is prepared on the first chip 20, various methods can be used, for example, the rigid support body 40 can be prepared on the first chip 20 by at least one of the following methods: a rigid medium layer is prepared on the first chip 20, and the rigid support body 40 is prepared on the rigid medium layer through a photolithography-etching process; the rigid support body 40 is directly etched on the first chip 20.

[0088] The above-mentioned photo-etching process includes two parts of photo-etching process and etching process, wherein the photo-etching process is an important step in the semiconductor device manufacturing process, which uses exposure and development to draw geometric pattern structure on the photoresist layer, and then the pattern on the photo mask is transferred to the substrate by etching process. For example, when the rigid support 40 is prepared on the first chip 20, the pattern (e.g. columnar pattern) of the rigid support 40 can be drawn on the mask by the photo-etching process first, and then the (columnar) pattern is transferred to the first chip 20 by the etching process to obtain the rigid support 40 prepared on the first chip 20. When the rigid support 40 is columnar, it is a rigid column. In addition, when the rigid support 40 is directly etched on the first chip 20, it can be directly etched on the first chip 20 according to the material and shape of the rigid support 40.

[0089] It should be noted that when the first chip 20 and the second chip 30 are mechanically and electrically connected by the rigid support 40 and the connecting body 50, various combined methods can be used, so the corresponding preparation methods also include various methods. Hereinafter, the connection mode of the connecting body 50 is taken as welding as an example to explain the preparation of the connecting body 50 and the steps of connecting the first chip 20 to the second chip 30 through the rigid support 40 and the connecting body 50.

[0090] It should be noted that the first preparation method and the second preparation method are both for the case that the connecting body 50 is on the first chip 20, and the third preparation method is for the case that the connecting body 50 is on the first chip 20 and the second chip 30 respectively.

[0091] The first preparation method is for the case that the connecting body 50 is on the first chip 20 and the connecting body 50 is a type of superconducting thin film. In this case, a layer of superconducting thin film is deposited on the rigid support 40, and the superconducting thin film at the position corresponding to the contact point of the second chip 30 is used as a welding portion, and the first chip 20 is welded to the second chip 30 through the welding portion. For example, in the preparation, the following method can be used: in the preparation of the connecting body 50, a type of superconducting thin film, i.e., a first superconducting thin film, can be prepared on the rigid support 40 on the first chip 20, and the first superconducting thin film at the position corresponding to the contact point of the second chip 30 is formed into a welding portion, wherein the connecting body 50 includes the first superconducting thin film and the welding portion; and the first chip 20 is connected to the second chip 30 through the rigid support 40 and the connecting body 50, including: welding the first chip 20 to the second chip 30 through the welding portion. In this preparation process, when the first superconducting thin film at the position corresponding to the contact point of the second chip 30 is formed into a welding portion, a method of applying pressure to the first superconducting thin film at the corresponding position while applying ultrasonic vibration can be used to form the welding portion, through which the first chip 20 is welded to the second chip 30. By using the above preparation method, since only one type of superconducting thin film can be prepared, the preparation process is simple, and the preparation efficiency can be effectively guaranteed.

[0092] The second preparation method is for the case that the connecting body 50 is on the first chip 20 and the connecting body 50 includes multiple types of superconducting thin films. In this case, a type of superconducting thin film (i.e., the first superconducting thin film described above) is deposited on the rigid support 40, and another type of superconducting thin film (second superconducting thin film) is added as a welding portion on the first superconducting thin film at the position corresponding to the contact point of the second chip 30, and the first chip 20 is welded to the second chip 30 through the welding portion. For example, in the preparation of the connecting body 50, the following processing method can be used: a type of superconducting thin film (first superconducting thin film) is prepared on the rigid support 40 on the first chip 20, and another superconducting thin film (second superconducting thin film) is prepared (added) as a welding portion on the first superconducting thin film at the position corresponding to the contact point of the second chip 30, wherein the connecting body 50 includes the first superconducting thin film and the second superconducting thin film as the welding portion. The first chip 20 is connected to the second chip 30 through the rigid support 40 and the connecting body 50, including: welding the first chip 20 to the second chip 30 through the welding portion. By separately preparing the welding portion for welding on the first superconducting thin film on the rigid support 40, the welding portion can be another type of superconducting thin film, which provides another connection method for welding. In addition, in this welding method, the material of the first superconducting thin film does not need to be consistent with that of the welding portion, so that a new flexible welding method can be provided under the condition of adapting to material selection.

[0093] The third preparation mode is for the case that the connection body 50 includes one or more types of superconducting thin films, and part of the connection body 50 is on the first chip 20 and another part of the connection body 50 is on the second chip 30. In this case, the first superconducting thin film is deposited on the rigid support body 40, the welding part (the third superconducting thin film) is welded to the second chip 30, and the first chip 20 is welded to the second chip 30 by the combination of the first superconducting thin film and the welding part. For example, the following method can be used: when the connection body 50 is prepared, the welding part is welded to the contact point of the second chip 30, and the first superconducting thin film is prepared on the rigid support body 40 on the first chip 20, wherein the connection body 50 includes the first superconducting thin film and the welding part; and the first chip 20 is connected to the second chip 30 through the rigid support body 40 and the connection body 50, including: connecting the first chip 20 to the second chip 30 by combining the welding part with the first superconducting thin film. Based on the different positions of the welding part, the preparation mode of the quantum chip is also different. In the mode of preparing the welding part on the second chip 30, the material of the first superconducting thin film on the rigid support body 40 on the first chip 20 and the welding part prepared on the second chip 30 can also be different, so that the flexible selection of the material can also be effectively adapted to obtain the required quantum chip.

[0094] In the embodiments of the present application, a quantum computer is also provided, Figure 7 is a structural schematic diagram of a quantum computer provided according to an embodiment of the present application, as Figure 7 shown, the quantum computer 70 includes the quantum chip 10 of any of the above.

[0095] Based on the above embodiments and optional embodiments, an optional implementation is provided.

[0096] In the mainstream Flip-chip process in the related art, the In column simultaneously plays a mechanical support and electrical conduction role. However, the In deposition process has relatively low maturity, the process is complex, and the related preparation steps can reduce the performance of the quantum bit; at the same time, the In is soft in texture, the control degree is poor in the crimping process, and crimping tilt is prone to occur, and the electrical conduction is formed by mechanical contact, which is prone to poor contact, resulting in reduced yield. On this basis, it is thought that a fixed height support structure can be prepared on the side of the chip to solve the crimping tilt problem, but the In column preparation is still one of the necessary steps, and the problems of low maturity, complex process, and large-area In surface oxide layer that can reduce the performance of the superconducting quantum bit have not been solved.

[0097] Based on the above problems, in the present optional embodiment, a new Flip-chip process scheme for a quantum processor is provided, that is, a method for preparing a quantum chip based on flip-chip technology, which can effectively solve the defects of the above-mentioned traditional In column scheme.

[0098] In the alternative embodiment, the first chip 20 is represented by a silicon (Si) substrate 1, the second chip 30 is represented by a silicon substrate 2, the rigid support 40 is represented by a rigid column of silicon oxide, and the connecting body 50 is represented by an Al film. The alternative embodiment will be described below in conjunction with the accompanying drawings.

[0099] S1, obtaining the first chip 20, Figure 8 is a schematic diagram of the first chip 20 according to the alternative embodiment, as shown by a silicon (Si) substrate 1. It should be noted that the substrate 1 here can be of any material other than Si, such as a sapphire substrate, etc. Figure 8 S2, when the rigid support 40 is prepared on the first chip 20, a rigid dielectric layer is prepared.

[0100] is a schematic diagram of the preparation of the rigid dielectric layer when the rigid support 40 is prepared on the first chip 20 according to the alternative embodiment, as shown by a silicon oxide (SiOx) on a silicon (Si) substrate 1. The thickness of the silicon oxide (SiOx) can be the gap height designed for Flip-chip. It should be noted that the rigid dielectric layer can be of other materials other than SiOx, such as silicon nitride SiNx, etc. The rigid dielectric layer can also be only some materials with high hardness, for example, some metals, non-metals, alloys, and compounds, etc. Figure 9 Figure 9 S3, based on the rigid dielectric layer, a rigid column as the rigid support 40 is prepared, i.e. through a photolithography-etching process, the rigid dielectric layer is prepared into a rigid column structure. is a schematic diagram of the preparation of the rigid column structure from the rigid dielectric layer according to the alternative embodiment, as shown by a columnar silicon oxide (SiOx) prepared on a silicon (Si) substrate 1. It should be noted that the columnar silicon oxide prepared on the silicon (Si) substrate 1 can be prepared by other means in addition to the photolithography-etching process adopted in the above S2 and S3 steps, for example, by directly etching the substrate to form a structure as shown.

[0101] Figure 10 S4, when the connecting body 50 is prepared, a superconducting material film is prepared through a thin film deposition process, i.e. a solderable superconducting film is deposited on the rigid support 40 on the first chip 20. Figure 10 is a schematic diagram of the preparation of the superconducting film on the rigid column structure according to the alternative embodiment, as shown by a superconducting film deposited on the columnar silicon oxide (SiOx) on the silicon (Si) substrate 1. Figure 10

[0102] S4, when the connecting body 50 is prepared, a superconducting material film is prepared through a thin film deposition process, i.e. a solderable superconducting film is deposited on the rigid support 40 on the first chip 20. Figure 11 is a schematic diagram of the preparation of the superconducting film on the rigid column structure according to the alternative embodiment, as shown by a superconducting film deposited on the columnar silicon oxide (SiOx) on the silicon (Si) substrate 1. Figure 11 ​​As shown, Al film is deposited on the columnar silicon oxide by thin film deposition process. It should be noted that the above-mentioned superconducting film material is Al film, which is only an example, and other superconducting material films can also be used, such as aluminum, tantalum, tin, titanium, zirconium, nitride, carbide, oxide, etc. In addition, the above-mentioned Al film can be deposited by thin film deposition, or other methods, such as physical or chemical plating methods. For example, PVD, CVD, or other plating methods, etc.

[0103] S5, the structure obtained in S4 is inverted and pressure-bonded to the second chip 30 (i.e. the target chip), and the Al film is welded to the second chip 30 by applying pressure to the Si substrate 2 and ultrasonic vibration. Figure 12 is a schematic diagram of the first chip 20 with the rigid support 40 and the superconducting film prepared according to the present alternative embodiment, which is inverted and mounted on the second chip 30, as shown in Figure 12 When the first chip 20 with the rigid support 40 and the superconducting film is inverted and mounted on the second chip 30, the first chip 20 is welded to the second chip 30 by welding the superconducting film to the corresponding contact points of the second chip 30. When pressure is applied to the Al superconducting film, ultrasonic vibration is applied at the same time to weld the Al superconducting film to the second chip 30. It should be noted that when other superconducting film materials are used in the above-mentioned S4, an Al plating layer can be added to the other superconducting film material, or an Al plating layer can be welded to the position of the second chip 30 that contacts the first chip 20.

[0104] S6, the contact part of the Al film and the second chip 30 forms a bonding point (bonding), i.e. the Al of the contact part realizes bonding, and constitutes a complete Flip-chip. Figure 13 is a schematic diagram of the complete quantum chip finally obtained according to the present alternative embodiment, as shown in Figure 13 The material of the black part in the figure is also Al film, which is the same as the Al film deposited on the rigid support 40. The difference between the black part and the Al film deposited on the rigid support 40 is that the Al film at this position is welded to the second chip 30 by applying pressure and ultrasonic vibration, i.e. the Al at this position forms a bonding point and is connected in contact with the second chip 30. The quantum chip is obtained by inverting the first chip 20 on the target chip (second chip 30) through the above-mentioned structure, and the quantum chip is obtained based on the Flip-chip process.

[0105] Compared with the related art, the complete indium is deposited between the two chips, or some support structures are added in the periphery of the indium after the complete indium is deposited, but no matter which way is adopted, the deposition of the complete indium column will inevitably bring the problems existing in the preparation of the indium column and the large-area oxidation of the indium column. By adopting the optional implementation manner, a completely different preparation idea is adopted, the indium column is completely replaced, and it is a completely new preparation manner (regardless of the preparation material or the preparation manner), so that the stable mechanical connection and reliable electrical connection between the flip-chip can be realized without the indium column.

[0106] Therefore, based on the above optional implementation manner, the following beneficial effects can be achieved:

[0107] The use of In is abandoned, and a more mature semiconductor preparation process is adopted, so as to avoid the difficulty and complexity brought by the In-related process.

[0108] The flexible In column is replaced by the rigid column, has good mechanical properties, greatly improves the mechanical properties of the column structure, improves the process parameter window of the compression bonding process, and the equal-height characteristic of the rigid column effectively solves the compression tilt problem and improves the yield.

[0109] Since In is not used, the poor quality In surface is replaced by a good quality traditional superconducting thin film material, which can effectively avoid the problem of performance reduction of the superconducting quantum bit caused by the oxidation of the In surface.

[0110] The bonding force of the Al bonding point is much greater than that of the flexible In column, and the mechanical and electrical connection reliability is also much higher than that of the flexible In column, thereby improving the yield of the Flip-chip process and the reliability of the final device. In addition, the Al bonding point has high compatibility with the connected surface and can be directly connected to a variety of common superconductors. The In column has strong selectivity to the surface of some connected materials and needs to prepare a buffer transition layer.

[0111] The quantum chip obtained based on the above preparation method can have some functions, and the functions of the quantum chip will be described below in combination with the specific functions of the quantum chip.

[0112] Figure 14 is a schematic diagram of a quantum chip according to another optional implementation manner of the present application, as Figure 14As shown, the quantum chip 10 comprises: a first chip 20, a second chip 30, and a rigid support 40 and a connecting body 50 between the first chip 20 and the second chip 30, wherein the rigid support 40 supports between the first chip 20 and the second chip 30, the connecting body 50 forms an electrical connection between the first chip 20 and the second chip 30, a plurality of quantum bits 80 (which can be arranged in an array) are arranged on the first chip 20, a read resonant cavity 90 and a quantum bit controller 100 are arranged on the second chip 30, and the first chip 20 and the second chip 30 are connected in a flip-chip manner, wherein the electrical connection formed by the connecting body 50 includes a first electrical connection and a second electrical connection, the read resonant cavity 90 is configured to read the state of the plurality of quantum bits 80 based on the first electrical connection, and the quantum bit controller 100 is configured to adjust a magnetic communication signal input to the plurality of quantum bits 80 based on the second electrical connection to control the plurality of quantum bits 80.

[0113] Through the above embodiment, since the rigid support 40 and the connecting body 50 are used, the structure can replace the indium column structure used in the related art. Since indium is not used, there is no performance degradation of the quantum chip caused by the introduction of the indium surface oxide layer. With the above structure, since there is no oxide layer, the problem of performance degradation of the quantum chip caused by the introduction of the oxide layer can be effectively avoided. With the above structure, compared with the flip-chip technology of the quantum chip in the related art, there are few alternative materials, and indium is the mainstream choice. This effectively solves the technical problem and provides a way to replace the indium column structure.

[0114] Compared with the indium column structure in the related art, the position of the indium column is effectively avoided, and the problem of affecting the performance of the quantum bit at this position due to oxidation is avoided. For example, in the related art, since the indium column is used, the decoherence time (relaxation time) of the plurality of quantum bits 80 at the position of the indium column is affected, thereby affecting the precision of the plurality of quantum bits 80. In the embodiment of the present application, the structure of the rigid support 40 and the connecting body 50 is used. Since indium is not used, there is no indium surface oxide layer. Therefore, the plurality of quantum bits 80 at the position of the rigid support 40 and the connecting body 50 on the first chip 20 will not be affected by the decoherence time due to the oxide layer, thereby indirectly improving the precision of the plurality of quantum bits 80 themselves.

[0115] For example, in the related art, since an indium post is used, the position of the indium post, when near the readout resonator 90, the efficiency and accuracy of the quantum device (e.g., superconducting quantum interference device) in the readout resonator 90 are affected by the oxidation layer of the indium post. In the embodiment of the present application, the structure including the rigid support body 40 and the connecting body 50 is used instead of the indium post near the readout resonator 90, since no indium is used, there is no oxidation layer on the surface of the indium, and thus the position of the structure of the rigid support body 40 and the connecting body 50 on the first chip 20 corresponding to the readout resonator 90 will not affect the reading efficiency and accuracy of the readout resonator, so that the reading efficiency and accuracy of the readout resonator 90 are ensured.

[0116] For example, in the related art, since an indium post is used, the position of the indium post, when near the readout resonator 90, the efficiency and accuracy of the quantum device (e.g., superconducting quantum interference device) in the readout resonator 90 are affected by the oxidation layer of the indium post. In the embodiment of the present application, the structure including the rigid support body 40 and the connecting body 50 is used instead of the indium post near the readout resonator 90, since no indium is used, there is no oxidation layer on the surface of the indium, and thus the position of the structure of the rigid support body 40 and the connecting body 50 on the first chip 20 corresponding to the readout resonator 90 will not affect the reading efficiency and accuracy of the readout resonator, so that the reading efficiency and accuracy of the readout resonator 90 are ensured.

[0117] For example, in the related art, since an indium post is used, the position of the indium post, when near the readout resonator 90, the efficiency and accuracy of the quantum device (e.g., superconducting quantum interference device) in the readout resonator 90 are affected by the oxidation layer of the indium post. In the embodiment of the present application, the structure including the rigid support body 40 and the connecting body 50 is used instead of the indium post near the readout resonator 90, since no indium is used, there is no oxidation layer on the surface of the indium, and thus the position of the structure of the rigid support body 40 and the connecting body 50 on the first chip 20 corresponding to the readout resonator 90 will not affect the reading efficiency and accuracy of the readout resonator, so that the reading efficiency and accuracy of the readout resonator 90 are ensured.

[0118] The various transmission lines used by the quantum bit controller 100 are replaced by the structure of the embodiment of the present application at the position of the indium post in the related art, so that the signal-to-noise ratio of the transmission line can be effectively improved, and the control accuracy can be improved.

[0119] As an optional embodiment, the second electrical connection can use various transmission methods, for example, a coplanar waveguide can be used to transmit a magnetic communication signal.

[0120] As an optional embodiment, the rigid support 40 is a rigid column, the first superconducting thin film is arranged on the outer surface of the rigid column arranged on the first chip 20, and the connecting body 50 forms the electrical connection between the first chip 20 and the second chip 30 in a manner including a crimping manner and a welding manner.

[0121] The crimping manner is to compress and displace the metal within a specified limit, and the crimping connection can generate metal mutual flow, so that the contact pair of materials is symmetrically deformed, the connection is similar to cold welding connection, better mechanical strength and electrical continuity can be obtained, and more severe environmental conditions can be resisted. In the embodiment of the application, the connecting body 50 is crimped to form the electrical connection between the first chip 20 and the second chip 30. Therefore, in the case that the electrical connection manner is the above-mentioned crimping manner, the second superconducting thin film is arranged on the first superconducting thin film at a position corresponding to the top end of the rigid column, and the first chip 20 is crimped to the second chip 30 in a flip-chip manner.

[0122] The welding manner in a broad sense refers to a process of permanently connecting workpieces by heating or pressing or both, with or without filler material, so that the materials of the workpieces are combined at the atomic level. The welding manner can be classified in many ways. According to the state of the metal during the welding process, the welding method can be divided into three categories: fusion welding, pressure welding and brazing. Among them, the pressure welding refers to a welding method in which pressure is applied to the welded parts (with or without heating) to complete the welding. Pressure welding can have two forms. One is to heat the contact part of the welded metal to a plastic state or a partially melted state, and then apply a certain pressure to make the metal atoms combine with each other to form a firm welded joint. The other is to apply sufficient pressure on the contact surface of the welded metal without heating, and rely on the plastic deformation caused by the pressure to make the atoms close to each other to obtain a firm joint. In pressure welding, one welding method is ultrasonic welding, which uses high-frequency vibration waves to transmit to the surfaces of two objects to be welded, and under pressure, the surfaces of the two objects are rubbed to form a fusion between the molecular layers.

[0123] The process types of ultrasonic welding include various types, for example, 1) fusion welding: the welding head with ultrasonic super high frequency vibration is used to generate friction heat on the joint surface of two plastic blocks under moderate pressure to instantaneously melt and join the two plastic blocks. 2) forming: the concave welding head is pressed against the outer circle of the plastic product, and the welding head emits ultrasonic super high frequency vibration to melt and form the plastic to cover the metal object to fix it. 3) embedding: the metal parts (such as nuts, screws, etc.) are instantaneously extruded into the plastic holes reserved in the metal parts by the welding head and appropriate pressure. 4) riveting: the riveting method refers to the welding head pressing the protruding part of the object to make it hot melt into a rivet, thereby mechanically riveting the two objects. 5) spot welding: spot welding refers to the point welding of objects with difficult welding lines, which can also achieve the effect of fusion welding.

[0124] The ultrasonic welding has many advantages, such as energy saving, environmental protection, high precision, non-melting of welding materials, non-fragile metal characteristics, good conductivity after welding, extremely low or almost zero resistance coefficient, low requirement for the surface of the welded metal, oxidation or plating, short welding time, no need for any flux, gas or solder, no spark, environmental protection and safety.

[0125] Based on the particularity of the quantum chip, the welding method used in the embodiment of the present application can be selected from the above-mentioned pressure welding, for example, the ultrasonic welding method in the above-mentioned pressure welding. That is, the pressure is applied to the connecting body 50 in combination with ultrasonic vibration, that is, the ultrasonic disturbance is applied at the same time as the pressure is applied, so as to achieve the electrical connection between the first chip 20 and the second chip 30.

[0126] As an optional embodiment, when the above-mentioned electrical connection selects the welding method, the welding method can also be various, for example, it can include at least one of the following: the first superconducting film at the position corresponding to the top end of the rigid column is welded on the second chip 30 in the flip-chip manner of the first chip 20; the second superconducting film is arranged at the position corresponding to the top end of the rigid column on the first superconducting film, and the second superconducting film is welded on the second chip 30 in the flip-chip manner of the first chip 20; the third superconducting film is arranged at the position corresponding to the top end of the rigid column after the flip-chip of the first chip 20 on the second chip 30, and the first chip 20 is connected to the second chip 30 by welding the third superconducting film to the first superconducting film. The above-mentioned various types of welding methods used in the embodiment of the present application are described in detail in the above-mentioned preparation method of the quantum chip, and will not be described here.

[0127] It should be noted that the above-mentioned structure of the rigid support body 40 and the connecting body 50 is used to replace the indium column in the related art, which is only applied to the Flip-Chip structure of the quantum chip. Of course, the above-mentioned structure can also be applied to the Flip-Chip structure wafer product before the wafer is cut, and the above-mentioned rigid support body 40 and connecting body 50 are used between the wafers. After obtaining the wafer product of the Flip-Chip structure, the wafer product is cut to obtain the quantum chip of the Flip-Chip structure.

[0128] Based on the above-mentioned optional embodiments, the structure of the rigid support body 40 and the connecting body 50 is used to replace the indium column in the related art in the quantum chip using the flip-chip technology, which effectively avoids the instability, inclination and surface oxidation layer caused by the indium column, and the problems caused by the chip performance, so that the quantum chip is more stable, more accurate and higher performance. In addition, the connecting body 50 is welded by ultrasonic welding, which can make the electrical connection between the quantum chips more stable, and achieve the effect of mechanical structure and electrical connection.

[0129] It should be noted that in the above-mentioned embodiments of the present application, the description of each embodiment has its own emphasis, and the parts not described in detail in a certain embodiment can be referred to the related description of other embodiments.

[0130] The technical features of the above embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above embodiments are described, however, as long as the combination of the technical features does not exist contradictory, it should be considered as the scope of the present application.

[0131] The above is only the preferred embodiment of the present application, it should be noted that for ordinary skilled in the art, without departing from the principles of the present application, can make a number of improvements and refinements, these improvements and refinements should also be considered as the protection scope of the present application.

Claims

1. A quantum chip, characterized by, The application relates to a quantum chip, comprising: a first chip, a second chip, and a rigid support and a connecting body between the first chip and the second chip, wherein the rigid support supports between the first chip and the second chip, the connecting body forms an electrical connection between the first chip and the second chip, a plurality of quantum bits are arranged on the first chip, a reading resonant cavity and a quantum bit controller are arranged on the second chip, and the first chip and the second chip are connected in a flip-chip mode, wherein the electrical connection formed by the connecting body comprises a first electrical connection and a second electrical connection, the reading resonant cavity is used for reading the states of the plurality of quantum bits based on the first electrical connection, and the quantum bit controller is used for adjusting a magnetic communication signal input to the plurality of quantum bits based on the second electrical connection to control the plurality of quantum bits, wherein the connecting body forms the electrical connection between the first chip and the second chip in a welding mode, the welding mode is a mode of applying pressure to the connecting body in combination with ultrasonic vibration, the rigid support is used for mechanically fixing between the first chip and the second chip, the height of the rigid support is the distance between the first chip and the second chip, and the connecting body is used for realizing superconducting connection between the first chip and the second chip. The control of the plurality of quantum bits by the quantum bit controller comprises: driving the plurality of quantum bits to jump between different energy levels and adjusting the frequency of the plurality of quantum bits.

2. The quantum chip of claim 1, wherein, The second electrical connection adopts a form of a coplanar waveguide to transmit the magnetic communication signal.

3. The quantum chip of claim 1, wherein, The rigid support is a rigid column, the rigid column is arranged on the first chip, a first superconducting film is arranged on the outer surface of the rigid column, and the connecting body forms the electrical connection between the first chip and the second chip in a crimping mode.

4. The quantum chip of claim 1, wherein, In the case that the mode of the electrical connection is the crimping mode, a second superconducting film is arranged on the first superconducting film at a position corresponding to the top end of the rigid column, and the first chip is crimped to the second chip in a flip-chip mode.

5. The quantum chip of claim 4, wherein, The welding mode comprises at least one of the following:

6. The quantum chip of claim 4, wherein, The first chip is welded to the second chip in a flip-chip mode at the first superconducting film at a position corresponding to the top end of the rigid column; A second superconducting film is arranged on the first superconducting film at a position corresponding to the top end of the rigid column, and the first chip is welded to the second chip in a flip-chip mode at the second superconducting film; A third superconducting film is arranged on the second chip at a position corresponding to the top end of the rigid column after the first chip is flipped, and the first chip is connected to the second chip by welding the third superconducting film to the first superconducting film. The application relates to a quantum chip, comprising: a first chip, a second chip, and a rigid support and a connecting body between the first chip and the second chip, wherein the rigid support supports between the first chip and the second chip, the connecting body forms an electrical connection between the first chip and the second chip, a plurality of quantum bits are arranged on the first chip, a reading resonant cavity and a quantum bit controller are arranged on the second chip, and the first chip and the second chip are connected in a flip-chip mode, wherein the electrical connection formed by the connecting body comprises a first electrical connection and a second electrical connection, the reading resonant cavity is used for reading the states of the plurality of quantum bits based on the first electrical connection, and the quantum bit controller is used for adjusting a magnetic communication signal input to the plurality of quantum bits based on the second electrical connection to control the plurality of quantum bits, wherein the connecting body forms the electrical connection between the first chip and the second chip in a welding mode, the welding mode is a mode of applying pressure to the connecting body in combination with ultrasonic vibration, the rigid support is used for mechanically fixing between the first chip and the second chip, the height of the rigid support is the distance between the first chip and the second chip, and the connecting body is used for realizing superconducting connection between the first chip and the second chip.

7. A quantum chip, characterized by ​ A first chip, a second chip, and a rigid support and a connecting body between the first chip and the second chip, wherein the rigid support supports between the first chip and the second chip, the connecting body forms an electrical connection between the first chip and the second chip, the first chip is provided with a plurality of quantum bits, the second chip is provided with a read resonant cavity and a quantum bit controller, the first chip and the second chip are connected in a flip-chip manner, wherein the electrical connection formed by the connecting body includes a first electrical connection and a second electrical connection, the read resonant cavity is used to read the state of the plurality of quantum bits based on the first electrical connection, and the quantum bit controller is used to adjust a magnetic communication signal input to the plurality of quantum bits based on the second electrical connection to control the plurality of quantum bits.

8. The quantum chip of claim 7, wherein, The rigid support includes a rigid column.

9. The quantum chip of claim 8, wherein, The material of the rigid column is at least one of metal, non-metal, alloy, and compound.

10. The quantum chip of claim 7, wherein, The connecting body includes a welding portion, and the electrical connection between the first chip and the second chip is formed in a welded manner at the welding portion.

11. The quantum chip of claim 10, wherein, The welding portion is a superconducting thin film.

12. The quantum chip of claim 11, wherein, The superconducting thin film is at least one of aluminum, tantalum, tin, titanium, zirconium, nitride, carbide, and oxide.

13. The quantum chip of claim 7, wherein, The first chip, the rigid support, and the connecting body are connected to the second chip as a whole.

14. The quantum chip of claim 7, wherein, The rigid support has a first part of the connecting body thereon, the second chip has a second part of the connecting body thereon, the first chip, the rigid support, and the first part are connected as a whole, the second chip and the second part are connected as another whole, and the whole and the another whole are connected.

15. A quantum device, comprising: Comprising: A first chip, a rigid support, and a connecting body, wherein the first chip is connected to one end of the rigid support, and the other end of the rigid support is connected to the connecting body, the rigid support is used to support between the first chip and a second chip of another quantum device, form a gap between the first chip and the second chip, and the connecting body is used to form an electrical connection between the first chip and the second chip, the first chip is provided with a plurality of quantum bits, the second chip is provided with a read resonant cavity and a quantum bit controller, the first chip and the second chip are connected in a flip-chip manner, wherein the electrical connection formed by the connecting body includes a first electrical connection and a second electrical connection, the read resonant cavity is used to read the state of the plurality of quantum bits based on the first electrical connection, and the quantum bit controller is used to adjust a magnetic communication signal input to the plurality of quantum bits based on the second electrical connection to control the plurality of quantum bits.

16. A method of fabricating a quantum chip, the method comprising: Comprising: ​ Preparation of a rigid support on a first chip; Preparation of a connecting body; The first chip is connected to the second chip through the rigid support and the connecting body, wherein the rigid support is supported between the first chip and the second chip, the connecting body forms an electrical connection between the first chip and the second chip, the first chip is provided with a plurality of quantum bits, the second chip is provided with a reading resonant cavity and a quantum bit controller, and the first chip and the second chip are connected in a flip-chip manner, wherein the electrical connection formed by the connecting body includes a first electrical connection and a second electrical connection, the reading resonant cavity is used to read the state of the plurality of quantum bits based on the first electrical connection, and the quantum bit controller is used to adjust a magnetic communication signal input to the plurality of quantum bits based on the second electrical connection to control the plurality of quantum bits.

17. The method of claim 16, wherein, The rigid support includes a rigid column, and the connecting body includes a first superconducting thin film covering an outer surface of the rigid column and a welding portion.

18. The method of claim 17, wherein The connecting body is prepared by preparing the first superconducting thin film on the rigid column on the first chip and forming the welding portion at a position corresponding to a contact point of the second chip on the first superconducting thin film, and the connecting body includes the first superconducting thin film and the welding portion; The first chip is connected to the second chip through the welding portion.

19. The method of claim 17, wherein The connecting body is prepared by preparing the first superconducting thin film on the rigid column on the first chip, preparing a second superconducting thin film on the first superconducting thin film at a position corresponding to the contact point of the second chip, and taking the second superconducting thin film as the welding portion, and the connecting body includes the first superconducting thin film and the welding portion; The first chip is connected to the second chip through the welding portion.

20. The method of claim 17, wherein The connecting body is prepared by welding a third superconducting thin film at the contact point of the second chip and taking the third superconducting thin film as the welding portion, and the first superconducting thin film is prepared on the rigid column on the first chip, and the connecting body includes the first superconducting thin film and the welding portion; The first chip is connected to the second chip by combining the welding portion with the first superconducting thin film.

21. A quantum computer, comprising: The quantum chip of any one of claims 1 to 14. The quantum chip of any one of claims 1 to 14.

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