A GOA cascade circuit and method for fast switching between forward and reverse scanning

Abstract

The present invention discloses a GOA cascade circuit and method for fast forward and reverse scanning. The GOA cascade circuit includes a control module, a detection module, and a GOA driver module; the control module is electrically connected to one end of the detection module and one end of the GOA driver module respectively; the other end of the detection module is electrically connected to a row pixel TFT; the other end of the GOA driver module is electrically connected to the row pixel TFT; the detection module is used to detect the charge amount of the row pixel TFT of the current display partition; the control module is used to control the GOA driver module to perform partition scanning on the display screen; the GOA driver module outputs different refresh frequencies to multiple partitions of the display screen to optimize the display quality of the display screen. By detecting the scanned row pixels and obtaining their charge status, the display partitions with insufficient charge are recharged and reversed row by row, thereby achieving different refresh frequencies in different areas of the same display screen, improving the flexibility of image repair, and improving display quality.

Description

Technical Field

[0001] The present invention relates to the technical field of display panels, and in particular to a GOA cascade circuit and method for fast switching between forward and reverse scanning. Background Art

[0002] GOA (Gate Driven on Array) technology is often used in the field of display screen gate drive technology. However, a GOA drive circuit generally supports either forward scanning or reverse scanning. That is, in actual display processes, existing displays often only support one of the two.

[0003] However, a single forward or reverse scan drive scanning method lacks flexibility. For example, sometimes, based on display quality requirements, it is necessary to switch to reverse scanning during the forward scan process. Existing display screens usually wait until the current number of scan lines is completed, that is, a full scan cycle is completed before starting the reverse scan in the next frame. This method is time-consuming, especially in high refresh rate application scenarios. It is also inflexible when a second image repair is required, thus reducing display quality.

[0004] In summary, a driving circuit capable of switching between forward and reverse scanning at any time is needed, which can be applied in the display field to improve display quality. Summary of the Invention

[0005] Existing display screens cannot switch flexibly when performing secondary repairs on the screen, which takes a long time and reduces the display quality.

[0006] In order to solve the above problems, the present application proposes a GOA cascade circuit and method for fast switching between forward and reverse scanning.

[0007] In a first aspect, a GOA cascade circuit with fast forward and reverse scanning switching includes:

[0008] Control module;

[0009] Detection module;

[0010] GOA driver module;

[0011] The control module is electrically connected to one end of the detection module and one end of the GOA driving module respectively;

[0012] The other end of the detection module is electrically connected to the row pixel TFT;

[0013] The other end of the GOA driving module is electrically connected to the row pixel TFT;

[0014] The detection module is used to detect the charge amount of the row pixel TFT of the current display partition;

[0015] The GOA driving modules are cascaded row by row to perform partition scanning on the display screen respectively;

[0016] The control module is used to control the GOA driving module to perform partition scanning on the display screen;

[0017] The partition scan is:

[0018] The GOA driving module outputs different refresh frequencies to the multiple partitions of the display screen respectively, so as to optimize the display quality of the display screen.

[0019] In conjunction with the GOA cascade circuit with fast forward and reverse scanning switching described in the first aspect of the present invention, in a first possible implementation manner, the GOA driver module includes:

[0020] Start unit;

[0021] Output unit;

[0022] Pull-down unit;

[0023] The startup unit is electrically connected to the output unit and the pull-down unit respectively, and is used to drive the main transistor of the output unit to turn on to output a gate driving signal;

[0024] The pull-down unit is also electrically connected to the output unit and is used to keep the input terminal of the output unit at a low level during the pull-down stage to prevent the main transistor from malfunctioning.

[0025] In combination with the first possible implementation of the first aspect of the present invention, in a second possible implementation, the detection module is also used to obtain the GOA driving module information of the last row Gn and the first row G1 of the current partition after the row pixel TFT charge amount of the current partition is less than the specified value.

[0026] In combination with the second possible implementation manner of the first aspect of the present invention, in a third possible implementation manner, the step of controlling the GOA driver module to perform partition scanning on the display screen includes:

[0027] After the forward scan of the current partition is completed, the level signal of the forward scan signal end of the GOA driving module of the last row of the current partition is controlled to be converted from high level to low level;

[0028] Control the level signal of the reverse scan signal end of the GOA driving module of the last row of the current partition, converting it from low level to high level;

[0029] For the Gth n OK, G n-1 Rows G1, …, G1 are scanned in reverse order.

[0030] In combination with the third possible implementation manner of the first aspect of the present invention, in a fourth possible implementation manner, the controlling the GOA driver module to perform partition scanning on the display screen further includes:

[0031] After the reverse scan of the current partition is completed, the level signal of the forward scan signal end of the GOA driving module of the first row of the current partition is controlled to be converted from low level to high level;

[0032] Sequentially process the G1th row, G2th row, ..., Gth row of the current partition. n Scan forward.

[0033] In conjunction with the fourth possible implementation manner of the first aspect of the present invention, in a fifth possible implementation manner, the reverse scanning includes:

[0034] The G n The high level signal output by the row is used as the G n-1 The start signal of the row main transistor.

[0035] In conjunction with the fifth possible implementation manner of the first aspect of the present invention, in a sixth possible implementation manner, the forward scanning includes:

[0036] The G n-1 The high level signal output by the row is used as the G n The start signal of the row main transistor.

[0037] In combination with the sixth possible implementation manner of the first aspect of the present invention, in a seventh possible implementation manner, the start unit includes: a clock signal terminal, a start signal terminal, a forward sweep signal terminal, a reverse sweep signal terminal, a set signal terminal, a first transistor, and a second transistor;

[0038] The output unit includes: a main transistor and a capacitor;

[0039] The pull-down unit includes: a DC signal terminal, a low level input terminal, a pull-up level input terminal, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, and a tenth transistor;

[0040] The clock signal terminal is electrically connected to the main transistor;

[0041] The start signal terminal is electrically connected to the gate of the first transistor;

[0042] The positive scan signal terminal is electrically connected to the drain of the first transistor;

[0043] The reverse scan signal terminal is electrically connected to the source of the second transistor;

[0044] The set signal terminal is electrically connected to the gate of the second transistor;

[0045] The gate of the third transistor, the drain of the third transistor, and the drain of the fourth transistor are electrically connected to each other and then electrically connected to the DC signal terminal;

[0046] The drain of the fifth transistor, the drain of the sixth transistor, the drain of the seventh transistor, the drain of the eighth transistor, the drain of the ninth transistor, and the drain of the tenth transistor are connected in common and then electrically connected to the low-level input terminal;

[0047] The gate of the ninth transistor and the gate of the tenth transistor are connected together and electrically connected to the pull-up level input terminal;

[0048] The source of the first transistor, the drain of the second transistor, the gate of the fifth transistor, the gate of the sixth transistor, the source of the seventh transistor, the source of the ninth transistor, the gate of the main transistor, and the first end of the capacitor are connected to point P.

[0049] The source of the third transistor, the gate of the fourth transistor, and the source of the fifth transistor are connected in common;

[0050] The source of the fourth transistor, the source of the sixth transistor, the gate of the seventh transistor, and the gate of the eighth transistor are connected to point A;

[0051] The source of the main transistor, the second end of the capacitor, the source of the eighth transistor, and the source of the tenth transistor are commonly connected to the output end.

[0052] In a second aspect, a method for fast switching between forward and reverse scanning is provided, using the cascade circuit described in the first aspect, comprising the steps of:

[0053] The GOA driver module scans the display screen in different partitions;

[0054] Different refresh frequencies are output to the multiple subareas of the display screen respectively, so as to optimize the display quality of the display screen.

[0055] In conjunction with the method for fast switching between forward and reverse scanning described in the second aspect of the present invention, in a first possible implementation manner, the step of controlling the GOA driver module to perform partition scanning on the display screen includes:

[0056] After the forward scan of the current partition is completed, the level signal of the forward scan signal end of the GOA driving module of the last row of the current partition is controlled to be converted from high level to low level;

[0057] Control the level signal of the reverse scan signal end of the GOA driving module of the last row of the current partition, converting it from low level to high level;

[0058] For the Gth n OK, G n-1Rows G1, …, G1 are scanned in reverse order.

[0059] The GOA cascade circuit and method for fast forward and reverse scanning described in the present invention detects the scanned row pixels to obtain their charging status, and performs secondary charging on the insufficiently charged display partitions and reverse scans them row by row, thereby achieving different refresh frequencies in different areas of the same display screen, increasing the flexibility of image restoration, and improving display quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0060] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0061] Figure 1 This is a schematic diagram of the GOA cascade circuit module connection;

[0062] Figure 2 This is a schematic diagram of the GOA driver module cascade;

[0063] Figure 3 This is the GOA driver module connection diagram;

[0064] Figure 4 Display a partition diagram for the display screen;

[0065] Figure 5 This is a schematic diagram of the GOA driver module circuit connection;

[0066] Figure 6 This is a schematic diagram of the driving timing of each signal end of the GOA driver module in forward and reverse scanning;

[0067] Figure 7 This is a schematic diagram of the forward and reverse scan output drive timing of the GOA driver module;

[0068] Figure 8 This is the first schematic diagram of the method for quickly switching between forward and reverse scanning;

[0069] Figure 9 This is the second schematic diagram of the forward and reverse scanning fast switching method; DETAILED DESCRIPTION

[0070] The following will clearly and completely describe the technical solutions of the present invention in conjunction with the accompanying drawings. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, other embodiments obtained by ordinary technicians in this field without creative work are all within the scope of protection of the present invention.

[0071] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this invention pertains. The terms used in this specification of the present invention are for the purpose of describing specific embodiments only and are not intended to limit the present invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0072] It should be noted that when an element is referred to as being “fixed on” or “disposed on” another element, it may be directly on the other element or indirectly on the other element. When an element is referred to as being “connected to” another element, it may be directly connected to the other element or indirectly connected to the other element.

[0073] It should be understood that the terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on this application.

[0074] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. Throughout the description of this application, "plurality" means two or more, unless otherwise specifically defined.

[0075] Circuit Example

[0076] Existing display screens cannot switch flexibly when performing secondary repairs on the screen, which takes a long time and reduces the display quality.

[0077] In order to solve the above problems, the present application proposes a GOA cascade circuit with fast switching between forward and reverse scanning.

[0078] A GOA cascade circuit with fast switching of forward and reverse scanning, such as Figure 1 , Figure 1This is a schematic diagram of the connection of the GOA cascade circuit module; it includes a control module 100, a detection module 200 and a GOA driver module 300; the control module 100 is electrically connected to one end of the detection module 200 and one end of the GOA driver module 300 respectively; the other end of the detection module 200 is electrically connected to the row pixel TFT; the other end of the GOA driver module 300 is electrically connected to the row pixel TFT; the detection module 200 is used to detect the charge amount of the row pixel TFT of the current display partition; the GOA driver module 300 is cascaded row by row to perform partition scanning on the display screen respectively; the control module 100 is used to control the GOA driver module 300 to perform partition scanning on the display screen; partition scanning is: the GOA driver module 300 outputs different refresh frequencies to multiple partitions of the display screen respectively to optimize the display quality of the display screen.

[0079] The GOA driver modules 300 (SN1 to SN6) are cascaded row by row, such as Figure 2 , Figure 2 : is a schematic diagram of the cascade connection of the GOA driving modules 300. The number of GOA driving modules 300 corresponds to the number of rows, so there can be n of them, forming a GOA cascade circuit of the display screen to scan the display screen row by row.

[0080] The detection module 200 is used to obtain the row pixel TFT charge information of the current partition and transmit it to the control module 100 for algorithm comparison. For display partitions with a charge less than a specified value, secondary charging is required for backscanning to improve the display quality of the partition, achieve different refresh frequencies for different partitions of the display screen, and improve the flexibility of picture repair.

[0081] Example 1

[0082] In this embodiment, the GOA driving module 300 can be implemented as follows: Figure 3 , Figure 3 This is a schematic diagram of the GOA driver module 300 module connection; it includes a startup unit 310, an output unit 320, and a pull-down unit 330; the startup unit 310 is electrically connected to the output unit 320 and the pull-down unit 330, respectively, and is used to drive the main transistor of the output unit 320 to turn on to output a gate drive signal; the pull-down unit 330 is used to keep the input end of the output unit 320 at a low level during the pull-down stage to prevent the main transistor from malfunctioning.

[0083] Specifically, such as Figure 5 , Figure 5 Schematic diagram of the circuit connection of the GOA driving module 300; the starting unit 310 includes: a clock signal terminal CK, a start signal terminal STV, a forward scan signal terminal FW, a reverse scan signal terminal BW, a set signal terminal RST, a first transistor T1, and a second transistor T2.

[0084] The output unit 320 includes a main transistor T11 and a capacitor C.

[0085] The pull-down unit 330 includes: a DC signal terminal VDD, a low level input terminal VGL, a pull-up level input terminal GLV, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, and a tenth transistor T10.

[0086] The clock signal terminal CK is electrically connected to the main transistor T11.

[0087] The start signal terminal STV is electrically connected to the gate of the first transistor T1 .

[0088] The positive scan signal terminal FW is electrically connected to the drain of the first transistor T1.

[0089] The reverse scan signal terminal BW is electrically connected to the source of the second transistor T2.

[0090] The set signal terminal RST is electrically connected to the gate of the second transistor T2.

[0091] The gate of the third transistor T3 , the drain of the third transistor T3 , and the drain of the fourth transistor T4 are electrically connected to the DC signal terminal VDD.

[0092] The drain of the fifth transistor T5 , the drain of the sixth transistor T6 , the drain of the seventh transistor T7 , the drain of the eighth transistor T8 , the drain of the ninth transistor T9 , and the drain of the tenth transistor T10 are connected in common and electrically connected to the low level input terminal VGL.

[0093] The gate of the ninth transistor T9 and the gate of the tenth transistor T10 are commonly connected to the pull-up level input terminal GLV.

[0094] The source of the first transistor T1, the drain of the second transistor T2, the gate of the fifth transistor T5, the gate of the sixth transistor T6, the source of the seventh transistor T7, the source of the ninth transistor T9, the gate of the main transistor T11, and the first end of the capacitor C are connected to point P.

[0095] The source of the third transistor T3 , the gate of the fourth transistor T4 , and the source of the fifth transistor T5 are connected in common.

[0096] The source of the fourth transistor T4 , the source of the sixth transistor T6 , the gate of the seventh transistor T7 , and the gate of the eighth transistor T8 are connected to point A in common.

[0097] The source of the main transistor T11 , the second end of the capacitor C, the source of the eighth transistor T8 , and the source of the tenth transistor T10 are commonly connected to the output terminal Gout.

[0098] In the forward scan stage, the forward scan signal terminal FW is at a high level, the reverse scan BW is at a low level, and the high-level pulse signal of the start signal terminal STV turns on the first transistor T1, and the P point becomes a high level. The clock signal terminal CK signal changes from a low level to a high level, causing the P point to be boosted twice, and the main transistor T11 is fully turned on, so that the output terminal Gout outputs a high-level pulse with the same phase as CK, completing the gate drive output of the current row.

[0099] The pull-up level input terminal GLV is pulled high only in the front and back porch stages, turning on the ninth transistor T9, pulling down point P, and turning on the tenth transistor T10, pulling down the output terminal Gout, performing a discharge action, and the output terminal Gout is at a low level in the display stage.

[0100] In the pull-down stage, the DC signal terminal VDD is normally at a high level, the third transistor T3 and the fourth transistor T4 are turned on, and the common node A is at a high level, thereby turning on the seventh transistor T7 and the eighth transistor T8. The low-level input terminal VGL passes through the seventh transistor T7 and the eighth transistor T8 to pull down the common point P and the output terminal Gout.

[0101] At the same time, the output terminal Gout of the next stage Gn+1 is connected to the gate of the second transistor T2, so that the second transistor T2 is turned on. At this time, the low-level signal of the reverse scan signal terminal BW pulls down the common contact point P again to prevent the current stage Gout from malfunctioning.

[0102] During the forward scanning process, the detection module 200 obtains the charging status of the current scanning area. If the charging levels of the row pixel TFTs in all display areas are normal, the process continues until the scanning of the current frame image is completed.

[0103] Example 2

[0104] In this embodiment, different from the first embodiment, the detection module 200 obtains the GOA driving module 300 information of the last row Gn and the first row G1 of the current partition after the charge amount of the row pixel TFT of the current partition is less than the specified value.

[0105] Since the charge amount of the row pixel TFT of the current display partition is less than the specified value, the current display partition needs to be scanned and charged for the second time, which is the Backward stage.

[0106] Control the GOA driver module 300 to perform partition scanning on the display screen. In the Backward phase, the principle is as follows:

[0107] After the forward scan of the current partition is completed, the level signal of the forward scan signal terminal of the GOA driving module 300 of the last row of the current partition is controlled to be converted from a high level to a low level;

[0108] Control the level signal of the reverse scan signal terminal of the GOA driving module 300 of the last row of the current partition, converting it from low level to high level;

[0109] For the Gth n OK, G n-1 Rows G1, …, G1 are scanned in reverse order.

[0110] After the current display partition is scanned, the forward scan is performed. The principle is as follows:

[0111] After the reverse scan of the current partition is completed, the level signal of the forward scan signal terminal of the first row GOA driving module 300 of the current partition is controlled to be converted from low level to high level;

[0112] Sequentially process the G1th row, G2th row, ..., Gth row of the current partition. n Scan forward.

[0113] After the current display partition is scanned twice, it is equivalent to doubling the refresh frequency of the current display partition, which is beneficial to improving the display quality.

[0114] Please refer to Figure 6 and Figure 7 , Figure 6 This is a schematic diagram of the driving timing of each signal end of the GOA driving module 300 for forward and reverse scanning. Figure 7 Schematic diagram of the forward and reverse scan output drive timing of the GOA driver module 300; when G8 outputs a high level, the forward scan signal terminal FW changes from a high level to a low level, and the reverse scan signal terminal BW changes from a low level to a high level, that is, at this time, the forward scan changes to the reverse scan, and the high level output by G8 turns on the second transistor T2 of the GOA driver module 300 in the seventh row, and the high level of the reverse scan signal terminal BW causes the P point of the GOA driver module 300 in the current seventh row to become a high level. The same circuit working principle, G7 outputs a high level, and it can be concluded from the cascade relationship that after G7, G6 outputs a high level, until G1 outputs a high level pulse, the forward scan signal terminal FW changes from a low level to a high level, the reverse scan signal terminal BW changes from a high level to a low level, and the forward scan drive starts again, that is, G1, G2, ..., Gn scans are performed in sequence.

[0115] If the TFT of the row pixels in the display partition is insufficiently charged, it can be reversed for secondary charging, which optimizes the display effect. In addition, it can also achieve the effect of different refresh rates in different areas of the same screen. Figure 4 , Figure 4 This is a schematic diagram of the display partitions. If the current display partition A2 is scanned forward and then reversely scanned, the refresh rate of the A2 area can be twice that of the display partitions A1 and A3.

[0116] Example 3

[0117] Different from the embodiment 2, the reverse scanning of the current partition can also be specifically implemented as follows: when scanning in the reverse direction, the Gth partition is n The high level signal output by the row is used as the G n-1 The start signal of the row main transistor.

[0118] During the second forward scan, the G n-1 The high level signal output by the row is used as the G n The start signal of the row main transistor.

[0119] Method Example

[0120] A method for fast switching between forward and reverse scanning, such as Figure 8 , Figure 8 This is a first schematic diagram of a method for fast switching between forward and reverse scanning; the cascade circuit of the first aspect is used, including the steps of:

[0121] The GOA driving module 300 scans the display screen in different zones respectively;

[0122] Different refresh rates are output to multiple partitions of the display screen to optimize the display quality of the display screen.

[0123] In this embodiment, the control GOA driving module 300 performs partition scanning on the display screen, such as Figure 9 , Figure 9 This is a second schematic diagram of a method for fast switching between forward and reverse scanning, specifically including:

[0124] After the forward scan of the current partition is completed, the level signal of the forward scan signal terminal of the GOA driving module 300 of the last row of the current partition is controlled to be converted from a high level to a low level;

[0125] Control the level signal of the reverse scan signal terminal of the GOA driving module 300 of the last row of the current partition, converting it from low level to high level;

[0126] For the Gth n OK, G n-1 Rows G1, …, G1 are scanned in reverse order.

[0127] The present invention implements a GOA cascade circuit and method for fast switching between forward and reverse scanning, detects scanned row pixels, obtains their charging status, and performs secondary charging on insufficiently charged display partitions and reverse scanning row by row, thereby achieving different refresh frequencies in different areas of the same display screen, increasing the flexibility of image restoration, and improving display quality.

[0128] The above are only preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A GOA cascade circuit with fast switching between forward and reverse scanning, characterized in that: include: Control module; Detection module; GOA driver module; The control module is electrically connected to one end of the detection module and one end of the GOA driving module respectively; The other end of the detection module is electrically connected to the row pixel TFT; The other end of the GOA driving module is electrically connected to the row pixel TFT; The detection module is used to detect the charge amount of the row pixel TFT of the current display partition; The GOA driving modules are cascaded row by row to perform partition scanning on the display screen respectively; The control module is used to control the GOA driving module to perform partition scanning on the display screen; The partition scan is: The GOA driving module outputs different refresh frequencies to multiple partitions of the display screen respectively to optimize the display quality of the display screen; The detection module is also used to obtain the GOA driving module information of the last row Gn and the first row G1 of the current partition after the TFT charge amount of the row pixels of the current partition is less than the specified value; The controlling the GOA driving module to perform partition scanning on the display screen includes: After the forward scan of the current partition is completed, the level signal of the forward scan signal end of the GOA driving module of the last row of the current partition is controlled to be converted from high level to low level; Control the level signal of the reverse scan signal end of the GOA driving module of the last row of the current partition, converting it from low level to high level; For the Gth n OK, G n-1 Rows G1, …, G1 are scanned in reverse order.

2. The GOA cascade circuit with fast forward and reverse scanning switching according to claim 1, characterized in that: The GOA driver module includes: Start unit; Output unit; Pull-down unit; The startup unit is electrically connected to the output unit and the pull-down unit respectively, and is used to drive the main transistor of the output unit to turn on to output a gate driving signal; The pull-down unit is also electrically connected to the output unit and is used to keep the input terminal of the output unit at a low level during the pull-down stage to prevent the main transistor from malfunctioning.

3. The GOA cascade circuit with fast forward and reverse scanning switching according to claim 2, characterized in that: The method further comprises: controlling the GOA driving module to perform partition scanning on the display screen; After the reverse scan of the current partition is completed, the level signal of the forward scan signal end of the GOA driving module of the first row of the current partition is controlled to be converted from low level to high level; Sequentially process the G1th row, G2th row, ..., Gth row of the current partition. n Scan forward.

4. The GOA cascade circuit with fast switching between forward and reverse scanning according to claim 2, characterized in that: The reverse scanning includes: The G n The high level signal output by the row is used as the G n-1 The start signal of the row main transistor.

5. The GOA cascade circuit with fast forward and reverse scanning switching according to claim 3, characterized in that: The forward scan includes: The G n-1 The high level signal output by the row is used as the G n The start signal of the row main transistor.

6. The GOA cascade circuit with fast switching of forward and reverse scanning according to any one of claims 2 to 5, characterized in that: The startup unit includes: a clock signal terminal, a startup signal terminal, a forward scan signal terminal, a reverse scan signal terminal, a set signal terminal, a first transistor, and a second transistor; The output unit includes: a main transistor and a capacitor; The pull-down unit includes: a DC signal terminal, a low level input terminal, a pull-up level input terminal, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, and a tenth transistor; The clock signal terminal is electrically connected to the main transistor; The start signal terminal is electrically connected to the gate of the first transistor; The positive scan signal terminal is electrically connected to the drain of the first transistor; The reverse scan signal terminal is electrically connected to the source of the second transistor; The set signal terminal is electrically connected to the gate of the second transistor; The gate of the third transistor, the drain of the third transistor, and the drain of the fourth transistor are electrically connected to each other and then electrically connected to the DC signal terminal; The drain of the fifth transistor, the drain of the sixth transistor, the drain of the seventh transistor, the drain of the eighth transistor, the drain of the ninth transistor, and the drain of the tenth transistor are connected in common and then electrically connected to the low-level input terminal; The gate of the ninth transistor and the gate of the tenth transistor are connected together and electrically connected to the pull-up level input terminal; The source of the first transistor, the drain of the second transistor, the gate of the fifth transistor, the gate of the sixth transistor, the source of the seventh transistor, the source of the ninth transistor, the gate of the main transistor, and the first end of the capacitor are connected to point P. The source of the third transistor, the gate of the fourth transistor, and the source of the fifth transistor are connected in common; The source of the fourth transistor, the source of the sixth transistor, the gate of the seventh transistor, and the gate of the eighth transistor are connected to point A; The source of the main transistor, the second end of the capacitor, the source of the eighth transistor, and the source of the tenth transistor are commonly connected to the output end.

7. A method for fast switching between forward and reverse scanning, using the cascade circuit according to any one of claims 1 to 6, characterized in that: Including steps: The GOA driver module performs partition scanning on the display screen; Outputting different refresh frequencies to the multiple partitions of the display screen respectively to optimize the display quality of the display screen; The GOA driver module performs partition scanning on the display screen, including: After the forward scan of the current partition is completed, the level signal of the forward scan signal end of the GOA driving module of the last row of the current partition is controlled to be converted from high level to low level; Control the level signal of the reverse scan signal end of the GOA driving module of the last row of the current partition, converting it from low level to high level; For the Gth n OK, G n-1 Rows G1, …, G1 are scanned in reverse order.

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