A method for fabricating a GaN-based HEMT low-resistivity gold-free ohmic contact electrode

Abstract

This invention discloses a method for fabricating low-resistance gold-free ohmic contact electrodes for GaN-based HEMTs, comprising the following steps: preparing a nanopattern master for the ohmic contact region; copying the master pattern onto a soft polymer film using thermal embossing to obtain an intermediate soft template; uniformly coating a layer of nanoimprint adhesive on the surface of the GaN-based wafer barrier layer; placing the intermediate soft template on the surface of the nanoimprint adhesive and transferring the nanopattern onto the nanoimprint adhesive using nanoimprint technology; removing residual nanoimprint adhesive at the bottom of the nanopattern using inductively coupled plasma (ICP) etching technology to expose the barrier layer; completely etching away the barrier layer using dry etching technology, etching down to below the two-dimensional electron gas to form a nanopore array; removing the remaining nanoimprint adhesive from the wafer surface; sequentially depositing multiple layers of gold-free ohmic metal in the source / drain regions and performing alloy annealing treatment at 500–700°C to form source / drain electrodes. This invention can effectively reduce ohmic contact resistance and improve the frequency characteristics of HEMT devices.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device fabrication technology, specifically relating to a method for fabricating a GaN-based HEMT low-resistivity gold-free ohmic contact electrode. Background Technology

[0002] Third-generation semiconductors, represented by gallium nitride (GaN), possess characteristics such as large bandgap, high breakdown field strength, and high mobility, leading to rapid development in high-power, high-frequency microwave, and optoelectronic fields, becoming a new research hotspot. With breakthroughs in GaN-based epitaxial technology, various GaN-based electronic devices have also begun to be researched and developed. Due to the spontaneous polarization and piezoelectric polarization effects of group III nitride materials, a high-density, high-electron-mobility two-dimensional electron gas is formed in undoped AlGaN / GaN heterojunctions. The high conductivity of the two-dimensional electron gas channel and the high breakdown voltage of GaN materials make GaN-based HEMT (High Electron Mobility Transistor) devices an important research direction for high-frequency, high-power devices. With the continuous development of 5G / 6G wireless communication technology, the demand for high-frequency performance of HEMTs in solid-state microwave RF devices used in base stations is becoming increasingly urgent, making it crucial to improve the high-frequency characteristics of these devices. In the fabrication of AlGaN / GaN HEMT devices, the source and drain metals need to form ohmic contacts with the two-dimensional electron gas in the AlGaN / GaN heterojunction. For GaN-based HEMT devices, reducing the ohmic contact resistance is one of the important ways to effectively improve the high-frequency characteristics of GaN-based HEMTs. In order to achieve both high two-dimensional electron gas and low scattering effect, both AlGaN and GaN must be undoped materials. However, AlGaN has a larger bandgap than GaN, making it more difficult to form ohmic contacts between the metal and the two-dimensional electron gas. Therefore, how to reduce the ohmic contact resistance of GaN-based HEMTs has become a widely studied topic in the industry.

[0003] Common methods for fabricating ohmic contacts in the industry include high-temperature alloying and selective regrowth (SGR) techniques. High-temperature alloying typically involves stacking four metal layers (Ti / Al / Ni / Au) on an AlGaN surface and then rapidly annealing them at 800–1000°C in a nitrogen atmosphere to form the ohmic contact. This method uses high annealing temperatures, which negatively impacts the surface morphology of the metal electrodes. Higher temperatures result in rougher surfaces, leading to uneven electric field distribution and affecting high-frequency characteristics. Furthermore, its ability to reduce ohmic contact resistance is limited; additionally, gold-doped ohmic contacts pose a risk of gold contamination. Selective regrowth (SGR) techniques first use dry etching to create the source / drain regrowth region pattern, and then use MOCVD or MBE to regrow a silicon-doped region with a silicon concentration of 10%. 20 cm -3The process involves first creating n+GaN, then covering it with Ti / Pt / Au electrodes to reduce ohmic contact resistance. While this method effectively reduces the contact resistance between the ohmic metal and the n+GaN semiconductor, it also introduces resistance at the interface between n+GaN and the two-dimensional electron gas (2D electron gas). Furthermore, MOCVD secondary epitaxial growth is typically performed at temperatures above 900°C, leading to barrier layer degradation and increased sheet resistance. MBE growth is slow, inefficient, and expensive. Therefore, this method presents complex manufacturing processes, significant technical bottlenecks, and high production costs. Currently, some researchers are using etching to reduce the distance between the ohmic contact and the 2D electron gas, even allowing the metal to directly contact the 2D electron gas, thereby reducing ohmic contact resistance. Literature reports that etching to a distance of 1–2 nm from the 2D electron gas channel is optimal; however, conventional dry etching precision is difficult to control, resulting in poor repeatability. Once etching below the 2D electron gas level, the 2D electron gas in the source / drain region is interrupted, and the ohmic contact resistance actually increases. Summary of the Invention

[0004] To address the shortcomings of existing technologies, the present invention aims to provide a method for fabricating a GaN-based HEMT low-resistance gold-free ohmic contact electrode, thereby reducing process difficulty, decreasing ohmic contact resistance, and improving device performance.

[0005] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0006] A method for fabricating a GaN-based HEMT low-resistivity gold-free ohmic contact electrode includes the following steps:

[0007] S1. Prepare a nano-pattern master for the ohmic contact area, and use hot embossing to copy the master pattern onto a soft polymer film to obtain an intermediate soft template;

[0008] S2. A layer of nanoimprint adhesive is uniformly coated on the surface of the GaN-based wafer barrier layer;

[0009] S3. Place the intermediate soft template on the surface of the nanoimprint adhesive and use nanoimprint technology to transfer the nano-pattern onto the nanoimprint adhesive.

[0010] S4. Inductively coupled plasma (ICP) etching technology is used to remove the residual nanoimprint adhesive at the bottom of the nanopattern, exposing the barrier layer;

[0011] S5. The barrier layer is completely etched away using dry etching technology, and etched down to below the two-dimensional electron gas to form a nanopore array;

[0012] S6. Remove any remaining nanoimprint adhesive from the wafer surface;

[0013] S7. Deposit multiple layers of gold-free ohmic metal sequentially in the source and drain regions, and perform alloy annealing treatment at 500-700℃ to form source and drain electrodes.

[0014] Furthermore, in step S1, the nanopatterns are either a circular array or a polygonal array.

[0015] Furthermore, in step S1, the sum of the areas of the nanopatterns accounts for 50-60% of the total area of ​​the ohmic contact region.

[0016] Furthermore, the pore size of the nanopores is 100–500 nm.

[0017] Furthermore, the thickness of the GaN-based wafer barrier layer is 5–20 nm, and the depth of the nanopores is 5–50 nm.

[0018] Furthermore, the material of the barrier layer is selected from one of AlGaN, InAlN, ScAlN, and AlN.

[0019] Furthermore, in step S5, the reaction gas used in the dry etching is a Cl2 / BCl3 mixed gas.

[0020] Furthermore, in step S7, the specific steps for sequentially depositing multiple layers of gold-free ohmic metal in the source and drain regions are as follows: first, fill the nanopore array with a first metal to form a first metal layer, and then deposit a second metal to form a second metal layer.

[0021] Furthermore, the first metal is selected from Ti or Ta, and the second metal is selected from one of Ti / Al, Ti / W, and Ta / Al.

[0022] Furthermore, in step S7, the annealing time for the alloy annealing treatment is 30s to 5min, and the atmosphere is high-purity nitrogen.

[0023] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0024] (1) The present invention forms a nano-aperture array by etching in the source and drain regions, which greatly increases the sidewall area of ​​the contact between the ohmic metal and the semiconductor. The nano-aperture array is etched below the two-dimensional electron gas, which will not cause the two-dimensional electron gas in the source and drain regions to be interrupted. The ohmic metal and the two-dimensional electron gas are in direct contact, which reduces the potential barrier and increases the probability of electron tunneling. Therefore, it can effectively reduce the ohmic contact resistance and improve the frequency characteristics of HEMT devices.

[0025] (2) The present invention uses nanoimprint technology to create nano-patterns. The intermediate soft template can be reused. Compared with electron beam exposure process, it has the advantages of high efficiency and low cost, and is suitable for large-scale production.

[0026] (3) The present invention uses gold-free ohmic contact electrodes, which can be compatible with CMOS process, avoid gold contamination, and improve reliability. Attached Figure Description

[0027] Figure 1 This is a schematic diagram of the structure of the GaN-based HEMT low-resistivity gold-free ohmic contact electrode prepared according to the present invention.

[0028] Figure 2 This is a schematic diagram of the process flow of the present invention.

[0029] Figure 3 This is a schematic diagram of a circular array of nanopatterns in an embodiment of the present invention.

[0030] Figure 4 This is a schematic diagram of a hexagonal array nanopattern in an embodiment of the present invention.

[0031] Figure 5 This is a schematic diagram of a cross-shaped array of nanopatterns in an embodiment of the present invention.

[0032] Figure 6 This is a schematic diagram of the structure of the GaN-based HEMT ohmic contact electrode in Comparative Examples 1 and 2.

[0033] Figure 7 The diagram shows the structure of the GaN-based HEMT ohmic contact electrode in Comparative Examples 3 and 4.

[0034] Example of attached figures: 1-substrate, 2-GaN layer, 3-barrier layer, 4-two-dimensional electron gas layer, 5-nanometer aperture array, 6-ohmic metal, 7-nanometer pattern master, 8-intermediate soft template, 9-nanometer imprinting adhesive. Detailed Implementation

[0035] The present invention will be further described in detail below with reference to specific embodiments, so that those skilled in the art can more clearly understand the present invention. The examples given are only for explaining the present invention and are not intended to limit the scope of the present invention. In the embodiments of the present invention, unless otherwise specified, all raw material components are commercially available products well known to those skilled in the art; unless specifically specified, the technical means used are all conventional means well known to those skilled in the art.

[0036] The structure of the GaN-based HEMT low-resistivity gold-free ohmic contact electrode prepared in this embodiment of the invention is as follows: Figure 1 As shown, the process flow adopted is as follows: Figure 2 As shown, the specific preparation method includes the following steps:

[0037] S1. Prepare a nano-pattern master for the ohmic contact area, and use hot embossing to copy the master pattern onto a soft polymer film to obtain an intermediate soft template;

[0038] S2. A layer of nanoimprint adhesive is uniformly coated on the surface of the GaN-based wafer barrier layer;

[0039] S3. Place the intermediate soft template on the surface of the nanoimprint adhesive and use nanoimprint technology to transfer the nano-pattern onto the nanoimprint adhesive.

[0040] S4. ICP etching technology is used to remove residual nanoimprint adhesive at the bottom of the nanopattern, exposing the barrier layer;

[0041] S5. The barrier layer is completely etched away using dry etching technology, and etched down to below the two-dimensional electron gas to form a nanopore array;

[0042] S6. Remove any remaining nanoimprint adhesive from the wafer surface;

[0043] S7. Deposit multiple layers of gold-free ohmic metal sequentially in the source and drain regions, and perform alloy annealing treatment at 500-700℃ to form source and drain electrodes.

[0044] In some preferred embodiments, in step S1, the nanopattern is a circular array or a polygonal array, and the nanopattern master is a concave template made of metallic nickel or silicon with a nanopore array.

[0045] In some preferred embodiments, in step S1, the sum of the areas of the nanopatterns accounts for 50-60% of the total area of ​​the ohmic contact region.

[0046] In some preferred embodiments, the nanopatterns are a circular array, and the diameter of the formed nanopores is 100–500 nm.

[0047] In some preferred embodiments, the nanopattern is a polygonal array, including quadrilateral arrays, hexagonal arrays, and cross-shaped arrays, and the pore size of the formed nanopores is 100-500 nm.

[0048] In some preferred embodiments, the thickness of the GaN-based wafer barrier layer is 5–20 nm, and the depth of the nanopores is 5–50 nm, wherein the nanopores need to penetrate the barrier layer.

[0049] In some preferred embodiments, the material of the barrier layer is selected from AlGaN, InAlN, ScAlN, and AlN.

[0050] In some preferred embodiments, in step S5, the reaction gas used in the dry etching is a Cl2 / BCl3 mixed gas.

[0051] In some preferred embodiments, in step S6, O2 Plasma dry method is first used to remove the resist, and then wet method is used to remove the resist to remove the remaining nanoimprint adhesive on the wafer surface.

[0052] In some preferred embodiments, in step S7, the specific steps of sequentially depositing multiple layers of gold-free ohmic metal in the source and drain regions are as follows: first, a first metal is used to fill the nanopore array to form a first metal layer, and then a second metal is deposited to form a second metal layer.

[0053] In some preferred embodiments, the first metal is selected from Ti or Ta, and the second metal is selected from Ti / Al, Ti / W, and Ta / Al.

[0054] In some preferred embodiments, in step S7, the annealing time of the alloy annealing treatment is 30s to 5min, and the atmosphere is high-purity nitrogen.

[0055] Example 1

[0056] The method for fabricating a GaN-based HEMT low-resistivity gold-free ohmic contact electrode provided in this embodiment includes the following steps:

[0057] S1. Prepare a nano-pattern master for the ohmic contact area, and use hot embossing to copy the master pattern onto a soft polymer film to obtain an intermediate soft template; the nano-pattern is... Figure 3 The circular array shown has a diameter of 100 nm, and the sum of the areas of the circular arrays accounts for 50% of the total area of ​​the ohmic contact region.

[0058] S2. A layer of nanoimprint adhesive is uniformly coated on the surface of the 20nm-AlGaN / 300nm-GaN-based wafer barrier layer;

[0059] S3. Place the intermediate soft template on the surface of the nanoimprint adhesive, and use nanoimprint technology to transfer the nano-pattern onto the nanoimprint adhesive by ultraviolet light irradiation.

[0060] S4. ICP etching technology is used to remove residual nanoimprint adhesive at the bottom of the nanopattern, exposing the barrier layer;

[0061] S5. Dry etching is performed using Cl2 / BCl3 gas to completely remove the barrier layer and etch it below the two-dimensional electron gas to form a nanopore array; the thickness of the barrier layer is 20nm and the etching depth is 30nm.

[0062] S6. First, use O2 Plasma dry method to remove the resist, and then use wet method to remove the resist to remove the remaining nano-imprinting adhesive on the wafer surface.

[0063] S7. Using electron beam evaporation, Ti is first used to fill the nanopore array in the source / drain region, then Ti / Al is deposited, and then alloy annealing is performed at 500℃ for 30s in a high-purity nitrogen atmosphere to form the source / drain electrodes.

[0064] Example 2

[0065] The method for fabricating a GaN-based HEMT low-resistivity gold-free ohmic contact electrode provided in this embodiment includes the following steps:

[0066] S1. Prepare a nano-pattern master for the ohmic contact area, and use hot embossing to copy the master pattern onto a soft polymer film to obtain an intermediate soft template; the nano-pattern is... Figure 4 The hexagonal array shown has a side length of 250 nm, and the sum of the areas of the hexagonal array accounts for 50% of the total area of ​​the ohmic contact region.

[0067] S2. A layer of nanoimprint adhesive is uniformly coated on the surface of the 20nm-AlGaN / 300nm-GaN-based wafer barrier layer;

[0068] S3. Place the intermediate soft template on the surface of the nanoimprint adhesive, and use nanoimprint technology to transfer the nano-pattern onto the nanoimprint adhesive by ultraviolet light irradiation.

[0069] S4. ICP etching technology is used to remove residual nanoimprint adhesive at the bottom of the nanopattern, exposing the barrier layer;

[0070] S5. Dry etching is performed using Cl2 / BCl3 gas to completely remove the barrier layer and etch it below the two-dimensional electron gas to form a nanopore array; the thickness of the barrier layer is 20nm and the etching depth is 40nm.

[0071] S6. First, use O2 Plasma dry method to remove the resist, and then use wet method to remove the resist to remove the remaining nano-imprinting adhesive on the wafer surface.

[0072] S7. Using electron beam evaporation, Ti is first used to fill the nanopore array in the source / drain region, then Ti / Al is deposited, and then alloy annealing is performed at 500℃ for 30s in a high-purity nitrogen atmosphere to form the source / drain electrodes.

[0073] Example 3

[0074] The method for fabricating a GaN-based HEMT low-resistivity gold-free ohmic contact electrode provided in this embodiment includes the following steps:

[0075] S1. Prepare a nano-pattern master for the ohmic contact area, and use hot embossing to copy the master pattern onto a soft polymer film to obtain an intermediate soft template; the nano-pattern is... Figure 5 The cross-shaped array shown has a cross-shaped aperture width of 100 nm and an aperture length of 400 nm. The sum of the areas of the cross-shaped array accounts for 50% of the total area of ​​the ohmic contact region.

[0076] S2. A layer of nanoimprint adhesive is uniformly coated on the surface of the 20nm-AlGaN / 300nm-GaN-based wafer barrier layer;

[0077] S3. Place the intermediate soft template on the surface of the nanoimprint adhesive, and use nanoimprint technology to transfer the nano-pattern onto the nanoimprint adhesive by ultraviolet light irradiation.

[0078] S4. ICP etching technology is used to remove residual nanoimprint adhesive at the bottom of the nanopattern, exposing the barrier layer;

[0079] S5. Dry etching is performed using Cl2 / BCl3 gas to completely remove the barrier layer and etch it below the two-dimensional electron gas to form a nanopore array; the thickness of the barrier layer is 20nm and the etching depth is 30nm.

[0080] S6. First, use O2 Plasma dry method to remove the resist, and then use wet method to remove the resist to remove the remaining nano-imprinting adhesive on the wafer surface.

[0081] S7. Using electron beam evaporation, Ti is first used to fill the nanopore array in the source / drain region, then Ti / Al is deposited, and then alloy annealing is performed at 500℃ for 30s in a high-purity nitrogen atmosphere to form the source / drain electrodes.

[0082] Example 4

[0083] The method for fabricating a GaN-based HEMT low-resistivity gold-free ohmic contact electrode provided in this embodiment includes the following steps:

[0084] S1. Prepare a nano-pattern master for the ohmic contact area, and use hot embossing to copy the master pattern onto a soft polymer film to obtain an intermediate soft template; the nano-pattern is... Figure 3 The circular array shown has a diameter of 300 nm, and the sum of the areas of the circular arrays accounts for 60% of the total area of ​​the ohmic contact region.

[0085] S2. A layer of nanoimprint adhesive is uniformly coated on the surface of the 5nm-AlN / 300nm-GaN-based wafer barrier layer;

[0086] S3. Place the intermediate soft template on the surface of the nanoimprint adhesive, and use nanoimprint technology to transfer the nano-pattern onto the nanoimprint adhesive by ultraviolet light irradiation.

[0087] S4. ICP etching technology is used to remove residual nanoimprint adhesive at the bottom of the nanopattern, exposing the barrier layer;

[0088] S5. Dry etching is performed using Cl2 / BCl3 gas to completely remove the barrier layer and etch it below the two-dimensional electron gas to form a nanopore array; the thickness of the barrier layer is 5nm and the etching depth is 20nm.

[0089] S6. First, use O2 Plasma dry method to remove the resist, and then use wet method to remove the resist to remove the remaining nano-imprinting adhesive on the wafer surface.

[0090] S7. Using electron beam evaporation, Ti is first used to fill the nanopore array in the source / drain region, then Ti / W is deposited, and then alloy annealing is performed at 700℃ for 3 minutes in a high-purity nitrogen atmosphere to form the source / drain electrodes.

[0091] Example 5

[0092] The method for fabricating a GaN-based HEMT low-resistivity gold-free ohmic contact electrode provided in this embodiment includes the following steps:

[0093] S1. Prepare a nano-pattern master for the ohmic contact area, and use hot embossing to copy the master pattern onto a soft polymer film to obtain an intermediate soft template; the nano-pattern is... Figure 3 The circular array shown has a diameter of 100 nm, and the sum of the areas of the circular arrays accounts for 60% of the total area of ​​the ohmic contact region.

[0094] S2. A layer of nanoimprint adhesive is uniformly coated on the surface of the 5nm-AlN / 300nm-GaN-based wafer barrier layer;

[0095] S3. Place the intermediate soft template on the surface of the nanoimprint adhesive, and use nanoimprint technology to transfer the nano-pattern onto the nanoimprint adhesive by ultraviolet light irradiation.

[0096] S4. ICP etching technology is used to remove residual nanoimprint adhesive at the bottom of the nanopattern, exposing the barrier layer;

[0097] S5. Dry etching is performed using Cl2 / BCl3 gas to completely remove the barrier layer and etch it below the two-dimensional electron gas to form a nanopore array; the thickness of the barrier layer is 5nm and the etching depth is 10nm.

[0098] S6. First, use O2 Plasma dry method to remove the resist, and then use wet method to remove the resist to remove the remaining nano-imprinting adhesive on the wafer surface.

[0099] S7. Using electron beam evaporation, the source / drain region is first filled with a nanopore array of Ta, then Ta / Al is deposited, and then alloy annealing is performed at 600℃ for 5 minutes in a high-purity nitrogen atmosphere to form the source / drain electrodes.

[0100] Comparative Example 1

[0101] The GaN-based HEMT ohmic contact electrode structure provided in this comparative example is as follows: Figure 6 As shown, Ti / Al is stacked on the source / drain region of the 20nm-AlGaN / 300nm-GaN-based wafer barrier layer using traditional high-temperature alloying technology to form source / drain electrodes.

[0102] Comparative Example 2

[0103] The GaN-based HEMT ohmic contact electrode structure provided in this comparative example is as follows: Figure 6 As shown, Ti / W is stacked on the source / drain region of the 5nm-AlN / 300nm-GaN-based wafer barrier layer using traditional high-temperature alloying technology to form source / drain electrodes.

[0104] Comparative Example 3

[0105] The GaN-based HEMT ohmic contact electrode structure provided in this comparative example is as follows: Figure 7 As shown, the difference from Example 1 is that the etching depth of the nanopore array is 15 nm.

[0106] Comparative Example 4

[0107] The GaN-based HEMT ohmic contact electrode structure provided in this comparative example is as follows: Figure 7 As shown, the difference from Example 4 is that the etching depth of the nanopore array is 3 nm.

[0108] The ohmic contact electrode resistance Rc of the embodiments and comparative examples was tested, and the test results are shown in Table 1. The preparation method provided by the embodiments of the present invention can greatly improve the ohmic contact resistance. In particular, when the barrier layer is AlN with a high aluminum content, the higher the Al content, the more obvious the improvement effect.

[0109] Table 1. Ohmic contact resistance test results

[0110] Example Ohmic contact resistance Example 1 0.17Ω·mm Example 2 0.20Ω·mm Example 3 0.18Ω·mm Example 4 0.25Ω·mm Example 5 0.26Ω·mm Comparative Example 1 0.30Ω·mm Comparative Example 2 0.50Ω·mm Comparative Example 3 0.24Ω·mm Comparative Example 4 0.37Ω·mm

[0111] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for fabricating a GaN-based HEMT low-resistivity gold-free ohmic contact electrode, characterized in that, Includes the following steps: S1. Prepare a nano-pattern master for the ohmic contact area, and use hot embossing to copy the master pattern onto a soft polymer film to obtain an intermediate soft template; S2. A layer of nanoimprint adhesive is uniformly coated on the surface of the GaN-based wafer barrier layer; S3. Place the intermediate soft template on the surface of the nanoimprint adhesive and use nanoimprint technology to transfer the nano-pattern onto the nanoimprint adhesive. S4. ICP etching technology is used to remove residual nanoimprint adhesive at the bottom of the nanopattern, exposing the barrier layer; S5. The barrier layer is completely etched away using dry etching technology, and etched down to below the two-dimensional electron gas to form a nanopore array; S6. Remove any remaining nanoimprint adhesive from the wafer surface; S7. Deposit multiple layers of gold-free ohmic metal sequentially in the source and drain regions, and perform alloy annealing treatment at 500-700℃ to form source and drain electrodes.

2. The preparation method according to claim 1, characterized in that, In step S1, the nanopatterns are either a circular array or a polygonal array.

3. The preparation method according to claim 1, characterized in that, In step S1, the sum of the areas of the nanopatterns accounts for 50-60% of the total area of ​​the ohmic contact region.

4. The preparation method according to claim 1, characterized in that, The pore size of the nanopores is 100–500 nm.

5. The preparation method according to claim 1, characterized in that, The thickness of the GaN-based wafer barrier layer is 5–20 nm, and the depth of the nanopores is 5–50 nm.

6. The preparation method according to claim 1, characterized in that, The material of the barrier layer is selected from AlGaN, AlN, InAlN, ScAlN, and AlN.

7. The preparation method according to claim 1, characterized in that, In step S5, the reaction gas used in the dry etching is a Cl2 / BCl3 mixed gas.

8. The preparation method according to claim 1, characterized in that, In step S7, the specific steps for sequentially depositing multiple layers of gold-free ohmic metal in the source and drain regions are as follows: first, fill the nanopore array with a first metal to form a first metal layer, and then deposit a second metal to form a second metal layer.

9. The preparation method according to claim 8, characterized in that, The first metal is selected from Ti or Ta, and the second metal is selected from one of Ti / Al, Ti / W, and Ta / Al.

10. The preparation method according to claim 1, characterized in that, In step S7, the annealing time for the alloy annealing treatment is 30s to 5min, and the atmosphere is high-purity nitrogen.

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