A method for manufacturing a semiconductor structure and a semiconductor structure

Abstract

The application provides a preparation method of a semiconductor structure and the semiconductor structure. The preparation method comprises the following steps: sequentially stacking at least one layer on a virtual substrate layer, each layer being a low-temperature epitaxial layer and a high-temperature epitaxial layer formed by using a high-low temperature epitaxial growth process, and releasing strain through the low-temperature epitaxial layer, so that most dislocations and defects in a germanium-containing or / and silicon-containing material are limited in the low-temperature epitaxial layer. By using the characteristics that the thermal expansion coefficients of the germanium-containing or / and silicon-containing material are different due to temperature change in the high-low temperature growth process, a tensile-strained layer is prepared. By using the etching selectivity of the low-temperature epitaxial layer and the high-temperature epitaxial layer, the low-temperature epitaxial layer containing poor dislocation quality is selectively etched, a tensile-strained high-temperature epitaxial layer supported by a support structure is obtained, and the formed tensile-strained high-temperature epitaxial layer has the advantage of higher carrier mobility, which is beneficial to the preparation of a high-carrier-mobility light-emitting device and a MOS device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for preparing a semiconductor structure and the semiconductor structure thereof. Background Technology

[0002] In the semiconductor field, for the vast majority of transistors and their integrated circuits, high mobility means a reduced carrier transit time to the base region, which can effectively improve their operating frequency, speed, and amplification performance. Currently, conventional Ge (germanium) structures are usually compressive strained or relaxed structures, which can only be used to fabricate PMOS devices and are not suitable for NMOS devices, thus limiting their application scenarios. Summary of the Invention

[0003] This invention provides a method for fabricating a semiconductor structure and the semiconductor structure itself, to form a tensile-strained semiconductor structure containing germanium and / or silicon materials. This not only improves the carrier mobility of the semiconductor structure, but also allows it to be applied to the fabrication of devices such as, but not limited to, PMOS and NMOS devices, expanding the range of applications and improving the adaptability of the semiconductor structure.

[0004] In a first aspect, the present invention provides a method for fabricating a semiconductor structure, the method comprising: providing a substrate; forming a virtual substrate layer on the substrate; sequentially stacking at least one layer on the virtual substrate layer, wherein forming each layer comprises: firstly growing a low-temperature epitaxial layer at low temperature, and then growing a high-temperature epitaxial layer at high temperature, wherein the materials of the low-temperature epitaxial layer and the high-temperature epitaxial layer are both germanium-containing and / or silicon-containing materials; selectively etching away a portion of the low-temperature epitaxial layer in each layer according to the different etching selectivity ratios of the low-temperature epitaxial layer and the high-temperature epitaxial layer in each layer, and retaining the remaining portion of the low-temperature epitaxial layer in each layer as a support structure.

[0005] In the above scheme, at least one stack is first formed sequentially on a virtual substrate layer, and each stack consists of a low-temperature epitaxial layer and a high-temperature epitaxial layer formed sequentially using high and low temperature epitaxial growth processes. The strain is released through the low-temperature epitaxial layer, so that most of the dislocations and defects in the germanium-containing and / or silicon-containing materials are confined in the low-temperature epitaxial layer. Furthermore, by utilizing the characteristic that the thermal expansion coefficients of germanium-containing and / or silicon-containing materials expand and contract differently due to temperature changes during high and low temperature growth, tensile strain stacks can be prepared. Then, by utilizing the different etching selectivity ratios of the low-temperature epitaxial layer and the high-temperature epitaxial layer, the portion of the low-temperature epitaxial layer with poor dislocation-accommodating quality in each stack is selectively etched away, resulting in a tensile strain high-temperature epitaxial layer supported by a support structure. Furthermore, the method utilizes the characteristic that the light hole band shifts upward under tensile strain on germanium-containing materials, further enhancing carrier mobility. This results in a high-temperature epitaxial layer supported by a support structure, exhibiting even higher carrier mobility. It can also be applied to the fabrication of devices such as, but not limited to, PMOS and NMOS devices, expanding its application scope and improving the adaptability of semiconductor structures. This facilitates the fabrication of high-carrier-mobility light-emitting devices and MOS devices in the future silicon photonics industry and the field of MOS devices (specifically, NMOS or PMOS devices). Moreover, the epitaxial growth methods used in the above methods are all non-selective epitaxial growth methods, avoiding the complex fabrication process of selective epitaxy, simplifying the fabrication process, and resulting in a semiconductor structure with a larger strain than mechanical strain, making the semiconductor structure easier to flatten.

[0006] In one specific embodiment, the growth temperature of the low-temperature epitaxial layer is 200℃ to 450℃, which enhances the effect of strain release through the low-temperature epitaxial layer, thereby confining more dislocations and defects in germanium-containing and / or silicon-containing materials within the low-temperature epitaxial layer. The growth temperature of the high-temperature epitaxial layer is 450℃ to 950℃, which increases the tensile strain effect of the formed high-temperature epitaxial layer, thereby forming a semiconductor structure with higher carrier mobility.

[0007] In one specific embodiment, the materials of the low-temperature epitaxial layer and the high-temperature epitaxial layer are germanium, silicon, or germanium-silicon. This enhances the effect of releasing strain through the low-temperature epitaxial layer, confining more dislocations and defects in the germanium-containing and / or silicon-containing materials within the low-temperature epitaxial layer. Simultaneously, it increases the tensile strain effect of the formed high-temperature epitaxial layer, thereby creating a semiconductor structure with higher carrier mobility. In a more preferred embodiment, both the high-temperature epitaxial layer and the low-temperature epitaxial layer are made of germanium, utilizing the superior carrier mobility characteristics of germanium compared to silicon (germanium's electron mobility is 2.6 times that of silicon, and its hole mobility is 4.2 times that of silicon), resulting in a semiconductor structure with even higher electron and hole mobility.

[0008] In one specific embodiment, forming a virtual substrate layer on the substrate includes: firstly, epitaxially growing a germanium low-temperature virtual substrate layer on the substrate at low temperature; then, epitaxially growing a germanium high-temperature virtual substrate layer on the germanium low-temperature virtual substrate layer at high temperature, forming a virtual substrate layer formed by stacking the germanium low-temperature virtual substrate layer and the germanium high-temperature virtual substrate layer. The germanium low-temperature virtual substrate layer is used to release strain, so that more dislocations and defects of the germanium material are confined in the germanium low-temperature virtual substrate layer, preventing dislocations and defects from extending upward into the stack grown by high and low temperature epitaxy.

[0009] In one specific embodiment, the fabrication method further includes: forming a GAAFET (Gate all around Field Effect Transistor) device in at least one stack to facilitate the fabrication of a GAAFET device with high carrier mobility.

[0010] In one specific embodiment, forming a GAAFET device in at least one stack includes: etching a high-temperature epitaxial layer in each stack to form nanowires or nanosheets that serve as channels for the GAAFET device, thereby making the nanowires or nanosheets of the GAAFET device high-quality tensile strain structures to serve as channels for the GAAFET device, thereby fabricating a GAAFET device with high-quality tensile strain and high carrier mobility.

[0011] In a second aspect, the present invention also provides a semiconductor structure comprising a substrate; a virtual substrate layer formed on the substrate; at least one high-temperature epitaxial layer formed on the virtual substrate layer, wherein the virtual substrate layer and the at least one high-temperature epitaxial layer are stacked sequentially on top of each other; adjacent virtual substrate layers and high-temperature epitaxial layers, or adjacent high-temperature epitaxial layers, are separated by a support structure formed by low-temperature epitaxy; and the materials of the high-temperature epitaxial layer and the support structure are both germanium-containing and / or silicon-containing materials.

[0012] In the above scheme, at least one stack is first formed sequentially on a virtual substrate layer, and each stack consists of a low-temperature epitaxial layer and a high-temperature epitaxial layer formed sequentially using high and low temperature epitaxial growth processes. The strain is released through the low-temperature epitaxial layer, so that most of the dislocations and defects in the germanium-containing and / or silicon-containing materials are confined in the low-temperature epitaxial layer. Furthermore, taking advantage of the characteristic that the thermal expansion coefficients of germanium-containing and / or silicon-containing materials are significantly different due to temperature changes during high and low temperature growth, tensile strain stacks can be prepared. Then, by utilizing the different etching selectivity of the low-temperature epitaxial layer and the high-temperature epitaxial layer, the portion of the low-temperature epitaxial layer with poor dislocation-accommodating quality in each stack is selectively etched away, resulting in a tensile strain high-temperature epitaxial layer supported by a support structure. Furthermore, by utilizing the characteristic that the light hole band shifts upward under tensile strain on germanium-containing materials, the carrier mobility is further enhanced. This results in a high-temperature epitaxial layer supported by a support structure, exhibiting even higher carrier mobility. Simultaneously, it can be applied to the fabrication of devices such as, but not limited to, PMOS and NMOS devices, expanding the application range and improving the adaptability of semiconductor structures. This is beneficial for the future fabrication of high-carrier-mobility light-emitting devices and MOS devices in the silicon photonics and MOS device fields. Moreover, the epitaxial growth methods used in the above fabrication methods are all non-selective epitaxial growth methods, avoiding the complex fabrication process of selective epitaxy, simplifying the fabrication process, and resulting in a semiconductor structure with a larger strain than mechanical strain, making the semiconductor structure easier to flatten.

[0013] In one specific embodiment, the materials of the low-temperature epitaxial layer and the high-temperature epitaxial layer are germanium, silicon, or germanium-silicon. This enhances the strain release effect through the low-temperature epitaxial layer, confining more dislocations and defects in the germanium-containing and / or silicon-containing materials within it, while simultaneously increasing the tensile strain effect of the formed high-temperature epitaxial layer, thereby creating a semiconductor structure with higher carrier mobility. In a more preferred embodiment, both the high-temperature epitaxial layer and the low-temperature epitaxial layer are made of germanium, utilizing the superior carrier mobility characteristics of germanium compared to silicon (germanium's electron mobility is 2.6 times that of silicon, and its hole mobility is 4.2 times that of silicon), resulting in a semiconductor structure with even higher electron and hole mobility.

[0014] In one specific embodiment, a GAAFET device is formed in at least one epitaxial layer and a support structure to facilitate the fabrication of a GAAFET device with high carrier mobility.

[0015] In one specific implementation, the channel of the GAAFET device is formed by etching the high-temperature epitaxial layer in each stack to form nanowires or nanosheets, thereby making the nanowires or nanosheets of the GAAFET device high-quality tensile strain structure, which serves as the channel of the GAAFET device, thus fabricating a GAAFET device with high-quality tensile strain and high carrier mobility. Attached Figure Description

[0016] Figure 1 A flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of the present invention;

[0017] Figure 2 This is a cross-sectional view of one step in a method for fabricating a semiconductor structure according to an embodiment of the present invention.

[0018] Figure 3 This is a cross-sectional view of another step in a method for fabricating a semiconductor structure according to an embodiment of the present invention;

[0019] Figure 4 This is a cross-sectional view of another step in a method for fabricating a semiconductor structure according to an embodiment of the present invention;

[0020] Figure 5 A three-dimensional structural schematic diagram of another step in a method for fabricating a semiconductor structure according to an embodiment of the present invention;

[0021] Figure 6 A three-dimensional structural schematic diagram of another step in a method for fabricating a semiconductor structure according to an embodiment of the present invention;

[0022] Figure 7 This is a three-dimensional structural schematic diagram of another step in a method for preparing a semiconductor structure according to an embodiment of the present invention.

[0023] Figure label:

[0024] 10-Substrate; 20-Virtual Substrate Layer; 21-Germanium Low-Temperature Virtual Substrate Layer; 22-Germanium High-Temperature Virtual Substrate Layer

[0025] 30-Layer stack; 31-Low-temperature epitaxial layer; 32-High-temperature epitaxial layer; 33-Support structure

[0026] 41-Nanowire 42-Nanosheet 43-Gate 44-Source 45-Drain 46-Conductive pillar Detailed Implementation

[0027] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0028] To facilitate understanding of the semiconductor structure fabrication method provided in the embodiments of the present invention, the application scenarios of the semiconductor structure fabrication method provided in the embodiments of the present invention will be described first. This fabrication method is applied to the fabrication of semiconductor structures such as, but not limited to, light-emitting devices and MOS devices. The fabrication method of the semiconductor structure will be described in detail below with reference to the accompanying drawings.

[0029] refer to Figures 1-4 The method for preparing the semiconductor structure provided in this embodiment of the invention includes:

[0030] S10: Provides a substrate 10;

[0031] S20: A virtual substrate layer 20 is formed on the substrate 10;

[0032] S30: At least one stack 30 is sequentially stacked on the virtual substrate layer 20; wherein, forming each stack 30 includes: firstly growing a low-temperature epitaxial layer 31 at low temperature, and then growing a high-temperature epitaxial layer 32 at high temperature, and the materials of the low-temperature epitaxial layer 31 and the high-temperature epitaxial layer 32 are both germanium-containing and / or silicon-containing materials.

[0033] S40: Based on the different etching selectivity ratios of the low-temperature epitaxial layer 31 and the high-temperature epitaxial layer 32 in each stack 30, a portion of the low-temperature epitaxial layer 31 in each stack 30 is selectively etched away, leaving the remaining portion of the low-temperature epitaxial layer 31 in each stack 30 as the support structure 33.

[0034] In the above scheme, at least one stack 30 is first formed sequentially on the virtual substrate layer 20, and each stack 30 consists of a low-temperature epitaxial layer 31 and a high-temperature epitaxial layer 32 formed sequentially using high and low temperature epitaxial growth processes. The strain is released through the low-temperature epitaxial layer 31, so that most of the dislocations and defects in the germanium-containing and / or silicon-containing materials are confined in the low-temperature epitaxial layer 31. Furthermore, taking advantage of the characteristic that the thermal expansion coefficients of germanium-containing and / or silicon-containing materials are different due to temperature changes during high and low temperature growth, tensile strain stack 30 can be prepared. Then, taking advantage of the different etching selectivity ratios of the low-temperature epitaxial layer 31 and the high-temperature epitaxial layer 32, the portion of the low-temperature epitaxial layer 31 with poor dislocation-accommodating quality in each stack 30 is selectively etched away, resulting in a tensile strain high-temperature epitaxial layer 32 supported by the support structure 33. Furthermore, the method utilizes the characteristic that the light hole band shifts upward under tensile strain on germanium-containing materials, further enhancing carrier mobility. This results in a high-temperature epitaxial layer 32 supported by the support structure 33, exhibiting even higher carrier mobility. It can also be applied to the fabrication of devices such as, but not limited to, PMOS and NMOS devices, expanding its application range and improving the adaptability of semiconductor structures. This facilitates the fabrication of high-carrier-mobility light-emitting devices and MOS devices in the future silicon photonics and MOS device fields. Moreover, the epitaxial growth methods used in the above methods are all non-selective epitaxial growth methods, avoiding the complex fabrication process of selective epitaxy, simplifying the fabrication process, and resulting in a semiconductor structure with a larger strain than mechanical strain, making the semiconductor structure easier to flatten. The following is a detailed description of each step with reference to the accompanying drawings.

[0035] First, refer to Figure 1 and Figure 2 A substrate 10 is provided, which may be a silicon substrate 10 formed of a material such as, but not limited to, silicon, as a carrier for setting other material layers and microelectronic devices.

[0036] Next, refer to Figure 1 and Figure 3 A virtual substrate layer 20 is formed on the substrate 10. Specifically, when forming the virtual substrate layer 20, pure germanium can be used to form the germanium virtual substrate layer 20, or other materials can be used to form other types of virtual substrate layers 20. When specifically forming the germanium virtual substrate layer 20, refer to... Figure 3First, a germanium low-temperature virtual substrate layer 21 can be epitaxially grown on the substrate 10 at a low temperature. Then, a germanium high-temperature virtual substrate layer 22 can be epitaxially grown on the germanium low-temperature virtual substrate layer 21 at a high temperature, forming a virtual substrate layer 20 composed of the germanium low-temperature virtual substrate layer 21 and the germanium high-temperature virtual substrate layer 22 stacked together. By using a two-step high-low temperature epitaxial growth method to sequentially form the low-temperature germanium virtual substrate layer 20 and the high-temperature germanium virtual substrate layer 20, the strain of the germanium low-temperature virtual substrate layer 21 can be released, allowing more dislocations and defects in the germanium material to be confined within the germanium low-temperature virtual substrate layer 21, preventing dislocations and defects from extending upwards into the high-low temperature epitaxially grown stack 30. It should be understood that the formation method of the virtual substrate layer 20 is not limited to the method shown above; other methods can also be used.

[0037] Next, continue to refer to Figure 1 and Figure 3 At least one stacked layer 30 is sequentially stacked on the virtual substrate layer 20. The formation of each stacked layer 30 specifically includes the following two steps: first, a low-temperature epitaxial layer 31 is grown at a low temperature, followed by a high-temperature epitaxial layer 32, wherein both the low-temperature epitaxial layer 31 and the high-temperature epitaxial layer 32 are made of germanium-containing and / or silicon-containing materials. Specifically, the number of stacked layers 30 can be any value of at least one, such as 1, 2, 3, 4, or 5. Figure 3 The number of stacks 30 shown is 2, but the number of stacks 30 is not limited to this. Figure 3 The two shown are for reference only; the specific number depends on the microelectronic device to be fabricated. Each stack 30 consists of a low-temperature epitaxial layer 31 and a high-temperature epitaxial layer 32 stacked on top of the low-temperature epitaxial layer 31. The low-temperature epitaxial layer 31 in the bottommost stack 30 is grown on a virtual substrate using a low-temperature epitaxial growth process. Between two adjacent stacks 30, the low-temperature epitaxial layer 31 in the upper stack 30 is grown on the high-temperature epitaxial layer 32 in the lower stack 30 using a low-temperature epitaxial growth process.

[0038] Furthermore, the materials of the low-temperature epitaxial layer 31 and the high-temperature epitaxial layer 32 in each stack 30 are germanium-containing and / or silicon-containing materials. Specifically, each low-temperature epitaxial layer 31 and high-temperature epitaxial layer 32 can be prepared using germanium-containing but silicon-free materials, or using silicon-containing but germanium-free materials, or even using materials containing both silicon and germanium. When determining the germanium-containing and / or silicon-containing materials, the materials of the low-temperature epitaxial layer 31 and the high-temperature epitaxial layer 32 can be germanium, silicon, or germanium-silicon, which improves the effect of releasing strain through the low-temperature epitaxial layer 31, confining more dislocations and defects in the germanium-containing and / or silicon-containing materials within the low-temperature epitaxial layer 31, while simultaneously increasing the tensile strain effect of the formed high-temperature epitaxial layer 32, thereby forming a semiconductor structure with higher carrier mobility. In a more preferred embodiment, both the high-temperature epitaxial layer 32 and the low-temperature epitaxial layer 31 can be made of germanium, taking advantage of the superior carrier mobility characteristics of germanium compared to silicon (the electron mobility of germanium is 2.6 times that of silicon, and the hole mobility of germanium is 4.2 times that of silicon), so that the formed semiconductor structure has higher electron mobility and hole mobility.

[0039] Specifically, when the low-temperature epitaxial layer 31 is grown using a low-temperature epitaxial growth process, the growth temperature can be any temperature value between 200℃ and 450℃, such as 200℃, 240℃, 280℃, 300℃, 320℃, 350℃, 380℃, 400℃, 420℃, and 450℃. This improves the effect of releasing strain through the low-temperature epitaxial layer 31, allowing more dislocations and defects in germanium-containing and / or silicon-containing materials to be confined within the low-temperature epitaxial layer 31. Specifically, when the high-temperature epitaxial layer 32 is grown using a high-temperature epitaxial growth process, the growth temperature can be any value between 450℃ and 950℃, such as 450℃, 480℃, 500℃, 520℃, 550℃, 580℃, 600℃, 620℃, 650℃, 680℃, 700℃, 720℃, 750℃, 780℃, 800℃, 820℃, 850℃, 880℃, 900℃, 920℃, and 950℃, to increase the tensile strain effect of the formed high-temperature epitaxial layer 32, thereby forming a semiconductor structure with higher carrier mobility.

[0040] Next, refer to Figure 1 and Figure 4Based on the different etching selectivity ratios of the low-temperature epitaxial layer 31 and the high-temperature epitaxial layer 32 in each stack 30, a portion of the low-temperature epitaxial layer 31 in each stack 30 is selectively etched away, leaving the remaining portion of the low-temperature epitaxial layer 31 in each stack 30 as a support structure 33. That is, through selective etching, a portion of the low-temperature epitaxial layer 31 located at the bottom of each stack 30 is removed, allowing the remaining portion of the low-temperature epitaxial layer 31 to form a support structure 33 to support the high-temperature epitaxial layer 32 in each stack 30, thereby preventing the high-temperature epitaxial layer 32 from collapsing after the low-temperature epitaxial layer 31 is removed. In selective etching, the location of the low-temperature epitaxial layer 31 to be etched can be determined first. Then, windows are opened from top to bottom of at least one stack 30. Taking advantage of the different etching selectivity ratios of the low-temperature epitaxial layer 31 and the high-temperature epitaxial layer 32 in each stack 30, a portion of the low-temperature epitaxial layer 31 in each stack 30 is selectively etched away. The remaining portion of the low-temperature epitaxial layer 31 in each stack 30 serves as a support structure 33 to support the high-temperature epitaxial layers 32 between different stacks 30, preventing structural collapse. Specifically, when selectively etching a portion of the low-temperature epitaxial layer 31 in each stack 30, a suitable etching solution can be selected based on the difference in etching selectivity ratios between the low-temperature epitaxial layer 31 and the high-temperature epitaxial layer 32. Then, a wet selective etching process is performed to remove a portion of the low-temperature epitaxial layer 31.

[0041] Compared to existing methods for fabricating germanium structures, the above method first sequentially stacks at least one layer 30 on a virtual substrate layer 20. Each layer 30 consists of a low-temperature epitaxial layer 31 and a high-temperature epitaxial layer 32, formed sequentially using high- and low-temperature epitaxial growth processes. The strain is released through the low-temperature epitaxial layer 31, confining most dislocations and defects in the germanium- or / and silicon-containing materials within it. Furthermore, utilizing the characteristic that the thermal expansion coefficients of germanium- or / and silicon-containing materials vary significantly due to temperature changes during high- and low-temperature growth, tensile-strained layers 30 can be fabricated. Then, by utilizing the different etching selectivity ratios of the low-temperature epitaxial layer 31 and the high-temperature epitaxial layer 32, the portion of the low-temperature epitaxial layer 31 with poor dislocation-accommodating quality in each layer 30 is selectively etched away, resulting in a tensile-strained high-temperature epitaxial layer 32 supported by a support structure 33. Furthermore, the method utilizes the characteristic that the light hole band shifts upward when germanium-containing materials are subjected to tensile strain, further enhancing carrier mobility. This results in a high-temperature epitaxial layer 32 supported by the support structure 33, exhibiting even higher carrier mobility. Simultaneously, it can be applied to the fabrication of devices such as, but not limited to, PMOS and NMOS devices, expanding the application range and improving the adaptability of semiconductor structures. This facilitates the fabrication of high-carrier-mobility light-emitting devices and MOS devices in the future silicon photonics and MOS device fields. Moreover, the epitaxial growth methods used in the above fabrication methods are all non-selective epitaxial growth methods, avoiding the complex fabrication process of selective epitaxy, simplifying the fabrication process, and resulting in a semiconductor structure with a larger strain than mechanical strain, making the semiconductor structure easier to flatten.

[0042] Additionally, refer to Figures 5-7 The fabrication method may further include: forming a GAAFET device in at least one stack 30, that is, using the virtual substrate layer 20 and the high-temperature epitaxial layer 32 shown above, forming a GAAFET device in at least one stack 30 by a fabrication process, so as to fabricate a GAAFET device with high carrier mobility.

[0043] Specifically, when forming a GAAFET device in at least one stack 30, a patterning etching process can be used to etch the high-temperature epitaxial layer 32 in each stack 30 to form nanowires 41 or nanosheets 42 serving as the channel of the GAAFET device. This results in the nanowires 41 or nanosheets 42 of the GAAFET device being high-quality tensile-strain structures, which serve as the channel of the GAAFET device, thereby fabricating a GAAFET device with high-quality tensile strain and high carrier mobility. In other words, the high-temperature epitaxial layer 32 in each stack 30 is used as the material layer for fabricating the nanowires 41 or nanosheets 42 of the channel of the GAAFET device, and a patterning etching process is used to etch the nanowires 41 or nanosheets 42 as the channel for fabricating the GAAFET device. Figure 5The image shows nanowires 41 etched onto each high-temperature epitaxial layer 32 to form GAAFET devices, such as... Figure 6 The image shows nanosheets 42 etched onto each high-temperature epitaxial layer 32 to form GAAFET devices. Figure 5 and Figure 6 In this process, a gate 43 of a GAAFET device is formed above the virtual substrate. The gate 43 is stacked on each nanowire 41 or nanosheet 42, dividing each nanowire 41 or nanosheet 42 into two segments. The gate 43 can be fabricated using any process capable of fabricating the gate 43 shown in existing or future technologies. (Reference) Figure 7 Furthermore, the source 44 and drain 45 of the GAAFET device can be fabricated on both sides of the gate 43, respectively. The specific method for fabricating the source 44 and drain 45 can employ any process capable of fabricating the source 44 and drain 45 shown in existing or future technologies. (Reference) Figure 7 Conductive pillars 46 can also be formed in the source 44 and drain 45 to facilitate interconnection between the source 44 and drain 45 and other devices.

[0044] It should be noted that the microelectronic device formed in at least one stack 30 is not limited to the GAAFET device shown above. In addition, other types of microelectronic devices can be formed in at least one stack 30. For example, light-emitting devices can be formed in the remaining at least one stack 30, and other types of MOS devices can also be formed.

[0045] The fabrication method described above involves first sequentially stacking at least one layer 30 on a virtual substrate layer 20. Each layer 30 consists of a low-temperature epitaxial layer 31 and a high-temperature epitaxial layer 32, formed sequentially using high- and low-temperature epitaxial growth processes. The low-temperature epitaxial layer 31 releases strain, confining most dislocations and defects in the germanium- or / and silicon-containing materials within it. Furthermore, by utilizing the characteristic that the thermal expansion coefficients of germanium- or / and silicon-containing materials vary significantly due to temperature changes during high- and low-temperature growth, tensile-strained layers 30 can be fabricated. Then, by utilizing the different etching selectivity ratios of the low-temperature epitaxial layer 31 and the high-temperature epitaxial layer 32, the portion of the low-temperature epitaxial layer 31 with poor dislocation-accommodating quality in each layer 30 is selectively etched away, resulting in a tensile-strained high-temperature epitaxial layer 32 supported by a support structure 33. Furthermore, the method utilizes the characteristic that the light hole band shifts upward when germanium-containing materials are subjected to tensile strain, further enhancing carrier mobility. This results in a high-temperature epitaxial layer 32 supported by the support structure 33, exhibiting even higher carrier mobility. Simultaneously, it can be applied to the fabrication of devices such as, but not limited to, PMOS and NMOS devices, expanding the application range and improving the adaptability of semiconductor structures. This facilitates the fabrication of high-carrier-mobility light-emitting devices and MOS devices in the future silicon photonics and MOS device fields. Moreover, the epitaxial growth methods used in the above fabrication methods are all non-selective epitaxial growth methods, avoiding the complex fabrication process of selective epitaxy, simplifying the fabrication process, and resulting in a semiconductor structure with a larger strain than mechanical strain, making the semiconductor structure easier to flatten.

[0046] In addition, embodiments of the present invention also provide a semiconductor structure, see reference. Figure 1 and Figure 4 The semiconductor structure includes a substrate 10; a virtual substrate layer 20 is formed on the substrate 10; at least one high-temperature epitaxial layer 32 is formed on the virtual substrate layer 20, and the virtual substrate layer 20 and the at least one high-temperature epitaxial layer 32 are stacked sequentially; adjacent virtual substrate layers 20 and high-temperature epitaxial layers 32, or adjacent high-temperature epitaxial layers 32, are separated by a support structure 33 formed by low-temperature epitaxy; and the materials of the high-temperature epitaxial layer 32 and the support structure 33 are both germanium-containing and / or silicon-containing materials.

[0047] In the above scheme, at least one stack 30 is first formed sequentially on the virtual substrate layer 20, and each stack 30 consists of a low-temperature epitaxial layer 31 and a high-temperature epitaxial layer 32 formed sequentially using high and low temperature epitaxial growth processes. The strain is released through the low-temperature epitaxial layer 31, so that most of the dislocations and defects in the germanium-containing and / or silicon-containing materials are confined in the low-temperature epitaxial layer 31. Furthermore, taking advantage of the characteristic that the thermal expansion coefficients of germanium-containing and / or silicon-containing materials are different due to temperature changes during high and low temperature growth, tensile strain stack 30 can be prepared. Then, taking advantage of the different etching selectivity ratios of the low-temperature epitaxial layer 31 and the high-temperature epitaxial layer 32, the portion of the low-temperature epitaxial layer 31 with poor dislocation-accommodating quality in each stack 30 is selectively etched away, resulting in a tensile strain high-temperature epitaxial layer 32 supported by the support structure 33. Furthermore, the upward shift of the light hole band in germanium-containing materials under tensile strain further enhances carrier mobility. This results in a high-temperature epitaxial layer 32 supported by the support structure 33, exhibiting even higher carrier mobility. It can also be applied to the fabrication of devices such as, but not limited to, PMOS and NMOS devices, expanding its application scope and improving the adaptability of semiconductor structures. This facilitates the fabrication of high-carrier-mobility light-emitting devices and MOS devices in the future silicon photonics and MOS device fields. Moreover, the epitaxial growth methods used in the above fabrication methods are all non-selective epitaxial growth methods, avoiding the complex fabrication process of selective epitaxy, simplifying the fabrication process, and resulting in a semiconductor structure with a larger strain than mechanical strain, making the semiconductor structure easier to flatten. The following section provides a detailed description of each of the above structures with reference to the accompanying drawings.

[0048] When setting up base 10, refer to Figure 4 The substrate 10 may be a silicon substrate 10 formed of materials such as, but not limited to, silicon, as a carrier for setting other material layers and microelectronic devices.

[0049] When forming the virtual substrate layer 20 on the substrate 10, pure germanium can be used to form the germanium virtual substrate layer 20, or other materials can be used to form other types of virtual substrate layers 20. For specific details on forming the germanium virtual substrate layer 20, refer to... Figure 4First, a germanium low-temperature virtual substrate layer 21 can be epitaxially grown on the substrate 10 at a low temperature. Then, a germanium high-temperature virtual substrate layer 22 can be epitaxially grown on the germanium low-temperature virtual substrate layer 21 at a high temperature, forming a virtual substrate layer 20 composed of the germanium low-temperature virtual substrate layer 21 and the germanium high-temperature virtual substrate layer 22 stacked together. By using a two-step high-low temperature epitaxial growth method to sequentially form the low-temperature germanium virtual substrate layer 20 and the high-temperature germanium virtual substrate layer 20, the strain of the germanium low-temperature virtual substrate layer 21 can be released, allowing more dislocations and defects in the germanium material to be confined within the germanium low-temperature virtual substrate layer 21, preventing dislocations and defects from extending upwards into the high-low temperature epitaxially grown stack 30. It should be understood that the formation method of the virtual substrate layer 20 is not limited to the method shown above; other methods can also be used.

[0050] refer to Figure 4 At least one high-temperature epitaxial layer 32 is formed on the virtual substrate layer 20, and the virtual substrate layer 20 and the at least one high-temperature epitaxial layer 32 are stacked one on top of the other in sequence; adjacent virtual substrate layers 20 and high-temperature epitaxial layers 32, or adjacent high-temperature epitaxial layers 32, are separated by a support structure 33 formed by low-temperature epitaxy; and the materials of the high-temperature epitaxial layer 32 and the support structure 33 are both germanium-containing and / or silicon-containing materials.

[0051] Specifically, when forming at least one high-temperature epitaxial layer 32 and support structure 33 as described above, refer to Figure 1 and Figure 3 First, at least one stacked layer 30 can be sequentially stacked on the virtual substrate layer 20. The formation of each stacked layer 30 specifically includes the following two steps: first, a low-temperature epitaxial layer 31 is grown at a low temperature, followed by a high-temperature epitaxial layer 32, wherein both the low-temperature epitaxial layer 31 and the high-temperature epitaxial layer 32 are made of germanium-containing and / or silicon-containing materials. Specifically, the number of stacked layers 30 can be any value of at least one, such as 1, 2, 3, 4, or 5. Figure 3 The number of stacks 30 shown is 2, but the number of stacks 30 is not limited to this. Figure 3 The two shown are for reference only; the specific number depends on the microelectronic device to be fabricated. Each stack 30 consists of a low-temperature epitaxial layer 31 and a high-temperature epitaxial layer 32 stacked on top of the low-temperature epitaxial layer 31. The low-temperature epitaxial layer 31 in the bottommost stack 30 is grown on a virtual substrate using a low-temperature epitaxial growth process. Between two adjacent stacks 30, the low-temperature epitaxial layer 31 in the upper stack 30 is grown on the high-temperature epitaxial layer 32 in the lower stack 30 using a low-temperature epitaxial growth process.

[0052] Furthermore, the materials of the low-temperature epitaxial layer 31 and the high-temperature epitaxial layer 32 in each stack 30 are germanium-containing and / or silicon-containing materials. Specifically, each low-temperature epitaxial layer 31 and high-temperature epitaxial layer 32 can be prepared using germanium-containing but silicon-free materials, or using silicon-containing but germanium-free materials, or even using materials containing both silicon and germanium. When determining the germanium-containing and / or silicon-containing materials, the materials of the low-temperature epitaxial layer 31 and the high-temperature epitaxial layer 32 can be germanium, silicon, or germanium-silicon, which improves the effect of releasing strain through the low-temperature epitaxial layer 31, confining more dislocations and defects in the germanium-containing and / or silicon-containing materials within the low-temperature epitaxial layer 31, while simultaneously increasing the tensile strain effect of the formed high-temperature epitaxial layer 32, thereby forming a semiconductor structure with higher carrier mobility. In a more preferred embodiment, both the high-temperature epitaxial layer 32 and the low-temperature epitaxial layer 31 can be made of germanium, taking advantage of the superior carrier mobility characteristics of germanium compared to silicon (the electron mobility of germanium is 2.6 times that of silicon, and the hole mobility of germanium is 4.2 times that of silicon), so that the formed semiconductor structure has higher electron mobility and hole mobility.

[0053] Specifically, when the low-temperature epitaxial layer 31 is grown using a low-temperature epitaxial growth process, the growth temperature can be any temperature value between 200℃ and 450℃, such as 200℃, 240℃, 280℃, 300℃, 320℃, 350℃, 380℃, 400℃, 420℃, and 450℃. This improves the effect of releasing strain through the low-temperature epitaxial layer 31, allowing more dislocations and defects in germanium-containing and / or silicon-containing materials to be confined within the low-temperature epitaxial layer 31. Specifically, when the high-temperature epitaxial layer 32 is grown using a high-temperature epitaxial growth process, the growth temperature can be any value between 450℃ and 950℃, such as 450℃, 480℃, 500℃, 520℃, 550℃, 580℃, 600℃, 620℃, 650℃, 680℃, 700℃, 720℃, 750℃, 780℃, 800℃, 820℃, 850℃, 880℃, 900℃, 920℃, and 950℃, to increase the tensile strain effect of the formed high-temperature epitaxial layer 32, thereby forming a semiconductor structure with higher carrier mobility.

[0054] Afterwards, refer to Figure 1 and Figure 4Based on the different etching selectivity ratios of the low-temperature epitaxial layer 31 and the high-temperature epitaxial layer 32 in each stack 30, a portion of the low-temperature epitaxial layer 31 in each stack 30 is selectively etched away, leaving the remaining portion of the low-temperature epitaxial layer 31 in each stack 30 as a support structure 33. That is, through selective etching, a portion of the low-temperature epitaxial layer 31 located at the bottom of each stack 30 is removed, allowing the remaining portion of the low-temperature epitaxial layer 31 to form a support structure 33 to support the high-temperature epitaxial layer 32 in each stack 30, thereby preventing the high-temperature epitaxial layer 32 from collapsing after the low-temperature epitaxial layer 31 is removed. In selective etching, the location of the low-temperature epitaxial layer 31 to be etched can be determined first. Then, windows are opened from top to bottom of at least one stack 30. Taking advantage of the different etching selectivity ratios of the low-temperature epitaxial layer 31 and the high-temperature epitaxial layer 32 in each stack 30, a portion of the low-temperature epitaxial layer 31 in each stack 30 is selectively etched away. The remaining portion of the low-temperature epitaxial layer 31 in each stack 30 serves as a support structure 33 to support the high-temperature epitaxial layers 32 between different stacks 30, preventing structural collapse. Specifically, when selectively etching a portion of the low-temperature epitaxial layer 31 in each stack 30, a suitable etching solution can be selected based on the difference in etching selectivity ratios between the low-temperature epitaxial layer 31 and the high-temperature epitaxial layer 32. Then, a wet selective etching process is performed to remove a portion of the low-temperature epitaxial layer 31.

[0055] refer to Figures 5-7 Furthermore, a GAAFET device can be formed in at least one epitaxial layer and support structure 33. Specifically, using the virtual substrate layer 20 and high-temperature epitaxial layer 32 shown above, a GAAFET device can be formed in at least one stack 30 through a fabrication process, thereby facilitating the fabrication of a GAAFET device with high carrier mobility. Specifically, when forming a GAAFET device in at least one stack 30, the high-temperature epitaxial layer 32 in each stack 30 can be used as the material layer for the nanowires 41 or nanosheets 42 of the channel in the GAAFET device. Through a pattern etching process, the nanowires 41 or nanosheets 42 are etched to serve as the channel for the GAAFET device, thus making the nanowires 41 or nanosheets 42 of the GAAFET device a high-quality tensile strain structure. Using this as the channel for the GAAFET device, a high-quality tensile strain and high carrier mobility GAAFET device can be fabricated. Figure 5 The image shows nanowires 41 etched onto each high-temperature epitaxial layer 32 to form GAAFET devices, such as... Figure 6 The image shows nanosheets 42 etched onto each high-temperature epitaxial layer 32 to form GAAFET devices. Figure 5 and Figure 6In this process, a gate 43 of a GAAFET device is formed above the virtual substrate. The gate 43 is stacked on each nanowire 41 or nanosheet 42, dividing each nanowire 41 or nanosheet 42 into two segments. The gate 43 can be fabricated using any process capable of fabricating the gate 43 shown in existing or future technologies. (Reference) Figure 7 Furthermore, the source 44 and drain 45 of the GAAFET device can be fabricated on both sides of the gate 43, respectively. The specific method for fabricating the source 44 and drain 45 can employ any process capable of fabricating the source 44 and drain 45 shown in existing or future technologies. (Reference) Figure 7 Conductive pillars 46 can also be formed in the source 44 and drain 45 to facilitate interconnection between the source 44 and drain 45 and other devices.

[0056] It should be noted that the microelectronic device formed in at least one stack 30 is not limited to the GAAFET device shown above. In addition, other types of microelectronic devices can be formed in at least one stack 30. For example, light-emitting devices can be formed in the remaining at least one stack 30, and other types of MOS devices can also be formed.

[0057] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: Provide a base; A virtual substrate layer is formed on the substrate; At least one stack is sequentially stacked on the virtual substrate layer; wherein, forming each stack includes: firstly, growing a low-temperature epitaxial layer at a low temperature, and then growing a high-temperature epitaxial layer at a high temperature, and the materials of the low-temperature epitaxial layer and the high-temperature epitaxial layer are both germanium-containing and / or silicon-containing materials; Based on the different etching selectivity ratios of low-temperature epitaxial layers and high-temperature epitaxial layers in each stack, a portion of the low-temperature epitaxial layers in each stack are selectively etched away, while the remaining portion of the low-temperature epitaxial layers in each stack is retained as a support structure. The growth temperature of the low-temperature epitaxial layer is 200℃~450℃; the growth temperature of the high-temperature epitaxial layer is 450℃~950℃.

2. The preparation method according to claim 1, characterized in that, The materials of the low-temperature epitaxial layer and the high-temperature epitaxial layer are germanium, silicon, or germanium-silicon.

3. The preparation method according to claim 1, characterized in that, The process of forming a virtual substrate layer on the substrate includes: First, a germanium low-temperature virtual substrate layer is epitaxially grown on the substrate at a low temperature. Subsequently, a high-temperature germanium virtual substrate layer is epitaxially grown on the germanium low-temperature virtual substrate layer to form a virtual substrate layer formed by stacking the germanium low-temperature virtual substrate layer and the germanium high-temperature virtual substrate layer.

4. The preparation method according to claim 1, characterized in that, Also includes: A GAAFET device is formed in the at least one stack.

5. The preparation method according to claim 4, characterized in that, The formation of the GAAFET device in the at least one stack includes: Etching the high-temperature epitaxial layer in each stack forms nanowires or nanosheets that serve as the channel for the GAAFET device.

6. A semiconductor structure, characterized in that, include: Base; A virtual substrate layer is formed on the substrate; At least one high-temperature epitaxial layer is formed on the virtual substrate layer, and the virtual substrate layer and the at least one high-temperature epitaxial layer are stacked sequentially on top of each other; adjacent virtual substrate layers and high-temperature epitaxial layers, or adjacent high-temperature epitaxial layers, are separated by a support structure formed by a low-temperature epitaxial layer; and the materials of the high-temperature epitaxial layer and the support structure are both germanium-containing and / or silicon-containing materials. The growth temperature of the low-temperature epitaxial layer is 200℃~450℃; the growth temperature of the high-temperature epitaxial layer is 450℃~950℃.

7. The semiconductor structure as described in claim 6, characterized in that, The materials of the low-temperature epitaxial layer and the high-temperature epitaxial layer are germanium, silicon, or germanium-silicon.

8. The semiconductor structure as described in claim 6, characterized in that, A GAAFET device is formed in the at least one epitaxial layer and the support structure.

9. The semiconductor structure as described in claim 8, characterized in that, The channel of the GAAFET device is formed by etching the high-temperature epitaxial layer in each stack to create nanowires or nanosheets.

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