A cascade inverter leakage current suppression and power balance modulation method and system

Abstract

The present invention provides a cascade inverter leakage current suppression and power balance modulation method and system, belonging to the technical field of cascade H-bridge inverter modulation. The present invention improves the carrier structure so that the H-bridge 1 carrier and the H-bridge 2 carrier appear alternately with the same period within any modulation range, thereby realizing power sharing under full modulation, and generating a pre-processing signal marking the module output; determining the parasitic capacitance voltage sum of the leakage current excitation source of the two H-bridge cascade inverters, listing all switch combinations whose output levels satisfy the parasitic capacitance voltage sum and are equal, and completing module output analysis for the combination; selecting the corresponding switch combination in combination with the pre-processing signal of power distribution, thereby realizing power sharing and leakage current suppression under full modulation. The present invention solves the problem of leakage current suppression and power balance of two H-bridge cascade inverters.

Description

Technical Field

[0001] The invention belongs to the technical field of cascade H-bridge inverter modulation, and in particular relates to a cascade inverter leakage current suppression and power balance modulation method and system. Background Art

[0002] Compared with traditional photovoltaic inverters, Cascaded H-Bridge (CHB) multi-level inverters have the advantages of low harmonic content, increased voltage level and capacity. CHB cascade inverters can save isolation transformers, and are widely popular for their small size and high efficiency. However, due to the lack of electrical isolation, photovoltaic modules will generate a common ground loop between the earth and the power grid, thereby generating leakage current. Leakage current will reduce the power quality and reliability of the system, affect the stable operation of the equipment, and even endanger personal safety. Therefore, both domestic and foreign countries have imposed relevant restrictions on photovoltaic safety standards.

[0003] At present, domestic and foreign scholars have conducted a lot of research on cascade inverters, and have achieved fruitful results in modulation, control, hardware improvement, etc. However, these studies only focus on the leakage current problem of CHB photovoltaic inverters, and each cascade module is equivalent to an ideal model. In actual engineering, due to the inconsistency of operating power and loss of each module, long-term operation will lead to large differences in the parameters of each module, and it cannot be regarded as an ideal model.

[0004] Power balancing between modules of the cascaded H-bridge is also one of the hot topics in CHB research. In recent years, scholars have proposed power balancing strategies based on modulation improvement, pulse cycling, and carrier freedom, which have made great breakthroughs in theory and practice. The loss and performance of CHB photovoltaic inverters are comprehensive during operation, so power balancing and leakage current suppression should be considered in a unified category. However, there is currently no relevant research on the comprehensive consideration of power balancing and leakage current. Summary of the invention

[0005] In view of the above-mentioned deficiencies in the prior art, the present invention provides a method and system for cascade inverter leakage current suppression and power balance modulation, which solves the problem of leakage current suppression and power balance of two H-bridge cascade inverters.

[0006] In order to achieve the above purpose, the technical solution adopted by the present invention is:

[0007] This solution provides a cascade inverter leakage current suppression and power balance modulation method, including the following steps:

[0008] S1. Using the improved carrier structure, the power of the two cascaded H bridges in any modulation range is evenly distributed, and a pre-processed signal indicating the module output is generated;

[0009] S2, converting the pre-processed signal of each marker module output into a parasitic capacitor voltage and a constant switch combination;

[0010] S3. Select a corresponding switch combination in combination with the pre-processed signal of power average distribution to achieve power sharing and leakage current suppression under full modulation.

[0011] Furthermore, the step S1 includes the following steps:

[0012] S101. Define the symmetrical triangular carrier with an amplitude of 1 as V tri , define the switching period as T s , define t z is the time t versus T s Find the remainder and define V z is a step function, when 0<t z <0.5T s Time V z =1, when 0.5T s <t z <T s Time V z =0, V z Negate, where t z =(t,T s );

[0013] S102: Obtain carrier V according to the parameters defined in step S101. C1 , Carrier V C2 , Carrier V C1b and carrier V C2b The representation of which is that the carrier V C1 and carrier V C2 In the modulation wave V m The positive half-cycle comparison phase appears alternately, and the waveform period is the same. The carrier V C1b and carrier V C2b It appears alternately in the comparison phase of the negative half cycle of the modulation wave with the same period;

[0014] S103, the modulation wave V m Respectively with carrier V C1 and carrier V C2 Compare and generate preprocessed signal m 1 and m 2 , when V m ≥V C1 Time 1 =1, otherwise m 1 =0; when V m ≥V C2 Time 2 =1, otherwise m 2 =0, where m1 、m 2 The pre-processed signals representing the outputs of the first marking module and the second marking module of the positive half cycle of the power frequency respectively;

[0015] S104, the modulation wave V m Respectively with carrier V C1b and carrier V C2b Compare and generate preprocessed signal m 1b and m 2b , when V m ≥V C1b Time 1b =0, otherwise m 1b =1; when V m ≥V C2b Time 2 =0, otherwise m 2 =1, where m 1b 、m 2b Respectively represent the preprocessed signals of the output of the first marking module and the second marking module in the negative half cycle of the power frequency.

[0016] Furthermore, the carrier V C1 , Carrier V C2 , Carrier V C1b and carrier V C2b The representation is as follows:

[0017]

[0018] Furthermore, the step S2 is specifically as follows:

[0019] Assume that the DC voltage of the two cascaded H bridges is the same, denoted as U dc1 =U dc2 =U dc , and assume that the parasitic capacitance of the two cascaded H bridges is the same, denoted by C PV1 =C PV2 =C PV , get the expression of total leakage current, and based on the expression of total leakage current, get the suppression leakage current as suppression U c1 +U c2 ;

[0020] Let S a1 and S b1 are the switch signals on the A bridge arm and the B bridge arm of the first flag module respectively, and S a2 and S b2 The switch signals on the A bridge arm and the B bridge arm of the second flag module are respectively, the switch signal 1 represents on, 0 represents off, and the upper and lower switch signals of the same bridge arm are reversed. c1 +U c2Perform the calculations and list all output levels that satisfy the parasitic capacitance voltage and equal switching combinations.

[0021] Furthermore, the total leakage current is expressed as:

[0022] i g =C PV1* Ud c1 / dt+C PV2* Ud c2 / dt=C PV* d(U c1 +U c2 ) / dt

[0023] Among them, i g Represents the total leakage current, C PV1 With C PV2 Respectively represent the parasitic capacitance of the first and second marking modules, U c1 and U c2 They represent the parasitic capacitance voltage, d represents the differential, t represents the time, C PV Represents the parasitic capacitance of two cascaded H-bridges.

[0024] Furthermore, the pair U c1 +U c2 The calculation is as follows:

[0025] U c1 +U c2 =-U dc -U grid

[0026] Among them, U c1 +U c2 It represents the leakage current excitation source of two H-bridge cascade inverters - the voltage sum of parasitic capacitors, U grid Indicates the grid voltage.

[0027] Furthermore, the switch combination includes:

[0028] Power frequency positive half cycle: +2U dc (1010),+U dc (1000) The first indicator module output, +U dc (1110) second flag module output;

[0029] 0:(1100),(0011);

[0030] Negative half cycle of power frequency: -2Udc(0101), -Udc(0111) first mark module output -Udc(0001) second mark module output.

[0031] Furthermore, in step S3, a corresponding switch combination is selected in combination with the pre-processed signal of power distribution, which is specifically:

[0032] The switch combination with constant Uc1+Uc2 is selected in combination with the preprocessing signal of power distribution to realize power sharing and leakage current suppression under full modulation.

[0033] The present invention provides a cascade inverter leakage current suppression and power balance modulation system, comprising:

[0034] The first processing module is used to evenly distribute the power of the two cascaded H bridges within any modulation range by using an improved carrier structure, and generate a pre-processing signal indicating the output of the module;

[0035] A second processing module, used for converting the pre-processed signal outputted by each marking module into a parasitic capacitor voltage and a constant switch combination;

[0036] The third processing module is used to select a corresponding switch combination in combination with the pre-processing signal of power average distribution to achieve power sharing and leakage current suppression under full modulation.

[0037] The beneficial effects of the present invention are:

[0038] The invention comprises two parts, power distribution and switch signal generation. The power distribution module improves the carrier structure so that the H-bridge 1 carrier and the H-bridge 2 carrier appear alternately with the same period within any modulation range, thereby realizing power equalization under full modulation, and generating a pre-processing signal marking the module output; and calculating the leakage current excitation source of two H-bridge cascade inverters-parasitic capacitor voltage sum, listing all switch combinations whose output levels meet the parasitic capacitor voltage sum equalization, and completing module output analysis for the combination; and then selecting the corresponding switch combination in combination with the power distribution pre-processing signal, thereby realizing power equalization and leakage current suppression under full modulation, and solving the leakage current suppression and power balancing problems of two H-bridge cascade inverters. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 It is a topology diagram of two H-bridge photovoltaic and cascade.

[0040] Figure 2 To simplify the equivalent model diagram.

[0041] Figure 3 Schematic diagram of power sharing and modulation wave generation.

[0042] Figure 4 It is the parasitic capacitance voltage waveform.

[0043] Figure 5 Figure 2 is the DC side current waveform of the two H-bridges.

[0044] Figure 6 This is the leakage current waveform.

[0045] Figure 7 A schematic diagram of the system structure. DETAILED DESCRIPTION

[0046] The specific implementation modes of the present invention are described below so that those skilled in the art can understand the present invention. However, it should be clear that the present invention is not limited to the scope of the specific implementation modes. For those of ordinary skill in the art, as long as various changes are within the spirit and scope of the present invention as defined and determined by the attached claims, these changes are obvious, and all inventions and creations utilizing the concept of the present invention are protected.

[0047] Example 1

[0048] like Figure 3 As shown, the present invention provides a method for suppressing leakage current and balancing power of a cascade inverter. The method includes a power distribution stage to realize the average power distribution of two cascade H bridges and generate a pre-processing signal marking the module output; a switch signal generation part converts the output signal of each module into a switch combination to ensure the total parasitic capacitance voltage of the system is constant, and the implementation method is as follows:

[0049] S1. Using the improved carrier structure, the power of the two cascaded H bridges in any modulation range is evenly distributed, and a pre-processed signal indicating the module output is generated. The implementation method is as follows:

[0050] S101. Define the symmetrical triangular carrier with an amplitude of 1 as V tri , define the switching period as T s , define t z is the time t versus T s Find the remainder and define V z is a step function, when 0<t z <0.5T s Time V z =1, when 0.5T s <t z <T s Time V z =0, V z Negate, where t z =(t,T s );

[0051] S102: Obtain carrier V according to the parameters defined in step S101. C1 , Carrier V C2 , Carrier V C1b and carrier V C2b The representation of which is that the carrier V C1 and carrier VC2 In the modulation wave V m The positive half-cycle comparison phase appears alternately, and the waveform period is the same. The carrier V C1b and carrier V C2b It appears alternately in the comparison phase of the negative half cycle of the modulation wave with the same period;

[0052] S103, the modulation wave V m Respectively with carrier V C1 and carrier V C2 Compare and generate preprocessed signal m 1 and m 2 , when V m ≥V C1 Time 1 =1, otherwise m 1 =0; when V m ≥V C2 Time 2 =1, otherwise m 2 =0, where m 1 、m 2 The pre-processed signals representing the outputs of the first marking module and the second marking module of the positive half cycle of the power frequency respectively;

[0053] S104, the modulation wave V m Respectively with carrier V C1b and carrier V C2b Compare and generate preprocessed signal m 1b and m 2b , when V m ≥V C1b Time 1b =0, otherwise m 1b =1; when V m ≥V C2b Time 2 =0, otherwise m 2 =1, where m 1b 、m 2b Respectively represent the preprocessed signals of the output of the first marking module and the second marking module in the negative half cycle of the power frequency.

[0054] In this embodiment, power distribution is achieved by modulating the wave V m With carrier V C1 、V C2 、V C1b 、V C2b Compare to get the preprocessed signal m 1 、m 2 、m 1b 、m 2b .

[0055] In this embodiment, a symmetrical triangular carrier with an amplitude of 1 is defined as V tri, define the switching period as T s , define t z is the time t versus T s Find the remainder, that is, t z =(t,T s ); define V z is a step function, when 0<t z <0.5T s Time V z =1, when 0.5T s <t z <T s Time V z =0, V z Negate; each carrier can be described as

[0056] In this embodiment, the preprocessed signal m 1 、m 2 The generation method is the modulation wave V m and respectively carrier V C1 、V C2 Compare, when V m ≥V C1 Time 1 =1, otherwise m 1 =0; Similarly, when V m ≥V C2 Time 2 =1, otherwise m 2 =0; preprocessing signal m 1b 、m 2b The generation method is the modulation wave V m and respectively carrier V C1b 、V C2b Compare, when V m ≥V C1b Time 1b =0, otherwise m 1b =1; Similarly, when V m ≥V C2b Time 2 =0, otherwise m 2 =1. Since V C1 、V C2 They appear alternately in the comparison stage of the positive half cycle of the modulation wave, and the waveform period is the same, so the power is evenly divided between the two modules in the positive half cycle; similarly, V C1b 、V C2b It appears alternately in the comparison phase of the negative half cycle of the modulation wave with the same period, thus achieving equal power sharing between the two modules in the negative half cycle.

[0057] In this embodiment, by analyzing the carrier information, it can be known that V C1 、VC2 In the two stages of the positive half-cycle amplitude [0,1] and [1,2], they appear alternately with the same period, so the modulation wave V m Regardless of the value, the power sharing of the positive half-cycle can be achieved; the analysis of the negative half-cycle is similar and will not be repeated here.

[0058] S2. Convert the pre-processed signal of each marker module output into a parasitic capacitor voltage and a constant switch combination, which is specifically:

[0059] Assume that the DC voltage of the two cascaded H bridges is the same, denoted as U dc1 =U dc2 =U dc , and assume that the parasitic capacitance of the two cascaded H bridges is the same, denoted by C PV1 =C PV2 =C PV , get the expression of total leakage current, and based on the expression of total leakage current, get the suppression leakage current as suppression U c1 +U c2 ;

[0060] Let S a1 and S b1 are the switch signals on the A bridge arm and the B bridge arm of the first flag module respectively, and S a2 and S b2 The switch signals on the A bridge arm and the B bridge arm of the second flag module are respectively, the switch signal 1 represents on, 0 represents off, and the upper and lower switch signals of the same bridge arm are reversed. c1 +U c2 Perform the calculations and list all output levels that satisfy the parasitic capacitance voltage and equal switching combinations.

[0061] In this embodiment, it is assumed that the DC side voltages of the two H-bridges are the same, denoted as U dc1 =U dc2 =U dc ; Assume that the parasitic capacitance of the two H bridges is the same, denoted as C PV1 =C PV2 =C PV ; then the total leakage current value of the system can be described as i g =C PV1* Ud c1 / dt+C PV2* Ud c2 / dt=C PV* d(U c1 +U c2 ) / dt,U c1 , U c2 Respectively represent the parasitic capacitance voltage of H bridge 1 and H bridge 2, i g Represents the total leakage current, C PV1 With C PV2Respectively represent the parasitic capacitance of the first and second marking modules, U c1 and U c2 They represent the parasitic capacitance voltage, d represents the differential, t represents the time, C PV represents the parasitic capacitance of the two cascaded H bridges. Therefore, the key to suppressing leakage current is to suppress U c1 +U c2 The high frequency components of Figure 1-2 As shown, Figure 1 This is a two-module cascade H-bridge topology diagram. In the figure, module 1 is the first mark module, module 2 is the second mark module, and the filter inductor L 1 =L 2 =L,U grid is the grid voltage signal; Figure 2 for Figure 1 Simplified model diagram, where U AiNi Indicates the midpoint voltage of bridge arm A of module i, U BiNi Represents the midpoint voltage of bridge arm B of module i.

[0062] In this embodiment, let S a1 , S b1 are the switch signals on the A bridge arm and the B bridge arm of the first flag module, S a2 , S b2 They are the switch signals on the A bridge arm and the B bridge arm of module 2, respectively. The switch signal "1" indicates conduction, and "0" indicates off. The upper and lower switch signals of the same bridge arm are opposite. Calculate U c1 +U c2 The switching function is represented by U c1 +U c2 =(-S a1 -S b2 )*U dc -U grid , where i g Indicates the total leakage current value, U c1 and U c2 Respectively represent the parasitic capacitance voltage of H-bridge 1 and H-bridge 2, considering the maximum positive level of the inverter output +2U dc When the switch combination 1010 (S a1 , S b1 , S a2 , S b2 ), output maximum negative level -2U dc When the switch combination 0101, U c1 +U c2 =-U dc -U grid , where U grid Indicates the grid voltage, so during the switching process, only S a1 , Sb2 The sum is 1, S b1 , S a2 Can be freely combined into four switch states, a total of eight switch states (S a1 , S b1 , S a2 , S b2 ):

[0063] Power frequency positive half cycle: +2U dc (1010),+U dc (1000) The first indicator module output, +U dc (1110) second flag module output;

[0064] 0:(1100),(0011);

[0065] Negative half cycle of power frequency: -2Udc(0101), -Udc(0111) first mark module output -Udc(0001) second mark module output.

[0066] The corresponding relationship is shown in Table 1, which shows the relationship between the preprocessing signal and the switch signal.

[0067] Table 1

[0068]

[0069]

[0070] S3, modulation stage: select the corresponding switch combination in combination with the pre-processed signal of power distribution to achieve power sharing and leakage current suppression under full modulation, which is specifically:

[0071] The switch combination with constant Uc1+Uc2 is selected in combination with the preprocessing signal of power distribution to realize power sharing and leakage current suppression under full modulation.

[0072] In this embodiment, a simulation model is built to verify the effectiveness of the proposed modulation method. Simulation parameters: U dc =30V, U grid =50V, C PV =50nF, L 1 =L 2 =2mH, switching frequency f s =2000Hz, grid voltage switching frequency i grid =5A.

[0073] In this embodiment, Figure 4 As shown, it is the parasitic capacitance U of H bridge 1 c1 Parasitic capacitance U c2 , U c1 with Uc2 Both contain a large number of high-frequency components, and after superposition, they present a 50Hz low-frequency component. This shows that the proposed modulation method effectively suppresses the high-frequency components of the parasitic capacitance voltage and .

[0074] In this embodiment, Figure 5 As shown, it is the photovoltaic side current i of H bridge 1 dc1 The photovoltaic side current i dc2 , in the figure dcl with i dc2 It shows alternating performance, and its effective values ​​are 1.766Arms and 1.768Arms respectively, and the power sharing effect is good.

[0075] In this embodiment, Figure 6 As shown, it is the leakage current i of H bridge 1 g1 With H bridge 2 leakage current i g2 , in the figure g1 with i g2 The amplitude is about 150mA, and the effective value is about 75mA; g is the total system leakage current i g =i g1 +i g2 , it can be seen from the figure that the amplitude is about 1mA and the effective value is 0.58mA.

[0076] In summary, the modulation method proposed in the present invention effectively achieves leakage current suppression and power sharing.

[0077] Example 2

[0078] In this embodiment, Figure 7 As shown, the present invention provides a cascade inverter leakage current suppression and power balance modulation system, comprising:

[0079] The first processing module is used to evenly distribute the power of the two cascaded H bridges within any modulation range by using an improved carrier structure, and generate a pre-processing signal indicating the output of the module;

[0080] A second processing module, used for converting the pre-processed signal outputted by each marking module into a parasitic capacitor voltage and a constant switch combination;

[0081] The third processing module is used to select a corresponding switch combination in combination with the pre-processing signal of power average distribution to achieve power sharing and leakage current suppression under full modulation.

[0082] In this embodiment, the present invention realizes leakage current suppression and power sharing of a two-module H-bridge cascade inverter by improving the modulation strategy without adding hardware.

[0083] like Figure 7The modulation system provided in the illustrated embodiment can execute the technical solution shown in the modulation system of the above method embodiment, and its implementation principle and beneficial effects are similar, which will not be repeated here.

[0084] In this embodiment, the present application can divide the functional units according to the modulation system. For example, each function can be divided into each functional unit, or two or more functions can be integrated into one processing unit. The above integrated unit can be implemented in the form of hardware or in the form of software functional units. It should be noted that the division of units in the present invention is schematic and is only a logical division. There may be other division methods in actual implementation.

[0085] In this embodiment, in order to realize the principles and beneficial effects of the modulation system, the modulation system includes hardware structures and / or software modules corresponding to the execution of various functions. Those skilled in the art should easily realize that, in combination with the schematic units and algorithm steps described in the embodiments disclosed in the present invention, the present invention can be implemented in the form of hardware and / or a combination of hardware and computer software. Whether a function is executed in a hardware or computer software driven manner depends on the specific application and design constraints of the technical solution. Different methods can be used for each specific application to implement the described function, but such implementation should not be considered to exceed the scope of this application.

[0086] In this embodiment, the present invention utilizes a power distribution module to improve the carrier structure so that within any modulation range, the H-bridge 1 carrier and the H-bridge 2 carrier appear alternately with the same period, thereby achieving power balancing under full modulation, and generating a preprocessing signal marking the module output; and calculating the leakage current excitation source of the two H-bridge cascade inverters - the parasitic capacitor voltage sum, listing all switch combinations whose output levels satisfy the parasitic capacitor voltage sum being equal, and completing the module output analysis for the combination; and then selecting the corresponding switch combination in combination with the power distribution preprocessing signal, thereby achieving power balancing and leakage current suppression under full modulation, solving the problem of leakage current suppression and power balancing of the two H-bridge cascade inverters, and effectively achieving leakage current suppression and power balancing.

[0087] The above embodiments are only used to illustrate the technical method of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical method of the present invention may be modified or replaced by equivalents without departing from the spirit and scope of the technical method of the present invention.

Claims

1. A method for suppressing leakage current and balancing power in cascade inverters. It is characterized in that The following steps are involved: S1. Using the improved carrier structure, the power of the two cascaded H bridges in any modulation range is evenly distributed, and a pre-processed signal indicating the module output is generated; The step S1 comprises the following steps: S101. Define a symmetrical triangular carrier wave with an amplitude of 1 as V tri , the switching cycle is defined as T s ,definition t z For time t right T s Find the remainder, define V z is a step function, when 0< t z <0.5 T s hour V z =1, when 0.5 T s < t z < T s hour V z =0, for V z Negate, where t z =( t , T s ); S102: According to the parameters defined in step S101, the carrier V C1 , Carrier V C2 , Carrier V C1b and carrier V C2b The representation of which is V C1 and carrier V C2 In the modulation wave V m The positive half-cycle comparison phase appears alternately, and the waveform period is the same. V C1b and carrier V C2b It appears alternately in the comparison phase of the negative half cycle of the modulation wave with the same period; S103, the modulated wave V m Carrier V C1 and carrier V C2 Compare and generate preprocessed signals m 1 and m 2 ,when V m ≥ V C1 hour m 1 =1, otherwise m 1 =0; when V m ≥ V C2 hour m 2 =1, otherwise m 2 =0, where m 1 , m 2 The pre-processed signals representing the outputs of the first marking module and the second marking module of the positive half cycle of the power frequency respectively; S104, the modulated wave V m Carrier V C1b and carrier V C2b Compare and generate preprocessed signals m 1b and m 2b ,when V m ≥ V C1b hour m 1b =0, otherwise m 1b =1; when V m ≥ V C2b hour m 2 =0, otherwise m 2 =1, where m 1b , m 2b The pre-processed signals representing the outputs of the first marking module and the second marking module of the negative half cycle of the power frequency respectively; The carrier V C1 , Carrier V C2 , Carrier V C1b and carrier V C2b The representation is as follows: V C1 = V tri* V z +( V tri +1) * V C2 = V tri* +( V tri +1) * V z V Cb1 =( V tri -2) * V z +( V tri -1) * V Cb2 =( V tri -1) * V z +( V tri -2) * ； S2, converting the pre-processed signal of each marker module output into a parasitic capacitor voltage and a constant switch combination; S3. Select a corresponding switch combination in combination with the pre-processed signal of power average distribution to achieve power sharing and leakage current suppression under full modulation.

2. The method for suppressing leakage current and balancing power of cascade inverter according to claim 1, It is characterized in that The step S2 is specifically as follows: Assume that the DC voltage of the two cascaded H bridges is the same, which can be expressed as U dc1 = U dc2 = U dc , and assuming that the parasitic capacitance of the two cascaded H bridges is the same, it is recorded as C PV1 = C PV2 = C PV , get the expression of the total leakage current, and based on the expression of the total leakage current, get the suppression leakage current as suppression U c1 + U c2 ; set up S a1 and S b1 are the switch signals on the A bridge arm and the B bridge arm of the first flag module respectively. S a2 and S b2 The switch signals on the A bridge arm and the B bridge arm of the second flag module are respectively, the switch signal 1 represents on, 0 represents off, and the upper and lower switch signals of the same bridge arm are reversed. U c1 + U c2 Perform the calculations and list all output levels that satisfy the parasitic capacitance voltage and equal switching combinations.

3. The cascade inverter leakage current suppression and power balancing modulation method according to claim 2, It is characterized in that The total leakage current is expressed as: i g = C PV1* d U c1 / d t+ C PV2* d U c2 / d t = C PV* d( U c1 +U c2 ) / d t in, i g represents the total leakage current, C PV1 and C PV2 Respectively represent the parasitic capacitance of the first marking module and the second marking module, U c1 and U c2 They represent the parasitic capacitance voltage, d represents the differential, t Indicates time, C PV Represents the parasitic capacitance of two cascaded H-bridges.

4. The method for suppressing leakage current and balancing power of cascade inverter according to claim 3, It is characterized in that The pair U c1 + U c2 The calculation is as follows: U c1 +U c2 =- U dc -U grid in, U c1 +U c2 represents the leakage current excitation source of the two H-bridge cascade inverters - the parasitic capacitor voltage and, U grid Indicates the grid voltage.

5. The method for suppressing leakage current and balancing power of cascade inverter according to claim 4, It is characterized in that The switch combination comprises: Power frequency positive half cycle: +2 U dc (1010) , + U dc (1000) The first sign module output, + U dc (1110) second flag module output; 0：(1100), (0011)； Negative half cycle of power frequency: -2Udc(0101), -Udc(0111) The first mark module output -Udc(0001) The second mark module output.

6. The method for suppressing leakage current and balancing power of cascade inverters according to claim 5, It is characterized in that In step S3, the corresponding switch combination is selected in combination with the pre-processed signal of power distribution, which is specifically: Preprocessing signal selection combined with power allocation U c1 +U c2 The constant switch combination realizes power sharing and leakage current suppression under full modulation.

7. A system for the cascade inverter leakage current suppression and power balance modulation method according to any one of claims 1 to 6, It is characterized in that include: The first processing module is used to evenly distribute the power of the two cascaded H bridges within any modulation range by using an improved carrier structure, and generate a pre-processing signal indicating the output of the module; A second processing module, used for converting the pre-processed signal outputted by each marking module into a parasitic capacitor voltage and a constant switch combination; The third processing module is used to select a corresponding switch combination in combination with the pre-processing signal of power average distribution to achieve power sharing and leakage current suppression under full modulation.

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