High efficiency area n-path filter

Abstract

The N-path filter includes a plurality of switched-capacitor circuits, respectively controlled by a plurality of logic signals, and connected to a plurality of shunt common nodes. Each switched-capacitor circuit includes a corresponding switch and a corresponding balanced metal-oxide-semiconductor (MOS) capacitor. The corresponding switch is configured to controllably connect a shunt common node to a corresponding intermediate node according to a corresponding logic signal of the logic signals. The corresponding balanced MOS capacitor is connected to the corresponding intermediate node, wherein the corresponding balanced MOS capacitor exhibits a capacitance at the corresponding intermediate node with reference to a power node and a ground node.

Description

Technical Field

[0001] This disclosure generally relates to N-path filters, and more particularly to N-path filters with high efficiency area. Background Technology

[0002] like Figure 1A As shown, a bandpass network 100 includes a source-end network 110 for transmitting an input voltage signal V. in Coupled to an output node 101; a load impedance Z 150 A load network 150 is used to draw a load current I from the output node 101. load ; and the shunt impedance Z 120 An N-path filter 120 is used to draw a shunt current I from the output node 101. sh The output voltage signal V of output node 101 out Depends on the impedance of the source network 110 and the load impedance Z 150 and shunt impedance Z 120 .like Figure 1B As shown, in one embodiment, the N-path filter 120 is a shunt network comprising four switched-capacitor circuits 121, 122, 123, and 124 connected in parallel. These four switched-capacitor circuits 121, 122, 123, and 124 are controlled by four logic signals LO1, LO2, LO3, and LO4, respectively. Each switched-capacitor circuit 121 (122, 123, 124) includes a switch 141 (142, 143, 144) and a capacitor 131 (132, 133, 134). The switch 141 (142, 143, 144) is controlled by the logic signal LO1 (LO2, LO3, LO4) and is connected in series with the capacitor 131 (132, 133, 134). The four logic signals LO1, LO2, LO3, and LO4 form a frequency f. LO A four-phase clock signal. The shunt impedance Z of the N-path filter 120. 120 Frequency response to frequency f LO It has a peak value at a certain point, and the frequency response changes as the frequency value deviates from the frequency f. LO And roll off.

[0003] Bandpass networks 100 are frequently used in the front end of zero intermediate frequency (zero-IF) wireless receivers to suppress unwanted obstruction frequencies, which are frequencies deviating from the desired frequency of the signal to be received. The four-phase clock signal is generated by a local oscillator that adjusts the oscillation signal to the frequency of the desired signal. Consider one case where, at frequency f... LOIn the vicinity of the relevant frequency range, the impedance of the source network 110 is nearly constant. At this time, when the shunt impedance Z... 120 The larger the impedance value, the greater the shunt current I flowing from output node 101. sh The smaller the value, the greater the output voltage signal V. load The higher the voltage level, the better. Thus, the bandpass network 100 can provide a signal with a central frequency of frequency f. LO The bandpass response of the N-path filter 120. The principle of the N-path filter 120 and how to implement a bandpass filter with it are well-known existing technologies, and therefore will not be described in detail here. The bandwidth of the bandpass network 100 is determined by the load impedance Z. 150 and shunt impedance Z 120 Decision (assuming at frequency f) LO In the vicinity of the relevant frequency range, the impedance of the source network 110 is nearly constant. To obtain a narrow bandwidth, capacitors 131, 132, 133, and 134 need to be sufficiently large. In this case, the bandpass network 100 is integrated onto a silicon substrate using complementary metal-oxide-semiconductor (CMOS) technology, wherein capacitors 131, 132, 133, and 134 can be implemented as metal-oxide-metal (MOM) capacitors or metal-oxide-semiconductor (MOS) capacitors, which are constructed by connecting the source and drain of a MOS transistor. MOS capacitors have a high density and therefore high area efficiency. However, the capacitance value of a MOS capacitor is not fixed but varies depending on the voltage applied to the MOS transistor. Specifically, the capacitance value of a MOS capacitor increases as the absolute value of the gate-source voltage of the MOS transistor increases. Therefore, if MOS capacitors are implemented to realize capacitors 131, 132, 133, and 134, the shunt impedance Z... 120 The output voltage signal V will be out Changes occur, causing nonlinear distortion.

[0004] What those skilled in the art desire is an N-path filter that has an efficient area and is unaffected by nonlinear distortion. Summary of the Invention

[0005] In one embodiment, the N-path filter includes a plurality of switched-capacitor circuits controlled by a plurality of logic signals and connected to a shunt common node. Each switched-capacitor circuit includes a switch controllably connecting the shunt common node to a corresponding intermediate node according to a corresponding logic signal of the logic signals, and a corresponding balanced MOS capacitor connected to the corresponding intermediate node, wherein the corresponding balanced MOS capacitor exhibits a capacitance at the corresponding intermediate node with reference to a first power node and a ground node, and N is an integer greater than 1. BRIEF DESCRIPTION OF DRAWINGS

[0006] Figure 1A A schematic diagram of a prior art bandpass network including an N-path filter.

[0007] Figure 1B A schematic diagram of a prior art N-path filter.

[0008] Figure 2 A schematic diagram of an N-path filter according to one embodiment of the present disclosure.

[0009] Figure 3A A schematic diagram of a balanced MOS capacitor according to a first embodiment of the present disclosure.

[0010] Figure 3B A schematic diagram of a balanced MOS capacitor according to a second embodiment of the present disclosure.

[0011] Figure 3C A schematic diagram of a balanced MOS capacitor according to a third embodiment of the present disclosure.

[0012] Figure 3D A schematic diagram of a balanced MOS capacitor according to a fourth embodiment of the present disclosure.

[0013] Figure 4 A schematic diagram of Figure 3A a balanced MOS capacitor of

[0014] LEGEND

[0015] 100: bandpass network

[0016] 110: source network

[0017] 120: N-path filter

[0018] 121: switched-capacitor circuit

[0019] 131: capacitor

[0020] 141: switch

[0021] LO1: logic signal

[0022] 122: switched-capacitor circuit

[0023] 132: capacitor

[0024] 142: switch

[0025] LO2: logic signal

[0026] 123: switched-capacitor circuit

[0027] 133: capacitor

[0028] 143: switch

[0029] LO3: logic signal

[0030] 124: switched-capacitor circuit

[0031] 134: capacitor

[0032] 144: switch

[0033] LO4: logic signal

[0034] Z 120 : shunt impedance

[0035] 150: load network

[0036] Z 150 : load impedance

[0037] 101: output node

[0038] V in : input voltage signal

[0039] V out : output voltage signal

[0040] I sh : shunt current

[0041] I load : load current

[0042] 200: N-path filter

[0043] Z 200 : shunt impedance

[0044] 211: switched-capacitor circuit

[0045] 221: balanced MOS capacitor

[0046] 231: switch

[0047] 241: intermediate node

[0048] 212: switched-capacitor circuit

[0049] 222: balanced MOS capacitor

[0050] 232: switch

[0051] 242: intermediate node

[0052] 213: switched capacitor circuit

[0053] 223: balanced MOS capacitor

[0054] 233: switch

[0055] 243: intermediate node

[0056] 214: switched capacitor circuit

[0057] 224: balanced MOS capacitor

[0058] 234: switch

[0059] 244: intermediate node

[0060] 201: shunt common node

[0061] V sh : shunt voltage signal

[0062] V DD : power supply node

[0063] V SS : ground node

[0064] 310: balanced MOS capacitor

[0065] 311: NMOS transistor

[0066] 312: PMOS transistor

[0067] 319: intermediate node

[0068] 320: balanced MOS capacitor

[0069] 321: NMOS transistor

[0070] 322: NMOS transistor

[0071] 329: intermediate node

[0072] 330: balanced MOS capacitor

[0073] 331: PMOS transistor

[0074] 332: NMOS transistor

[0075] 339: intermediate node

[0076] 340: balanced MOS capacitor

[0077] 341: PMOS transistor

[0078] 342: PMOS transistor

[0079] 349: intermediate node DETAILED DESCRIPTION

[0080] The present disclosure relates to N-path filters. While the specification describes particular embodiments of the present disclosure, and what is described is presently considered to be a preferred way of implementing the application, it is understood that the application can be carried out in various ways and is not limited to the particular exemplary implementations described below, or to the particular manner in which any of the exemplary implementations are implemented. In other instances, well-known details are not shown or described to avoid obscuring aspects of the present disclosure.

[0081] Those of ordinary skill in the art will appreciate the terminology and underlying concepts related to microelectronics technology used herein, such as "voltage", "current", "signal", "clock signal", "frequency", "phase", "load", "shunt", "zero-IF radio receiver", "bandpass filter", "switch", "capacitor", "parallel connection", "circuit node", "ground", "direct current", "alternating current", "power supply", "MOS transistor", "CMOS technology", "N-channel metal oxide semiconductor (NMOS) transistor", and "P-channel metal oxide semiconductor (PMOS) transistor". Such terminology is used in the context of microelectronics technology, and the relevant concepts are apparent to those skilled in the art, and therefore are not explained in detail herein.

[0082] Without further explanation, units of measure such as pico-Farad (pF), nano-meter (nm), and micrometer (pm) are understood by those of ordinary skill in the art.

[0083] Without delving into a tedious description of how one element in a circuit schematic is connected to another, those skilled in the art can read a schematic of a circuit containing electronic elements (e.g., inductors, capacitors, resistors, NMOS transistors, PMOS transistors, etc.). Those skilled in the art can also recognize the symbols for ground, the symbols for capacitors, the symbols for inductors, the symbols for resistors, and the symbols for PMOS and NMOS transistors, and can recognize the "source terminal," the "gate terminal," and the "drain terminal" of the symbols for PMOS and NMOS transistors. For MOS transistors, for the sake of brevity in the description, "source terminal" is referred to simply as "source," "gate terminal" is referred to simply as "gate," and "drain terminal" is referred to simply as "drain" hereinafter.

[0084] A circuit is an integration of transistors, capacitors, resistors, and / or other electronic devices, and they are connected to each other in a certain way to achieve a certain function.

[0085] A network is a circuit or a collection of circuits.

[0086] A power supply node is a circuit node that has a nearly constant voltage, and a ground node is the same. Both power supply and ground nodes are DC nodes, but have different voltage levels; that is, the voltage level of a power supply node is greater than that of a ground node. In accordance with a convention widely used in the literature, "V DD " is denoted as a power supply node, and "V SS " is denoted as a ground node. Although the DC level of a ground node is generally 0 V (volt), it is not limited to this (i.e., it is not necessary to be 0 V). The point is that there is a potential difference between a power supply node and a ground node. For a certain circuit, if the DC voltage levels of all nodes are raised by the same amount, the operation of the circuit will remain unchanged. Therefore, in the appended claims, "a first DC node" is used to describe a ground node, and "a second DC node" is used to describe a power supply node.

[0087] In this document, "circuit node" is often simply referred to as "node" when it is clear from the context that the meaning of "node" is "circuit node."

[0088] A signal is a voltage with a variable level that carries some information and can change over time. The level of a signal at a certain point in time represents the state of the signal at that point in time. In this document, "signal" and "voltage signal" refer to the same thing, and thus can be interchanged.

[0089] A logic signal is a voltage signal that has two states: a low state and a high state. A logic signal is in the high state when its voltage level is above a trip point; otherwise (i.e., when its voltage level is not above the trip point), the logic signal is in the low state. The low state is also referred to as a "0" state, and the high state is also referred to as a "1" state. With respect to a logic signal Q, when it is said that the logic signal Q is "high" ("high level") or "low" ("low level"), it means that the logic signal Q is in the high state; or that the logic signal Q is in the low state. Similarly, when it is said that the logic signal Q is "1" or "0", it means that the logic signal Q is in the "1" state; or that the logic signal Q is in the "0" state.

[0090] The trip point of the first logic signal is not necessarily the same as the trip point of the second logic signal.

[0091] The first logic signal is said to be the logical inverse of the second logic signal if the first logic signal and the second logic signal are always in opposite states. That is, when the first logic signal is "low level", the second logic signal is "high level"; and when the first logic signal is "high level", the second logic signal is "low level". When the first logic signal is the logical inverse of the second logic signal, the first logic signal is said to be complementary to the second logic signal.

[0092] A logic signal is often used as a control signal to enable or disable the function of a circuit. A logic signal is said to be "active" when it is in the logic state that enables the function of the circuit; otherwise (i.e., when the logic signal is in the logic state that disables the function of the circuit), the logic signal is said to be "inactive". A logic signal is said to be "active high" when it is active at the high level. A logic signal is said to be "active low" when it is active at the low level.

[0093] A switch is used extensively in this document. A switch is a device that controllably connects a first node to a second node according to the control of a logic signal. When the logic signal is active, the switch is open and behaves as a short circuit; when the logic signal is inactive, the switch is closed and behaves as an open circuit.

[0094] A switch can be implemented by an NMOS transistor whose gate voltage is controlled by an active high logic signal, and whose source and drain are connected to the first node and the second node, respectively. In this case, the trip point of the active high logic signal is the same as the source voltage of the first node plus the threshold voltage of the NMOS transistor.

[0095] Alternatively, the switch can be implemented by a PMOS transistor whose gate voltage is controlled by the active low logic signal, and the first node and the second node are connected to the source and the drain of the PMOS transistor, respectively. In this case, the transition point of the active low logic signal is equal to the source voltage of the first node minus the threshold voltage of the PMOS transistor (which is a positive voltage according to the convention used herein).

[0096] Alternatively, the switch can be implemented by a PMOS transistor whose gate voltage is controlled by the active low logic signal, and the first node and the second node are connected to the source and the drain of the PMOS transistor, respectively. In this case, the transition point of the active low logic signal is equal to the source voltage of the first node minus the threshold voltage of the PMOS transistor (which is a positive voltage according to the convention used herein).

[0097] A clock signal is a periodic logic signal that periodically toggles between a low state and a high state. A multiphase clock signal comprises a plurality of clock signals. The clock signals have the same frequency and the same waveform, but are uniformly displaced in time.

[0098] Referring to Figure 2 , which is a schematic diagram of an N-path filter 200 according to an embodiment of the present disclosure. The N-path filter 200 comprises four switched-capacitor circuits 211, 212, 213, 214 connected to a shunt common node 201. The switched-capacitor circuit 211 (212, 213, 214) comprises a switch 231 (232, 233, 234) for controllably connecting the shunt common node 201 to an intermediate node 241 (242, 243, 244) according to a logic signal LO1 (LO2, LO3, LO4), and a balanced MOS capacitor 221 (222, 223, 224) for providing a capacitance at the intermediate node 241 (242, 243, 244) with reference to a power supply node V DD and a ground node V SS . The four logic signals LO1, LO2, LO3, LO4 form a four-phase clock signal with a frequency f LO . The N-path filter 200 can be used to replace the N-path filter 120 in the bandpass network 100 of Figure 1A . In this case, Figure 2 the shunt common node 201 of the N-path filter 200 is identical to the output node 101 of the bandpass network 100 of Figure 1A , and the shunt voltage signal V sh at the shunt common node 201 of the N-path filter 200 is identical to the output voltage signal V outSimilar to the N-path filter 120, the shunt impedance Z of the N-path filter 200 is... 200 Frequency response to frequency f LO It has a peak value at a certain point, and the frequency response changes as the frequency value deviates from the frequency f. LO And roll down. With Figure 1B The main difference between the N-path filter 120 and the N-path filter 200 lies in the use of balanced MOS capacitors. Balanced MOS capacitors have two distinct characteristics. First, a balanced MOS capacitor is a combination of a lower capacitor (referenced to the ground terminal) and an upper capacitor (referenced to the power node). Second, the balanced MOS capacitors implement a complementary structure, where an increase in the capacitance of the lower capacitor results in a decrease in the capacitance of the upper capacitor, and vice versa (i.e., a decrease in the capacitance of the lower capacitor results in an increase in the capacitance of the upper capacitor). Thus, while the total capacitance exhibits voltage dependence, it is nearly symmetrical near the mid-voltage between the power node and the ground node. Many circuits can implement balanced MOS capacitors, which will be described in detail later.

[0099] like Figure 3A As shown, in the first embodiment, the balancing MOS capacitor 310 includes an NMOS transistor 311 and a PMOS transistor 312. The source and drain of the NMOS transistor 311 are connected to the ground node V. SS The gate of NMOS transistor 311 is connected to intermediate node 319. The source and drain of PMOS transistor 312 are connected to power node V. DD The gate of PMOS transistor 312 is connected to intermediate node 319.

[0100] like Figure 3B As shown, in the second embodiment, the balancing MOS capacitor 320 includes a first NMOS transistor 321 and a second NMOS transistor 322. The source and drain of the NMOS transistor 321 are connected to the ground node V. SS The gate of NMOS transistor 321 is connected to intermediate node 329. The source and drain of NMOS transistor 322 are connected to intermediate node 329, and the gate of NMOS transistor 322 is connected to power node V. DD .

[0101] like Figure 3C As shown, in the third embodiment, the balancing MOS capacitor 330 includes a PMOS transistor 331 and an NMOS transistor 332. The source and drain of the PMOS transistor 331 are connected to the intermediate node 339, while the gate of the PMOS transistor 331 is connected to the ground node V. SSThe source and drain of NMOS transistor 332 are connected to intermediate node 339, while the gate of NMOS transistor 332 is connected to power node V. DD .

[0102] like Figure 3D As shown, in the fourth embodiment, the balancing MOS capacitor 340 includes a first PMOS transistor 341 and a second PMOS transistor 342. The source and drain of the PMOS transistor 341 are connected to the intermediate node 349, while the gate of the PMOS transistor 341 is connected to the ground node V. SS The source and drain of PMOS transistor 342 are connected to the power supply node V. DD The gate of PMOS transistor 342 is connected to intermediate node 349.

[0103] Each of the balanced MOS capacitors 310, 320, 330, and 340 includes a lower MOS transistor to implement the lower capacitor and an upper MOS transistor to implement the upper capacitor. When the voltage at the intermediate node of the balanced MOS capacitor rises (falls), the absolute value of the gate-source voltage of the lower MOS transistor increases (decreases), causing the capacitance of the lower MOS transistor to increase (decrease); simultaneously, the absolute value of the gate-source voltage of the upper MOS transistor decreases (increases), causing the capacitance of the upper MOS transistor to decrease (increase).

[0104] Any one of the four balanced MOS capacitors 310, 320, 330, and 340 can be used to specifically implement the four balanced MOS capacitors 221, 222, 223, and 224.

[0105] For example, but not limited to: using 55nm CMOS process technology; power node V DD 1.2V; ground node V SS It is 0V; Figure 3A The balancing MOS capacitor 310 is used to embody the four balancing MOS capacitors 221, 222, 223, and 224; the "W / L" (which represents width / length) of the NMOS transistor 311 is 392*1m / 1μm; and the "W / L" of the PMOS transistor 312 is 392*1m / 1μm. Figure 4 The capacitance of the balancing MOS capacitor 310 is shown as a function of the voltage at intermediate node 319. The capacitance is symmetrical around 575mV, which can be referred to as the common-mode voltage of the balancing MOS capacitor 310. Although this capacitance is obviously nonlinear, due to the aforementioned symmetry, the nonlinearity of this capacitance is of even order. In one embodiment, the shunt voltage signal V shThis is an AC signal, and the DC level of this AC signal is the same as the common-mode voltage of the balancing MOS capacitor 310. In the branch voltage signal V... sh The capacitance of the N-path filter 200 during the positive half-cycle (which is above the common-mode voltage) will be the same as that during the shunt voltage signal V. sh The capacitance of the N-path filter 200 during the negative half-cycle (below the common-mode voltage). Thus, the nonlinearity of the N-path filter 200 is balanced, and the N-path filter 200 does not affect the shunt voltage signal V. sh This introduces even-order distortion. In one embodiment, the N-path filter 200 is used in the front end of a zero-IF receiver. As is known from the prior art, even-order distortion caused by strong and undesirable obstructions is often the most serious damage to a zero-IF receiver. However, the N-path filter 200 does not cause even-order distortion. Therefore, despite having nonlinear capacitance, the N-path filter 200 can still be used in the front end of a zero-IF receiver. Due to the use of MOS capacitors, the N-path filter 200 can have high area efficiency.

[0106] Although Figure 2 The N-path filter 200 is shown to include four switched-capacitor circuits 211, 212, 213, and 214. These four switched-capacitor circuits 211, 212, 213, and 214 are controlled by four logic signals LO1, LO2, LO3, and LO4, respectively. These four logic signals LO1, LO2, LO3, and LO4 form a four-phase clock signal, but the filter is not limited to this. Generally, the N-path filter 200 can include several switched-capacitor circuits, and these switched-capacitor circuits are each controlled by several logic signals, where these logic signals have the same frequency but are uniformly shifted in time to form a multi-phase clock signal.

[0107] In CMOS technology, MOS capacitors can be implemented using variable capacitors, which are a type of MOS device and come in two types: N-type and P-type. An N-type variable capacitor can function as an NMOS transistor with its source and drain connected. A P-type variable capacitor can function as a PMOS transistor with its source and drain connected. A variable capacitor can be considered an embodiment of a MOS capacitor.

[0108] Those skilled in the art will readily observe that many modifications and variations can be made to the apparatus and method while retaining the teachings of this disclosure. Therefore, the foregoing should not be construed as being defined solely by the statement of the appended claims.

Claims

1. An N-path filter comprising a plurality of switched-capacitor circuits controlled by a plurality of logic signals and connected to a shunt common node, wherein each switched-capacitor circuit comprises: a switch controllably connecting the shunt common node to a corresponding intermediate node according to a corresponding logic signal of the logic signals; and a balanced metal oxide semiconductor capacitor connected to the corresponding intermediate node, wherein the balanced metal oxide semiconductor capacitor exhibits a capacitance at the corresponding intermediate node with reference to a first DC node and a second DC node, a voltage level of the corresponding intermediate node being greater than a voltage level of the first DC node and less than a voltage level of the second DC node, wherein N is an integer greater than 1.

2. The N-path filter of claim 1, wherein the logic signals form a multiphase clock signal.

3. The N-path filter of claim 2, wherein the capacitance of the corresponding intermediate node depends on a voltage of the corresponding intermediate node and exhibits symmetry above and below a common mode voltage level. ​ ​ ​ wherein ​ ​ ​

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