A low-power high-speed level-shifting circuit

Abstract

The application provides a low-power high-speed level shift circuit, comprising a low-voltage-high-voltage level shift module, an auxiliary latch module, a self-adaptive narrow pulse generation module and an auxiliary pull-up module; the low-voltage-high-voltage level shift module comprises a low-voltage-high-voltage level shift circuit and a signal processing circuit; the auxiliary pull-up module comprises two auxiliary pull-up circuits arranged at two high-side output S and R points of the low-voltage-high-voltage level shift circuit; the auxiliary pull-up circuit comprises an inverter, a NAND gate and a PMOS tube; the auxiliary latch module comprises an auxiliary latch circuit, which is used for generating two signal control signals A and B and is connected to the two auxiliary pull-up circuits to control the two PMOS tubes to provide an additional pull-up current only when the potential of the output point of the branch assisted by the tube is flipped from low to high. On the basis of ensuring sufficient dV / dt resistance, the application can effectively reduce the power consumption and delay of the level shift circuit, realize high-frequency operation of the driving circuit and ensure the high efficiency of the power supply system.

Description

Technical Field

[0001] This invention relates to power integrated circuits, and more particularly to a low-power, high-speed level shifting circuit that can be applied to the gate drive circuit of gallium nitride power transistors. Background Technology

[0002] With the continuous development of 5G communication technology, new energy transportation, cloud computing servers, and other fields, the market demand for high power density and high efficiency power supply systems is constantly increasing. Traditional silicon-based power transistors have reached their physical performance limits, making it difficult to further improve their operating frequency and efficiency. Gallium nitride (GaN) transistors, with their significant advantages such as high switching speed, low switching losses, and high voltage withstand, can replace silicon-based power transistors in power supply systems to improve the system's switching frequency and power density.

[0003] like Figure 1 As shown, the core of the gallium nitride (GaN) power transistor drive circuit is the high-voltage level shift circuit. Its function is to convert the signal from the low-voltage power rail to the high-voltage power rail, thereby driving the high-side power transistor. Transient noise (dV / dt noise) is one of the biggest challenges currently faced by the high-voltage level shift circuit. It is generated by the sudden change in the floating ground VS during the switching process of the high-voltage power transistor, and is coupled to the high-voltage power rail VB through the bootstrap capacitor C1, and then to the low-voltage to high-voltage level shift circuit. In traditional solutions, to eliminate the influence of dV / dt noise, a positive feedback latch circuit composed of PMOS transistors MP1 and MP2 is usually added at the output of the low-voltage to high-voltage level shift circuit 001 to enhance noise immunity.

[0004] A traditional level shifting circuit, as shown in Figure 2(a), includes a low-voltage to high-voltage level shifting circuit 001 and a signal processing circuit 002. The input signal IN is converted to the high-voltage power rail after entering the high-voltage level shifting circuit and output from points S' and R' to the subsequent circuit. Due to the cross-coupling structure of the positive feedback latch circuit, the circuit has excellent dV / dt resistance. The output signals S' and R' of the low-voltage to high-voltage level shifting circuit 001 are shaped by a buffer circuit composed of inverters INV8 and INV9. Finally, the shaped signal enters the RS flip-flop, is processed and restored, and then output.

[0005] However, in the above scheme, due to the different switching capabilities of the two signal paths, the transmission speeds of the two branches are different, as shown by the S' and R' waveforms in Figure 2(b). The specific principle causing the above phenomenon is shown in Figures 3(a) and 3(b): When the input signal changes from low to high, as shown in Figure 3(a), the high-voltage NMOS transistor HMN1 and the high-voltage PMOS transistor HMP1 will turn on quickly, pulling the potential at point S' low. As the potential at point S' decreases, the PMOS transistor MP2 turns on, pulling the potential at point R' high. Since the current capability of the high-voltage transistor is much greater than that of the low-voltage transistor, the potential at point S' will be quickly pulled down by the pull-down current provided by the high-voltage transistors HMN1 and HMP1, while the potential at point R' will be pulled up by the low-voltage transistor. The process of MP2 rising is relatively slow. When the input signal changes from high to low, as shown in Figure 3(b), the high-voltage NMOS transistor HMN2 and the high-voltage PMOS transistor HMP2 will turn on quickly, pulling the potential at point R' down. As the potential at point R' decreases, the PMOS transistor MP1 turns on, pulling the potential at point S' up. Since the current capability of the high-voltage transistor is much greater than that of the low-voltage transistor, the potential at point R' will be quickly pulled down by the pull-down current provided by the high-voltage transistors HMN2 and HMP2, while the process of the potential at point S' being pulled up by the low-voltage transistor MP1 is relatively slow. Therefore, the circuit delay will be greatly increased, as shown in the circuit waveform in Figure 2, where the rise time t of the potentials at points S' and R' is... _up1 Very large, the delay t of the output signal OUT' relative to the input signal IN. _delay1 The rise time is also significant. Furthermore, an excessively long signal rise time also increases the power consumption of the entire level shifting circuit. Therefore, there is an urgent need to develop a low-power, high-speed level shifting technology. Summary of the Invention

[0006] To address the issues of high delay and high power consumption in the existing technologies, this invention proposes a low-power, high-speed level shifting circuit. While ensuring sufficient dV / dt resistance, it effectively reduces the power consumption and delay of the level shifting circuit, enabling high-frequency operation of the drive circuit and ensuring the high efficiency of the power supply system.

[0007] To achieve the above-mentioned objectives, the present invention employs the following technical solution: a low-power high-speed level shifting circuit, comprising a low-voltage-to-high-voltage level shifting module, an auxiliary latching module, an adaptive narrow pulse generation module, and an auxiliary pull-up module. The low-voltage-to-high-voltage level shifting module is jointly composed of a low-voltage-to-high-voltage level shifting circuit 001 and a signal processing circuit 002. The low-voltage-to-high-voltage level shifting circuit 001 includes high-voltage NMOS transistors HMN1, HMN2, HMP1, HMP2, MP1, and MP2, and an inverter INV1. The connection relationships are as follows: the gate of high-voltage NMOS transistor HMN1 is connected to the input signal IN and the input terminal of inverter INV1; the source of high-voltage NMOS transistor HMN1 is connected to the ground signal VSSL of the low-voltage domain power rail; the drain of high-voltage NMOS transistor HMN1 is connected to the drain of high-voltage PMOS transistor HMP1; and the gate of high-voltage NMOS transistor HMN2 is connected to the input terminal of inverter INV1. At the output terminals, the source of the high-voltage NMOS transistor HMN2 is connected to the ground signal VSSL of the low-voltage power rail; the drain of the high-voltage NMOS transistor HMN2 is connected to the drain of the high-voltage PMOS transistor HMP2; the gate of the high-voltage PMOS transistor HMP1 is connected to the ground signal VSSH of the high-voltage power rail, one end of resistor R2, the source of NMOS transistor MN1, the source of NMOS transistor MN2, and the gate of high-voltage PMOS transistor HMP2; the source of high-voltage PMOS transistor HPM1 is connected to the gate of PMOS transistor MP3, the drain of PMOS transistor MN1, the gate of PMOS transistor MP2, one end of resistor R1, the drain of PMOS transistor MP5, and the inverter. The input terminal of INV9 is connected to the gate of high-voltage PMOS transistor HMP2, the ground signal VSSH of the high-voltage power rail, one end of resistor R2, the source of NMOS transistor MN2, the source of NMOS transistor MN1, and the gate of high-voltage PMOS transistor HMP1. The source of high-voltage PMOS transistor HMP2 is connected to the gate of PMOS transistor MP4, the drain of PMOS transistor MN2, the gate of PMOS transistor MP1, the drain of PMOS transistor MP5, and the input terminal of inverter INV8. The gate of PMOS transistor MP1 is connected to the drain of PMOS transistor MP2, the input terminal of inverter INV8, the gate of PMOS transistor MP4, and the input terminal of PMOS transistor M... The drain of P6 is connected to the source of the high-voltage PMOS transistor HMP2. The source of PMOS transistor MP1 is connected to the power signal VDDH of the high-voltage power rail. The drain of PMOS transistor MP1 is connected to one end of resistor R1, the drain of PMOS transistor MP5, the gate of PMOS transistor MP3, the source of high-voltage PMOS transistor HMP1, the input of inverter INV9, and the gate of PMOS transistor MP2. The gate of PMOS transistor MP2 is connected to the drain of PMOS transistor MP1, the input of inverter INV9, the gate of PMOS transistor MP3, the drain of PMOS transistor MP5, one end of resistor R1, and the source of high-voltage PMOS transistor HMP1.The source of PMOS transistor MP2 is connected to the power supply signal VDDH of the high-voltage power rail. The drain of PMOS transistor MP2 is connected to the drain of PMOS transistor MP6, the gate of PMOS transistor MP4, the source of high-voltage PMOS transistor HMP2, the input of inverter INV8, and the gate of PMOS transistor MP1. The input of inverter INV1 is connected to the input signal IN and the source of high-voltage NMOS transistor HMN1. The output of inverter INV1 is connected to the source of high-voltage NMOS transistor HMN2. The power supply and ground terminals of inverter INV1 are connected to the power supply signal VDDL of the low-voltage power rail and the ground signal VSSL, respectively.

[0008] Signal processing circuit 002 includes inverter INV8, inverter INV9, and RS flip-flop. The connection relationship is as follows: the input terminal of inverter INV8 is connected to the gate of PMOS transistor MP1, the drain of PMOS transistor MP2, the drain of PMOS transistor MP6, the gate of PMOS transistor MP4, and the source of high-voltage PMOS transistor HMP2. The output terminal of inverter INV8 is connected to the R terminal of RS flip-flop. The input terminal of inverter INV9 is connected to the gate of PMOS transistor MP2, the drain of PMOS transistor MP1, the drain of PMOS transistor MP5, one end of resistor R1, the gate of PMOS transistor MP3, and the source of high-voltage PMOS transistor HMP2. The output terminal of inverter INV9 is connected to the S terminal of RS flip-flop. The output terminal of RS flip-flop is connected to the output OUT.

[0009] The feature is that, based on the high-voltage level shifting circuit, two auxiliary pull-up circuits 003 and 004 are added at the two output points S and R on the high side to assist the rapid flipping of the level from low to high at points S and R. The auxiliary pull-up circuit 003 at point S includes inverters INV2, INV3, and INV4, a NAND gate NAND1, and a PMOS transistor MP5. The connections are as follows: the input of inverter INV2 is connected to the drain of PMOS transistor MP4, the drain of NMOS transistor MN2, and the gate of NMOS transistor MN1; the output of inverter INV2 is connected to the input of inverter INV3; the output of inverter INV3 is connected to the input of inverter INV4; the output of inverter INV4 is connected to one input of NAND gate NAND1; and the other input of NAND gate NAND1 is connected to PMOS transistor MP5. The drain of S-channel transistor MP8 and one end of resistor R5 are connected to the output of NAND gate NAND1 and the gate of PMOS transistor MP5. The source of PMOS transistor MP5 is connected to the power supply signal VDDH of the high-voltage power rail. The drain of PMOS transistor MP5 is connected to the drain of PMOS transistor MP1, the gate of PMOS transistor MP2, one end of resistor R1, the source of high-voltage PMOS transistor HMP1, the gate of PMOS transistor MP3, and the input of inverter INV9. The power supply and ground terminals of inverters INV2, INV3, and INV4 are respectively connected to the power supply signal VDDH of the high-voltage power rail and the floating ground signal VSSH. The auxiliary pull-up circuit 004 at point R includes inverters INV5, INV6, and INV7, a NAND gate NAND2, and a PMOS transistor MP6. The connections are as follows: the input of inverter INV5 is connected to the drain of PMOS transistor MP3, the drain of NMOS transistor MN1, the gate of NMOS transistor MN2, and the other end of resistor R2; the output of inverter INV5 is connected to the input of inverter INV6; the output of inverter INV6 is connected to the input of inverter INV7; and the output of inverter INV7 is connected to one input of NAND gate NAND2. The input terminal is connected to the drain of PMOS transistor MP8 and one end of resistor R5. The output terminal of NAND gate NAND2 is connected to the gate of PMOS transistor MP6. The source of PMOS transistor MP6 is connected to the power supply signal VDDH of the high-voltage power rail. The drain of PMOS transistor MP6 is connected to the drain of PMOS transistor MP2, the gate of PMOS transistor MP1, the source of high-voltage PMOS transistor HMP2, the gate of PMOS transistor MP4, and the input terminal of inverter INV8. The power supply terminals and ground terminals of inverters INV2, INV3, and INV4 are respectively connected to the power supply signal VDDH of the high-voltage power rail and the floating ground signal VSSH.

[0010] The auxiliary latch module is composed of an auxiliary latch circuit 005, which includes PMOS transistor MP3, PMOS transistor MP4, NMOS transistor MN1 and NMOS transistor MN2. The source of NMOS transistor MN1 is connected to the ground signal VSSH of the high-voltage power rail, one end of resistor R2, the source of NMOS transistor MN2, the gate of high-voltage PMOS transistor HMP1, and the gate of high-voltage PMOS transistor HMP2. The gate of NMOS transistor MN1 is connected to the drain of PMOS transistor MP4 and the drain of NMOS transistor MN2. The drain of NMOS transistor MN1 is connected to the drain of PMOS transistor MP3, the other end of resistor R2, and the gate of NMOS transistor MN2. The source of NMOS transistor MN2 is connected to the ground signal VSSH of the high-voltage power rail, one end of resistor R2, the source of NMOS transistor MN1, the gate of high-voltage PMOS transistor HMP2, and the gate of high-voltage PMOS transistor HMP1. The gate of NMOS transistor MN2 is connected to the drain of PMOS transistor MP3, the other end of resistor R2, and the drain of NMOS transistor MN1. The drain of NMOS transistor MN2 is connected to the drain of PMOS transistor MP4 and the drain of NMOS transistor MN2. The gate of MOS transistor MN1 and the drain of PMOS transistor MP3 are connected to the drain of NMOS transistor MN1, the other end of resistor R2, and the gate of NMOS transistor MN2. The gate of PMOS transistor MP3 is connected to the source of high-voltage PMOS transistor HMP1, the drain of PMOS transistor MP1, the gate of PMOS transistor MP2, one end of resistor R1, the drain of PMOS transistor MP5, and the input of inverter INV9. The source of PMOS transistor MP3 is connected to the power signal VDDH of the high-voltage power rail. The drain of PMOS transistor MP4 is connected to the drain of NMOS transistor MN2 and the gate of NMOS transistor MN1. The gate of PMOS transistor MP4 is connected to the source of high-voltage PMOS transistor HMP2, the drain of PMOS transistor MP2, the gate of PMOS transistor MP1, the drain of PMOS transistor MP6, and the input of inverter INV8. The source of PMOS transistor MP3 is connected to the power signal VDDH of the high-voltage power rail.

[0011] Furthermore, the adaptive narrow pulse generation module is composed of an adaptive narrow pulse generation circuit 006, including a PMOS transistor MP7, a PMOS transistor MP8, and a resistor R5. The connections are as follows: the gate of PMOS transistor MP7 is connected to the gate of PMOS transistor MP4, the source of high-voltage PMOS transistor HMP2, the drain of PMOS transistor MP2, the gate of PMOS transistor MP1, the drain of PMOS transistor MP6, and the input of inverter INV8. The source of PMOS transistor MP7 is connected to the power signal VDDH of the high-voltage power rail. The drain of PMOS transistor MP7 is connected to the source of PMOS transistor MP8. The gate of PMOS transistor MP8 is connected to the gate of PMOS transistor MP3, the source of high-voltage PMOS transistor HMP1, the drain of PMOS transistor MP1, the gate of PMOS transistor MP2, the drain of PMOS transistor MP5, one end of resistor R1, and the input of inverter INV9. The source of PMOS transistor MP8 is connected to the drain of PMOS transistor MP7. The drain of PMOS transistor MP8 is connected to one end of resistor R5, and the other end of resistor R5 is connected to the ground signal VSSH of the high-voltage power rail.

[0012] Furthermore, there are pull-up resistors R1 and pull-down resistors R2, which provide the circuit with an initial state when it is initially powered on, thus avoiding the generation of indeterminate states.

[0013] Compared with the prior art, the present invention has the following advantages and significant effects:

[0014] (1) It can effectively reduce the delay of signal transmission. The auxiliary pull-up circuits 003 and 004 can provide an additional pull-up current when the output terminals S and R of the low-voltage to high-voltage level shift circuit 001 flip from low to high, which can cause the level to flip quickly and improve the overall response speed of the circuit.

[0015] (2) It can effectively reduce the loss during the level switching process. The auxiliary pull-up circuits 003 and 004 reduce the signal switching rise time and the switching loss of high voltage transistors HMP1, HMN1 and HMP2, HMN2 during this process. In addition, the two auxiliary pull-up circuits proposed in this invention will not generate additional conduction loss.

[0016] (3) The auxiliary branch does not require high voltage tubes and is composed entirely of low voltage tubes, so it will not increase the additional chip area. Attached Figure Description

[0017] Figure 1 This is a typical application diagram of a gallium nitride (GaN) driver circuit;

[0018] Figure 2(a) and Figure 2(b) are the structural diagram of a traditional high-voltage level shift circuit and the working waveform diagram under the input pulse signal, respectively.

[0019] Figures 3(a) and 3(b) are schematic diagrams of the fast and slow paths of signal flipping in a traditional high-voltage level shift circuit, respectively.

[0020] Figure 4(a) is a circuit diagram of the low-power high-speed level shift circuit proposed in this invention, and Figure 4(b) is a circuit diagram of the adaptive narrow pulse generation circuit.

[0021] Figure 5 This is a specific waveform diagram illustrating the low latency and low power consumption achieved by the present invention;

[0022] Figure 6 This is a waveform diagram of the input pulse signal for this invention.

[0023] Figure 7 This is a comparison diagram of the operating waveforms of the present invention and conventional circuits. Detailed Implementation

[0024] The present invention will be further described below with reference to the accompanying drawings and specific embodiments.

[0025] Figures 4(a) and 4(b) show the specific circuit diagrams of the low-power, high-speed level shift circuit proposed in this invention, used to convert signals from the low-voltage domain to the high-voltage domain. The circuit includes a low-voltage to high-voltage level shift circuit 001 (Figure 4(a)), a signal processing circuit 002, an auxiliary pull-up circuit 003, an auxiliary pull-up circuit 004, an auxiliary latch circuit 005, and an adaptive narrow pulse generation circuit 006 (Figure 4(b)). The low-voltage domain power rail is ground signal VSSL-power signal VDDL, and the high-voltage domain power rail is ground signal VSSH-power signal VDDH.

[0026] The low-power, high-speed level shifter circuit is based on a traditional high-voltage level shifter circuit, with the addition of two auxiliary pull-up circuits 003 and 004, an auxiliary latch circuit 005, and an adaptive pulse generation circuit 006. The two auxiliary pull-up circuits 003 and 004 are completely symmetrical, including inverters INV2-INV4, NAND gate NAND1, PMOS transistor MP5, and inverters INV5-INV7, NAND gate NAND2, and PMOS transistor MP6. In auxiliary pull-up circuit 003, inverters INV2-INV4 form a delay circuit to delay the input B signal for a certain period of time t. _delayThe input signal is then fed to NAND gate NAND1. The B signal is generated by the auxiliary latch circuit. The other input of NAND gate NAND1 is connected to the adaptive narrow pulse UP signal generated by the adaptive narrow pulse generation circuit 006. The delay circuit composed of inverters INV2 to INV4, together with NAND gate NAND1, constitutes the control circuit for the pull-up PMOS transistor MP5. This circuit controls PMOS transistor MP5 to provide a pull-up current as the potential at point S slowly rises from low to high, assisting in a rapid rise in the potential at point S. Similarly, in the auxiliary pull-up circuit 004, inverters INV5 to INV7 constitute a delay circuit, used to delay the input A signal for a period of time t. _delay The signal is then input to NAND gate NAND2. Signal A is generated by the auxiliary latch circuit. The other input of NAND gate NAND2 is connected to the adaptive narrow pulse UP signal generated by the adaptive narrow pulse generation circuit 006. The delay circuit composed of inverters INV5 to INV7 together with NAND gate NAND2 constitutes the control circuit of pull-up PMOS transistor MP6, which is used to control PMOS transistor MP6 to provide a pull-up current when the potential of point R slowly rises from low to high, so as to assist the potential of point R to rise quickly.

[0027] The auxiliary latch circuit 005 consists of PMOS transistors MP3 and MP4 and NMOS transistors MN1 and MN2. NMOS transistors MN1 and MN2 form a positive feedback structure. The gates of the PMOS transistors on both sides are connected to the output points S and R of the low-voltage to high-voltage level shift circuit 001, respectively, to generate two control signals A and B, which are connected to two auxiliary pull-up circuits. This controls the pull-up transistors MP5 and MP6 to provide an additional pull-up current only when the output point potential of the branch assisted by the transistor flips from low to high. This avoids providing pull-up current when the output point potential flips from high to low, which would affect the circuit transmission speed and cause unnecessary losses.

[0028] Figure 4(b) shows the specific structure of an adaptive narrow pulse generation circuit 006 used in this invention, which generates an adaptive narrow pulse signal UP to control the pull-up transistor. It includes PMOS transistors MP7 and MP8 and resistor R5. The gates of the two PMOS transistors are connected to points S and R of the low-voltage to high-voltage level shift circuit 001, respectively, and are used as switching transistors. As can be seen from the working waveform diagram of the input pulse signal of the conventional high-voltage level shift circuit in Figure 2(b), when the two output signals S and R of the high-voltage level shift circuit are flipped, due to a certain speed difference, both points are simultaneously at a low potential for a period of time. Only by adding an extra pull-up current to the slow path during this period can the circuit's response speed be improved. Therefore, two PMOS switching transistors MP7 and MP8 are connected in series. Only when the gate signals R and S of both switching transistors are low will the branch conduct, and the UP signal will be high (VDDH). In other cases, the UP signal is low (VSSH). Thus, a control narrow pulse signal can be adaptively generated according to the potential changes at S and R to control the pull-up transistor.

[0029] Figure 5 The diagram shows the specific waveforms illustrating the low latency and low power consumption achieved by this invention. When the input signal IN changes from low to high, the high-voltage NMOS transistor HMN1 and the high-voltage PMOS transistor HMP1 quickly turn on, rapidly pulling the potential at point S to a low level. Meanwhile, the potential at point R is flipped by a pull-up current generated by the positive feedback of PMOS transistor MP2. Since the current capability of the low-voltage transistor is much lower than that of the high-voltage transistor, the flipping speed of the R potential is slower than that of point S. At this time, due to the different flipping speeds of points S and R, both points S and R will be below the threshold voltage Vth_P of the PMOS transistor for a period of time. During this period, both PMOS switches in the adaptive narrow pulse generation circuit are turned on, the UP signal potential becomes high, and an adaptive narrow pulse is generated and input to the NAND gate NAND1. Furthermore, as point S becomes low, PMOS transistor MP3 turns on, and the signal at point A quickly flips to a high level. After a delay of t in the inverter chain INV2~INV4, the signal continues to flow. _delay After inputting NAND gate NAND1, the potential at point A goes high, turning on NMOS transistor MN2 through positive feedback, and the signal at point B goes low. After passing through inverter chain INV5~INV7 and delayed by t... _delayThe input is then fed into NAND gate NAND2. Similarly, when the input signal IN changes from high to low, the high-voltage NMOS transistor HMN2 and the high-voltage PMOS transistor HMP2 quickly turn on, rapidly pulling the potential at point R to a low level. Meanwhile, the potential at point S is flipped by a pull-up current generated by the positive feedback of PMOS transistor MP1. Because the current capability of the low-voltage transistor is much lower than that of the high-voltage transistor, the flipping speed of the S potential is slower than that of point R. At this time, due to the different flipping speeds of points R and S, both points R and S will simultaneously be below the threshold voltage Vth_P of the PMOS transistor for a period of time. During this period, both PMOS switches in the adaptive narrow pulse generation circuit are turned on, the UP signal potential becomes high, and an adaptive narrow pulse is generated and input to NAND gate NAND1. Additionally, as point R becomes low, PMOS transistor MP4 turns on, and the signal at point B quickly flips to a high level. After a delay of t by the inverter chain INV5~INV7, the signal is then processed. _delay After inputting NAND gate NAND1, the potential at point B becomes high, which turns on NMOS transistor MN1 through positive feedback, causing the signal at point A to become low. After passing through inverter chain INV2~INV4 and delayed by t... _delay The input is then processed by NAND gate NAND1. The UP signal generates a high-level narrow pulse on both the rising and falling edges of the input signal IN. After passing through NAND gate NAND2 with signal A, the resulting D signal generates a low-level narrow pulse only on the rising edge of the IN signal, controlling the pull-up transistor MP6 to conduct at this time, providing additional pull-up current to assist point R in rapidly toggling from low to high. After passing through NAND gate NAND1 with signal B, the resulting C signal generates a low-level narrow pulse only on the falling edge of the IN signal, controlling the pull-up transistor MP5 to conduct at this time, providing additional pull-up current to assist point S in rapidly toggling from low to high.

[0030] Figure 6 , Figure 7 The diagram shows the working waveform of the input pulse signal of this invention and a comparison diagram of the working waveforms of this invention and a conventional circuit. In the low-power high-speed level shift circuit proposed in this invention, the switching delay of the slow path is t. _up2 The final transmission delay between the output signal OUT and the input signal IN is t. _delay2 It is significantly less than the path flip delay t in traditional circuits. _up1 and signal transmission delay t _delay1 This improves the overall circuit transmission speed while reducing switching losses during the high-voltage tube's conduction period.

Claims

1. A low-power, high-speed level shifting circuit, characterized in that, It includes a low-voltage to high-voltage level shifting module, an auxiliary latch module, an adaptive narrow pulse generation module, and an auxiliary pull-up module. The low-voltage to high-voltage level shifting module includes a low-voltage to high-voltage level shifting circuit and a signal processing circuit. The auxiliary pull-up module includes two auxiliary pull-up circuits respectively located at the two output S and R points on the high side of the low-voltage to high-voltage level shifting circuit. The auxiliary pull-up circuit includes an inverter, a NAND gate, and a PMOS transistor. The auxiliary latch module includes an auxiliary latch circuit used to generate two control signals A and B, which are connected to the two auxiliary pull-up circuits to control the two pull-up PMOS transistors to provide an additional pull-up current only when the output point potential of the branch assisted by the transistor flips from low to high. The low-voltage to high-voltage level shifting circuit includes high-voltage NMOS transistors HMN1 and HMN2, high-voltage PMOS transistors HMP1 and HMP2, PMOS transistors MP1 and MP2, and an inverter INV1. The connections are as follows: the gate of high-voltage NMOS transistor HMN1 is connected to the input signal IN and the input terminal of inverter INV1; the source of high-voltage NMOS transistor HMN1 is connected to the ground signal VSSL of the low-voltage power rail; the drain of high-voltage NMOS transistor HMN1 is connected to the drain of high-voltage PMOS transistor HMP1; the gate of high-voltage NMOS transistor HMN2 is connected to the output terminal of inverter INV1; and the source of high-voltage NMOS transistor HMN2 is connected to the ground of the low-voltage power rail. Signal VSSL, the drain of high-voltage NMOS transistor HMN2 is connected to the drain of high-voltage PMOS transistor HMP2, the gate of high-voltage PMOS transistor HMP1 is connected to the ground signal VSSH of the high-voltage power rail, one end of resistor R2, the source of NMOS transistor MN1, the source of NMOS transistor MN2, and the gate of high-voltage PMOS transistor HMP2, the source of high-voltage PMOS transistor HPM1 is connected to the gate of PMOS transistor MP3, the drain of PMOS transistor MN1, the gate of PMOS transistor MP2, one end of resistor R1, the drain of PMOS transistor MP5, and the input of inverter INV9, the gate of high-voltage PMOS transistor HMP2 is connected to the ground signal VSSH of the high-voltage power rail, one end of resistor R2, and the NMOS transistor... The source of MN2, the source of NMOS transistor MN1, and the gate of high-voltage PMOS transistor HMP1 are connected. The source of high-voltage PMOS transistor HMP2 is connected to the gate of PMOS transistor MP4, the drain of PMOS transistor MN2, the gate of PMOS transistor MP1, the drain of PMOS transistor MP5, and the input of inverter INV8. The gate of PMOS transistor MP1 is connected to the drain of PMOS transistor MP2, the input of inverter INV8, the gate of PMOS transistor MP4, the drain of PMOS transistor MP6, and the source of high-voltage PMOS transistor HMP2. The source of PMOS transistor MP1 is connected to the power signal VDDH of the high-voltage power rail. The drain of PMOS transistor MP1 is connected to one end of resistor R1 and PMOS transistor MP5. The circuit connects the drain of PMOS transistor MP1, the gate of PMOS transistor MP3, the source of high-voltage PMOS transistor HMP1, the input of inverter INV9, and the gate of PMOS transistor MP2. The gate of PMOS transistor MP2 is connected to the drain of PMOS transistor MP1, the input of inverter INV9, the gate of PMOS transistor MP3, the drain of PMOS transistor MP5, one end of resistor R1, and the source of high-voltage PMOS transistor HMP1. The source of PMOS transistor MP2 is connected to the power signal VDDH of the high-voltage power rail. The drain of PMOS transistor MP2 is connected to the drain of PMOS transistor MP6, the gate of PMOS transistor MP4, the source of high-voltage PMOS transistor HMP2, the input of inverter INV8, and the gate of PMOS transistor MP1.The input terminal of inverter INV1 is connected to the input signal IN and the source of high-voltage NMOS transistor HMN1. The output terminal of inverter INV1 is connected to the source of high-voltage NMOS transistor HMN2. The power supply terminal and ground terminal of inverter INV1 are connected to the power supply signal VDDL and the ground signal VSSL of the low-voltage power rail, respectively. The signal processing circuit includes inverter INV8, inverter INV9, and RS flip-flop. The connection relationship is as follows: the input terminal of inverter INV8 is connected to the gate of PMOS transistor MP1, the drain of PMOS transistor MP2, the drain of PMOS transistor MP6, the gate of PMOS transistor MP4, and the source of high-voltage PMOS transistor HMP2. The output terminal of inverter INV8 is connected to the R terminal of RS flip-flop. The input terminal of inverter INV9 is connected to the gate of PMOS transistor MP2, the drain of PMOS transistor MP1, the drain of PMOS transistor MP5, one end of resistor R1, the gate of PMOS transistor MP3, and the source of high-voltage PMOS transistor HMP2. The output terminal of inverter INV9 is connected to the S terminal of RS flip-flop. The output terminal of RS flip-flop is connected to the output OUT. The auxiliary pull-up circuit at point S includes inverters INV2, INV3, and INV4, a NAND gate NAND1, and a PMOS transistor MP5. The connections are as follows: the input of inverter INV2 is connected to the drain of PMOS transistor MP4, the drain of NMOS transistor MN2, and the gate of NMOS transistor MN1; the output of inverter INV2 is connected to the input of inverter INV3; the output of inverter INV3 is connected to the input of inverter INV4; the output of inverter INV4 is connected to one input of NAND gate NAND1; and the other input of NAND gate NAND1 is connected to the PMOS transistor MP5. The drain of MP8 and one end of resistor R5 are connected to the output of NAND gate NAND1 and the gate of PMOS transistor MP5. The source of PMOS transistor MP5 is connected to the power supply signal VDDH of the high-voltage power rail. The drain of PMOS transistor MP5 is connected to the drain of PMOS transistor MP1, the gate of PMOS transistor MP2, one end of resistor R1, the source of high-voltage PMOS transistor HMP1, the gate of PMOS transistor MP3, and the input of inverter INV9. The power supply and ground terminals of inverters INV2, INV3, and INV4 are respectively connected to the power supply signal VDDH of the high-voltage power rail and the floating ground signal VSSH. The auxiliary pull-up circuit at point R includes inverters INV5, INV6, and INV7, a NAND gate NAND2, and a PMOS transistor MP6. The connections are as follows: the input of inverter INV5 is connected to the drain of PMOS transistor MP3, the drain of NMOS transistor MN1, the gate of NMOS transistor MN2, and the other end of resistor R2; the output of inverter INV5 is connected to the input of inverter INV6; the output of inverter INV6 is connected to the input of inverter INV7; the output of inverter INV7 is connected to one input of NAND gate NAND2; and the other input of NAND gate NAND2... The input terminal is connected to the drain of PMOS transistor MP8 and one end of resistor R5. The output terminal of NAND gate NAND2 is connected to the gate of PMOS transistor MP6. The source of PMOS transistor MP6 is connected to the power supply signal VDDH of the high-voltage power rail. The drain of PMOS transistor MP6 is connected to the drain of PMOS transistor MP2, the gate of PMOS transistor MP1, the source of high-voltage PMOS transistor HMP2, the gate of PMOS transistor MP4, and the input terminal of inverter INV8. The power supply terminals and ground terminals of inverters INV2, INV3, and INV4 are respectively connected to the power supply signal VDDH of the high-voltage power rail and the floating ground signal VSSH. The auxiliary latching circuit includes PMOS transistors MP3, MP4, NMOS transistors MN1 and MN2. The source of NMOS transistor MN1 is connected to the ground signal VSSH of the high-voltage power rail, one end of resistor R2, the source of NMOS transistor MN2, the gate of high-voltage PMOS transistors HMP1 and HMP2, and the gate of NMOS transistor MN1 is connected to the drain of PMOS transistor MP4 and the drain of NMOS transistor MN2. The drain of NMOS transistor MN1 is connected to the drain of PMOS transistor MP3, the other end of resistor R2, and the gate of NMOS transistor MN2. The source of NMOS transistor MN2 is connected to the ground signal VSSH of the high-voltage power rail, one end of resistor R2, the source of NMOS transistor MN1, the gate of high-voltage PMOS transistor HMP2, and the gate of high-voltage PMOS transistor HMP1, and the gate of NMOS transistor MN2 is connected to the drain of PMOS transistor MP3, the other end of resistor R2, and the drain of NMOS transistor MN1. The drain of S-channel transistor MN2 is connected to the drain of PMOS transistor MP4 and the gate of NMOS transistor MN1. The drain of PMOS transistor MP3 is connected to the drain of NMOS transistor MN1, the other end of resistor R2, and the gate of NMOS transistor MN2. The gate of PMOS transistor MP3 is connected to the source of high-voltage PMOS transistor HMP1, the drain of PMOS transistor MP1, the gate of PMOS transistor MP2, one end of resistor R1, the drain of PMOS transistor MP5, and the input of inverter INV9. The source of PMOS transistor MP3 is connected to the power signal VDDH of the high-voltage power rail. The drain of PMOS transistor MP4 is connected to the drain of NMOS transistor MN2 and the gate of NMOS transistor MN1. The gate of PMOS transistor MP4 is connected to the source of high-voltage PMOS transistor HMP2, the drain of PMOS transistor MP2, the gate of PMOS transistor MP1, the drain of PMOS transistor MP6, and the input of inverter INV8. The source of PMOS transistor MP3 is connected to the power signal VDDH of the high-voltage power rail. The adaptive narrow pulse generation module consists of an adaptive narrow pulse generation circuit, including PMOS transistors MP7 and MP8 and resistor R5. The connections are as follows: the gate of PMOS transistor MP7 is connected to the gate of PMOS transistor MP4, the source of high-voltage PMOS transistor HMP2, the drain of PMOS transistor MP2, the gate of PMOS transistor MP1, the drain of PMOS transistor MP6, and the input of inverter INV8; the source of PMOS transistor MP7 is connected to the power signal VDDH of the high-voltage power rail; and the PMOS transistor MP7... The drain of PMOS transistor MP8 is connected to the source of PMOS transistor MP8. The gate of PMOS transistor MP8 is connected to the gate of PMOS transistor MP3, the source of high-voltage PMOS transistor HMP1, the drain of PMOS transistor MP1, the gate of PMOS transistor MP2, the drain of PMOS transistor MP5, one end of resistor R1, and the input of inverter INV9. The source of PMOS transistor MP8 is connected to the drain of PMOS transistor MP7. The drain of PMOS transistor MP8 is connected to one end of resistor R5. The other end of resistor R5 is connected to the ground signal VSSH of the high-voltage power rail.

Images